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This driver also fixup the DSDT table to adapt with the difference between 1P and 2P system. Cc: Thang Nguyen Cc: Chuong Tran Cc: Phong Vo Cc: Leif Lindholm Cc: Michael D Kinney Cc: Ard Biesheuvel Cc: Nate DeSimone Signed-off-by: Nhi Pham Acked-by: Leif Lindholm --- Platform/Ampere/JadePkg/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf | 4 = + Platform/Ampere/JadePkg/Drivers/AcpiPlatformDxe/AcpiPlatform.h | 12 = + Silicon/Ampere/AmpereAltraPkg/Include/Platform/Ac01.h | 60 = ++++ Platform/Ampere/JadePkg/Drivers/AcpiPlatformDxe/AcpiDsdt.c | 90 = +++++ Platform/Ampere/JadePkg/Drivers/AcpiPlatformDxe/AcpiIort.c | 349 = ++++++++++++++++++++ Platform/Ampere/JadePkg/Drivers/AcpiPlatformDxe/AcpiMcfg.c | 151 = +++++++++ Platform/Ampere/JadePkg/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.c | 10 = + 7 files changed, 676 insertions(+) diff --git a/Platform/Ampere/JadePkg/Drivers/AcpiPlatformDxe/AcpiPlatformDx= e.inf b/Platform/Ampere/JadePkg/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf index 72e78fb4e31e..415f795d2a54 100644 --- a/Platform/Ampere/JadePkg/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf +++ b/Platform/Ampere/JadePkg/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf @@ -18,7 +18,9 @@ [Sources.common] AcpiApei.c AcpiApei.h AcpiDsdt.c + AcpiIort.c AcpiMadt.c + AcpiMcfg.c AcpiNfit.c AcpiPcct.c AcpiPlatform.h @@ -43,6 +45,7 @@ [LibraryClasses] BaseLib DebugLib FlashLib + HobLib MailboxInterfaceLib SystemFirmwareInterfaceLib TimerLib @@ -66,6 +69,7 @@ [Guids] gEfiAcpiTableGuid gEfiEventReadyToBootGuid gPlatformInfoHobGuid + gRootComplexInfoHobGuid =20 [Protocols] gEfiAcpiTableProtocolGuid ## ALWAYS_CONSUMED diff --git a/Platform/Ampere/JadePkg/Drivers/AcpiPlatformDxe/AcpiPlatform.h= b/Platform/Ampere/JadePkg/Drivers/AcpiPlatformDxe/AcpiPlatform.h index b5035067a47b..170aeff24d59 100644 --- a/Platform/Ampere/JadePkg/Drivers/AcpiPlatformDxe/AcpiPlatform.h +++ b/Platform/Ampere/JadePkg/Drivers/AcpiPlatformDxe/AcpiPlatform.h @@ -71,4 +71,16 @@ AcpiInstallSratTable ( VOID ); =20 +EFI_STATUS +EFIAPI +AcpiInstallMcfg ( + VOID + ); + +EFI_STATUS +EFIAPI +AcpiInstallIort ( + VOID + ); + #endif /* ACPI_PLATFORM_H_ */ diff --git a/Silicon/Ampere/AmpereAltraPkg/Include/Platform/Ac01.h b/Silico= n/Ampere/AmpereAltraPkg/Include/Platform/Ac01.h index 132c0d6d6cac..d45688f88401 100644 --- a/Silicon/Ampere/AmpereAltraPkg/Include/Platform/Ac01.h +++ b/Silicon/Ampere/AmpereAltraPkg/Include/Platform/Ac01.h @@ -279,4 +279,64 @@ // #define AC01_PCIE_MMIO32_SIZE_1P_LIST 0x10000000, 0x10000000, 0x1000000= 0, 0x10000000, 0x8000000, 0x10000000, 0x10000000, 0x10000000, 0, 0, 0, 0, 0= , 0, 0, 0 =20 +// +// DSDT RCA2 PCIe MMIO32 Attribute +// +#define AC01_PCIE_RCA2_QMEM_LIST 0x0000000000000000, 0x00000000600= 00000, 0x000000006FFFFFFF, 0x0000000000000000, 0x0000000010000000 + +// +// DSDT RCA3 PCIe MMIO32 Attribute +// +#define AC01_PCIE_RCA3_QMEM_LIST 0x0000000000000000, 0x00000000700= 00000, 0x000000007FFFFFFF, 0x0000000000000000, 0x0000000010000000 + +// +// DSDT RCB0 PCIe MMIO32 Attribute +// +#define AC01_PCIE_RCB0_QMEM_LIST 0x0000000000000000, 0x00000000010= 00000, 0x000000000FFFFFFF, 0x0000000000000000, 0x000000000F000000 + +// +// DSDT RCB1 PCIe MMIO32 Attribute +// +#define AC01_PCIE_RCB1_QMEM_LIST 0x0000000000000000, 0x00000000100= 00000, 0x000000001FFFFFFF, 0x0000000000000000, 0x0000000010000000 + +// +// DSDT RCB2 PCIe MMIO32 Attribute +// +#define AC01_PCIE_RCB2_QMEM_LIST 0x0000000000000000, 0x00000000200= 00000, 0x000000002FFFFFFF, 0x0000000000000000, 0x0000000010000000 + +// +// DSDT RCB3 PCIe MMIO32 Attribute +// +#define AC01_PCIE_RCB3_QMEM_LIST 0x0000000000000000, 0x00000000300= 00000, 0x000000003FFFFFFF, 0x0000000000000000, 0x0000000010000000 + +// +// TBU PMU IRQ array +// +#define AC01_SMMU_TBU_PMU_IRQS_LIST 224, 230, 236, 242, 160, 170, 180= , 190, 544, 550, 556, 562, 480, 490, 500, 510 + +// +// TCU PMU IRQ array +// +#define AC01_SMMU_TCU_PMU_IRQS_LIST 256, 257, 258, 259, 260, 261, 262= , 263, 576, 577, 578, 579, 580, 581, 582, 583 + +// +// Max TBU PMU of Root Complex A +// +#define AC01_RCA_MAX_TBU_PMU 6 + +// +// Max TBU PMU of Root Complex B +// +#define AC01_RCB_MAX_TBU_PMU 10 + +// +// TBU Base offset of Root Complex A +// +#define AC01_RCA_TBU_PMU_OFFSET_LIST 0x40000, 0x60000, 0xA0000, 0xE000= 0, 0x100000, 0x140000 + +// +// TBU Base offset of Root Complex B +// +#define AC01_RCB_TBU_PMU_OFFSET_LIST 0x40000, 0x60000, 0xA0000, 0xE000= 0, 0x120000, 0x160000, 0x180000, 0x1C0000, 0x200000, 0x240000 + #endif /* PLATFORM_AC01_H_ */ diff --git a/Platform/Ampere/JadePkg/Drivers/AcpiPlatformDxe/AcpiDsdt.c b/P= latform/Ampere/JadePkg/Drivers/AcpiPlatformDxe/AcpiDsdt.c index 82bfbb90f07f..885ad8fc3511 100644 --- a/Platform/Ampere/JadePkg/Drivers/AcpiPlatformDxe/AcpiDsdt.c +++ b/Platform/Ampere/JadePkg/Drivers/AcpiPlatformDxe/AcpiDsdt.c @@ -6,6 +6,7 @@ =20 **/ =20 +#include #include #include #include @@ -40,6 +41,24 @@ typedef struct { OP_REGION_DWORD_DATA RegionBase; OP_REGION_DWORD_DATA RegionLen; } AML_OP_REGION; + +typedef struct { + UINT64 AddressGranularity; + UINT64 AddressMin; + UINT64 AddressMax; + UINT64 AddressTranslation; + UINT64 RangeLength; +} QWORD_MEMORY; + +STATIC QWORD_MEMORY mQMemList[] =3D { + { AC01_PCIE_RCA2_QMEM_LIST }, + { AC01_PCIE_RCA3_QMEM_LIST }, + { AC01_PCIE_RCB0_QMEM_LIST }, + { AC01_PCIE_RCB1_QMEM_LIST }, + { AC01_PCIE_RCB2_QMEM_LIST }, + { AC01_PCIE_RCB3_QMEM_LIST } +}; + #pragma pack() =20 EFI_STATUS @@ -543,6 +562,76 @@ AcpiPatchPcieAerFwFirst ( return Status; } =20 +VOID +AcpiPatchPcieMmio32 ( + EFI_ACPI_SDT_PROTOCOL *AcpiSdtProtocol, + EFI_ACPI_HANDLE TableHandle + ) +{ + AC01_ROOT_COMPLEX *RootComplexList; + CHAR8 *NextDescriptor, *Buffer; + CHAR8 NodePath[256]; + EFI_ACPI_DATA_TYPE DataType; + EFI_ACPI_HANDLE ObjectHandle; + EFI_STATUS Status; + EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptor; + UINTN DataSize; + UINTN Idx; + VOID *Hob; + + Hob =3D GetFirstGuidHob (&gRootComplexInfoHobGuid); + if (Hob =3D=3D NULL) { + return; + } + + RootComplexList =3D (AC01_ROOT_COMPLEX *)GET_GUID_HOB_DATA (Hob); + + for (Idx =3D 0; Idx < AC01_PCIE_MAX_ROOT_COMPLEX; Idx++) { + if (!RootComplexList[Idx].Active) { + // + // Patch for disabled Root Complex + // + AsciiSPrint (NodePath, sizeof (NodePath), "\\_SB.PCI%X._STA", Idx); + UpdateStatusMethodObject (AcpiSdtProtocol, TableHandle, NodePath, 0x= 0); + continue; + } + + if (!IsSlaveSocketActive () && Idx <=3D SOCKET0_LAST_RC) { + // + // Patch MMIO32 resource in 1P system + // + AsciiSPrint (NodePath, sizeof (NodePath), "\\_SB.PCI%X.RBUF", Idx); + Status =3D AcpiSdtProtocol->FindPath (TableHandle, NodePath, &Object= Handle); + if (EFI_ERROR (Status)) { + continue; + } + + Status =3D AcpiSdtProtocol->GetOption (ObjectHandle, 2, &DataType, (= VOID *)&Buffer, &DataSize); + if (EFI_ERROR (Status)) { + continue; + } + + if (DataType !=3D EFI_ACPI_DATA_TYPE_CHILD) { + AcpiSdtProtocol->Close (ObjectHandle); + continue; + } + + NextDescriptor =3D Buffer + 5; // Point to first address space descr= iptor + while ((NextDescriptor - Buffer) < DataSize) { + Descriptor =3D (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)NextDescriptor= ; + if (Descriptor->Desc =3D=3D ACPI_QWORD_ADDRESS_SPACE_DESCRIPTOR + && Descriptor->ResType =3D=3D ACPI_ADDRESS_SPACE_TYPE_MEM) { + CopyMem (&Descriptor->AddrSpaceGranularity, &mQMemList[Idx - 2],= sizeof (QWORD_MEMORY)); + break; + } + NextDescriptor +=3D (Descriptor->Len + sizeof (ACPI_LARGE_RESOURCE= _HEADER)); + } + + AcpiSdtProtocol->Close (ObjectHandle); + } + } +} + EFI_STATUS AcpiPatchDsdtTable ( VOID @@ -593,6 +682,7 @@ AcpiPatchDsdtTable ( AcpiPatchNvdimm (AcpiSdtProtocol, TableHandle); AcpiPatchPcieNuma (AcpiSdtProtocol, TableHandle); AcpiPatchPcieAerFwFirst (AcpiSdtProtocol, TableHandle); + AcpiPatchPcieMmio32 (AcpiSdtProtocol, TableHandle); =20 AcpiSdtProtocol->Close (TableHandle); AcpiUpdateChecksum ((UINT8 *)Table, Table->Length); diff --git a/Platform/Ampere/JadePkg/Drivers/AcpiPlatformDxe/AcpiIort.c b/P= latform/Ampere/JadePkg/Drivers/AcpiPlatformDxe/AcpiIort.c new file mode 100644 index 000000000000..b8f8cfa356af --- /dev/null +++ b/Platform/Ampere/JadePkg/Drivers/AcpiPlatformDxe/AcpiIort.c @@ -0,0 +1,349 @@ +/** @file + + Copyright (c) 2020 - 2021, Ampere Computing LLC. All rights reserved. + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define __AC01_ID_MAPPING(In, Num, Out, Ref, Flags) \ + { \ + In, \ + Num, \ + Out, \ + OFFSET_OF (AC01_IO_REMAPPING_STRUCTURE, Ref), \ + Flags \ + } + +#define TCU_TO_SMMU_OFFSET 0x2000 +#define PAGE1_TO_PMCG_OFFSET 0x10000 + +STATIC AC01_ROOT_COMPLEX *mRootComplexList; + +STATIC UINT32 mTbuPmuIrqArray[] =3D { AC01_SMMU_TBU_PMU_IRQS_LIST }; +STATIC UINT32 mTcuPmuIrqArray[] =3D { AC01_SMMU_TCU_PMU_IRQS_LIST }; +STATIC UINT64 mRcaTbuPmuOffset[] =3D { AC01_RCA_TBU_PMU_OFFSET_LIST }; +STATIC UINT64 mRcbTbuPmuOffset[] =3D { AC01_RCB_TBU_PMU_OFFSET_LIST }; + +#pragma pack(1) + +typedef struct { + EFI_ACPI_6_0_IO_REMAPPING_NODE Node; + UINT64 Base; + UINT32 Flags; + UINT32 Reserved; + UINT64 VatosAddress; + UINT32 Model; + UINT32 Event; + UINT32 Pri; + UINT32 Gerr; + UINT32 Sync; + UINT32 ProximityDomain; + UINT32 DeviceIdMapping; +} EFI_ACPI_6_2_IO_REMAPPING_SMMU3_NODE; + +typedef struct { + EFI_ACPI_6_0_IO_REMAPPING_ITS_NODE Node; + UINT32 ItsIdentifier; +} AC01_ITS_NODE; + +typedef struct { + EFI_ACPI_6_0_IO_REMAPPING_RC_NODE Node; + EFI_ACPI_6_0_IO_REMAPPING_ID_TABLE RcIdMapping; +} AC01_RC_NODE; + +typedef struct { + EFI_ACPI_6_2_IO_REMAPPING_SMMU3_NODE Node; + EFI_ACPI_6_0_IO_REMAPPING_ID_TABLE InterruptMsiMapping; + EFI_ACPI_6_0_IO_REMAPPING_ID_TABLE InterruptMsiMappingSingle; +} AC01_SMMU_NODE; + +typedef struct { + EFI_ACPI_6_0_IO_REMAPPING_TABLE Iort; + AC01_ITS_NODE ItsNode[2]; + AC01_RC_NODE RcNode[2]; + AC01_SMMU_NODE SmmuNode[2]; +} AC01_IO_REMAPPING_STRUCTURE; + +#pragma pack() + +EFI_ACPI_6_0_IO_REMAPPING_TABLE mIortHeader =3D { + .Header =3D __ACPI_HEADER ( + EFI_ACPI_6_0_IO_REMAPPING_TABLE_SIGNATURE, + AC01_IO_REMAPPING_STRUCTURE, + EFI_ACPI_IO_REMAPPING_TABLE_REVISION + ), + .NumNodes =3D 0, // To be filled + .NodeOffset =3D sizeof (EFI_ACPI_6_0_IO_REMAPPING_TABLE), + 0 +}; + +AC01_ITS_NODE mItsNodeTemplate =3D { + .Node =3D { + { + EFI_ACPI_IORT_TYPE_ITS_GROUP, + sizeof (EFI_ACPI_6_0_IO_REMAPPING_ITS_NODE) + 4, + 0x0, + 0x0, + 0x0, + 0x0, + }, + .NumItsIdentifiers =3D 1, + }, + .ItsIdentifier =3D 1, +}; + +AC01_RC_NODE mRcNodeTemplate =3D { + { + { + EFI_ACPI_IORT_TYPE_ROOT_COMPLEX, + sizeof (AC01_RC_NODE), + 0x1, + 0x0, + 0x1, + OFFSET_OF (AC01_RC_NODE, RcIdMapping), + }, + EFI_ACPI_IORT_MEM_ACCESS_PROP_CCA, + 0x0, + 0x0, + EFI_ACPI_IORT_MEM_ACCESS_FLAGS_CPM | + EFI_ACPI_IORT_MEM_ACCESS_FLAGS_DACS, + EFI_ACPI_IORT_ROOT_COMPLEX_ATS_UNSUPPORTED, + .PciSegmentNumber =3D 0, + .MemoryAddressSize =3D 64, + }, + __AC01_ID_MAPPING (0x0, 0xffff, 0x0, SmmuNode, 0), +}; + +AC01_SMMU_NODE mSmmuNodeTemplate =3D { + { + { + EFI_ACPI_IORT_TYPE_SMMUv3, + sizeof (AC01_SMMU_NODE), + 0x2, // Revision + 0x0, + 0x2, // Mapping Count + OFFSET_OF (AC01_SMMU_NODE, InterruptMsiMapping), + }, + .Base =3D 0, + EFI_ACPI_IORT_SMMUv3_FLAG_COHAC_OVERRIDE | EFI_ACPI_IORT_SMMUv3_FLAG_P= ROXIMITY_DOMAIN, + 0, + 0, + 0, + 0, + 0, + 0x0, + 0x0, + 0, // Proximity domain - need fill in + .DeviceIdMapping =3D 1, + }, + __AC01_ID_MAPPING (0x0, 0xffff, 0, SmmuNode, 0), + __AC01_ID_MAPPING (0x0, 0x1, 0, SmmuNode, 1), +}; + +EFI_ACPI_6_0_IO_REMAPPING_PMCG_NODE mPmcgNodeTemplate =3D { + { + EFI_ACPI_IORT_TYPE_PMCG, + sizeof (EFI_ACPI_6_0_IO_REMAPPING_PMCG_NODE), + 0x1, + 0x0, + 0x0, + 0x0, + }, + 0, // Page 0 Base. Need to be filled + 0, // GSIV. Need to be filled + 0, // Node reference. Need to be filled + 0, // Page 1 Base. Need to be filled +}; + +STATIC +VOID +ConstructIort ( + VOID *IortBuffer, + UINT32 RcCount, + UINT32 SmmuPmuAgentCount, + UINT32 HeaderCount, + INT32 *EnabledRCs + ) +{ + AC01_ROOT_COMPLEX *RootComplex; + UINT32 Idx, Idx1; + UINT32 ItsOffset[AC01_PCIE_MAX_ROOT_COMPLEX]; + UINT32 SmmuNodeOffset[AC01_PCIE_MAX_ROOT_COMPLEX]; + UINT64 *TbuPmuOffset; + UINTN MaxTbuPmu; + VOID *IortIter, *SmmuIter, *PmcgIter; + + IortIter =3D IortBuffer; + mIortHeader.Header.Length =3D HeaderCount; + mIortHeader.NumNodes =3D (3 * RcCount) + SmmuPmuAgentCount, + CopyMem (IortIter, &mIortHeader, sizeof (EFI_ACPI_6_0_IO_REMAPPING_TABLE= )); + + IortIter +=3D sizeof (EFI_ACPI_6_0_IO_REMAPPING_TABLE); + for (Idx =3D 0; Idx < RcCount; Idx++) { + ItsOffset[Idx] =3D IortIter - IortBuffer; + mItsNodeTemplate.ItsIdentifier =3D EnabledRCs[Idx]; + CopyMem (IortIter, &mItsNodeTemplate, sizeof (AC01_ITS_NODE)); + IortIter +=3D sizeof (AC01_ITS_NODE); + } + + SmmuIter =3D IortIter + RcCount * sizeof (AC01_RC_NODE); + PmcgIter =3D SmmuIter + RcCount * sizeof (AC01_SMMU_NODE); + for (Idx =3D 0; Idx < RcCount; Idx++) { + SmmuNodeOffset[Idx] =3D SmmuIter - IortBuffer; + RootComplex =3D &mRootComplexList[EnabledRCs[Idx]]; + mSmmuNodeTemplate.Node.Base =3D RootComplex->TcuBase; + mSmmuNodeTemplate.InterruptMsiMapping.OutputBase =3D EnabledRCs[Idx] <= < 16; + mSmmuNodeTemplate.InterruptMsiMapping.OutputReference =3D ItsOffset[Id= x]; + mSmmuNodeTemplate.InterruptMsiMappingSingle.OutputBase =3D EnabledRCs[= Idx] << 16; + mSmmuNodeTemplate.InterruptMsiMappingSingle.OutputReference =3D ItsOff= set[Idx]; + /* All RCs on master be assigned to node 0, while remote RCs will be a= ssigned to first remote node */ + mSmmuNodeTemplate.Node.ProximityDomain =3D 0; + if ((RootComplex->TcuBase & SLAVE_SOCKET_BASE_ADDRESS_OFFSET) !=3D 0) = { + // RootComplex on remote socket + switch (CpuGetSubNumaMode ()) { + case SUBNUMA_MODE_MONOLITHIC: + mSmmuNodeTemplate.Node.ProximityDomain +=3D MONOLITIC_NUM_OF_REGIO= N; + break; + case SUBNUMA_MODE_HEMISPHERE: + mSmmuNodeTemplate.Node.ProximityDomain +=3D HEMISPHERE_NUM_OF_REGI= ON; + break; + case SUBNUMA_MODE_QUADRANT: + mSmmuNodeTemplate.Node.ProximityDomain +=3D QUADRANT_NUM_OF_REGION= ; + break; + } + } + CopyMem (SmmuIter, &mSmmuNodeTemplate, sizeof (AC01_SMMU_NODE)); + SmmuIter +=3D sizeof (AC01_SMMU_NODE); + + if (SmmuPmuAgentCount =3D=3D 0) { + continue; + } + + // + // Add TBU PMCG nodes + // + if (RootComplex->Type =3D=3D RootComplexTypeA) { + MaxTbuPmu =3D AC01_RCA_MAX_TBU_PMU; + TbuPmuOffset =3D mRcaTbuPmuOffset; + } else { + MaxTbuPmu =3D AC01_RCB_MAX_TBU_PMU; + TbuPmuOffset =3D mRcbTbuPmuOffset; + } + + for (Idx1 =3D 0; Idx1 < MaxTbuPmu; Idx1++) { + mPmcgNodeTemplate.Base =3D RootComplex->TcuBase + TCU_TO_SMMU_OFFSET= + TbuPmuOffset[Idx1]; + mPmcgNodeTemplate.Page1Base =3D mPmcgNodeTemplate.Base + PAGE1_TO_PM= CG_OFFSET; + mPmcgNodeTemplate.NodeReference =3D SmmuNodeOffset[Idx]; + mPmcgNodeTemplate.OverflowInterruptGsiv =3D mTbuPmuIrqArray[EnabledR= Cs[Idx]] + Idx1; + CopyMem (PmcgIter, &mPmcgNodeTemplate, sizeof (mPmcgNodeTemplate)); + PmcgIter +=3D sizeof (mPmcgNodeTemplate); + } + + // + // Add TCU PMCG node + // + mPmcgNodeTemplate.Base =3D RootComplex->TcuBase + TCU_TO_SMMU_OFFSET; + mPmcgNodeTemplate.Page1Base =3D mPmcgNodeTemplate.Base + PAGE1_TO_PMCG= _OFFSET; + mPmcgNodeTemplate.NodeReference =3D SmmuNodeOffset[Idx]; + mPmcgNodeTemplate.OverflowInterruptGsiv =3D mTcuPmuIrqArray[EnabledRCs= [Idx]]; + CopyMem (PmcgIter, &mPmcgNodeTemplate, sizeof (mPmcgNodeTemplate)); + PmcgIter +=3D sizeof (mPmcgNodeTemplate); + } + + for (Idx =3D 0; Idx < RcCount; Idx++) { + mRcNodeTemplate.Node.PciSegmentNumber =3D mRootComplexList[EnabledRCs[= Idx]].Logical; + mRcNodeTemplate.RcIdMapping.OutputReference =3D SmmuNodeOffset[Idx]; + CopyMem (IortIter, &mRcNodeTemplate, sizeof (AC01_RC_NODE)); + IortIter +=3D sizeof (AC01_RC_NODE); + } +} + +EFI_STATUS +EFIAPI +AcpiInstallIort ( + VOID + ) +{ + EFI_ACPI_TABLE_PROTOCOL *AcpiTableProtocol; + EFI_STATUS Status; + INT32 EnabledRCs[AC01_PCIE_MAX_ROOT_COMPLEX]= ; + UINT32 RcCount, SmmuPmuAgentCount, TotalCount= ; + UINT8 Idx; + UINTN TableKey; + VOID *Hob; + VOID *IortBuffer; + + Hob =3D GetFirstGuidHob (&gRootComplexInfoHobGuid); + if (Hob =3D=3D NULL) { + return EFI_NOT_FOUND; + } + + mRootComplexList =3D (AC01_ROOT_COMPLEX *)GET_GUID_HOB_DATA (Hob); + + for (Idx =3D 0, RcCount =3D 0; Idx < AC01_PCIE_MAX_ROOT_COMPLEX; Idx++) = { + if (mRootComplexList[Idx].Active) { + EnabledRCs[RcCount++] =3D Idx; + } + } + EnabledRCs[RcCount] =3D -1; + + Status =3D gBS->LocateProtocol ( + &gEfiAcpiTableProtocolGuid, + NULL, + (VOID **)&AcpiTableProtocol + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "IORT: Unable to locate ACPI table entry\n")); + return Status; + } + + SmmuPmuAgentCount =3D 0; + for (Idx =3D 0; Idx < RcCount; Idx++) { + if (mRootComplexList[EnabledRCs[Idx]].Type =3D=3D RootComplexTypeA) { + SmmuPmuAgentCount +=3D AC01_RCA_MAX_TBU_PMU; + } else { + SmmuPmuAgentCount +=3D AC01_RCB_MAX_TBU_PMU; + } + // Plus 1 TCU + SmmuPmuAgentCount +=3D 1; + } + + TotalCount =3D sizeof (EFI_ACPI_6_0_IO_REMAPPING_TABLE) + + RcCount * (sizeof (AC01_ITS_NODE) + sizeof (AC01_RC_NODE) += sizeof (AC01_SMMU_NODE)) + + SmmuPmuAgentCount * sizeof (EFI_ACPI_6_0_IO_REMAPPING_PMCG_= NODE); + + IortBuffer =3D AllocateZeroPool (TotalCount); + if (IortBuffer =3D=3D NULL) { + return EFI_OUT_OF_RESOURCES; + } + + ConstructIort (IortBuffer, RcCount, SmmuPmuAgentCount, TotalCount, Enabl= edRCs); + + Status =3D AcpiTableProtocol->InstallAcpiTable ( + AcpiTableProtocol, + IortBuffer, + TotalCount, + &TableKey + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "IORT: Unable to install IORT table entry\n")); + } + + FreePool (IortBuffer); + return Status; +} diff --git a/Platform/Ampere/JadePkg/Drivers/AcpiPlatformDxe/AcpiMcfg.c b/P= latform/Ampere/JadePkg/Drivers/AcpiPlatformDxe/AcpiMcfg.c new file mode 100644 index 000000000000..0b04246f06fa --- /dev/null +++ b/Platform/Ampere/JadePkg/Drivers/AcpiPlatformDxe/AcpiMcfg.c @@ -0,0 +1,151 @@ +/** @file + + Copyright (c) 2020 - 2021, Ampere Computing LLC. All rights reserved. + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +// Required to be 1 to match the kernel quirk for ECAM +#define EFI_ACPI_MCFG_OEM_REVISION 1 + +STATIC AC01_ROOT_COMPLEX *mRootComplexList; + +#pragma pack(1) + +typedef struct +{ + UINT64 BaseAddress; + UINT16 SegGroupNum; + UINT8 StartBusNum; + UINT8 EndBusNum; + UINT32 Reserved2; +} EFI_MCFG_CONFIG_STRUCTURE; + +typedef struct +{ + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT64 Reserved1; +} EFI_MCFG_TABLE_CONFIG; + +#pragma pack() + +EFI_MCFG_TABLE_CONFIG mMcfgHeader =3D { + { + EFI_ACPI_6_1_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRES= S_DESCRIPTION_TABLE_SIGNATURE, + 0, // To be filled + 1, + 0x00, // Checksum will be updated at runtime + EFI_ACPI_OEM_ID, + EFI_ACPI_OEM_TABLE_ID, + EFI_ACPI_MCFG_OEM_REVISION, + EFI_ACPI_CREATOR_ID, + EFI_ACPI_CREATOR_REVISION + }, + 0x0000000000000000, // Reserved +}; + +EFI_MCFG_CONFIG_STRUCTURE mMcfgNodeTemplate =3D { + .BaseAddress =3D 0, + .SegGroupNum =3D 0, + .StartBusNum =3D 0, + .EndBusNum =3D 255, + .Reserved2 =3D 0, +}; + +STATIC +VOID +ConstructMcfg ( + VOID *McfgBuffer, + UINT32 McfgCount, + INT32 *EnabledRCs + ) +{ + AC01_ROOT_COMPLEX *RootComplex; + UINT32 Idx; + VOID *Iter =3D McfgBuffer; + + mMcfgHeader.Header.Length =3D McfgCount; + CopyMem (Iter, &mMcfgHeader, sizeof (EFI_MCFG_TABLE_CONFIG)); + + Iter +=3D sizeof (EFI_MCFG_TABLE_CONFIG); + for (Idx =3D 0; EnabledRCs[Idx] !=3D -1; Idx++) { + RootComplex =3D &mRootComplexList[EnabledRCs[Idx]]; + mMcfgNodeTemplate.BaseAddress =3D RootComplex->MmcfgBase; + mMcfgNodeTemplate.SegGroupNum =3D RootComplex->Logical; + CopyMem (Iter, &mMcfgNodeTemplate, sizeof (EFI_MCFG_CONFIG_STRUCTURE))= ; + Iter +=3D sizeof (EFI_MCFG_CONFIG_STRUCTURE); + } +} + +EFI_STATUS +EFIAPI +AcpiInstallMcfg ( + VOID + ) +{ + EFI_ACPI_TABLE_PROTOCOL *AcpiTableProtocol; + EFI_STATUS Status; + INT32 EnabledRCs[AC01_PCIE_MAX_ROOT_COMPLEX]; + UINT32 RcCount, McfgCount; + UINT8 Idx; + UINTN TableKey; + VOID *Hob; + VOID *McfgBuffer; + + Hob =3D GetFirstGuidHob (&gRootComplexInfoHobGuid); + if (Hob =3D=3D NULL) { + return EFI_NOT_FOUND; + } + + mRootComplexList =3D (AC01_ROOT_COMPLEX *)GET_GUID_HOB_DATA (Hob); + + for (Idx =3D 0, RcCount =3D 0; Idx < AC01_PCIE_MAX_ROOT_COMPLEX; Idx++) = { + if (mRootComplexList[Idx].Active) { + EnabledRCs[RcCount++] =3D Idx; + } + } + EnabledRCs[RcCount] =3D -1; + + Status =3D gBS->LocateProtocol ( + &gEfiAcpiTableProtocolGuid, + NULL, + (VOID **)&AcpiTableProtocol + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "MCFG: Unable to locate ACPI table entry\n")); + return Status; + } + + McfgCount =3D sizeof (EFI_MCFG_TABLE_CONFIG) + sizeof (EFI_MCFG_CONFIG_S= TRUCTURE) * RcCount; + McfgBuffer =3D AllocateZeroPool (McfgCount); + if (McfgBuffer =3D=3D NULL) { + return EFI_OUT_OF_RESOURCES; + } + + ConstructMcfg (McfgBuffer, McfgCount, EnabledRCs); + + Status =3D AcpiTableProtocol->InstallAcpiTable ( + AcpiTableProtocol, + McfgBuffer, + McfgCount, + &TableKey + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "MCFG: Unable to install MCFG table entry\n")); + } + FreePool (McfgBuffer); + return Status; +} diff --git a/Platform/Ampere/JadePkg/Drivers/AcpiPlatformDxe/AcpiPlatformDx= e.c b/Platform/Ampere/JadePkg/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.c index c4022eb056e0..117f3872a84a 100644 --- a/Platform/Ampere/JadePkg/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.c +++ b/Platform/Ampere/JadePkg/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.c @@ -93,6 +93,16 @@ InstallAcpiOnReadyToBoot ( DEBUG ((DEBUG_INFO, "Installed NFIT table\n")); } =20 + Status =3D AcpiInstallIort (); + if (!EFI_ERROR (Status)) { + DEBUG ((DEBUG_INFO, "Installed IORT table\n")); + } + + Status =3D AcpiInstallMcfg (); + if (!EFI_ERROR (Status)) { + DEBUG ((DEBUG_INFO, "Installed MCFG table\n")); + } + Status =3D AcpiPopulateBert (); if (!EFI_ERROR (Status)) { DEBUG ((DEBUG_INFO, "Populate BERT record\n")); --=20 2.17.1