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Cc: Thang Nguyen Cc: Chuong Tran Cc: Phong Vo Cc: Leif Lindholm Cc: Michael D Kinney Cc: Ard Biesheuvel Cc: Nate DeSimone Signed-off-by: Nhi Pham Reviewed-by: Leif Lindholm --- Platform/Ampere/JadePkg/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf | 2 + Silicon/Ampere/AmpereAltraPkg/Drivers/PcieInitPei/PcieInitPei.inf | 5 += ++ Platform/Ampere/JadePkg/Drivers/AcpiPlatformDxe/AcpiIort.c | 32 += +++++++++++---- Silicon/Ampere/AmpereAltraPkg/Drivers/PcieInitPei/PcieInitPei.c | 40 += +++++++++++++++++-- 4 files changed, 69 insertions(+), 10 deletions(-) diff --git a/Platform/Ampere/JadePkg/Drivers/AcpiPlatformDxe/AcpiPlatformDx= e.inf b/Platform/Ampere/JadePkg/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf index 415f795d2a54..804e761a1524 100644 --- a/Platform/Ampere/JadePkg/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf +++ b/Platform/Ampere/JadePkg/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf @@ -52,6 +52,7 @@ [LibraryClasses] UefiBootServicesTableLib UefiDriverEntryPoint UefiLib + UefiRuntimeServicesTableLib =20 [Pcd] gArmPlatformTokenSpaceGuid.PcdCoreCount @@ -70,6 +71,7 @@ [Guids] gEfiEventReadyToBootGuid gPlatformInfoHobGuid gRootComplexInfoHobGuid + gRootComplexConfigFormSetGuid =20 [Protocols] gEfiAcpiTableProtocolGuid ## ALWAYS_CONSUMED diff --git a/Silicon/Ampere/AmpereAltraPkg/Drivers/PcieInitPei/PcieInitPei.= inf b/Silicon/Ampere/AmpereAltraPkg/Drivers/PcieInitPei/PcieInitPei.inf index 17ac1672dac8..32d60bec1440 100644 --- a/Silicon/Ampere/AmpereAltraPkg/Drivers/PcieInitPei/PcieInitPei.inf +++ b/Silicon/Ampere/AmpereAltraPkg/Drivers/PcieInitPei/PcieInitPei.inf @@ -31,9 +31,14 @@ [LibraryClasses] DebugLib HobLib PeimEntryPoint + PeiServicesLib + +[Ppis] + gEfiPeiReadOnlyVariable2PpiGuid =20 [Guids] gRootComplexInfoHobGuid + gRootComplexConfigFormSetGuid gPlatformInfoHobGuid =20 [Depex] diff --git a/Platform/Ampere/JadePkg/Drivers/AcpiPlatformDxe/AcpiIort.c b/P= latform/Ampere/JadePkg/Drivers/AcpiPlatformDxe/AcpiIort.c index b8f8cfa356af..97be85c51f25 100644 --- a/Platform/Ampere/JadePkg/Drivers/AcpiPlatformDxe/AcpiIort.c +++ b/Platform/Ampere/JadePkg/Drivers/AcpiPlatformDxe/AcpiIort.c @@ -7,6 +7,7 @@ **/ =20 #include +#include #include #include #include @@ -17,6 +18,7 @@ #include #include #include +#include #include #include =20 @@ -282,8 +284,10 @@ AcpiInstallIort ( EFI_ACPI_TABLE_PROTOCOL *AcpiTableProtocol; EFI_STATUS Status; INT32 EnabledRCs[AC01_PCIE_MAX_ROOT_COMPLEX]= ; + ROOT_COMPLEX_CONFIG_VARSTORE_DATA VarStoreConfig; UINT32 RcCount, SmmuPmuAgentCount, TotalCount= ; UINT8 Idx; + UINTN BufferSize; UINTN TableKey; VOID *Hob; VOID *IortBuffer; @@ -313,14 +317,28 @@ AcpiInstallIort ( } =20 SmmuPmuAgentCount =3D 0; - for (Idx =3D 0; Idx < RcCount; Idx++) { - if (mRootComplexList[EnabledRCs[Idx]].Type =3D=3D RootComplexTypeA) { - SmmuPmuAgentCount +=3D AC01_RCA_MAX_TBU_PMU; - } else { - SmmuPmuAgentCount +=3D AC01_RCB_MAX_TBU_PMU; + + // + // Check SMMU setting + // + BufferSize =3D sizeof (VarStoreConfig); + Status =3D gRT->GetVariable ( + ROOT_COMPLEX_CONFIG_VARSTORE_NAME, + &gRootComplexConfigFormSetGuid, + NULL, + &BufferSize, + &VarStoreConfig + ); + if (!EFI_ERROR (Status) && VarStoreConfig.SmmuPmu) { + for (Idx =3D 0; Idx < RcCount; Idx++) { + if (mRootComplexList[EnabledRCs[Idx]].Type =3D=3D RootComplexTypeA) = { + SmmuPmuAgentCount +=3D AC01_RCA_MAX_TBU_PMU; + } else { + SmmuPmuAgentCount +=3D AC01_RCB_MAX_TBU_PMU; + } + // Plus 1 TCU + SmmuPmuAgentCount +=3D 1; } - // Plus 1 TCU - SmmuPmuAgentCount +=3D 1; } =20 TotalCount =3D sizeof (EFI_ACPI_6_0_IO_REMAPPING_TABLE) + diff --git a/Silicon/Ampere/AmpereAltraPkg/Drivers/PcieInitPei/PcieInitPei.= c b/Silicon/Ampere/AmpereAltraPkg/Drivers/PcieInitPei/PcieInitPei.c index cdd907d378e8..17f6112ea207 100644 --- a/Silicon/Ampere/AmpereAltraPkg/Drivers/PcieInitPei/PcieInitPei.c +++ b/Silicon/Ampere/AmpereAltraPkg/Drivers/PcieInitPei/PcieInitPei.c @@ -8,6 +8,7 @@ =20 #include =20 +#include #include #include #include @@ -15,7 +16,9 @@ #include #include #include +#include #include +#include =20 #include "RootComplexNVParam.h" =20 @@ -43,8 +46,39 @@ BuildRootComplexData ( ) { AC01_ROOT_COMPLEX *RootComplex; + BOOLEAN ConfigFound; + EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariablePpi; + EFI_STATUS Status; + ROOT_COMPLEX_CONFIG_VARSTORE_DATA RootComplexConfig; UINT8 RCIndex; UINT8 PcieIndex; + UINTN DataSize; + + ConfigFound =3D FALSE; + + // + // Get the Root Complex config from NVRAM + // + Status =3D PeiServicesLocatePpi ( + &gEfiPeiReadOnlyVariable2PpiGuid, + 0, + NULL, + (VOID **)&VariablePpi + ); + if (!EFI_ERROR (Status)) { + DataSize =3D sizeof (RootComplexConfig); + Status =3D VariablePpi->GetVariable ( + VariablePpi, + ROOT_COMPLEX_CONFIG_VARSTORE_NAME, + &gRootComplexConfigFormSetGuid, + NULL, + &DataSize, + &RootComplexConfig + ); + if (!EFI_ERROR (Status)) { + ConfigFound =3D TRUE; + } + } =20 ZeroMem (&mRootComplexList, sizeof (AC01_ROOT_COMPLEX) * AC01_PCIE_MAX_R= OOT_COMPLEX); =20 @@ -58,9 +92,9 @@ BuildRootComplexData ( =20 for (RCIndex =3D 0; RCIndex < AC01_PCIE_MAX_ROOT_COMPLEX; RCIndex++) { RootComplex =3D &mRootComplexList[RCIndex]; - RootComplex->Active =3D TRUE; - RootComplex->DevMapLow =3D 0; - RootComplex->DevMapHigh =3D 0; + RootComplex->Active =3D ConfigFound ? RootComplexConfig.RCStatus[RCInd= ex] : TRUE; + RootComplex->DevMapLow =3D ConfigFound ? RootComplexConfig.RCBifurcati= onLow[RCIndex] : 0; + RootComplex->DevMapHigh =3D ConfigFound ? RootComplexConfig.RCBifurcat= ionLow[RCIndex] : 0; RootComplex->Socket =3D RCIndex / AC01_PCIE_MAX_RCS_PER_SOCKET; RootComplex->ID =3D RCIndex % AC01_PCIE_MAX_RCS_PER_SOCKET; RootComplex->CsrBase =3D mCsrBase[RCIndex]; --=20 2.17.1