From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-pf1-f170.google.com (mail-pf1-f170.google.com [209.85.210.170]) by mx.groups.io with SMTP id smtpd.web10.993.1639692514211318164 for ; Thu, 16 Dec 2021 14:08:34 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@nuviainc-com.20210112.gappssmtp.com header.s=20210112 header.b=6lN9ManC; spf=pass (domain: nuviainc.com, ip: 209.85.210.170, mailfrom: rebecca@nuviainc.com) Received: by mail-pf1-f170.google.com with SMTP id z6so519790pfe.7 for ; Thu, 16 Dec 2021 14:08:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nuviainc-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=591SE4XbY8Z+W0Z5Cr2I4953BCT++lgXkPuvm5SFjXQ=; b=6lN9ManClHoxiLta0tz8DkgDLAMqRQqjL9xKAJnTfnPsWFBmtms1SGxFgNfcRo1Ivx nusXWrZrJPqj60JHkOeZOW/qdgha/GCWNtPND4wMKntuEJ6GG/NiFiJ70r3Ftn2yHecf eW9qA1X8LoQYql2tRpdTFFPDUF0LIFfME5KXdltJKRv/XFALEKn0HHSQQi4cJ58459Rf EtSxTN9ZKEs2215+MEbrZkND+mW4IOeVTiTh3GBNvsQM9wVcMwOX4NP7COImCayxzHcl vLkhBw9/m8nvJxwPW9mRWAuXo3V63LwvxYWVyjS8gjy/NeFRkQSaoSYtXP1e6X0JlKdo 58gA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=591SE4XbY8Z+W0Z5Cr2I4953BCT++lgXkPuvm5SFjXQ=; b=5jTMiCkaVlXm8M2JjfnoQE4k/t1E5oReUb5O83aPNpmL+65mmvnGxm6MkQFKlo5F1y ItuEaa04Qm63lrbl8Zytdutwbzoo5XE2uIn4hFWHZLNmf0YYRbohj3XfGYJeVhlrJE4w FoT/j2lBjWqQtjCEBOUeu0rE034ZiEJ0CkjuDQ0OJZ1SEZd8xr09RQM+DYPtKvLt4U1n uKjrmJt9Rn8k2EeYsNSSJWcYXQkHWougrxFzs6touX/SnX3XfnCvubEpQsWhMcU+rFSp 1sjc+z/SvjwGsPPTC3yQpqhKxu1pVEh7XWK7AzEp2r/RaPyGrzlYxnqf+7S3ry4YILvX RnWA== X-Gm-Message-State: AOAM532Ah50uQBCZOuHnTVo1VY+4gLRSkAu72K0HyfPe4GNC8CfsRl3e V5goD8tktBfpKyoNMul2tFOtaXJUy4Rlmq5B6v2ObdbijEJtPjOfCfMzFvtN2mN1rpVLsgm6wlD taVj7gaNJuq5p89VEpwT4W1inCBpRJoW3O0W0J733cWnOr+YIdOr9eWa2FOK9TkpueaE6bA== X-Google-Smtp-Source: ABdhPJzBu+v9FWHTvL/gYqZfgrqLxzMu0YqIIGId50vReDxI70O8Wgdb9rvEOcbbQjbOcL8OHwT6/Q== X-Received: by 2002:a05:6a00:188e:b0:4a4:f2fd:d7b9 with SMTP id x14-20020a056a00188e00b004a4f2fdd7b9mr15725392pfh.20.1639692513482; Thu, 16 Dec 2021 14:08:33 -0800 (PST) Return-Path: Received: from linbox.ba.nuviainc.com ([2601:681:4300:69e:9e7b:efff:fe2b:884c]) by smtp.gmail.com with ESMTPSA id 32sm5982619pgs.48.2021.12.16.14.08.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Dec 2021 14:08:33 -0800 (PST) From: "Rebecca Cran" To: devel@edk2.groups.io, Ard Biesheuvel , Samer El-Haj-Mahmoud , Leif Lindholm , Sami Mujawar , Wenyi Xie , Peng Xie , Ling Jia , Yiqi Shu , Nhi Pham , Vu Nguyen , Thang Nguyen , Chuong Tran , Pete Batard , Masami Hiramatsu , Graeme Gregory , Radoslaw Biernacki , Marcin Wojtas Cc: Rebecca Cran Subject: [PATCH v2 12/17] Silicon/AMD: Update Styx code to work with changes ARM_CORE_INFO struct Date: Thu, 16 Dec 2021 15:07:55 -0700 Message-Id: <20211216220800.9628-13-rebecca@nuviainc.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211216220800.9628-1-rebecca@nuviainc.com> References: <20211216220800.9628-1-rebecca@nuviainc.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit The ARM_CORE_INFO struct has been updated so the MPIDR is now a single field instead of separate cluster/core fields. Update the Styx code in AcpiPlatformDxe, PlatInitPei and StyxDtbLoaderLib. Signed-off-by: Rebecca Cran --- Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatform.c | 3 +-- Silicon/AMD/Styx/Drivers/PlatInitPei/PlatInitPei.c | 8 +++---- Silicon/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.c | 22 +++++++++----------- 3 files changed, 15 insertions(+), 18 deletions(-) diff --git a/Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatform.c b/Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatform.c index 7c267542db19..5f059110ff0c 100644 --- a/Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatform.c +++ b/Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatform.c @@ -100,8 +100,7 @@ EnableAvailableCores ( while (CoreCount--) { for (Index = 0; Index < MAX_CORES; Index++) { - if (GicC[Index].MPIDR == GET_MPID (ArmCoreInfoTable->ClusterId, - ArmCoreInfoTable->CoreId)) { + if (GicC[Index].MPIDR == ArmCoreInfoTable->Mpidr) { GicC[Index].Flags |= EFI_ACPI_5_1_GIC_ENABLED; break; } diff --git a/Silicon/AMD/Styx/Drivers/PlatInitPei/PlatInitPei.c b/Silicon/AMD/Styx/Drivers/PlatInitPei/PlatInitPei.c index 3f359ffbd2d8..45490aa33c5a 100644 --- a/Silicon/AMD/Styx/Drivers/PlatInitPei/PlatInitPei.c +++ b/Silicon/AMD/Styx/Drivers/PlatInitPei/PlatInitPei.c @@ -166,12 +166,12 @@ PlatInitPeiEntryPoint ( ASSERT (CpuResetInfo.CoreStatus.Status != CPU_CORE_DISABLED); ASSERT (CpuResetInfo.CoreStatus.Status != CPU_CORE_UNDEFINED); - mAmdMpCoreInfoTable[Index].ClusterId = CpuResetInfo.CoreStatus.ClusterId; - mAmdMpCoreInfoTable[Index].CoreId = CpuResetInfo.CoreStatus.CoreId; + mAmdMpCoreInfoTable[Index].Mpidr = GET_MPID (CpuResetInfo.CoreStatus.ClusterId, + CpuResetInfo.CoreStatus.CoreId); DEBUG ((EFI_D_ERROR, "Core[%d]: ClusterId = %d CoreId = %d\n", - Index, mAmdMpCoreInfoTable[Index].ClusterId, - mAmdMpCoreInfoTable[Index].CoreId)); + Index, GET_MPIDR_AFF1 (mAmdMpCoreInfoTable[Index].Mpidr), + GET_MPIDR_AFF0 (mAmdMpCoreInfoTable[Index].Mpidr))); // Next core in Table ++Index; diff --git a/Silicon/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.c b/Silicon/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.c index 75e529021d09..178fb5698504 100644 --- a/Silicon/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.c +++ b/Silicon/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.c @@ -50,7 +50,7 @@ ClusterInRange ( ) { do { - if (ClusterId == ArmCoreInfoTable[LowIndex].ClusterId) + if (ClusterId == GET_MPIDR_AFF1 (ArmCoreInfoTable[LowIndex].Mpidr)) return TRUE; } while (++LowIndex <= HighIndex); @@ -70,7 +70,7 @@ NumberOfCoresInCluster ( Cores = 0; for (Index = 0; Index < NumberOfEntries; ++Index) { - if (ClusterId == ArmCoreInfoTable[Index].ClusterId) + if (ClusterId == GET_MPIDR_AFF1 (ArmCoreInfoTable[Index].Mpidr)) ++Cores; } @@ -92,7 +92,7 @@ NumberOfClustersInTable ( Cores = NumberOfEntries; while (Cores) { ++Clusters; - ClusterId = ArmCoreInfoTable[Index].ClusterId; + ClusterId = GET_MPIDR_AFF1 (ArmCoreInfoTable[Index].Mpidr); Cores -= NumberOfCoresInCluster (ArmCoreInfoTable, NumberOfEntries, ClusterId); @@ -100,7 +100,7 @@ NumberOfClustersInTable ( do { ++Index; } while (ClusterInRange (ArmCoreInfoTable, - ArmCoreInfoTable[Index].ClusterId, + GET_MPIDR_AFF1 (ArmCoreInfoTable[Index].Mpidr), 0, Index-1)); } } @@ -402,8 +402,7 @@ PrepareFdt ( fdt_setprop_string (Fdt, CpuNode, "enable-method", "psci"); - MpId = (UINTN)GET_MPID (ArmCoreInfoTable[Index].ClusterId, - ArmCoreInfoTable[Index].CoreId); + MpId = ArmCoreInfoTable[Index].Mpidr; MpId = cpu_to_fdt64 (MpId); fdt_setprop (Fdt, CpuNode, "reg", &MpId, sizeof (MpId)); fdt_setprop (Fdt, CpuNode, "compatible", mCpuCompatible, @@ -417,7 +416,7 @@ PrepareFdt ( fdt_setprop_cell (Fdt, CpuNode, "d-cache-line-size", 64); fdt_setprop_cell (Fdt, CpuNode, "d-cache-sets", 256); fdt_setprop_cell (Fdt, CpuNode, "l2-cache", - L2Phandle[ArmCoreInfoTable[Index].ClusterId]); + L2Phandle[GET_MPIDR_AFF1 (ArmCoreInfoTable[Index].Mpidr)]); } // Create /cpu-map node @@ -435,7 +434,7 @@ PrepareFdt ( return EFI_INVALID_PARAMETER; } - ClusterId = ArmCoreInfoTable[ClusterIndex].ClusterId; + ClusterId = GET_MPIDR_AFF1 (ArmCoreInfoTable[ClusterIndex].Mpidr); CoreIndex = ClusterIndex; CoresInCluster = NumberOfCoresInCluster (ArmCoreInfoTable, ArmCoreCount, @@ -454,7 +453,7 @@ PrepareFdt ( if (CoresInCluster) { do { --CoreIndex; - } while (ClusterId != ArmCoreInfoTable[CoreIndex].ClusterId); + } while (ClusterId != GET_MPIDR_AFF1 (ArmCoreInfoTable[CoreIndex].Mpidr)); } } @@ -463,7 +462,7 @@ PrepareFdt ( do { --ClusterIndex; } while (ClusterInRange (ArmCoreInfoTable, - ArmCoreInfoTable[ClusterIndex].ClusterId, + GET_MPIDR_AFF1 (ArmCoreInfoTable[ClusterIndex].Mpidr), ClusterIndex + 1, ArmCoreCount - 1)); } @@ -481,8 +480,7 @@ PrepareFdt ( // append PMU interrupts for (Index = 0; Index < ArmCoreCount; Index++) { - MpId = (UINTN)GET_MPID (ArmCoreInfoTable[Index].ClusterId, - ArmCoreInfoTable[Index].CoreId); + MpId = (UINTN)ArmCoreInfoTable[Index].Mpidr; Status = AmdMpCoreInfoProtocol->GetPmuSpiFromMpId (MpId, &PmuInt.IntId); if (EFI_ERROR (Status)) { -- 2.31.1