[PATCH v5 2/4] Silicon/ARM/NeoverseN1Soc: Update PCDs to support multiple PCI root ports

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From: "Khasim Mohammed" <khasim.mohammed@arm.com>
To: devel@edk2.groups.io
Cc: nd@arm.com, Khasim Syed Mohammed <khasim.mohammed@arm.com>
Subject: [PATCH v5 2/4] Silicon/ARM/NeoverseN1Soc: Update PCDs to support multiple PCI root ports
Date: Wed, 22 Dec 2021 06:44:38 +0530	[thread overview]
Message-ID: <20211222011440.3687-3-khasim.mohammed@arm.com> (raw)
In-Reply-To: <20211222011440.3687-1-khasim.mohammed@arm.com>

PCD entries are updated to remove the hardcoded assignments and to
add support for multiple PCI root ports.

Signed-off-by: Khasim Syed Mohammed <khasim.mohammed@arm.com>
---
 .../AslTables/SsdtPci.asl                     |  8 +--
 .../AslTables/SsdtRemotePci.asl               |  4 +-
 .../ConfigurationManager.c                    | 24 ++++----
 .../ConfigurationManagerDxe.inf               | 18 ++++--
 Platform/ARM/N1Sdp/N1SdpPlatform.dec          |  8 ---
 Platform/ARM/N1Sdp/N1SdpPlatform.dsc          |  1 -
 .../Library/PlatformLib/PlatformLib.inf       |  1 +
 .../Library/PlatformLib/PlatformLibMem.c      |  4 +-
 Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec   | 58 +++++++++++--------
 9 files changed, 68 insertions(+), 58 deletions(-)

diff --git a/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/AslTables/SsdtPci.asl b/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/AslTables/SsdtPci.asl
index cdbd42c154..9922673d0d 100644
--- a/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/AslTables/SsdtPci.asl
+++ b/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/AslTables/SsdtPci.asl
@@ -80,8 +80,8 @@ DefinitionBlock("SsdtPci.aml", "SSDT", 1, "ARMLTD", "N1Sdp",
     Device(PCI0) {
       Name (_HID, EISAID("PNP0A08")) // PCI Express Root Bridge
       Name (_CID, EISAID("PNP0A03")) // Compatible PCI Root Bridge
-      Name (_SEG, Zero)              // PCI Segment Group number
-      Name (_BBN, Zero)              // PCI Base Bus Number
+      Name (_SEG, FixedPcdGet32 (PcdPcieSegmentNumber)) // Segment Number
+      Name (_BBN, FixedPcdGet32 (PcdPcieBusBaseNumber)) // Bus Base Number
       Name (_CCA, 1)                 // Cache Coherency Attribute
 
       // Root Complex 0
@@ -166,8 +166,8 @@ DefinitionBlock("SsdtPci.aml", "SSDT", 1, "ARMLTD", "N1Sdp",
     Device(PCI1) {
       Name (_HID, EISAID("PNP0A08")) // PCI Express Root Bridge
       Name (_CID, EISAID("PNP0A03")) // Compatible PCI Root Bridge
-      Name (_SEG, 1)                 // PCI Segment Group number
-      Name (_BBN, Zero)              // PCI Base Bus Number
+      Name (_SEG, FixedPcdGet32 (PcdCcixSegmentNumber)) // Segment Number
+      Name (_BBN, FixedPcdGet32 (PcdCcixBusBaseNumber)) // Bus Base Number
       Name (_CCA, 1)                 // Cache Coherency Attribute
 
     // Root Complex 1
diff --git a/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/AslTables/SsdtRemotePci.asl b/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/AslTables/SsdtRemotePci.asl
index b6bec7c106..4c6e0c762f 100644
--- a/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/AslTables/SsdtRemotePci.asl
+++ b/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/AslTables/SsdtRemotePci.asl
@@ -76,8 +76,8 @@ DefinitionBlock("SsdtRemotePci.aml", "SSDT", 1, "ARMLTD", "N1Sdp",
       Device(PCI2) {
       Name (_HID, EISAID("PNP0A08")) // PCI Express Root Bridge
       Name (_CID, EISAID("PNP0A03")) // Compatible PCI Root Bridge
-      Name (_SEG, 2)                 // PCI Segment Group number
-      Name (_BBN, Zero)              // PCI Base Bus Number
+      Name (_SEG, FixedPcdGet32 (PcdRemotePcieSegmentNumber)) // Segment Number
+      Name (_BBN, FixedPcdGet32 (PcdRemotePcieBusBaseNumber)) // BusBase Number
       Name (_CCA, 1)                 // Cache Coherency Attribute
 
       // Remote Root Complex 0
diff --git a/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c b/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c
index 9c91372c11..f50623ae3f 100644
--- a/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c
+++ b/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c
@@ -1047,24 +1047,24 @@ EDKII_PLATFORM_REPOSITORY_INFO N1sdpRepositoryInfo = {
   {
     // PCIe ECAM
     {
-      0x70000000,      // Base Address
-      0x0,             // Segment Group Number
-      0x0,             // Start Bus Number
-      17               // End Bus Number
+      FixedPcdGet64 (PcdPcieExpressBaseAddress),   // Base Address
+      FixedPcdGet32 (PcdPcieSegmentNumber),        // Segment Group Number
+      FixedPcdGet32 (PcdPcieBusMin),               // Start Bus Number
+      FixedPcdGet32 (PcdPcieBusMax)                // End Bus Number
     },
     // CCIX ECAM
     {
-      0x68000000,      // Base Address
-      0x1,             // Segment Group Number
-      0x0,               // Start Bus Number
-      17               // End Bus Number
+      FixedPcdGet32 (PcdCcixExpressBaseAddress),   // Base Address
+      FixedPcdGet32 (PcdCcixSegmentNumber),        // Segment Group Number
+      FixedPcdGet32 (PcdCcixBusMin),               // Start Bus Number
+      FixedPcdGet32 (PcdCcixBusMax)                // End Bus Number
     },
     //Remote Chip PCIe ECAM
     {
-      0x40070000000,   // Base Address
-      0x2,             // Segment Group Number
-      0x0,             // Start Bus Number
-      17               // End Bus Number
+      FixedPcdGet64 (PcdRemotePcieBaseAddress),   // Base Address
+      FixedPcdGet32 (PcdRemotePcieSegmentNumber),        // Segment Group Number
+      FixedPcdGet32 (PcdRemotePcieBusMin),               // Start Bus Number
+      FixedPcdGet32 (PcdRemotePcieBusMax)                // End Bus Number
     }
   },
 
diff --git a/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerDxe.inf b/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerDxe.inf
index 027a4202ff..3a8711c6f1 100644
--- a/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerDxe.inf
+++ b/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerDxe.inf
@@ -76,8 +76,6 @@
   gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase
   gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate
 
-  gArmN1SdpTokenSpaceGuid.PcdPcieExpressBaseAddress
-
   gArmNeoverseN1SocTokenSpaceGuid.PcdExtMemorySpace
   gArmNeoverseN1SocTokenSpaceGuid.PcdDramBlock2Base
 
@@ -91,6 +89,8 @@
   gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusCount
   gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusMax
   gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusMin
+  gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusBaseNumber
+  gArmNeoverseN1SocTokenSpaceGuid.PcdPcieExpressBaseAddress
   gArmNeoverseN1SocTokenSpaceGuid.PcdPcieIoBase
   gArmNeoverseN1SocTokenSpaceGuid.PcdPcieIoMaxBase
   gArmNeoverseN1SocTokenSpaceGuid.PcdPcieIoSize
@@ -105,11 +105,13 @@
   gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio64Translation
   gArmNeoverseN1SocTokenSpaceGuid.PcdPcieRootPortConfigBaseAddress
   gArmNeoverseN1SocTokenSpaceGuid.PcdPcieRootPortConfigBaseSize
+  gArmNeoverseN1SocTokenSpaceGuid.PcdPcieSegmentNumber
 
   # CCIX
   gArmNeoverseN1SocTokenSpaceGuid.PcdCcixBusCount
   gArmNeoverseN1SocTokenSpaceGuid.PcdCcixBusMax
   gArmNeoverseN1SocTokenSpaceGuid.PcdCcixBusMin
+  gArmNeoverseN1SocTokenSpaceGuid.PcdCcixBusBaseNumber
   gArmNeoverseN1SocTokenSpaceGuid.PcdCcixExpressBaseAddress
   gArmNeoverseN1SocTokenSpaceGuid.PcdCcixIoBase
   gArmNeoverseN1SocTokenSpaceGuid.PcdCcixIoMaxBase
@@ -125,6 +127,7 @@
   gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio64Translation
   gArmNeoverseN1SocTokenSpaceGuid.PcdCcixRootPortConfigBaseAddress
   gArmNeoverseN1SocTokenSpaceGuid.PcdCcixRootPortConfigBaseSize
+  gArmNeoverseN1SocTokenSpaceGuid.PcdCcixSegmentNumber
 
   # Coresight
   gArmN1SdpTokenSpaceGuid.PcdCsComponentSize
@@ -158,9 +161,14 @@
   gArmN1SdpTokenSpaceGuid.PcdCsTpiuMaxBase
 
   # Remote PCIe
-  gArmN1SdpTokenSpaceGuid.PcdRemotePcieIoTranslation
-  gArmN1SdpTokenSpaceGuid.PcdRemotePcieMmio32Translation
-  gArmN1SdpTokenSpaceGuid.PcdRemotePcieMmio64Translation
+  gArmNeoverseN1SocTokenSpaceGuid.PcdRemotePcieBaseAddress
+  gArmNeoverseN1SocTokenSpaceGuid.PcdRemotePcieBusBaseNumber
+  gArmNeoverseN1SocTokenSpaceGuid.PcdRemotePcieBusMax
+  gArmNeoverseN1SocTokenSpaceGuid.PcdRemotePcieBusMin
+  gArmNeoverseN1SocTokenSpaceGuid.PcdRemotePcieIoTranslation
+  gArmNeoverseN1SocTokenSpaceGuid.PcdRemotePcieMmio32Translation
+  gArmNeoverseN1SocTokenSpaceGuid.PcdRemotePcieMmio64Translation
+  gArmNeoverseN1SocTokenSpaceGuid.PcdRemotePcieSegmentNumber
 
 [Depex]
   TRUE
diff --git a/Platform/ARM/N1Sdp/N1SdpPlatform.dec b/Platform/ARM/N1Sdp/N1SdpPlatform.dec
index 2ab6c20dcc..16937197b8 100644
--- a/Platform/ARM/N1Sdp/N1SdpPlatform.dec
+++ b/Platform/ARM/N1Sdp/N1SdpPlatform.dec
@@ -34,9 +34,6 @@
   gArmN1SdpTokenSpaceGuid.PcdRamDiskBase|0x88000000|UINT32|0x00000001
   gArmN1SdpTokenSpaceGuid.PcdRamDiskSize|0x18000000|UINT32|0x00000002
 
-  # PCIe
-  gArmN1SdpTokenSpaceGuid.PcdPcieExpressBaseAddress|0x70000000|UINT32|0x00000007
-
   # External memory
   gArmNeoverseN1SocTokenSpaceGuid.PcdExtMemorySpace|0|UINT64|0x00000029
 
@@ -92,8 +89,3 @@
   # unmapped reserved region results in a DECERR response.
   #
   gArmN1SdpTokenSpaceGuid.PcdCsComponentSize|0x1000|UINT32|0x00000049
-
-  # Remote Chip PCIe
-  gArmN1SdpTokenSpaceGuid.PcdRemotePcieIoTranslation|0x40075200000|UINT64|0x0000004A
-  gArmN1SdpTokenSpaceGuid.PcdRemotePcieMmio32Translation|0x40000000000|UINT64|0x0000004B
-  gArmN1SdpTokenSpaceGuid.PcdRemotePcieMmio64Translation|0x40000000000|UINT64|0x0000004C
diff --git a/Platform/ARM/N1Sdp/N1SdpPlatform.dsc b/Platform/ARM/N1Sdp/N1SdpPlatform.dsc
index 7488bdc036..cb2049966c 100644
--- a/Platform/ARM/N1Sdp/N1SdpPlatform.dsc
+++ b/Platform/ARM/N1Sdp/N1SdpPlatform.dsc
@@ -127,7 +127,6 @@
   gArmTokenSpaceGuid.PcdGicRedistributorsBase|0x300C0000
 
   # PCIe
-  gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x70000000
   gEmbeddedTokenSpaceGuid.PcdPrePiCpuIoSize|24
   gEfiMdeModulePkgTokenSpaceGuid.PcdSrIovSupport|FALSE
 
diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf
index 8e2154aadf..96e590cdd8 100644
--- a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf
+++ b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf
@@ -43,6 +43,7 @@
   gArmNeoverseN1SocTokenSpaceGuid.PcdExtMemorySpace
   gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusMax
   gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusMin
+  gArmNeoverseN1SocTokenSpaceGuid.PcdPcieExpressBaseAddress
   gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio32Base
   gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio32Size
   gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio64Base
diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c
index 1c4a445c5e..339fa07b32 100644
--- a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c
+++ b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c
@@ -115,8 +115,8 @@ ArmPlatformGetVirtualMemoryMap (
   VirtualMemoryTable[Index].Attributes      = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
 
   // PCIe ECAM Configuration Space
-  VirtualMemoryTable[++Index].PhysicalBase  = PcdGet64 (PcdPciExpressBaseAddress);
-  VirtualMemoryTable[Index].VirtualBase     = PcdGet64 (PcdPciExpressBaseAddress);
+  VirtualMemoryTable[++Index].PhysicalBase  = PcdGet64 (PcdPcieExpressBaseAddress);
+  VirtualMemoryTable[Index].VirtualBase     = PcdGet64 (PcdPcieExpressBaseAddress);
   VirtualMemoryTable[Index].Length          = (FixedPcdGet32 (PcdPcieBusMax) -
                                                FixedPcdGet32 (PcdPcieBusMin) + 1) *
                                               SIZE_1MB;
diff --git a/Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec b/Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec
index eea2d58402..d91ed28319 100644
--- a/Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec
+++ b/Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec
@@ -29,11 +29,11 @@
   gArmNeoverseN1SocTokenSpaceGuid.PcdDramBlock2Base|0|UINT64|0x00000001
 
   #PCIe
-  gArmNeoverseN1SocTokenSpaceGuid.PcdPcieRootPortConfigBaseAddress|0x60000000|UINT32|0x00000002
-  gArmNeoverseN1SocTokenSpaceGuid.PcdPcieRootPortConfigBaseSize|0x00001000|UINT32|0x00000003
-  gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusCount|18|UINT32|0x00000004
-  gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusMax|17|UINT32|0x00000005
-  gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusMin|0|UINT32|0x00000006
+  gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusCount|18|UINT32|0x00000002
+  gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusMax|17|UINT32|0x00000003
+  gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusMin|0|UINT32|0x00000004
+  gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusBaseNumber|0|UINT32|0x00000005
+  gArmNeoverseN1SocTokenSpaceGuid.PcdPcieExpressBaseAddress|0x70000000|UINT64|0x00000006
   gArmNeoverseN1SocTokenSpaceGuid.PcdPcieIoBase|0x0|UINT32|0x00000007
   gArmNeoverseN1SocTokenSpaceGuid.PcdPcieIoMaxBase|0x001FFFF|UINT32|0x00000008
   gArmNeoverseN1SocTokenSpaceGuid.PcdPcieIoSize|0x020000|UINT32|0x00000009
@@ -46,30 +46,40 @@
   gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio64MaxBase|0x28FFFFFFFF|UINT64|0x00000010
   gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio64Size|0x2000000000|UINT64|0x00000011
   gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio64Translation|0x0|UINT64|0x00000012
+  gArmNeoverseN1SocTokenSpaceGuid.PcdPcieRootPortConfigBaseAddress|0x60000000|UINT32|0x00000013
+  gArmNeoverseN1SocTokenSpaceGuid.PcdPcieRootPortConfigBaseSize|0x00001000|UINT32|0x00000014
+  gArmNeoverseN1SocTokenSpaceGuid.PcdPcieSegmentNumber|0|UINT32|0x00000015
 
   # CCIX
   gArmNeoverseN1SocTokenSpaceGuid.PcdCcixBusCount|18|UINT32|0x00000016
   gArmNeoverseN1SocTokenSpaceGuid.PcdCcixBusMax|17|UINT32|0x00000017
   gArmNeoverseN1SocTokenSpaceGuid.PcdCcixBusMin|0|UINT32|0x00000018
-  gArmNeoverseN1SocTokenSpaceGuid.PcdCcixExpressBaseAddress|0x68000000|UINT32|0x00000019
-  gArmNeoverseN1SocTokenSpaceGuid.PcdCcixIoBase|0x0|UINT32|0x0000001A
-  gArmNeoverseN1SocTokenSpaceGuid.PcdCcixIoMaxBase|0x01FFFF|UINT32|0x0000001B
-  gArmNeoverseN1SocTokenSpaceGuid.PcdCcixIoSize|0x020000|UINT32|0x0000001C
-  gArmNeoverseN1SocTokenSpaceGuid.PcdCcixIoTranslation|0x6D200000|UINT32|0x00000001D
-  gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio32Base|0x69200000|UINT32|0x0000001E
-  gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio32MaxBase|0x6D1FFFFF|UINT32|0x00000001F
-  gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio32Size|0x04000000|UINT32|0x00000020
-  gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio32Translation|0x0|UINT32|0x00000021
-  gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio64Base|0x2900000000|UINT64|0x00000022
-  gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio64MaxBase|0x48FFFFFFFF|UINT64|0x00000023
-  gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio64Size|0x2000000000|UINT64|0x00000024
-  gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio64Translation|0x0|UINT64|0x00000025
-  gArmNeoverseN1SocTokenSpaceGuid.PcdCcixRootPortConfigBaseAddress|0x62000000|UINT32|0x00000026
-  gArmNeoverseN1SocTokenSpaceGuid.PcdCcixRootPortConfigBaseSize|0x00001000|UINT32|0x00000027
+  gArmNeoverseN1SocTokenSpaceGuid.PcdCcixBusBaseNumber|0|UINT32|0x00000019
+  gArmNeoverseN1SocTokenSpaceGuid.PcdCcixExpressBaseAddress|0x68000000|UINT32|0x0000001A
+  gArmNeoverseN1SocTokenSpaceGuid.PcdCcixIoBase|0x0|UINT32|0x0000001B
+  gArmNeoverseN1SocTokenSpaceGuid.PcdCcixIoMaxBase|0x00FFFFFF|UINT32|0x0000001C
+  gArmNeoverseN1SocTokenSpaceGuid.PcdCcixIoSize|0x01000000|UINT32|0x0000001D
+  gArmNeoverseN1SocTokenSpaceGuid.PcdCcixIoTranslation|0x6D200000|UINT32|0x00000001E
+  gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio32Base|0x69200000|UINT32|0x0000001F
+  gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio32MaxBase|0x6D1FFFFF|UINT32|0x000000020
+  gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio32Size|0x04000000|UINT32|0x00000021
+  gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio32Translation|0x0|UINT32|0x00000022
+  gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio64Base|0x2900000000|UINT64|0x00000023
+  gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio64MaxBase|0x48FFFFFFFF|UINT64|0x00000024
+  gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio64Size|0x2000000000|UINT64|0x00000025
+  gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio64Translation|0x0|UINT64|0x00000026
+  gArmNeoverseN1SocTokenSpaceGuid.PcdCcixRootPortConfigBaseAddress|0x62000000|UINT32|0x00000027
+  gArmNeoverseN1SocTokenSpaceGuid.PcdCcixRootPortConfigBaseSize|0x00001000|UINT32|0x00000028
+  gArmNeoverseN1SocTokenSpaceGuid.PcdCcixSegmentNumber|1|UINT32|0x00000029
 
-  gArmNeoverseN1SocTokenSpaceGuid.PcdExtMemorySpace|0x40000000000|UINT64|0x00000029
+  gArmNeoverseN1SocTokenSpaceGuid.PcdExtMemorySpace|0x40000000000|UINT64|0x00000030
 
   # Remote Chip PCIe
-  gArmNeoverseN1SocTokenSpaceGuid.PcdRemotePcieIoTranslation|0x40075200000|UINT64|0x0000004A
-  gArmNeoverseN1SocTokenSpaceGuid.PcdRemotePcieMmio32Translation|0x40000000000|UINT64|0x0000004B
-  gArmNeoverseN1SocTokenSpaceGuid.PcdRemotePcieMmio64Translation|0x40000000000|UINT64|0x0000004C
+  gArmNeoverseN1SocTokenSpaceGuid.PcdRemotePcieBaseAddress|0x40070000000|UINT64|0x0000004A
+  gArmNeoverseN1SocTokenSpaceGuid.PcdRemotePcieBusBaseNumber|0|UINT32|0x0000004B
+  gArmNeoverseN1SocTokenSpaceGuid.PcdRemotePcieBusMax|17|UINT32|0x0000004C
+  gArmNeoverseN1SocTokenSpaceGuid.PcdRemotePcieBusMin|0|UINT32|0x0000004D
+  gArmNeoverseN1SocTokenSpaceGuid.PcdRemotePcieIoTranslation|0x40075200000|UINT64|0x0000004E
+  gArmNeoverseN1SocTokenSpaceGuid.PcdRemotePcieMmio32Translation|0x40000000000|UINT64|0x0000004F
+  gArmNeoverseN1SocTokenSpaceGuid.PcdRemotePcieMmio64Translation|0x40000000000|UINT64|0x00000050
+  gArmNeoverseN1SocTokenSpaceGuid.PcdRemotePcieSegmentNumber|2|UINT32|0x00000051
-- 
2.17.1

next prev parent reply	other threads:[~2021-12-22  1:16 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-12-22  1:14 [PATCH v5 0/4] Enable CCIX port as PCIe root host on N1SDP Khasim Mohammed
2021-12-22  1:14 ` [PATCH v5 1/4] Silicon/ARM/NeoverseN1Soc: Port PCI Segment Library Khasim Mohammed
2021-12-22  8:52   ` [edk2-devel] " PierreGondois
2022-01-19 15:01   ` Sami Mujawar
2021-12-22  1:14 ` Khasim Mohammed [this message]
2021-12-22  8:52   ` [edk2-devel] [PATCH v5 2/4] Silicon/ARM/NeoverseN1Soc: Update PCDs to support multiple PCI root ports PierreGondois
2022-01-19 15:01   ` Sami Mujawar
2021-12-22  1:14 ` [PATCH v5 3/4] Silicon/ARM/NeoverseN1Soc: Add CCIX root complex support Khasim Mohammed
2021-12-22  8:52   ` [edk2-devel] " PierreGondois
2022-01-19 15:02   ` Sami Mujawar
2021-12-22  1:14 ` [PATCH v5 4/4] Silicon/ARM/NeoverseN1Soc: Remove PciExpressLib use PciSegmentLib instead Khasim Mohammed
2021-12-22  8:51   ` [edk2-devel] " PierreGondois
2022-01-19 15:02   ` Sami Mujawar

find likely ancestor, descendant, or conflicting patches for this message:
( dfblob:cdbd42c15 dfblob:9922673d0 dfblob:b6bec7c10 dfblob:4c6e0c762
dfblob:9c91372c1 dfblob:f50623ae3 dfblob:027a4202f dfblob:3a8711c6f
dfblob:2ab6c20dc dfblob:16937197b dfblob:7488bdc03 dfblob:cb2049966
dfblob:8e2154aad dfblob:96e590cdd dfblob:1c4a445c5 dfblob:339fa07b3
dfblob:eea2d5840 dfblob:d91ed2831 )
 OR (
bs:"[PATCH v5 2/4] Silicon/ARM/NeoverseN1Soc: Update PCDs to support multiple PCI root ports" )
	(help)

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