* [PATCH v5 0/4] Enable CCIX port as PCIe root host on N1SDP
@ 2021-12-22 1:14 Khasim Mohammed
2021-12-22 1:14 ` [PATCH v5 1/4] Silicon/ARM/NeoverseN1Soc: Port PCI Segment Library Khasim Mohammed
` (3 more replies)
0 siblings, 4 replies; 13+ messages in thread
From: Khasim Mohammed @ 2021-12-22 1:14 UTC (permalink / raw)
To: devel; +Cc: nd, Khasim Syed Mohammed
The patch series removes PciExpressLib and enables CCIX port
as PCIe root on N1SDP.
V5:
- Split the CCIX patch, separate PCD updates and CCIX root port enablement.
- Use GET_SEG_ macro for segment detection and update logic accordingly.
V4:
- Remove PciExpressLib and use PciSegmentLib instead. More detailed explanation
is included in the patch.
V3:
- The conditional logic in GetPciExpressAddress is made simple.
- Removed few more PCD entries that were unused.
- Removed hardcoded entries.
V2:
- Removed few PCDs entries that were not used.
- Migrated to latest version edk2-platform and validated the patches.
V1:
- The PciExpressLib is updated to validate the PCIe addresses
and introducing corresponding PCD entries.
- A custom PCI Segment library is adapted from SynQuacerPciSegmentLib
and ported for N1Sdp.
- The root complex node info in PciHostBridge library is updated to
include the CCIX port information.
The changes can be seen at:
https://github.com/khasim/edk2-platforms-n1sdp/tree/n1sdp-ccix-root
Khasim Syed Mohammed (4):
Silicon/ARM/NeoverseN1Soc: Port PCI Segment Library
Silicon/ARM/NeoverseN1Soc: Update PCDs to support multiple PCI root ports
Silicon/ARM/NeoverseN1Soc: Add CCIX root complex support
Silicon/ARM/NeoverseN1Soc: Remove PciExpressLib use PciSegmentLib instead
.../AslTables/SsdtPci.asl | 8 +-
.../AslTables/SsdtRemotePci.asl | 4 +-
.../ConfigurationManager.c | 24 +-
.../ConfigurationManagerDxe.inf | 18 +-
Platform/ARM/N1Sdp/N1SdpPlatform.dec | 8 -
Platform/ARM/N1Sdp/N1SdpPlatform.dsc | 5 +-
.../PciExpressLib.c | 1589 ----------------
.../PciExpressLib.inf | 56 -
.../PciHostBridgeLib/PciHostBridgeLib.c | 71 +-
.../PciHostBridgeLib/PciHostBridgeLib.inf | 11 +-
.../Library/PciSegmentLib/PciSegmentLib.c | 1602 +++++++++++++++++
.../Library/PciSegmentLib/PciSegmentLib.inf | 38 +
.../Library/PlatformLib/PlatformLib.inf | 1 +
.../Library/PlatformLib/PlatformLibMem.c | 4 +-
Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec | 58 +-
15 files changed, 1785 insertions(+), 1712 deletions(-)
delete mode 100644 Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciExpressLib/PciExpressLib.c
delete mode 100644 Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciExpressLib/PciExpressLib.inf
create mode 100644 Silicon/ARM/NeoverseN1Soc/Library/PciSegmentLib/PciSegmentLib.c
create mode 100644 Silicon/ARM/NeoverseN1Soc/Library/PciSegmentLib/PciSegmentLib.inf
--
2.17.1
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH v5 1/4] Silicon/ARM/NeoverseN1Soc: Port PCI Segment Library
2021-12-22 1:14 [PATCH v5 0/4] Enable CCIX port as PCIe root host on N1SDP Khasim Mohammed
@ 2021-12-22 1:14 ` Khasim Mohammed
2021-12-22 8:52 ` [edk2-devel] " PierreGondois
2022-01-19 15:01 ` Sami Mujawar
2021-12-22 1:14 ` [PATCH v5 2/4] Silicon/ARM/NeoverseN1Soc: Update PCDs to support multiple PCI root ports Khasim Mohammed
` (2 subsequent siblings)
3 siblings, 2 replies; 13+ messages in thread
From: Khasim Mohammed @ 2021-12-22 1:14 UTC (permalink / raw)
To: devel; +Cc: nd, Khasim Syed Mohammed
The BasePCISegment Library in MdePkg doesn't allow configuring
multiple segments required for PCIe and CCIX root port
enumeration. Therefore, a custom PCI Segment library is adapted
from SynQuacerPciSegmentLib and ported for N1Sdp.
In addition to this, the hardware has few other limitations which affects
the access to the PCIe root port:
1. ECAM space is not contiguous, root port ECAM (BDF = 0:0:0) is isolated
from rest of the downstream hierarchy ECAM space.
2. Root port ECAM space is not capable of 8bit/16bit writes.
3. A slave error is generated when host accesses the configuration
space of non-available device or unimplemented function on a
given bus.
The description of the workarounds included for these limitations can
be found in the corresponding files of this patch.
Signed-off-by: Khasim Syed Mohammed <khasim.mohammed@arm.com>
---
.../Library/PciSegmentLib/PciSegmentLib.c | 1602 +++++++++++++++++
.../Library/PciSegmentLib/PciSegmentLib.inf | 38 +
2 files changed, 1640 insertions(+)
create mode 100644 Silicon/ARM/NeoverseN1Soc/Library/PciSegmentLib/PciSegmentLib.c
create mode 100644 Silicon/ARM/NeoverseN1Soc/Library/PciSegmentLib/PciSegmentLib.inf
diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PciSegmentLib/PciSegmentLib.c b/Silicon/ARM/NeoverseN1Soc/Library/PciSegmentLib/PciSegmentLib.c
new file mode 100644
index 0000000000..a39a414044
--- /dev/null
+++ b/Silicon/ARM/NeoverseN1Soc/Library/PciSegmentLib/PciSegmentLib.c
@@ -0,0 +1,1602 @@
+/** @file
+ PCI Segment Library for N1SDP SoC with multiple RCs
+
+ Having two distinct root complexes is not supported by the standard
+ set of PciLib/PciExpressLib/PciSegmentLib, this PciSegmentLib
+ reimplements the functionality to support multiple root ports on
+ different segment numbers.
+
+ On the NeoverseN1Soc, a slave error is generated when host accesses the
+ configuration space of non-available device or unimplemented function on a
+ given bus. So this library introduces a workaround using IsBdfValid(),
+ to return 0xFFFFFFFF for all such access.
+
+ In addition to this, the hardware has two other limitations which affect
+ access to the PCIe root port:
+ 1. ECAM space is not contiguous, root port ECAM (BDF = 0:0:0) is isolated
+ from rest of the downstream hierarchy ECAM space.
+ 2. Root port ECAM space is not capable of 8bit/16bit writes.
+ The description of the workarounds included for these limitations can
+ be found in the comments below.
+
+ Copyright (c) 2007 - 2012, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2021, ARM Limited. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Base.h>
+
+#include <Library/BaseLib.h>
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Library/PcdLib.h>
+#include <Library/PciSegmentLib.h>
+#include <NeoverseN1Soc.h>
+
+typedef enum {
+ PciCfgWidthUint8 = 0,
+ PciCfgWidthUint16,
+ PciCfgWidthUint32,
+ PciCfgWidthMax
+} PCI_CFG_WIDTH;
+
+/**
+ Assert the validity of a PCI Segment address.
+ A valid PCI Segment address should not contain 1's in bits 28..31 and 48..63
+
+ @param A The address to validate.
+ @param M Additional bits to assert to be zero.
+**/
+#define ASSERT_INVALID_PCI_SEGMENT_ADDRESS(A,M) \
+ ASSERT (((A) & (0xffff0000f0000000ULL | (M))) == 0)
+
+#define BUS_OFFSET 20
+#define DEV_OFFSET 15
+#define FUNC_OFFSET 12
+#define REG_OFFSET 4096
+
+#define EFI_PCIE_ADDRESS(bus, dev, func, reg) \
+ (UINT64) ( \
+ (((UINTN) bus) << BUS_OFFSET) | \
+ (((UINTN) dev) << DEV_OFFSET) | \
+ (((UINTN) func) << FUNC_OFFSET) | \
+ (((UINTN) (reg)) < REG_OFFSET ? \
+ ((UINTN) (reg)) : (UINT64) (LShiftU64 ((UINT64) (reg), 32))))
+
+#define GET_PCIE_BASE_ADDRESS(Address) (Address & 0xF8000000)
+
+/* Root port Entry, BDF Entries Count */
+#define BDF_TABLE_ENTRY_SIZE 4
+#define BDF_TABLE_HEADER_COUNT 2
+#define BDF_TABLE_HEADER_SIZE 8
+
+/* BDF table offsets for PCIe */
+#define PCIE_BDF_TABLE_OFFSET 0
+#define CCIX_BDF_TABLE_OFFSET (16 * 1024)
+
+#define GET_BUS_NUM(Address) (((Address) >> 20) & 0x7F)
+#define GET_DEV_NUM(Address) (((Address) >> 15) & 0x1F)
+#define GET_FUNC_NUM(Address) (((Address) >> 12) & 0x07)
+#define GET_REG_NUM(Address) ((Address) & 0xFFF)
+#define GET_SEG_NUM(Address) (((Address) >> 32) & 0xFFFF)
+
+CONST STATIC UINTN mDummyConfigData = 0xFFFFFFFF;
+
+/**
+ Check if the requested PCI address is a valid BDF address.
+
+ SCP performs the initial bus scan and prepares a table of valid BDF addresses
+ and shares them through non-trusted SRAM. This function validates if the PCI
+ address from any PCI request falls within the table of valid entries. If not,
+ this function will return 0xFFFFFFFF. This is a workaround to avoid bus fault
+ that happens when accessing unavailable PCI device due to RTL bug.
+
+ @param Address The address that encodes the PCI Bus, Device, Function and
+ Register.
+
+ @return The base address of PCI Express.
+
+**/
+STATIC
+UINTN
+IsBdfValid (
+ IN UINTN Address
+ )
+{
+ UINT16 Segment;
+ UINTN BdfCount;
+ UINTN BdfValue;
+ UINTN Count;
+ UINTN TableBase;
+ UINTN PciAddress;
+
+ Segment = GET_SEG_NUM (Address);
+ ASSERT ((Segment == 0) || (Segment == 1));
+
+ // Keep the Bus, Device, Function bits. Clear the rest.
+ PciAddress = Address & 0xFFFF000;
+
+ if (Segment == 0) {
+ TableBase = NEOVERSEN1SOC_NON_SECURE_SRAM_BASE + PCIE_BDF_TABLE_OFFSET;
+ } else {
+ TableBase = NEOVERSEN1SOC_NON_SECURE_SRAM_BASE + CCIX_BDF_TABLE_OFFSET;
+ }
+
+ BdfCount = MmioRead32 (TableBase + BDF_TABLE_ENTRY_SIZE);
+
+ /* Start from the second entry */
+ for (Count = BDF_TABLE_HEADER_COUNT;
+ Count < (BdfCount + BDF_TABLE_HEADER_COUNT);
+ Count++) {
+ BdfValue = MmioRead32 (TableBase + (Count * BDF_TABLE_ENTRY_SIZE));
+ if (BdfValue == PciAddress)
+ break;
+ }
+
+ if (Count == (BdfCount + BDF_TABLE_HEADER_COUNT)) {
+ return mDummyConfigData;
+ } else {
+ return PciAddress;
+ }
+}
+
+/**
+ Get the physical address of a configuration space register.
+
+ Implement a workaround to avoid generation of slave errors from the bus. That
+ is, retrieve the PCI Express Base Address via a PCD entry, add the incomming
+ address with that base address and check whether this converted address
+ points to a accessible BDF. If it is not accessible, return the address
+ of a dummy location so that a read from it does not cause a slave error.
+
+ In addition to this, implement a workaround for accessing the root port's
+ configuration space. The root port configuration space is not contiguous
+ with the rest of the downstream hierarchy configuration space. So determine
+ whether the specified address is for the root port and use a different base
+ address for it.
+
+ @param Address The address that encodes the PCI Bus, Device, Function and
+ Register.
+
+ @return Physical address of the configuration register that corresponds to the
+ PCI configuration register specified by input parameter 'Address'.
+
+**/
+STATIC
+VOID*
+GetPciExpressAddress (
+ IN UINTN Address
+ )
+{
+ BOOLEAN CheckRootPort;
+ UINT16 Segment;
+ UINT8 Bus;
+ UINT8 Device;
+ UINT8 Function;
+ UINT16 Register;
+ UINTN ConfigAddress;
+
+ Segment = GET_SEG_NUM (Address);
+ ASSERT ((Segment == 0) || (Segment == 1));
+
+ Bus = GET_BUS_NUM (Address);
+ Device = GET_DEV_NUM (Address);
+ Function = GET_FUNC_NUM (Address);
+ Register = GET_REG_NUM (Address);
+
+
+ CheckRootPort = (BOOLEAN) (Bus == 0) && (Device == 0) && (Function == 0);
+
+ if (CheckRootPort == FALSE) {
+ if (IsBdfValid (Address) == mDummyConfigData) {
+ return (VOID*) &mDummyConfigData;
+ }
+ }
+
+ if (Segment == 0) {
+ if (CheckRootPort == TRUE) {
+ ConfigAddress = (UINTN) PcdGet32 (PcdPcieRootPortConfigBaseAddress);
+ } else {
+ ConfigAddress = (UINTN) PcdGet64 (PcdPcieExpressBaseAddress);
+ }
+ } else {
+ if (CheckRootPort == TRUE) {
+ ConfigAddress = (UINTN) PcdGet32 (PcdCcixRootPortConfigBaseAddress);
+ } else {
+ ConfigAddress = (UINTN) PcdGet32 (PcdCcixExpressBaseAddress);
+ }
+ }
+
+ ConfigAddress += EFI_PCIE_ADDRESS (Bus, Device, Function, Register);
+ return (VOID *)ConfigAddress;
+}
+
+/**
+ Internal worker function to read a PCI configuration register.
+
+ @param Address The address that encodes the PCI Bus, Device, Function
+ and Register.
+ @param Width The width of data to read
+
+ @return The value read from the PCI configuration register.
+**/
+STATIC
+UINT32
+PciSegmentLibReadWorker (
+ IN UINT64 Address,
+ IN PCI_CFG_WIDTH Width
+ )
+{
+ UINTN PciAddress;
+
+ PciAddress = (UINTN) GetPciExpressAddress ((UINTN) Address);
+
+ switch (Width) {
+ case PciCfgWidthUint8:
+ return MmioRead8 (PciAddress);
+ case PciCfgWidthUint16:
+ return MmioRead16 (PciAddress);
+ case PciCfgWidthUint32:
+ return MmioRead32 (PciAddress);
+ default:
+ ASSERT (FALSE);
+ }
+
+ return 0;
+}
+
+/**
+ Internal worker function to write to a PCI configuration register.
+
+ @param Address The address that encodes the PCI Bus, Device, Function
+ and Register.
+ @param Width The width of data to write
+ @param Data The value to write.
+
+ @return The value written to the PCI configuration register.
+**/
+STATIC
+UINT32
+PciSegmentLibWriteWorker (
+ IN UINT64 Address,
+ IN PCI_CFG_WIDTH Width,
+ IN UINT32 Data
+ )
+{
+ UINT8 Offset;
+ UINT32 WData;
+ UINT64 AlignedAddress;
+ BOOLEAN CheckRootPort;
+
+ CheckRootPort = (GET_BUS_NUM (Address) == 0) &&
+ (GET_DEV_NUM (Address) == 0) &&
+ (GET_FUNC_NUM (Address) == 0);
+
+ // 8-bit and 16-bit writes to root port config space is not supported due to
+ // a hardware limitation. As a workaround, perform a read-update-write
+ // sequence on the whole 32-bit word of the root port config register such
+ // that only the specified 8-bits of that word are updated.
+
+ switch (Width) {
+ case PciCfgWidthUint8:
+ if (CheckRootPort == TRUE) {
+ Offset = Address & 0x3;
+ AlignedAddress = Address & ~(0x3);
+ WData = MmioRead32 ((UINTN) GetPciExpressAddress (AlignedAddress));
+ WData &= ~(0xFF << (8 * Offset));
+ WData |= (Data << (8 * Offset));
+ MmioWrite32 ((UINTN) GetPciExpressAddress (AlignedAddress), WData);
+ return Data;
+ } else {
+ MmioWrite8 ((UINTN) GetPciExpressAddress (Address), Data);
+ }
+ break;
+ case PciCfgWidthUint16:
+ if (CheckRootPort == TRUE) {
+ Offset = Address & 0x3;
+ AlignedAddress = Address & ~(0x3);
+ WData = MmioRead32 ((UINTN) GetPciExpressAddress (AlignedAddress));
+ WData &= ~(0xFFFF << (8 * Offset));
+ WData |= (Data << (8 * Offset));
+ MmioWrite32 ((UINTN) GetPciExpressAddress (AlignedAddress), WData);
+ return Data;
+ } else {
+ MmioWrite16 ((UINTN) GetPciExpressAddress (Address), Data);
+ }
+ break;
+ case PciCfgWidthUint32:
+ MmioWrite32 ((UINTN) GetPciExpressAddress (Address), Data);
+ break;
+ default:
+ ASSERT (FALSE);
+ }
+
+ return Data;
+}
+
+/**
+ Reads an 8-bit PCI configuration register.
+
+ Reads and returns the 8-bit PCI configuration register specified by Address.
+ This function must guarantee that all PCI read and write operations are
+ serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+
+ @param Address The address that encodes the PCI Segment, Bus,
+ Device, Function and Register.
+
+ @return The 8-bit PCI configuration register specified by the Address.
+**/
+UINT8
+EFIAPI
+PciSegmentRead8 (
+ IN UINT64 Address
+ )
+{
+ ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 0);
+
+ return (UINT8) PciSegmentLibReadWorker (Address, PciCfgWidthUint8);
+}
+
+/**
+ Writes an 8-bit PCI configuration register.
+
+ Writes the 8-bit Value in the PCI configuration register specified by the
+ Address. This function must guarantee that all PCI read and write operations
+ are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+
+ @param Address The address that encodes the PCI Segment, Bus,
+ Device, Function, and Register.
+ @param Value The value to write.
+
+ @return The value written to the PCI configuration register.
+**/
+UINT8
+EFIAPI
+PciSegmentWrite8 (
+ IN UINT64 Address,
+ IN UINT8 Value
+ )
+{
+ ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 0);
+
+ return (UINT8) PciSegmentLibWriteWorker (Address, PciCfgWidthUint8, Value);
+}
+
+/**
+ Performs a bitwise OR of an 8-bit PCI configuration register with
+ an 8-bit value.
+
+ Reads the 8-bit PCI configuration register specified by Address,
+ performs a bitwise OR between the read result and the value specified by
+ OrData, and writes the result to the 8-bit PCI configuration register
+ specified by Address.
+
+ The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations
+ are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+
+ @param Address The address that encodes the PCI Segment, Bus, Device,
+ Function, and Register.
+ @param OrData The value to OR with the PCI configuration register.
+
+ @return The value written to the PCI configuration register.
+**/
+UINT8
+EFIAPI
+PciSegmentOr8 (
+ IN UINT64 Address,
+ IN UINT8 OrData
+ )
+{
+ return PciSegmentWrite8 (Address,
+ (UINT8) (PciSegmentRead8 (Address) | OrData));
+}
+
+/**
+ Performs a bitwise AND of an 8-bit PCI configuration register with
+ an 8-bit value.
+
+ Reads the 8-bit PCI configuration register specified by Address,
+ performs a bitwise AND between the read result and the value specified by
+ AndData, and writes the result to the 8-bit PCI configuration register
+ specified by Address.
+
+ The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations
+ are serialized. If any reserved bits in Address are set, then ASSERT().
+
+ @param Address The address that encodes the PCI Segment, Bus, Device,
+ Function, and Register.
+ @param AndData The value to AND with the PCI configuration register.
+
+ @return The value written to the PCI configuration register.
+**/
+UINT8
+EFIAPI
+PciSegmentAnd8 (
+ IN UINT64 Address,
+ IN UINT8 AndData
+ )
+{
+ return PciSegmentWrite8 (Address,
+ (UINT8) (PciSegmentRead8 (Address) & AndData));
+}
+
+/**
+ Performs a bitwise AND of an 8-bit PCI configuration register with
+ an 8-bit value, followed by a bitwise OR with another 8-bit value.
+
+ Reads the 8-bit PCI configuration register specified by Address,
+ performs a bitwise AND between the read result and the value specified
+ by AndData, performs a bitwise OR between the result of the AND operation
+ and the value specified by OrData, and writes the result to the 8-bit
+ PCI configuration register specified by Address.
+
+ The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations
+ are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+
+ @param Address The address that encodes the PCI Segment, Bus, Device,
+ Function, and Register.
+ @param AndData The value to AND with the PCI configuration register.
+ @param OrData The value to OR with the PCI configuration register.
+
+ @return The value written to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+PciSegmentAndThenOr8 (
+ IN UINT64 Address,
+ IN UINT8 AndData,
+ IN UINT8 OrData
+ )
+{
+ return PciSegmentWrite8 (Address,
+ (UINT8) ((PciSegmentRead8 (Address) & AndData)
+ | OrData));
+}
+
+/**
+ Reads a bit field of a PCI configuration register.
+
+ Reads the bit field in an 8-bit PCI configuration register. The bit field is
+ specified by the StartBit and the EndBit. The value of the bit field is
+ returned.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If StartBit is greater than 7, then ASSERT().
+ If EndBit is greater than 7, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+
+ @param Address The PCI configuration register to read.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..7.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..7.
+
+ @return The value of the bit field read from the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+PciSegmentBitFieldRead8 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit
+ )
+{
+ return BitFieldRead8 (PciSegmentRead8 (Address), StartBit, EndBit);
+}
+
+/**
+ Writes a bit field to a PCI configuration register.
+
+ Writes Value to the bit field of the PCI configuration register. The bit
+ field is specified by the StartBit and the EndBit. All other bits in the
+ destination PCI configuration register are preserved. The new value of the
+ 8-bit register is returned.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If StartBit is greater than 7, then ASSERT().
+ If EndBit is greater than 7, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If Value is larger than the bitmask value range specified by StartBit
+ and EndBit, then ASSERT().
+
+ @param Address The PCI configuration register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..7.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..7.
+ @param Value The new value of the bit field.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+PciSegmentBitFieldWrite8 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 Value
+ )
+{
+ return PciSegmentWrite8 (Address,
+ BitFieldWrite8 (PciSegmentRead8 (Address),
+ StartBit,
+ EndBit,
+ Value));
+}
+
+/**
+ Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and
+ writes the result back to the bit field in the 8-bit port.
+
+ Reads the 8-bit PCI configuration register specified by Address, performs a
+ bitwise OR between the read result and the value specified by
+ OrData, and writes the result to the 8-bit PCI configuration register
+ specified by Address. The value written to the PCI configuration register is
+ returned. This function must guarantee that all PCI read and write operations
+ are serialized. Extra left bits in OrData are stripped.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If StartBit is greater than 7, then ASSERT().
+ If EndBit is greater than 7, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and
+ EndBit, then ASSERT().
+
+ @param Address The PCI configuration register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..7.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..7.
+ @param OrData The value to OR with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+PciSegmentBitFieldOr8 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 OrData
+ )
+{
+ return PciSegmentWrite8 (Address,
+ BitFieldOr8 (PciSegmentRead8 (Address),
+ StartBit,
+ EndBit,
+ OrData));
+}
+
+/**
+ Reads a bit field in an 8-bit PCI configuration register, performs a bitwise
+ AND, and writes the result back to the bit field in the 8-bit register.
+
+ Reads the 8-bit PCI configuration register specified by Address, performs a
+ bitwise AND between the read result and the value specified by AndData, and
+ writes the result to the 8-bit PCI configuration register specified by
+ Address. The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations are
+ serialized. Extra left bits in AndData are stripped.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If StartBit is greater than 7, then ASSERT().
+ If EndBit is greater than 7, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and
+ EndBit, then ASSERT().
+
+ @param Address The PCI configuration register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..7.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..7.
+ @param AndData The value to AND with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+PciSegmentBitFieldAnd8 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 AndData
+ )
+{
+ return PciSegmentWrite8 (Address,
+ BitFieldAnd8 (PciSegmentRead8 (Address),
+ StartBit,
+ EndBit,
+ AndData));
+}
+
+/**
+ Reads a bit field in an 8-bit port, performs a bitwise AND followed by a
+ bitwise OR, and writes the result back to the bit field in the
+ 8-bit port.
+
+ Reads the 8-bit PCI configuration register specified by Address, performs a
+ bitwise AND followed by a bitwise OR between the read result and
+ the value specified by AndData, and writes the result to the 8-bit PCI
+ configuration register specified by Address. The value written to the PCI
+ configuration register is returned. This function must guarantee that all PCI
+ read and write operations are serialized. Extra left bits in both AndData and
+ OrData are stripped.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If StartBit is greater than 7, then ASSERT().
+ If EndBit is greater than 7, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit
+ and EndBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit
+ and EndBit, then ASSERT().
+
+ @param Address The PCI configuration register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..7.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..7.
+ @param AndData The value to AND with the PCI configuration register.
+ @param OrData The value to OR with the result of the AND operation.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+PciSegmentBitFieldAndThenOr8 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 AndData,
+ IN UINT8 OrData
+ )
+{
+ return PciSegmentWrite8 (Address,
+ BitFieldAndThenOr8 (PciSegmentRead8 (Address),
+ StartBit,
+ EndBit,
+ AndData,
+ OrData));
+}
+
+/**
+ Reads a 16-bit PCI configuration register.
+
+ Reads and returns the 16-bit PCI configuration register specified by Address.
+ This function must guarantee that all PCI read and write operations
+ are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+
+ @param Address The address that encodes the PCI Segment, Bus, Device,
+ Function, and Register.
+
+ @return The 16-bit PCI configuration register specified by Address.
+
+**/
+UINT16
+EFIAPI
+PciSegmentRead16 (
+ IN UINT64 Address
+ )
+{
+ ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 1);
+
+ return (UINT16) PciSegmentLibReadWorker (Address, PciCfgWidthUint16);
+}
+
+/**
+ Writes a 16-bit PCI configuration register.
+
+ Writes the 16-bit PCI configuration register specified by Address with the
+ value specified by Value. Value is returned.
+ This function must guarantee that all PCI read and write operations
+ are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+
+ @param Address The address that encodes the PCI Segment, Bus, Device,
+ Function, and Register.
+ @param Value The value to write.
+
+ @return The Value written is returned.
+
+**/
+UINT16
+EFIAPI
+PciSegmentWrite16 (
+ IN UINT64 Address,
+ IN UINT16 Value
+ )
+{
+ ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 1);
+
+ return (UINT16) PciSegmentLibWriteWorker (Address, PciCfgWidthUint16, Value);
+}
+
+/**
+ Performs a bitwise OR of a 16-bit PCI configuration register with
+ a 16-bit value.
+
+ Reads the 16-bit PCI configuration register specified by Address, performs a
+ bitwise OR between the read result and the value specified by
+ OrData, and writes the result to the 16-bit PCI configuration register
+ specified by Address. The value written to the PCI configuration register is
+ returned. This function must guarantee that all PCI read and write operations
+ are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+
+ @param Address The address that encodes the PCI Segment, Bus, Device,
+ Function and Register.
+ @param OrData The value to OR with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+PciSegmentOr16 (
+ IN UINT64 Address,
+ IN UINT16 OrData
+ )
+{
+ return PciSegmentWrite16 (Address,
+ (UINT16) (PciSegmentRead16 (Address) | OrData));
+}
+
+/**
+ Performs a bitwise AND of a 16-bit PCI configuration register with
+ a 16-bit value.
+
+ Reads the 16-bit PCI configuration register specified by Address,
+ performs a bitwise AND between the read result and the value specified
+ by AndData, and writes the result to the 16-bit PCI configuration register
+ specified by the Address.
+
+ The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations
+ are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+
+ @param Address The address that encodes the PCI Segment, Bus, Device,
+ Function, and Register.
+ @param AndData The value to AND with the PCI configuration register.
+
+ @return The value written to the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+PciSegmentAnd16 (
+ IN UINT64 Address,
+ IN UINT16 AndData
+ )
+{
+ return PciSegmentWrite16 (Address,
+ (UINT16) (PciSegmentRead16 (Address) & AndData));
+}
+
+/**
+ Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
+ value, followed a bitwise OR with another 16-bit value.
+
+ Reads the 16-bit PCI configuration register specified by Address,
+ performs a bitwise AND between the read result and the value specified by
+ AndData, performs a bitwise OR between the result of the AND operation and
+ the value specified by OrData, and writes the result to the 16-bit PCI
+ configuration register specified by the Address.
+
+ The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations
+ are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+
+ @param Address The address that encodes the PCI Segment, Bus, Device,
+ Function, and Register.
+ @param AndData The value to AND with the PCI configuration register.
+ @param OrData The value to OR with the PCI configuration register.
+
+ @return The value written to the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+PciSegmentAndThenOr16 (
+ IN UINT64 Address,
+ IN UINT16 AndData,
+ IN UINT16 OrData
+ )
+{
+ return PciSegmentWrite16 (Address,
+ (UINT16) ((PciSegmentRead16 (Address) & AndData)
+ | OrData));
+}
+
+/**
+ Reads a bit field of a PCI configuration register.
+
+ Reads the bit field in a 16-bit PCI configuration register. The bit field is
+ specified by the StartBit and the EndBit. The value of the bit field is
+ returned.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+ If StartBit is greater than 15, then ASSERT().
+ If EndBit is greater than 15, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+
+ @param Address The PCI configuration register to read.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..15.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..15.
+
+ @return The value of the bit field read from the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+PciSegmentBitFieldRead16 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit
+ )
+{
+ return BitFieldRead16 (PciSegmentRead16 (Address), StartBit, EndBit);
+}
+
+/**
+ Writes a bit field to a PCI configuration register.
+
+ Writes Value to the bit field of the PCI configuration register. The bit
+ field is specified by the StartBit and the EndBit. All other bits in the
+ destination PCI configuration register are preserved. The new value of the
+ 16-bit register is returned.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+ If StartBit is greater than 15, then ASSERT().
+ If EndBit is greater than 15, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If Value is larger than the bitmask value range specified by StartBit and
+ EndBit, then ASSERT().
+
+ @param Address The PCI configuration register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..15.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..15.
+ @param Value The new value of the bit field.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+PciSegmentBitFieldWrite16 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 Value
+ )
+{
+ return PciSegmentWrite16 (Address,
+ BitFieldWrite16 (PciSegmentRead16 (Address),
+ StartBit,
+ EndBit,
+ Value));
+}
+
+/**
+ Reads the 16-bit PCI configuration register specified by Address,
+ performs a bitwise OR between the read result and the value specified
+ by OrData, and writes the result to the 16-bit PCI configuration register
+ specified by the Address.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+ If StartBit is greater than 15, then ASSERT().
+ If EndBit is greater than 15, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and
+ EndBit, then ASSERT().
+
+ @param Address The PCI configuration register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..15.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..15.
+ @param OrData The value to OR with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+PciSegmentBitFieldOr16 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 OrData
+ )
+{
+ return PciSegmentWrite16 (Address,
+ BitFieldOr16 (PciSegmentRead16 (Address),
+ StartBit,
+ EndBit,
+ OrData));
+}
+
+/**
+ Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR,
+ and writes the result back to the bit field in the 16-bit port.
+
+ Reads the 16-bit PCI configuration register specified by Address,
+ performs a bitwise OR between the read result and the value specified by
+ OrData, and writes the result to the 16-bit PCI configuration register
+ specified by the Address.
+
+ The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations are
+ serialized. Extra left bits in OrData are stripped.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+ If StartBit is greater than 7, then ASSERT().
+ If EndBit is greater than 7, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and
+ EndBit, then ASSERT().
+
+ @param Address The address that encodes the PCI Segment, Bus, Device,
+ Function, and Register.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ The ordinal of the least significant bit in a byte is
+ bit 0.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ The ordinal of the most significant bit in a byte is bit 7.
+ @param AndData The value to AND with the read value from the PCI
+ configuration register.
+
+ @return The value written to the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+PciSegmentBitFieldAnd16 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 AndData
+ )
+{
+ return PciSegmentWrite16 (Address,
+ BitFieldAnd16 (PciSegmentRead16 (Address),
+ StartBit,
+ EndBit,
+ AndData));
+}
+
+/**
+ Reads a bit field in a 16-bit port, performs a bitwise AND followed by a
+ bitwise OR, and writes the result back to the bit field in the
+ 16-bit port.
+
+ Reads the 16-bit PCI configuration register specified by Address, performs a
+ bitwise AND followed by a bitwise OR between the read result and
+ the value specified by AndData, and writes the result to the 16-bit PCI
+ configuration register specified by Address. The value written to the PCI
+ configuration register is returned. This function must guarantee that all PCI
+ read and write operations are serialized. Extra left bits in both AndData and
+ OrData are stripped.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If StartBit is greater than 15, then ASSERT().
+ If EndBit is greater than 15, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and
+ EndBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and
+ EndBit, then ASSERT().
+
+ @param Address The PCI configuration register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..15.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..15.
+ @param AndData The value to AND with the PCI configuration register.
+ @param OrData The value to OR with the result of the AND operation.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+PciSegmentBitFieldAndThenOr16 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 AndData,
+ IN UINT16 OrData
+ )
+{
+ return PciSegmentWrite16 (Address,
+ BitFieldAndThenOr16 (PciSegmentRead16 (Address),
+ StartBit,
+ EndBit,
+ AndData,
+ OrData));
+}
+
+/**
+ Reads a 32-bit PCI configuration register.
+
+ Reads and returns the 32-bit PCI configuration register specified by Address.
+ This function must guarantee that all PCI read and write operations
+ are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+
+ @param Address The address that encodes the PCI Segment, Bus,
+ Device, Function and Register.
+
+ @return The 32-bit PCI configuration register specified by Address.
+
+**/
+UINT32
+EFIAPI
+PciSegmentRead32 (
+ IN UINT64 Address
+ )
+{
+ ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 3);
+
+ return PciSegmentLibReadWorker (Address, PciCfgWidthUint32);
+}
+
+/**
+ Writes a 32-bit PCI configuration register.
+
+ Writes the 32-bit PCI configuration register specified by Address with the
+ value specified by Value. Value is returned. This function must guarantee
+ that all PCI read and write operations are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+
+ @param Address The address that encodes the PCI Segment, Bus, Device,
+ Function, and Register.
+ @param Value The value to write.
+
+ @return The parameter of Value.
+
+**/
+UINT32
+EFIAPI
+PciSegmentWrite32 (
+ IN UINT64 Address,
+ IN UINT32 Value
+ )
+{
+ ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 3);
+
+ return PciSegmentLibWriteWorker (Address, PciCfgWidthUint32, Value);
+}
+
+/**
+ Performs a bitwise OR of a 32-bit PCI configuration register with a
+ 32-bit value.
+
+ Reads the 32-bit PCI configuration register specified by Address,
+ performs a bitwise OR between the read result and the value specified
+ by OrData, and writes the result to the 32-bit PCI configuration register
+ specified by Address.
+
+ The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations
+ are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+
+ @param Address The address that encodes the PCI Segment, Bus, Device,
+ Function, and Register.
+ @param OrData The value to OR with the PCI configuration register.
+
+ @return The value written to the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+PciSegmentOr32 (
+ IN UINT64 Address,
+ IN UINT32 OrData
+ )
+{
+ return PciSegmentWrite32 (Address, PciSegmentRead32 (Address) | OrData);
+}
+
+/**
+ Performs a bitwise AND of a 32-bit PCI configuration register with
+ a 32-bit value.
+
+ Reads the 32-bit PCI configuration register specified by Address,
+ performs a bitwise AND between the read result and the value specified
+ by AndData, and writes the result to the 32-bit PCI configuration register
+ specified by Address.
+ The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations
+ are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+
+ @param Address The address that encodes the PCI Segment, Bus,
+ Device, Function and Register.
+ @param AndData The value to AND with the PCI configuration register.
+
+ @return The value written to the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+PciSegmentAnd32 (
+ IN UINT64 Address,
+ IN UINT32 AndData
+ )
+{
+ return PciSegmentWrite32 (Address, PciSegmentRead32 (Address) & AndData);
+}
+
+/**
+ Performs a bitwise AND of a 32-bit PCI configuration register with
+ a 32-bit value, followed by a bitwise OR with another 32-bit value.
+
+ Reads the 32-bit PCI configuration register specified by Address,
+ performs a bitwise AND between the read result and the value specified
+ by AndData, performs a bitwise OR between the result of the AND operation
+ and the value specified by OrData, and writes the result to the 32-bit
+ PCI configuration register specified by Address.
+
+ The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations
+ are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+
+ @param Address The address that encodes the PCI Segment, Bus, Device,
+ Function and Register.
+ @param AndData The value to AND with the PCI configuration register.
+ @param OrData The value to OR with the PCI configuration register.
+
+ @return The value written to the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+PciSegmentAndThenOr32 (
+ IN UINT64 Address,
+ IN UINT32 AndData,
+ IN UINT32 OrData
+ )
+{
+ return PciSegmentWrite32 (Address,
+ (PciSegmentRead32 (Address) & AndData) | OrData);
+}
+
+/**
+ Reads a bit field of a PCI configuration register.
+
+ Reads the bit field in a 32-bit PCI configuration register. The bit field is
+ specified by the StartBit and the EndBit. The value of the bit field is
+ returned.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+ If StartBit is greater than 31, then ASSERT().
+ If EndBit is greater than 31, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+
+ @param Address The PCI configuration register to read.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..31.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..31.
+
+ @return The value of the bit field read from the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+PciSegmentBitFieldRead32 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit
+ )
+{
+ return BitFieldRead32 (PciSegmentRead32 (Address), StartBit, EndBit);
+}
+
+/**
+ Writes a bit field to a PCI configuration register.
+
+ Writes Value to the bit field of the PCI configuration register. The bit
+ field is specified by the StartBit and the EndBit. All other bits in the
+ destination PCI configuration register are preserved. The new value of the
+ 32-bit register is returned.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+ If StartBit is greater than 31, then ASSERT().
+ If EndBit is greater than 31, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If Value is larger than the bitmask value range specified by StartBit
+ and EndBit, then ASSERT().
+
+ @param Address The PCI configuration register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..31.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..31.
+ @param Value The new value of the bit field.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+PciSegmentBitFieldWrite32 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 Value
+ )
+{
+ return PciSegmentWrite32 (Address,
+ BitFieldWrite32 (PciSegmentRead32 (Address),
+ StartBit,
+ EndBit,
+ Value));
+}
+
+/**
+ Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and
+ writes the result back to the bit field in the 32-bit port.
+
+ Reads the 32-bit PCI configuration register specified by Address, performs a
+ bitwise OR between the read result and the value specified by
+ OrData, and writes the result to the 32-bit PCI configuration register
+ specified by Address. The value written to the PCI configuration register is
+ returned. This function must guarantee that all PCI read and write operations
+ are serialized. Extra left bits in OrData are stripped.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If StartBit is greater than 31, then ASSERT().
+ If EndBit is greater than 31, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and
+ EndBit, then ASSERT().
+
+ @param Address The PCI configuration register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..31.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..31.
+ @param OrData The value to OR with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+PciSegmentBitFieldOr32 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 OrData
+ )
+{
+ return PciSegmentWrite32 (Address,
+ BitFieldOr32 (PciSegmentRead32 (Address),
+ StartBit,
+ EndBit,
+ OrData));
+}
+
+/**
+ Reads a bit field in a 32-bit PCI configuration register, performs a bitwise
+ AND, and writes the result back to the bit field in the 32-bit register.
+
+ Reads the 32-bit PCI configuration register specified by Address,
+ performs a bitwise AND between the read result and the value specified
+ by AndData, and writes the result to the 32-bit PCI configuration register
+ specified by Address. The value written to the PCI configuration register
+ is returned. This function must guarantee that all PCI read and write
+ operations are serialized. Extra left bits in AndData are stripped.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+ If StartBit is greater than 31, then ASSERT().
+ If EndBit is greater than 31, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and
+ EndBit, then ASSERT().
+
+ @param Address The PCI configuration register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..31.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..31.
+ @param AndData The value to AND with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+PciSegmentBitFieldAnd32 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 AndData
+ )
+{
+ return PciSegmentWrite32 (Address,
+ BitFieldAnd32 (PciSegmentRead32 (Address),
+ StartBit,
+ EndBit,
+ AndData));
+}
+
+/**
+ Reads a bit field in a 32-bit port, performs a bitwise AND followed by a
+ bitwise OR, and writes the result back to the bit field in the
+ 32-bit port.
+
+ Reads the 32-bit PCI configuration register specified by Address, performs a
+ bitwise AND followed by a bitwise OR between the read result and
+ the value specified by AndData, and writes the result to the 32-bit PCI
+ configuration register specified by Address. The value written to the PCI
+ configuration register is returned. This function must guarantee that all PCI
+ read and write operations are serialized. Extra left bits in both AndData and
+ OrData are stripped.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If StartBit is greater than 31, then ASSERT().
+ If EndBit is greater than 31, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit
+ and EndBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit
+ and EndBit, then ASSERT().
+
+ @param Address The PCI configuration register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..31.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..31.
+ @param AndData The value to AND with the PCI configuration register.
+ @param OrData The value to OR with the result of the AND operation.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+PciSegmentBitFieldAndThenOr32 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 AndData,
+ IN UINT32 OrData
+ )
+{
+ return PciSegmentWrite32 (
+ Address,
+ BitFieldAndThenOr32 (PciSegmentRead32 (Address),
+ StartBit,
+ EndBit,
+ AndData,
+ OrData));
+}
+
+/**
+ Reads a range of PCI configuration registers into a caller supplied buffer.
+
+ Reads the range of PCI configuration registers specified by StartAddress and
+ Size into the buffer specified by Buffer. This function only allows the PCI
+ configuration registers from a single PCI function to be read. Size is
+ returned. When possible 32-bit PCI configuration read cycles are used to read
+ from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit
+ and 16-bit PCI configuration read cycles may be used at the beginning and the
+ end of the range.
+
+ If any reserved bits in StartAddress are set, then ASSERT().
+ If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
+ If Size > 0 and Buffer is NULL, then ASSERT().
+
+ @param StartAddress The starting address that encodes the PCI Segment, Bus,
+ Device, Function and Register.
+ @param Size The size in bytes of the transfer.
+ @param Buffer The pointer to a buffer receiving the data read.
+
+ @return Size
+
+**/
+UINTN
+EFIAPI
+PciSegmentReadBuffer (
+ IN UINT64 StartAddress,
+ IN UINTN Size,
+ OUT VOID *Buffer
+ )
+{
+ UINTN ReturnValue;
+
+ ASSERT_INVALID_PCI_SEGMENT_ADDRESS (StartAddress, 0);
+ ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);
+
+ if (Size == 0) {
+ return Size;
+ }
+
+ ASSERT (Buffer != NULL);
+
+ // Save Size for return
+ ReturnValue = Size;
+
+ if ((StartAddress & BIT0) != 0) {
+ // Read a byte if StartAddress is byte aligned
+ *(volatile UINT8 *)Buffer = PciSegmentRead8 (StartAddress);
+ StartAddress += sizeof (UINT8);
+ Size -= sizeof (UINT8);
+ Buffer = (UINT8*)Buffer + 1;
+ }
+
+ if (Size >= sizeof (UINT16) && (StartAddress & BIT1) != 0) {
+ // Read a word if StartAddress is word aligned
+ WriteUnaligned16 (Buffer, PciSegmentRead16 (StartAddress));
+ StartAddress += sizeof (UINT16);
+ Size -= sizeof (UINT16);
+ Buffer = (UINT16*)Buffer + 1;
+ }
+
+ while (Size >= sizeof (UINT32)) {
+ // Read as many double words as possible
+ WriteUnaligned32 (Buffer, PciSegmentRead32 (StartAddress));
+ StartAddress += sizeof (UINT32);
+ Size -= sizeof (UINT32);
+ Buffer = (UINT32*)Buffer + 1;
+ }
+
+ if (Size >= sizeof (UINT16)) {
+ // Read the last remaining word if exist
+ WriteUnaligned16 (Buffer, PciSegmentRead16 (StartAddress));
+ StartAddress += sizeof (UINT16);
+ Size -= sizeof (UINT16);
+ Buffer = (UINT16*)Buffer + 1;
+ }
+
+ if (Size >= sizeof (UINT8)) {
+ // Read the last remaining byte if exist
+ *(volatile UINT8 *)Buffer = PciSegmentRead8 (StartAddress);
+ }
+
+ return ReturnValue;
+}
+
+/**
+ Copies the data in a caller supplied buffer to a specified range of PCI
+ configuration space.
+
+ Writes the range of PCI configuration registers specified by StartAddress and
+ Size from the buffer specified by Buffer. This function only allows the PCI
+ configuration registers from a single PCI function to be written. Size is
+ returned. When possible 32-bit PCI configuration write cycles are used to
+ write from StartAdress to StartAddress + Size. Due to alignment restrictions,
+ 8-bit and 16-bit PCI configuration write cycles may be used at the beginning
+ and the end of the range.
+
+ If any reserved bits in StartAddress are set, then ASSERT().
+ If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
+ If Size > 0 and Buffer is NULL, then ASSERT().
+
+ @param StartAddress The starting address that encodes the PCI Segment, Bus,
+ Device, Function and Register.
+ @param Size The size in bytes of the transfer.
+ @param Buffer The pointer to a buffer containing the data to write.
+
+ @return The parameter of Size.
+
+**/
+UINTN
+EFIAPI
+PciSegmentWriteBuffer (
+ IN UINT64 StartAddress,
+ IN UINTN Size,
+ IN VOID *Buffer
+ )
+{
+ UINTN ReturnValue;
+
+ ASSERT_INVALID_PCI_SEGMENT_ADDRESS (StartAddress, 0);
+ ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);
+
+ if (Size == 0) {
+ return 0;
+ }
+
+ ASSERT (Buffer != NULL);
+
+ // Save Size for return
+ ReturnValue = Size;
+
+ if ((StartAddress & BIT0) != 0) {
+ // Write a byte if StartAddress is byte aligned
+ PciSegmentWrite8 (StartAddress, *(UINT8*)Buffer);
+ StartAddress += sizeof (UINT8);
+ Size -= sizeof (UINT8);
+ Buffer = (UINT8*)Buffer + 1;
+ }
+
+ if (Size >= sizeof (UINT16) && (StartAddress & BIT1) != 0) {
+ // Write a word if StartAddress is word aligned
+ PciSegmentWrite16 (StartAddress, ReadUnaligned16 (Buffer));
+ StartAddress += sizeof (UINT16);
+ Size -= sizeof (UINT16);
+ Buffer = (UINT16*)Buffer + 1;
+ }
+
+ while (Size >= sizeof (UINT32)) {
+ // Write as many double words as possible
+ PciSegmentWrite32 (StartAddress, ReadUnaligned32 (Buffer));
+ StartAddress += sizeof (UINT32);
+ Size -= sizeof (UINT32);
+ Buffer = (UINT32*)Buffer + 1;
+ }
+
+ if (Size >= sizeof (UINT16)) {
+ // Write the last remaining word if exist
+ PciSegmentWrite16 (StartAddress, ReadUnaligned16 (Buffer));
+ StartAddress += sizeof (UINT16);
+ Size -= sizeof (UINT16);
+ Buffer = (UINT16*)Buffer + 1;
+ }
+
+ if (Size >= sizeof (UINT8)) {
+ // Write the last remaining byte if exist
+ PciSegmentWrite8 (StartAddress, *(UINT8*)Buffer);
+ }
+
+ return ReturnValue;
+}
diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PciSegmentLib/PciSegmentLib.inf b/Silicon/ARM/NeoverseN1Soc/Library/PciSegmentLib/PciSegmentLib.inf
new file mode 100644
index 0000000000..1d15f74faf
--- /dev/null
+++ b/Silicon/ARM/NeoverseN1Soc/Library/PciSegmentLib/PciSegmentLib.inf
@@ -0,0 +1,38 @@
+## @file
+# PCI Segment Library for N1Sdp SoC with multiple RCs
+#
+# Copyright (c) 2007 - 2014, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2021, ARM Limited. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010019
+ BASE_NAME = PciSegmentLib
+ FILE_GUID = b5ecc9c3-6b30-4f72-8a06-889b4ea8427e
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = PciSegmentLib
+
+[Sources]
+ PciSegmentLib.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ Platform/ARM/N1Sdp/N1SdpPlatform.dec
+ Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec
+
+[LibraryClasses]
+ BaseLib
+ DebugLib
+ IoLib
+
+[FixedPcd]
+ gArmNeoverseN1SocTokenSpaceGuid.PcdCcixExpressBaseAddress
+ gArmNeoverseN1SocTokenSpaceGuid.PcdPcieExpressBaseAddress
+ gArmNeoverseN1SocTokenSpaceGuid.PcdCcixRootPortConfigBaseAddress
+ gArmNeoverseN1SocTokenSpaceGuid.PcdCcixRootPortConfigBaseSize
+ gArmNeoverseN1SocTokenSpaceGuid.PcdPcieRootPortConfigBaseAddress
+ gArmNeoverseN1SocTokenSpaceGuid.PcdPcieRootPortConfigBaseSize
--
2.17.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH v5 2/4] Silicon/ARM/NeoverseN1Soc: Update PCDs to support multiple PCI root ports
2021-12-22 1:14 [PATCH v5 0/4] Enable CCIX port as PCIe root host on N1SDP Khasim Mohammed
2021-12-22 1:14 ` [PATCH v5 1/4] Silicon/ARM/NeoverseN1Soc: Port PCI Segment Library Khasim Mohammed
@ 2021-12-22 1:14 ` Khasim Mohammed
2021-12-22 8:52 ` [edk2-devel] " PierreGondois
2022-01-19 15:01 ` Sami Mujawar
2021-12-22 1:14 ` [PATCH v5 3/4] Silicon/ARM/NeoverseN1Soc: Add CCIX root complex support Khasim Mohammed
2021-12-22 1:14 ` [PATCH v5 4/4] Silicon/ARM/NeoverseN1Soc: Remove PciExpressLib use PciSegmentLib instead Khasim Mohammed
3 siblings, 2 replies; 13+ messages in thread
From: Khasim Mohammed @ 2021-12-22 1:14 UTC (permalink / raw)
To: devel; +Cc: nd, Khasim Syed Mohammed
PCD entries are updated to remove the hardcoded assignments and to
add support for multiple PCI root ports.
Signed-off-by: Khasim Syed Mohammed <khasim.mohammed@arm.com>
---
.../AslTables/SsdtPci.asl | 8 +--
.../AslTables/SsdtRemotePci.asl | 4 +-
.../ConfigurationManager.c | 24 ++++----
.../ConfigurationManagerDxe.inf | 18 ++++--
Platform/ARM/N1Sdp/N1SdpPlatform.dec | 8 ---
Platform/ARM/N1Sdp/N1SdpPlatform.dsc | 1 -
.../Library/PlatformLib/PlatformLib.inf | 1 +
.../Library/PlatformLib/PlatformLibMem.c | 4 +-
Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec | 58 +++++++++++--------
9 files changed, 68 insertions(+), 58 deletions(-)
diff --git a/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/AslTables/SsdtPci.asl b/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/AslTables/SsdtPci.asl
index cdbd42c154..9922673d0d 100644
--- a/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/AslTables/SsdtPci.asl
+++ b/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/AslTables/SsdtPci.asl
@@ -80,8 +80,8 @@ DefinitionBlock("SsdtPci.aml", "SSDT", 1, "ARMLTD", "N1Sdp",
Device(PCI0) {
Name (_HID, EISAID("PNP0A08")) // PCI Express Root Bridge
Name (_CID, EISAID("PNP0A03")) // Compatible PCI Root Bridge
- Name (_SEG, Zero) // PCI Segment Group number
- Name (_BBN, Zero) // PCI Base Bus Number
+ Name (_SEG, FixedPcdGet32 (PcdPcieSegmentNumber)) // Segment Number
+ Name (_BBN, FixedPcdGet32 (PcdPcieBusBaseNumber)) // Bus Base Number
Name (_CCA, 1) // Cache Coherency Attribute
// Root Complex 0
@@ -166,8 +166,8 @@ DefinitionBlock("SsdtPci.aml", "SSDT", 1, "ARMLTD", "N1Sdp",
Device(PCI1) {
Name (_HID, EISAID("PNP0A08")) // PCI Express Root Bridge
Name (_CID, EISAID("PNP0A03")) // Compatible PCI Root Bridge
- Name (_SEG, 1) // PCI Segment Group number
- Name (_BBN, Zero) // PCI Base Bus Number
+ Name (_SEG, FixedPcdGet32 (PcdCcixSegmentNumber)) // Segment Number
+ Name (_BBN, FixedPcdGet32 (PcdCcixBusBaseNumber)) // Bus Base Number
Name (_CCA, 1) // Cache Coherency Attribute
// Root Complex 1
diff --git a/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/AslTables/SsdtRemotePci.asl b/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/AslTables/SsdtRemotePci.asl
index b6bec7c106..4c6e0c762f 100644
--- a/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/AslTables/SsdtRemotePci.asl
+++ b/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/AslTables/SsdtRemotePci.asl
@@ -76,8 +76,8 @@ DefinitionBlock("SsdtRemotePci.aml", "SSDT", 1, "ARMLTD", "N1Sdp",
Device(PCI2) {
Name (_HID, EISAID("PNP0A08")) // PCI Express Root Bridge
Name (_CID, EISAID("PNP0A03")) // Compatible PCI Root Bridge
- Name (_SEG, 2) // PCI Segment Group number
- Name (_BBN, Zero) // PCI Base Bus Number
+ Name (_SEG, FixedPcdGet32 (PcdRemotePcieSegmentNumber)) // Segment Number
+ Name (_BBN, FixedPcdGet32 (PcdRemotePcieBusBaseNumber)) // BusBase Number
Name (_CCA, 1) // Cache Coherency Attribute
// Remote Root Complex 0
diff --git a/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c b/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c
index 9c91372c11..f50623ae3f 100644
--- a/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c
+++ b/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c
@@ -1047,24 +1047,24 @@ EDKII_PLATFORM_REPOSITORY_INFO N1sdpRepositoryInfo = {
{
// PCIe ECAM
{
- 0x70000000, // Base Address
- 0x0, // Segment Group Number
- 0x0, // Start Bus Number
- 17 // End Bus Number
+ FixedPcdGet64 (PcdPcieExpressBaseAddress), // Base Address
+ FixedPcdGet32 (PcdPcieSegmentNumber), // Segment Group Number
+ FixedPcdGet32 (PcdPcieBusMin), // Start Bus Number
+ FixedPcdGet32 (PcdPcieBusMax) // End Bus Number
},
// CCIX ECAM
{
- 0x68000000, // Base Address
- 0x1, // Segment Group Number
- 0x0, // Start Bus Number
- 17 // End Bus Number
+ FixedPcdGet32 (PcdCcixExpressBaseAddress), // Base Address
+ FixedPcdGet32 (PcdCcixSegmentNumber), // Segment Group Number
+ FixedPcdGet32 (PcdCcixBusMin), // Start Bus Number
+ FixedPcdGet32 (PcdCcixBusMax) // End Bus Number
},
//Remote Chip PCIe ECAM
{
- 0x40070000000, // Base Address
- 0x2, // Segment Group Number
- 0x0, // Start Bus Number
- 17 // End Bus Number
+ FixedPcdGet64 (PcdRemotePcieBaseAddress), // Base Address
+ FixedPcdGet32 (PcdRemotePcieSegmentNumber), // Segment Group Number
+ FixedPcdGet32 (PcdRemotePcieBusMin), // Start Bus Number
+ FixedPcdGet32 (PcdRemotePcieBusMax) // End Bus Number
}
},
diff --git a/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerDxe.inf b/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerDxe.inf
index 027a4202ff..3a8711c6f1 100644
--- a/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerDxe.inf
+++ b/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerDxe.inf
@@ -76,8 +76,6 @@
gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase
gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate
- gArmN1SdpTokenSpaceGuid.PcdPcieExpressBaseAddress
-
gArmNeoverseN1SocTokenSpaceGuid.PcdExtMemorySpace
gArmNeoverseN1SocTokenSpaceGuid.PcdDramBlock2Base
@@ -91,6 +89,8 @@
gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusCount
gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusMax
gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusMin
+ gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusBaseNumber
+ gArmNeoverseN1SocTokenSpaceGuid.PcdPcieExpressBaseAddress
gArmNeoverseN1SocTokenSpaceGuid.PcdPcieIoBase
gArmNeoverseN1SocTokenSpaceGuid.PcdPcieIoMaxBase
gArmNeoverseN1SocTokenSpaceGuid.PcdPcieIoSize
@@ -105,11 +105,13 @@
gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio64Translation
gArmNeoverseN1SocTokenSpaceGuid.PcdPcieRootPortConfigBaseAddress
gArmNeoverseN1SocTokenSpaceGuid.PcdPcieRootPortConfigBaseSize
+ gArmNeoverseN1SocTokenSpaceGuid.PcdPcieSegmentNumber
# CCIX
gArmNeoverseN1SocTokenSpaceGuid.PcdCcixBusCount
gArmNeoverseN1SocTokenSpaceGuid.PcdCcixBusMax
gArmNeoverseN1SocTokenSpaceGuid.PcdCcixBusMin
+ gArmNeoverseN1SocTokenSpaceGuid.PcdCcixBusBaseNumber
gArmNeoverseN1SocTokenSpaceGuid.PcdCcixExpressBaseAddress
gArmNeoverseN1SocTokenSpaceGuid.PcdCcixIoBase
gArmNeoverseN1SocTokenSpaceGuid.PcdCcixIoMaxBase
@@ -125,6 +127,7 @@
gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio64Translation
gArmNeoverseN1SocTokenSpaceGuid.PcdCcixRootPortConfigBaseAddress
gArmNeoverseN1SocTokenSpaceGuid.PcdCcixRootPortConfigBaseSize
+ gArmNeoverseN1SocTokenSpaceGuid.PcdCcixSegmentNumber
# Coresight
gArmN1SdpTokenSpaceGuid.PcdCsComponentSize
@@ -158,9 +161,14 @@
gArmN1SdpTokenSpaceGuid.PcdCsTpiuMaxBase
# Remote PCIe
- gArmN1SdpTokenSpaceGuid.PcdRemotePcieIoTranslation
- gArmN1SdpTokenSpaceGuid.PcdRemotePcieMmio32Translation
- gArmN1SdpTokenSpaceGuid.PcdRemotePcieMmio64Translation
+ gArmNeoverseN1SocTokenSpaceGuid.PcdRemotePcieBaseAddress
+ gArmNeoverseN1SocTokenSpaceGuid.PcdRemotePcieBusBaseNumber
+ gArmNeoverseN1SocTokenSpaceGuid.PcdRemotePcieBusMax
+ gArmNeoverseN1SocTokenSpaceGuid.PcdRemotePcieBusMin
+ gArmNeoverseN1SocTokenSpaceGuid.PcdRemotePcieIoTranslation
+ gArmNeoverseN1SocTokenSpaceGuid.PcdRemotePcieMmio32Translation
+ gArmNeoverseN1SocTokenSpaceGuid.PcdRemotePcieMmio64Translation
+ gArmNeoverseN1SocTokenSpaceGuid.PcdRemotePcieSegmentNumber
[Depex]
TRUE
diff --git a/Platform/ARM/N1Sdp/N1SdpPlatform.dec b/Platform/ARM/N1Sdp/N1SdpPlatform.dec
index 2ab6c20dcc..16937197b8 100644
--- a/Platform/ARM/N1Sdp/N1SdpPlatform.dec
+++ b/Platform/ARM/N1Sdp/N1SdpPlatform.dec
@@ -34,9 +34,6 @@
gArmN1SdpTokenSpaceGuid.PcdRamDiskBase|0x88000000|UINT32|0x00000001
gArmN1SdpTokenSpaceGuid.PcdRamDiskSize|0x18000000|UINT32|0x00000002
- # PCIe
- gArmN1SdpTokenSpaceGuid.PcdPcieExpressBaseAddress|0x70000000|UINT32|0x00000007
-
# External memory
gArmNeoverseN1SocTokenSpaceGuid.PcdExtMemorySpace|0|UINT64|0x00000029
@@ -92,8 +89,3 @@
# unmapped reserved region results in a DECERR response.
#
gArmN1SdpTokenSpaceGuid.PcdCsComponentSize|0x1000|UINT32|0x00000049
-
- # Remote Chip PCIe
- gArmN1SdpTokenSpaceGuid.PcdRemotePcieIoTranslation|0x40075200000|UINT64|0x0000004A
- gArmN1SdpTokenSpaceGuid.PcdRemotePcieMmio32Translation|0x40000000000|UINT64|0x0000004B
- gArmN1SdpTokenSpaceGuid.PcdRemotePcieMmio64Translation|0x40000000000|UINT64|0x0000004C
diff --git a/Platform/ARM/N1Sdp/N1SdpPlatform.dsc b/Platform/ARM/N1Sdp/N1SdpPlatform.dsc
index 7488bdc036..cb2049966c 100644
--- a/Platform/ARM/N1Sdp/N1SdpPlatform.dsc
+++ b/Platform/ARM/N1Sdp/N1SdpPlatform.dsc
@@ -127,7 +127,6 @@
gArmTokenSpaceGuid.PcdGicRedistributorsBase|0x300C0000
# PCIe
- gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x70000000
gEmbeddedTokenSpaceGuid.PcdPrePiCpuIoSize|24
gEfiMdeModulePkgTokenSpaceGuid.PcdSrIovSupport|FALSE
diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf
index 8e2154aadf..96e590cdd8 100644
--- a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf
+++ b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf
@@ -43,6 +43,7 @@
gArmNeoverseN1SocTokenSpaceGuid.PcdExtMemorySpace
gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusMax
gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusMin
+ gArmNeoverseN1SocTokenSpaceGuid.PcdPcieExpressBaseAddress
gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio32Base
gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio32Size
gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio64Base
diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c
index 1c4a445c5e..339fa07b32 100644
--- a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c
+++ b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c
@@ -115,8 +115,8 @@ ArmPlatformGetVirtualMemoryMap (
VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
// PCIe ECAM Configuration Space
- VirtualMemoryTable[++Index].PhysicalBase = PcdGet64 (PcdPciExpressBaseAddress);
- VirtualMemoryTable[Index].VirtualBase = PcdGet64 (PcdPciExpressBaseAddress);
+ VirtualMemoryTable[++Index].PhysicalBase = PcdGet64 (PcdPcieExpressBaseAddress);
+ VirtualMemoryTable[Index].VirtualBase = PcdGet64 (PcdPcieExpressBaseAddress);
VirtualMemoryTable[Index].Length = (FixedPcdGet32 (PcdPcieBusMax) -
FixedPcdGet32 (PcdPcieBusMin) + 1) *
SIZE_1MB;
diff --git a/Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec b/Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec
index eea2d58402..d91ed28319 100644
--- a/Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec
+++ b/Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec
@@ -29,11 +29,11 @@
gArmNeoverseN1SocTokenSpaceGuid.PcdDramBlock2Base|0|UINT64|0x00000001
#PCIe
- gArmNeoverseN1SocTokenSpaceGuid.PcdPcieRootPortConfigBaseAddress|0x60000000|UINT32|0x00000002
- gArmNeoverseN1SocTokenSpaceGuid.PcdPcieRootPortConfigBaseSize|0x00001000|UINT32|0x00000003
- gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusCount|18|UINT32|0x00000004
- gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusMax|17|UINT32|0x00000005
- gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusMin|0|UINT32|0x00000006
+ gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusCount|18|UINT32|0x00000002
+ gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusMax|17|UINT32|0x00000003
+ gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusMin|0|UINT32|0x00000004
+ gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusBaseNumber|0|UINT32|0x00000005
+ gArmNeoverseN1SocTokenSpaceGuid.PcdPcieExpressBaseAddress|0x70000000|UINT64|0x00000006
gArmNeoverseN1SocTokenSpaceGuid.PcdPcieIoBase|0x0|UINT32|0x00000007
gArmNeoverseN1SocTokenSpaceGuid.PcdPcieIoMaxBase|0x001FFFF|UINT32|0x00000008
gArmNeoverseN1SocTokenSpaceGuid.PcdPcieIoSize|0x020000|UINT32|0x00000009
@@ -46,30 +46,40 @@
gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio64MaxBase|0x28FFFFFFFF|UINT64|0x00000010
gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio64Size|0x2000000000|UINT64|0x00000011
gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio64Translation|0x0|UINT64|0x00000012
+ gArmNeoverseN1SocTokenSpaceGuid.PcdPcieRootPortConfigBaseAddress|0x60000000|UINT32|0x00000013
+ gArmNeoverseN1SocTokenSpaceGuid.PcdPcieRootPortConfigBaseSize|0x00001000|UINT32|0x00000014
+ gArmNeoverseN1SocTokenSpaceGuid.PcdPcieSegmentNumber|0|UINT32|0x00000015
# CCIX
gArmNeoverseN1SocTokenSpaceGuid.PcdCcixBusCount|18|UINT32|0x00000016
gArmNeoverseN1SocTokenSpaceGuid.PcdCcixBusMax|17|UINT32|0x00000017
gArmNeoverseN1SocTokenSpaceGuid.PcdCcixBusMin|0|UINT32|0x00000018
- gArmNeoverseN1SocTokenSpaceGuid.PcdCcixExpressBaseAddress|0x68000000|UINT32|0x00000019
- gArmNeoverseN1SocTokenSpaceGuid.PcdCcixIoBase|0x0|UINT32|0x0000001A
- gArmNeoverseN1SocTokenSpaceGuid.PcdCcixIoMaxBase|0x01FFFF|UINT32|0x0000001B
- gArmNeoverseN1SocTokenSpaceGuid.PcdCcixIoSize|0x020000|UINT32|0x0000001C
- gArmNeoverseN1SocTokenSpaceGuid.PcdCcixIoTranslation|0x6D200000|UINT32|0x00000001D
- gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio32Base|0x69200000|UINT32|0x0000001E
- gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio32MaxBase|0x6D1FFFFF|UINT32|0x00000001F
- gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio32Size|0x04000000|UINT32|0x00000020
- gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio32Translation|0x0|UINT32|0x00000021
- gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio64Base|0x2900000000|UINT64|0x00000022
- gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio64MaxBase|0x48FFFFFFFF|UINT64|0x00000023
- gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio64Size|0x2000000000|UINT64|0x00000024
- gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio64Translation|0x0|UINT64|0x00000025
- gArmNeoverseN1SocTokenSpaceGuid.PcdCcixRootPortConfigBaseAddress|0x62000000|UINT32|0x00000026
- gArmNeoverseN1SocTokenSpaceGuid.PcdCcixRootPortConfigBaseSize|0x00001000|UINT32|0x00000027
+ gArmNeoverseN1SocTokenSpaceGuid.PcdCcixBusBaseNumber|0|UINT32|0x00000019
+ gArmNeoverseN1SocTokenSpaceGuid.PcdCcixExpressBaseAddress|0x68000000|UINT32|0x0000001A
+ gArmNeoverseN1SocTokenSpaceGuid.PcdCcixIoBase|0x0|UINT32|0x0000001B
+ gArmNeoverseN1SocTokenSpaceGuid.PcdCcixIoMaxBase|0x00FFFFFF|UINT32|0x0000001C
+ gArmNeoverseN1SocTokenSpaceGuid.PcdCcixIoSize|0x01000000|UINT32|0x0000001D
+ gArmNeoverseN1SocTokenSpaceGuid.PcdCcixIoTranslation|0x6D200000|UINT32|0x00000001E
+ gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio32Base|0x69200000|UINT32|0x0000001F
+ gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio32MaxBase|0x6D1FFFFF|UINT32|0x000000020
+ gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio32Size|0x04000000|UINT32|0x00000021
+ gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio32Translation|0x0|UINT32|0x00000022
+ gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio64Base|0x2900000000|UINT64|0x00000023
+ gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio64MaxBase|0x48FFFFFFFF|UINT64|0x00000024
+ gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio64Size|0x2000000000|UINT64|0x00000025
+ gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio64Translation|0x0|UINT64|0x00000026
+ gArmNeoverseN1SocTokenSpaceGuid.PcdCcixRootPortConfigBaseAddress|0x62000000|UINT32|0x00000027
+ gArmNeoverseN1SocTokenSpaceGuid.PcdCcixRootPortConfigBaseSize|0x00001000|UINT32|0x00000028
+ gArmNeoverseN1SocTokenSpaceGuid.PcdCcixSegmentNumber|1|UINT32|0x00000029
- gArmNeoverseN1SocTokenSpaceGuid.PcdExtMemorySpace|0x40000000000|UINT64|0x00000029
+ gArmNeoverseN1SocTokenSpaceGuid.PcdExtMemorySpace|0x40000000000|UINT64|0x00000030
# Remote Chip PCIe
- gArmNeoverseN1SocTokenSpaceGuid.PcdRemotePcieIoTranslation|0x40075200000|UINT64|0x0000004A
- gArmNeoverseN1SocTokenSpaceGuid.PcdRemotePcieMmio32Translation|0x40000000000|UINT64|0x0000004B
- gArmNeoverseN1SocTokenSpaceGuid.PcdRemotePcieMmio64Translation|0x40000000000|UINT64|0x0000004C
+ gArmNeoverseN1SocTokenSpaceGuid.PcdRemotePcieBaseAddress|0x40070000000|UINT64|0x0000004A
+ gArmNeoverseN1SocTokenSpaceGuid.PcdRemotePcieBusBaseNumber|0|UINT32|0x0000004B
+ gArmNeoverseN1SocTokenSpaceGuid.PcdRemotePcieBusMax|17|UINT32|0x0000004C
+ gArmNeoverseN1SocTokenSpaceGuid.PcdRemotePcieBusMin|0|UINT32|0x0000004D
+ gArmNeoverseN1SocTokenSpaceGuid.PcdRemotePcieIoTranslation|0x40075200000|UINT64|0x0000004E
+ gArmNeoverseN1SocTokenSpaceGuid.PcdRemotePcieMmio32Translation|0x40000000000|UINT64|0x0000004F
+ gArmNeoverseN1SocTokenSpaceGuid.PcdRemotePcieMmio64Translation|0x40000000000|UINT64|0x00000050
+ gArmNeoverseN1SocTokenSpaceGuid.PcdRemotePcieSegmentNumber|2|UINT32|0x00000051
--
2.17.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH v5 3/4] Silicon/ARM/NeoverseN1Soc: Add CCIX root complex support
2021-12-22 1:14 [PATCH v5 0/4] Enable CCIX port as PCIe root host on N1SDP Khasim Mohammed
2021-12-22 1:14 ` [PATCH v5 1/4] Silicon/ARM/NeoverseN1Soc: Port PCI Segment Library Khasim Mohammed
2021-12-22 1:14 ` [PATCH v5 2/4] Silicon/ARM/NeoverseN1Soc: Update PCDs to support multiple PCI root ports Khasim Mohammed
@ 2021-12-22 1:14 ` Khasim Mohammed
2021-12-22 8:52 ` [edk2-devel] " PierreGondois
2022-01-19 15:02 ` Sami Mujawar
2021-12-22 1:14 ` [PATCH v5 4/4] Silicon/ARM/NeoverseN1Soc: Remove PciExpressLib use PciSegmentLib instead Khasim Mohammed
3 siblings, 2 replies; 13+ messages in thread
From: Khasim Mohammed @ 2021-12-22 1:14 UTC (permalink / raw)
To: devel; +Cc: nd, Khasim Syed Mohammed
This patch enables CCIX root complex support by updating
the root complex node info in PciHostBridge library.
Signed-off-by: Khasim Syed Mohammed <khasim.mohammed@arm.com>
---
.../PciHostBridgeLib/PciHostBridgeLib.c | 71 +++++++++++++++++--
.../PciHostBridgeLib/PciHostBridgeLib.inf | 11 ++-
2 files changed, 76 insertions(+), 6 deletions(-)
diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.c b/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.c
index 9332939f63..c3a14a6c17 100644
--- a/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.c
+++ b/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.c
@@ -1,7 +1,7 @@
/** @file
* PCI Host Bridge Library instance for ARM Neoverse N1 platform
*
-* Copyright (c) 2019 - 2020, ARM Limited. All rights reserved.
+* Copyright (c) 2019 - 2021, ARM Limited. All rights reserved.<BR>
*
* SPDX-License-Identifier: BSD-2-Clause-Patent
*
@@ -16,6 +16,8 @@
#include <Protocol/PciHostBridgeResourceAllocation.h>
#include <Protocol/PciRootBridgeIo.h>
+#define ROOT_COMPLEX_NUM 2
+
GLOBAL_REMOVE_IF_UNREFERENCED
STATIC CHAR16 CONST * CONST mPciHostBridgeLibAcpiAddressSpaceTypeStr[] = {
L"Mem", L"I/O", L"Bus"
@@ -28,7 +30,7 @@ typedef struct {
} EFI_PCI_ROOT_BRIDGE_DEVICE_PATH;
#pragma pack ()
-STATIC EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath[] = {
+STATIC EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath[ROOT_COMPLEX_NUM] = {
// PCIe
{
{
@@ -51,10 +53,33 @@ STATIC EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath[] = {
0
}
}
- }
+ },
+ //CCIX
+ {
+ {
+ {
+ ACPI_DEVICE_PATH,
+ ACPI_DP,
+ {
+ (UINT8)sizeof (ACPI_HID_DEVICE_PATH),
+ (UINT8)(sizeof (ACPI_HID_DEVICE_PATH) >> 8)
+ }
+ },
+ EISA_PNP_ID(0x0A09), // CCIX
+ 0
+ },
+ {
+ END_DEVICE_PATH_TYPE,
+ END_ENTIRE_DEVICE_PATH_SUBTYPE,
+ {
+ END_DEVICE_PATH_LENGTH,
+ 0
+ }
+ }
+ },
};
-STATIC PCI_ROOT_BRIDGE mPciRootBridge[] = {
+STATIC PCI_ROOT_BRIDGE mPciRootBridge[ROOT_COMPLEX_NUM] = {
{
0, // Segment
0, // Supports
@@ -90,7 +115,43 @@ STATIC PCI_ROOT_BRIDGE mPciRootBridge[] = {
0
},
(EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath[0]
- }
+ },
+ {
+ 1, // Segment
+ 0, // Supports
+ 0, // Attributes
+ TRUE, // DmaAbove4G
+ FALSE, // NoExtendedConfigSpace
+ FALSE, // ResourceAssigned
+ EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM | // AllocationAttributes
+ EFI_PCI_HOST_BRIDGE_MEM64_DECODE,
+ {
+ // Bus
+ FixedPcdGet32 (PcdCcixBusMin),
+ FixedPcdGet32 (PcdCcixBusMax)
+ }, {
+ // Io
+ FixedPcdGet64 (PcdCcixIoBase),
+ FixedPcdGet64 (PcdCcixIoBase) + FixedPcdGet64 (PcdCcixIoSize) - 1
+ }, {
+ // Mem
+ FixedPcdGet32 (PcdCcixMmio32Base),
+ FixedPcdGet32 (PcdCcixMmio32Base) + FixedPcdGet32 (PcdCcixMmio32Size) - 1
+ }, {
+ // MemAbove4G
+ FixedPcdGet64 (PcdCcixMmio64Base),
+ FixedPcdGet64 (PcdCcixMmio64Base) + FixedPcdGet64 (PcdCcixMmio64Size) - 1
+ }, {
+ // PMem
+ MAX_UINT64,
+ 0
+ }, {
+ // PMemAbove4G
+ MAX_UINT64,
+ 0
+ },
+ (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath[1]
+ },
};
/**
diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.inf b/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.inf
index 3ff1c592f2..3356c3ad35 100644
--- a/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.inf
+++ b/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.inf
@@ -1,7 +1,7 @@
## @file
# PCI Host Bridge Library instance for ARM Neoverse N1 platform.
#
-# Copyright (c) 2019 - 2020, ARM Limited. All rights reserved.
+# Copyright (c) 2019 - 2021, ARM Limited. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -42,6 +42,15 @@
gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio64Base
gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio64Size
+ gArmNeoverseN1SocTokenSpaceGuid.PcdCcixBusMin
+ gArmNeoverseN1SocTokenSpaceGuid.PcdCcixBusMax
+ gArmNeoverseN1SocTokenSpaceGuid.PcdCcixIoBase
+ gArmNeoverseN1SocTokenSpaceGuid.PcdCcixIoSize
+ gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio32Base
+ gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio32Size
+ gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio64Base
+ gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio64Size
+
[Protocols]
gEfiCpuIo2ProtocolGuid
--
2.17.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH v5 4/4] Silicon/ARM/NeoverseN1Soc: Remove PciExpressLib use PciSegmentLib instead
2021-12-22 1:14 [PATCH v5 0/4] Enable CCIX port as PCIe root host on N1SDP Khasim Mohammed
` (2 preceding siblings ...)
2021-12-22 1:14 ` [PATCH v5 3/4] Silicon/ARM/NeoverseN1Soc: Add CCIX root complex support Khasim Mohammed
@ 2021-12-22 1:14 ` Khasim Mohammed
2021-12-22 8:51 ` [edk2-devel] " PierreGondois
2022-01-19 15:02 ` Sami Mujawar
3 siblings, 2 replies; 13+ messages in thread
From: Khasim Mohammed @ 2021-12-22 1:14 UTC (permalink / raw)
To: devel; +Cc: nd, Khasim Syed Mohammed, Deepak Pandey
The patch removes PciExpressLib implementation for N1Sdp as:
a) The PciSegmentLib implementation for N1Sdp makes MmioRead() calls
instead of PciRead() which makes the PciExpressLib redundant.
b) Since N1Sdp requires multiple segments to be supported, PciExpressLib
and PciLib cannot be used, PciSegmentLib should be used instead as it
supports multiple segments.
Signed-off-by: Deepak Pandey <Deepak.Pandey@arm.com>
Signed-off-by: Khasim Syed Mohammed <khasim.mohammed@arm.com>
---
Platform/ARM/N1Sdp/N1SdpPlatform.dsc | 4 +-
.../PciExpressLib.c | 1589 -----------------
.../PciExpressLib.inf | 56 -
3 files changed, 1 insertion(+), 1648 deletions(-)
delete mode 100644 Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciExpressLib/PciExpressLib.c
delete mode 100644 Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciExpressLib/PciExpressLib.inf
diff --git a/Platform/ARM/N1Sdp/N1SdpPlatform.dsc b/Platform/ARM/N1Sdp/N1SdpPlatform.dsc
index cb2049966c..8dac1bc54c 100644
--- a/Platform/ARM/N1Sdp/N1SdpPlatform.dsc
+++ b/Platform/ARM/N1Sdp/N1SdpPlatform.dsc
@@ -75,9 +75,7 @@
[LibraryClasses.common.DXE_DRIVER]
FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib.inf
PciHostBridgeLib|Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.inf
- PciSegmentLib|MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf
- PciLib|MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf
- PciExpressLib|Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciExpressLib/PciExpressLib.inf
+ PciSegmentLib|Silicon/ARM/NeoverseN1Soc/Library/PciSegmentLib/PciSegmentLib.inf
[LibraryClasses.common.DXE_RUNTIME_DRIVER]
BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
diff --git a/Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciExpressLib/PciExpressLib.c b/Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciExpressLib/PciExpressLib.c
deleted file mode 100644
index bb0246b4a9..0000000000
--- a/Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciExpressLib/PciExpressLib.c
+++ /dev/null
@@ -1,1589 +0,0 @@
-/** @file
- Functions in this library instance make use of MMIO functions in IoLib to
- access memory mapped PCI configuration space.
-
- All assertions for I/O operations are handled in MMIO functions in the IoLib
- Library.
-
- Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
-
- On the NeoverseN1Soc, a slave error is generated when host accesses the
- configuration space of non-available device or unimplemented function on a
- given bus. So this library introduces a workaround using IsBdfValid(),
- to return 0xFFFFFFFF for all such access.
-
- In addition to this, the hardware has two other limitations which affect
- access to the PCIe root port:
- 1. ECAM space is not contiguous, root port ECAM (BDF = 0:0:0) is isolated
- from rest of the downstream hierarchy ECAM space.
- 2. Root port ECAM space is not capable of 8bit/16bit writes.
- The description of the workarounds included for these limitations can
- be found in the comments below.
-
- Copyright (c) 2020, ARM Limited. All rights reserved.
-
- SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
-
-#include <Base.h>
-
-#include <Library/BaseLib.h>
-#include <Library/PciExpressLib.h>
-#include <Library/IoLib.h>
-#include <Library/DebugLib.h>
-#include <Library/PcdLib.h>
-#include <NeoverseN1Soc.h>
-
-/**
- Assert the validity of a PCI address. A valid PCI address should contain 1's
- only in the low 28 bits.
-
- @param A The address to validate.
-
-**/
-#define ASSERT_INVALID_PCI_ADDRESS(A) \
- ASSERT (((A) & ~0xfffffff) == 0)
-
-/* Root port Entry, BDF Entries Count */
-#define BDF_TABLE_ENTRY_SIZE 4
-#define BDF_TABLE_HEADER_COUNT 2
-#define BDF_TABLE_HEADER_SIZE 8
-
-/* BDF table offsets for PCIe */
-#define PCIE_BDF_TABLE_OFFSET 0
-
-#define GET_BUS_NUM(Address) (((Address) >> 20) & 0x7F)
-#define GET_DEV_NUM(Address) (((Address) >> 15) & 0x1F)
-#define GET_FUNC_NUM(Address) (((Address) >> 12) & 0x07)
-#define GET_REG_NUM(Address) ((Address) & 0xFFF)
-
-/**
- BDF Table structure : (Header + BDF Entries)
- --------------------------------------------
- [Offset 0x00] ROOT PORT ADDRESS
- [Offset 0x04] BDF ENTRIES COUNT
- [Offset 0x08] BDF ENTRY 0
- [Offset 0x0C] BDF ENTRY 1
- [Offset 0x10] BDF ENTRY 2
- [Offset 0x14] BDF ENTRY 3
- [Offset 0x18] BDF ENTRY 4
- ...
- [Offset 0x--] BDF ENTRY N
- --------------------------------------------
-**/
-
-/**
- Value returned for reads on configuration space of unimplemented
- device functions.
-**/
-STATIC UINTN mDummyConfigData = 0xFFFFFFFF;
-
-/**
- Registers a PCI device so PCI configuration registers may be accessed after
- SetVirtualAddressMap().
-
- Registers the PCI device specified by Address so all the PCI configuration
- registers associated with that PCI device may be accessed after SetVirtualAddressMap()
- is called.
-
- If Address > 0x0FFFFFFF, then ASSERT().
-
- @param Address The address that encodes the PCI Bus, Device, Function and
- Register.
-
- @retval RETURN_SUCCESS The PCI device was registered for runtime access.
- @retval RETURN_UNSUPPORTED An attempt was made to call this function
- after ExitBootServices().
- @retval RETURN_UNSUPPORTED The resources required to access the PCI device
- at runtime could not be mapped.
- @retval RETURN_OUT_OF_RESOURCES There are not enough resources available to
- complete the registration.
-
-**/
-RETURN_STATUS
-EFIAPI
-PciExpressRegisterForRuntimeAccess (
- IN UINTN Address
- )
-{
- ASSERT_INVALID_PCI_ADDRESS (Address);
- return RETURN_UNSUPPORTED;
-}
-
-/**
- Check if the requested PCI address can be safely accessed.
-
- SCP performs the initial bus scan, prepares a table of valid BDF addresses
- and shares them through non-trusted SRAM. This function validates if the
- requested PCI address belongs to a valid BDF by checking the table of valid
- entries. If not, this function will return false. This is a workaround to
- avoid bus fault that occurs when accessing unavailable PCI device due to
- hardware bug.
-
- @param Address The address that encodes the PCI Bus, Device, Function and
- Register.
-
- @return TRUE BDF can be accessed, valid.
- @return FALSE BDF should not be accessed, invalid.
-
-**/
-STATIC
-BOOLEAN
-IsBdfValid (
- IN UINTN Address
- )
-{
- UINTN BdfCount;
- UINTN BdfValue;
- UINTN BdfEntry;
- UINTN Count;
- UINTN TableBase;
- UINTN ConfigBase;
-
- ConfigBase = Address & ~0xFFF;
- TableBase = NEOVERSEN1SOC_NON_SECURE_SRAM_BASE + PCIE_BDF_TABLE_OFFSET;
- BdfCount = MmioRead32 (TableBase + BDF_TABLE_ENTRY_SIZE);
- BdfEntry = TableBase + BDF_TABLE_HEADER_SIZE;
-
- /* Skip the header & check remaining entry */
- for (Count = 0; Count < BdfCount; Count++, BdfEntry += BDF_TABLE_ENTRY_SIZE) {
- BdfValue = MmioRead32 (BdfEntry);
- if (BdfValue == ConfigBase) {
- return TRUE;
- }
- }
-
- return FALSE;
-}
-
-/**
- Get the physical address of a configuration space register.
-
- Implement a workaround to avoid generation of slave errors from the bus. That
- is, retrieve the PCI Express Base Address via a PCD entry, add the incomming
- address with that base address and check whether this converted address
- points to a accessible BDF. If it is not accessible, return the address
- of a dummy location so that a read from it does not cause a slave error.
-
- In addition to this, implement a workaround for accessing the root port's
- configuration space. The root port configuration space is not contiguous
- with the rest of the downstream hierarchy configuration space. So determine
- whether the specified address is for the root port and use a different base
- address for it.
-
- @param Address The address that encodes the PCI Bus, Device, Function and
- Register.
-
- @return Physical address of the configuration register that corresponds to the
- PCI configuration register specified by input parameter 'Address'.
-
-**/
-STATIC
-VOID*
-GetPciExpressAddress (
- IN UINTN Address
- )
-{
- UINT8 Bus, Device, Function;
- UINTN ConfigAddress;
-
- Bus = GET_BUS_NUM (Address);
- Device = GET_DEV_NUM (Address);
- Function = GET_FUNC_NUM (Address);
-
- if ((Bus == 0) && (Device == 0) && (Function == 0)) {
- ConfigAddress = PcdGet32 (PcdPcieRootPortConfigBaseAddress) + Address;
- } else {
- ConfigAddress = PcdGet64 (PcdPciExpressBaseAddress) + Address;
- if (!IsBdfValid(Address)) {
- ConfigAddress = (UINTN)&mDummyConfigData;
- }
- }
-
- return (VOID *)ConfigAddress;
-}
-
-/**
- Reads an 8-bit PCI configuration register.
-
- Reads and returns the 8-bit PCI configuration register specified by Address.
- This function must guarantee that all PCI read and write operations are
- serialized.
-
- If Address > 0x0FFFFFFF, then ASSERT().
-
- @param Address The address that encodes the PCI Bus, Device, Function and
- Register.
-
- @return The read value from the PCI configuration register.
-
-**/
-UINT8
-EFIAPI
-PciExpressRead8 (
- IN UINTN Address
- )
-{
- ASSERT_INVALID_PCI_ADDRESS (Address);
- return MmioRead8 ((UINTN)GetPciExpressAddress (Address));
-}
-
-/**
- Writes an 8-bit PCI configuration register.
-
- Writes the 8-bit PCI configuration register specified by Address with the
- value specified by Value. Value is returned. This function must guarantee
- that all PCI read and write operations are serialized.
-
- If Address > 0x0FFFFFFF, then ASSERT().
-
- @param Address The address that encodes the PCI Bus, Device, Function and
- Register.
- @param Value The value to write.
-
- @return The value written to the PCI configuration register.
-
-**/
-UINT8
-EFIAPI
-PciExpressWrite8 (
- IN UINTN Address,
- IN UINT8 Value
- )
-{
- UINT8 Bus, Device, Function;
- UINT8 Offset;
- UINT32 Data;
-
- ASSERT_INVALID_PCI_ADDRESS (Address);
-
- Bus = GET_BUS_NUM (Address);
- Device = GET_DEV_NUM (Address);
- Function = GET_FUNC_NUM (Address);
-
- //
- // 8-bit and 16-bit writes to root port config space is not supported due to
- // a hardware limitation. As a workaround, perform a read-update-write
- // sequence on the whole 32-bit word of the root port config register such
- // that only the specified 8-bits of that word are updated.
- //
- if ((Bus == 0) && (Device == 0) && (Function == 0)) {
- Offset = Address & 0x3;
- Address &= 0xFFFFFFFC;
- Data = MmioRead32 ((UINTN)GetPciExpressAddress (Address));
- Data &= ~(0xFF << (8 * Offset));
- Data |= (Value << (8 * Offset));
- MmioWrite32 ((UINTN)GetPciExpressAddress (Address), Data);
- return Value;
- }
-
- return MmioWrite8 ((UINTN)GetPciExpressAddress (Address), Value);
-}
-
-/**
- Performs a bitwise OR of an 8-bit PCI configuration register with
- an 8-bit value.
-
- Reads the 8-bit PCI configuration register specified by Address, performs a
- bitwise OR between the read result and the value specified by
- OrData, and writes the result to the 8-bit PCI configuration register
- specified by Address. The value written to the PCI configuration register is
- returned. This function must guarantee that all PCI read and write operations
- are serialized.
-
- If Address > 0x0FFFFFFF, then ASSERT().
-
- @param Address The address that encodes the PCI Bus, Device, Function and
- Register.
- @param OrData The value to OR with the PCI configuration register.
-
- @return The value written back to the PCI configuration register.
-
-**/
-UINT8
-EFIAPI
-PciExpressOr8 (
- IN UINTN Address,
- IN UINT8 OrData
- )
-{
- ASSERT_INVALID_PCI_ADDRESS (Address);
- return MmioOr8 ((UINTN)GetPciExpressAddress (Address), OrData);
-}
-
-/**
- Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
- value.
-
- Reads the 8-bit PCI configuration register specified by Address, performs a
- bitwise AND between the read result and the value specified by AndData, and
- writes the result to the 8-bit PCI configuration register specified by
- Address. The value written to the PCI configuration register is returned.
- This function must guarantee that all PCI read and write operations are
- serialized.
-
- If Address > 0x0FFFFFFF, then ASSERT().
-
- @param Address The address that encodes the PCI Bus, Device, Function and
- Register.
- @param AndData The value to AND with the PCI configuration register.
-
- @return The value written back to the PCI configuration register.
-
-**/
-UINT8
-EFIAPI
-PciExpressAnd8 (
- IN UINTN Address,
- IN UINT8 AndData
- )
-{
- ASSERT_INVALID_PCI_ADDRESS (Address);
- return MmioAnd8 ((UINTN)GetPciExpressAddress (Address), AndData);
-}
-
-/**
- Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
- value, followed a bitwise OR with another 8-bit value.
-
- Reads the 8-bit PCI configuration register specified by Address, performs a
- bitwise AND between the read result and the value specified by AndData,
- performs a bitwise OR between the result of the AND operation and
- the value specified by OrData, and writes the result to the 8-bit PCI
- configuration register specified by Address. The value written to the PCI
- configuration register is returned. This function must guarantee that all PCI
- read and write operations are serialized.
-
- If Address > 0x0FFFFFFF, then ASSERT().
-
- @param Address The address that encodes the PCI Bus, Device, Function and
- Register.
- @param AndData The value to AND with the PCI configuration register.
- @param OrData The value to OR with the result of the AND operation.
-
- @return The value written back to the PCI configuration register.
-
-**/
-UINT8
-EFIAPI
-PciExpressAndThenOr8 (
- IN UINTN Address,
- IN UINT8 AndData,
- IN UINT8 OrData
- )
-{
- ASSERT_INVALID_PCI_ADDRESS (Address);
- return MmioAndThenOr8 (
- (UINTN)GetPciExpressAddress (Address),
- AndData,
- OrData
- );
-}
-
-/**
- Reads a bit field of a PCI configuration register.
-
- Reads the bit field in an 8-bit PCI configuration register. The bit field is
- specified by the StartBit and the EndBit. The value of the bit field is
- returned.
-
- If Address > 0x0FFFFFFF, then ASSERT().
- If StartBit is greater than 7, then ASSERT().
- If EndBit is greater than 7, then ASSERT().
- If EndBit is less than StartBit, then ASSERT().
-
- @param Address The PCI configuration register to read.
- @param StartBit The ordinal of the least significant bit in the bit field.
- Range 0..7.
- @param EndBit The ordinal of the most significant bit in the bit field.
- Range 0..7.
-
- @return The value of the bit field read from the PCI configuration register.
-
-**/
-UINT8
-EFIAPI
-PciExpressBitFieldRead8 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit
- )
-{
- ASSERT_INVALID_PCI_ADDRESS (Address);
- return MmioBitFieldRead8 (
- (UINTN)GetPciExpressAddress (Address),
- StartBit,
- EndBit
- );
-}
-
-/**
- Writes a bit field to a PCI configuration register.
-
- Writes Value to the bit field of the PCI configuration register. The bit
- field is specified by the StartBit and the EndBit. All other bits in the
- destination PCI configuration register are preserved. The new value of the
- 8-bit register is returned.
-
- If Address > 0x0FFFFFFF, then ASSERT().
- If StartBit is greater than 7, then ASSERT().
- If EndBit is greater than 7, then ASSERT().
- If EndBit is less than StartBit, then ASSERT().
- If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
-
- @param Address The PCI configuration register to write.
- @param StartBit The ordinal of the least significant bit in the bit field.
- Range 0..7.
- @param EndBit The ordinal of the most significant bit in the bit field.
- Range 0..7.
- @param Value The new value of the bit field.
-
- @return The value written back to the PCI configuration register.
-
-**/
-UINT8
-EFIAPI
-PciExpressBitFieldWrite8 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT8 Value
- )
-{
- ASSERT_INVALID_PCI_ADDRESS (Address);
- return MmioBitFieldWrite8 (
- (UINTN)GetPciExpressAddress (Address),
- StartBit,
- EndBit,
- Value
- );
-}
-
-/**
- Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and
- writes the result back to the bit field in the 8-bit port.
-
- Reads the 8-bit PCI configuration register specified by Address, performs a
- bitwise OR between the read result and the value specified by
- OrData, and writes the result to the 8-bit PCI configuration register
- specified by Address. The value written to the PCI configuration register is
- returned. This function must guarantee that all PCI read and write operations
- are serialized. Extra left bits in OrData are stripped.
-
- If Address > 0x0FFFFFFF, then ASSERT().
- If StartBit is greater than 7, then ASSERT().
- If EndBit is greater than 7, then ASSERT().
- If EndBit is less than StartBit, then ASSERT().
- If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
-
- @param Address The PCI configuration register to write.
- @param StartBit The ordinal of the least significant bit in the bit field.
- Range 0..7.
- @param EndBit The ordinal of the most significant bit in the bit field.
- Range 0..7.
- @param OrData The value to OR with the PCI configuration register.
-
- @return The value written back to the PCI configuration register.
-
-**/
-UINT8
-EFIAPI
-PciExpressBitFieldOr8 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT8 OrData
- )
-{
- ASSERT_INVALID_PCI_ADDRESS (Address);
- return MmioBitFieldOr8 (
- (UINTN)GetPciExpressAddress (Address),
- StartBit,
- EndBit,
- OrData
- );
-}
-
-/**
- Reads a bit field in an 8-bit PCI configuration register, performs a bitwise
- AND, and writes the result back to the bit field in the 8-bit register.
-
- Reads the 8-bit PCI configuration register specified by Address, performs a
- bitwise AND between the read result and the value specified by AndData, and
- writes the result to the 8-bit PCI configuration register specified by
- Address. The value written to the PCI configuration register is returned.
- This function must guarantee that all PCI read and write operations are
- serialized. Extra left bits in AndData are stripped.
-
- If Address > 0x0FFFFFFF, then ASSERT().
- If StartBit is greater than 7, then ASSERT().
- If EndBit is greater than 7, then ASSERT().
- If EndBit is less than StartBit, then ASSERT().
- If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
-
- @param Address The PCI configuration register to write.
- @param StartBit The ordinal of the least significant bit in the bit field.
- Range 0..7.
- @param EndBit The ordinal of the most significant bit in the bit field.
- Range 0..7.
- @param AndData The value to AND with the PCI configuration register.
-
- @return The value written back to the PCI configuration register.
-
-**/
-UINT8
-EFIAPI
-PciExpressBitFieldAnd8 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT8 AndData
- )
-{
- ASSERT_INVALID_PCI_ADDRESS (Address);
- return MmioBitFieldAnd8 (
- (UINTN)GetPciExpressAddress (Address),
- StartBit,
- EndBit,
- AndData
- );
-}
-
-/**
- Reads a bit field in an 8-bit port, performs a bitwise AND followed by a
- bitwise OR, and writes the result back to the bit field in the
- 8-bit port.
-
- Reads the 8-bit PCI configuration register specified by Address, performs a
- bitwise AND followed by a bitwise OR between the read result and
- the value specified by AndData, and writes the result to the 8-bit PCI
- configuration register specified by Address. The value written to the PCI
- configuration register is returned. This function must guarantee that all PCI
- read and write operations are serialized. Extra left bits in both AndData and
- OrData are stripped.
-
- If Address > 0x0FFFFFFF, then ASSERT().
- If StartBit is greater than 7, then ASSERT().
- If EndBit is greater than 7, then ASSERT().
- If EndBit is less than StartBit, then ASSERT().
- If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
- If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
-
- @param Address The PCI configuration register to write.
- @param StartBit The ordinal of the least significant bit in the bit field.
- Range 0..7.
- @param EndBit The ordinal of the most significant bit in the bit field.
- Range 0..7.
- @param AndData The value to AND with the PCI configuration register.
- @param OrData The value to OR with the result of the AND operation.
-
- @return The value written back to the PCI configuration register.
-
-**/
-UINT8
-EFIAPI
-PciExpressBitFieldAndThenOr8 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT8 AndData,
- IN UINT8 OrData
- )
-{
- ASSERT_INVALID_PCI_ADDRESS (Address);
- return MmioBitFieldAndThenOr8 (
- (UINTN)GetPciExpressAddress (Address),
- StartBit,
- EndBit,
- AndData,
- OrData
- );
-}
-
-/**
- Reads a 16-bit PCI configuration register.
-
- Reads and returns the 16-bit PCI configuration register specified by Address.
- This function must guarantee that all PCI read and write operations are
- serialized.
-
- If Address > 0x0FFFFFFF, then ASSERT().
- If Address is not aligned on a 16-bit boundary, then ASSERT().
-
- @param Address The address that encodes the PCI Bus, Device, Function and
- Register.
-
- @return The read value from the PCI configuration register.
-
-**/
-UINT16
-EFIAPI
-PciExpressRead16 (
- IN UINTN Address
- )
-{
- ASSERT_INVALID_PCI_ADDRESS (Address);
- return MmioRead16 ((UINTN)GetPciExpressAddress (Address));
-}
-
-/**
- Writes a 16-bit PCI configuration register.
-
- Writes the 16-bit PCI configuration register specified by Address with the
- value specified by Value. Value is returned. This function must guarantee
- that all PCI read and write operations are serialized.
-
- If Address > 0x0FFFFFFF, then ASSERT().
- If Address is not aligned on a 16-bit boundary, then ASSERT().
-
- @param Address The address that encodes the PCI Bus, Device, Function and
- Register.
- @param Value The value to write.
-
- @return The value written to the PCI configuration register.
-
-**/
-UINT16
-EFIAPI
-PciExpressWrite16 (
- IN UINTN Address,
- IN UINT16 Value
- )
-{
- UINT8 Bus, Device, Function;
- UINT8 Offset;
- UINT32 Data;
-
- ASSERT_INVALID_PCI_ADDRESS (Address);
-
- Bus = GET_BUS_NUM (Address);
- Device = GET_DEV_NUM (Address);
- Function = GET_FUNC_NUM (Address);
-
- //
- // 8-bit and 16-bit writes to root port config space is not supported due to
- // a hardware limitation. As a workaround, perform a read-update-write
- // sequence on the whole 32-bit word of the root port config register such
- // that only the specified 16-bits of that word are updated.
- //
- if ((Bus == 0) && (Device == 0) && (Function == 0)) {
- Offset = Address & 0x3;
- Address &= 0xFFFFFFFC;
- Data = MmioRead32 ((UINTN)GetPciExpressAddress (Address));
- Data &= ~(0xFFFF << (8 * Offset));
- Data |= (Value << (8 * Offset));
- MmioWrite32 ((UINTN)GetPciExpressAddress (Address), Data);
- return Value;
- }
-
- return MmioWrite16 ((UINTN)GetPciExpressAddress (Address), Value);
-}
-
-/**
- Performs a bitwise OR of a 16-bit PCI configuration register with
- a 16-bit value.
-
- Reads the 16-bit PCI configuration register specified by Address, performs a
- bitwise OR between the read result and the value specified by
- OrData, and writes the result to the 16-bit PCI configuration register
- specified by Address. The value written to the PCI configuration register is
- returned. This function must guarantee that all PCI read and write operations
- are serialized.
-
- If Address > 0x0FFFFFFF, then ASSERT().
- If Address is not aligned on a 16-bit boundary, then ASSERT().
-
- @param Address The address that encodes the PCI Bus, Device, Function and
- Register.
- @param OrData The value to OR with the PCI configuration register.
-
- @return The value written back to the PCI configuration register.
-
-**/
-UINT16
-EFIAPI
-PciExpressOr16 (
- IN UINTN Address,
- IN UINT16 OrData
- )
-{
- ASSERT_INVALID_PCI_ADDRESS (Address);
- return MmioOr16 ((UINTN)GetPciExpressAddress (Address), OrData);
-}
-
-/**
- Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
- value.
-
- Reads the 16-bit PCI configuration register specified by Address, performs a
- bitwise AND between the read result and the value specified by AndData, and
- writes the result to the 16-bit PCI configuration register specified by
- Address. The value written to the PCI configuration register is returned.
- This function must guarantee that all PCI read and write operations are
- serialized.
-
- If Address > 0x0FFFFFFF, then ASSERT().
- If Address is not aligned on a 16-bit boundary, then ASSERT().
-
- @param Address The address that encodes the PCI Bus, Device, Function and
- Register.
- @param AndData The value to AND with the PCI configuration register.
-
- @return The value written back to the PCI configuration register.
-
-**/
-UINT16
-EFIAPI
-PciExpressAnd16 (
- IN UINTN Address,
- IN UINT16 AndData
- )
-{
- ASSERT_INVALID_PCI_ADDRESS (Address);
- return MmioAnd16 ((UINTN)GetPciExpressAddress (Address), AndData);
-}
-
-/**
- Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
- value, followed a bitwise OR with another 16-bit value.
-
- Reads the 16-bit PCI configuration register specified by Address, performs a
- bitwise AND between the read result and the value specified by AndData,
- performs a bitwise OR between the result of the AND operation and
- the value specified by OrData, and writes the result to the 16-bit PCI
- configuration register specified by Address. The value written to the PCI
- configuration register is returned. This function must guarantee that all PCI
- read and write operations are serialized.
-
- If Address > 0x0FFFFFFF, then ASSERT().
- If Address is not aligned on a 16-bit boundary, then ASSERT().
-
- @param Address The address that encodes the PCI Bus, Device, Function and
- Register.
- @param AndData The value to AND with the PCI configuration register.
- @param OrData The value to OR with the result of the AND operation.
-
- @return The value written back to the PCI configuration register.
-
-**/
-UINT16
-EFIAPI
-PciExpressAndThenOr16 (
- IN UINTN Address,
- IN UINT16 AndData,
- IN UINT16 OrData
- )
-{
- ASSERT_INVALID_PCI_ADDRESS (Address);
- return MmioAndThenOr16 (
- (UINTN)GetPciExpressAddress (Address),
- AndData,
- OrData
- );
-}
-
-/**
- Reads a bit field of a PCI configuration register.
-
- Reads the bit field in a 16-bit PCI configuration register. The bit field is
- specified by the StartBit and the EndBit. The value of the bit field is
- returned.
-
- If Address > 0x0FFFFFFF, then ASSERT().
- If Address is not aligned on a 16-bit boundary, then ASSERT().
- If StartBit is greater than 15, then ASSERT().
- If EndBit is greater than 15, then ASSERT().
- If EndBit is less than StartBit, then ASSERT().
-
- @param Address The PCI configuration register to read.
- @param StartBit The ordinal of the least significant bit in the bit field.
- Range 0..15.
- @param EndBit The ordinal of the most significant bit in the bit field.
- Range 0..15.
-
- @return The value of the bit field read from the PCI configuration register.
-
-**/
-UINT16
-EFIAPI
-PciExpressBitFieldRead16 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit
- )
-{
- ASSERT_INVALID_PCI_ADDRESS (Address);
- return MmioBitFieldRead16 (
- (UINTN)GetPciExpressAddress (Address),
- StartBit,
- EndBit
- );
-}
-
-/**
- Writes a bit field to a PCI configuration register.
-
- Writes Value to the bit field of the PCI configuration register. The bit
- field is specified by the StartBit and the EndBit. All other bits in the
- destination PCI configuration register are preserved. The new value of the
- 16-bit register is returned.
-
- If Address > 0x0FFFFFFF, then ASSERT().
- If Address is not aligned on a 16-bit boundary, then ASSERT().
- If StartBit is greater than 15, then ASSERT().
- If EndBit is greater than 15, then ASSERT().
- If EndBit is less than StartBit, then ASSERT().
- If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
-
- @param Address The PCI configuration register to write.
- @param StartBit The ordinal of the least significant bit in the bit field.
- Range 0..15.
- @param EndBit The ordinal of the most significant bit in the bit field.
- Range 0..15.
- @param Value The new value of the bit field.
-
- @return The value written back to the PCI configuration register.
-
-**/
-UINT16
-EFIAPI
-PciExpressBitFieldWrite16 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT16 Value
- )
-{
- ASSERT_INVALID_PCI_ADDRESS (Address);
- return MmioBitFieldWrite16 (
- (UINTN)GetPciExpressAddress (Address),
- StartBit,
- EndBit,
- Value
- );
-}
-
-/**
- Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and
- writes the result back to the bit field in the 16-bit port.
-
- Reads the 16-bit PCI configuration register specified by Address, performs a
- bitwise OR between the read result and the value specified by
- OrData, and writes the result to the 16-bit PCI configuration register
- specified by Address. The value written to the PCI configuration register is
- returned. This function must guarantee that all PCI read and write operations
- are serialized. Extra left bits in OrData are stripped.
-
- If Address > 0x0FFFFFFF, then ASSERT().
- If Address is not aligned on a 16-bit boundary, then ASSERT().
- If StartBit is greater than 15, then ASSERT().
- If EndBit is greater than 15, then ASSERT().
- If EndBit is less than StartBit, then ASSERT().
- If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
-
- @param Address The PCI configuration register to write.
- @param StartBit The ordinal of the least significant bit in the bit field.
- Range 0..15.
- @param EndBit The ordinal of the most significant bit in the bit field.
- Range 0..15.
- @param OrData The value to OR with the PCI configuration register.
-
- @return The value written back to the PCI configuration register.
-
-**/
-UINT16
-EFIAPI
-PciExpressBitFieldOr16 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT16 OrData
- )
-{
- ASSERT_INVALID_PCI_ADDRESS (Address);
- return MmioBitFieldOr16 (
- (UINTN)GetPciExpressAddress (Address),
- StartBit,
- EndBit,
- OrData
- );
-}
-
-/**
- Reads a bit field in a 16-bit PCI configuration register, performs a bitwise
- AND, and writes the result back to the bit field in the 16-bit register.
-
- Reads the 16-bit PCI configuration register specified by Address, performs a
- bitwise AND between the read result and the value specified by AndData, and
- writes the result to the 16-bit PCI configuration register specified by
- Address. The value written to the PCI configuration register is returned.
- This function must guarantee that all PCI read and write operations are
- serialized. Extra left bits in AndData are stripped.
-
- If Address > 0x0FFFFFFF, then ASSERT().
- If Address is not aligned on a 16-bit boundary, then ASSERT().
- If StartBit is greater than 15, then ASSERT().
- If EndBit is greater than 15, then ASSERT().
- If EndBit is less than StartBit, then ASSERT().
- If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
-
- @param Address The PCI configuration register to write.
- @param StartBit The ordinal of the least significant bit in the bit field.
- Range 0..15.
- @param EndBit The ordinal of the most significant bit in the bit field.
- Range 0..15.
- @param AndData The value to AND with the PCI configuration register.
-
- @return The value written back to the PCI configuration register.
-
-**/
-UINT16
-EFIAPI
-PciExpressBitFieldAnd16 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT16 AndData
- )
-{
- ASSERT_INVALID_PCI_ADDRESS (Address);
- return MmioBitFieldAnd16 (
- (UINTN)GetPciExpressAddress (Address),
- StartBit,
- EndBit,
- AndData
- );
-}
-
-/**
- Reads a bit field in a 16-bit port, performs a bitwise AND followed by a
- bitwise OR, and writes the result back to the bit field in the
- 16-bit port.
-
- Reads the 16-bit PCI configuration register specified by Address, performs a
- bitwise AND followed by a bitwise OR between the read result and
- the value specified by AndData, and writes the result to the 16-bit PCI
- configuration register specified by Address. The value written to the PCI
- configuration register is returned. This function must guarantee that all PCI
- read and write operations are serialized. Extra left bits in both AndData and
- OrData are stripped.
-
- If Address > 0x0FFFFFFF, then ASSERT().
- If Address is not aligned on a 16-bit boundary, then ASSERT().
- If StartBit is greater than 15, then ASSERT().
- If EndBit is greater than 15, then ASSERT().
- If EndBit is less than StartBit, then ASSERT().
- If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
- If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
-
- @param Address The PCI configuration register to write.
- @param StartBit The ordinal of the least significant bit in the bit field.
- Range 0..15.
- @param EndBit The ordinal of the most significant bit in the bit field.
- Range 0..15.
- @param AndData The value to AND with the PCI configuration register.
- @param OrData The value to OR with the result of the AND operation.
-
- @return The value written back to the PCI configuration register.
-
-**/
-UINT16
-EFIAPI
-PciExpressBitFieldAndThenOr16 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT16 AndData,
- IN UINT16 OrData
- )
-{
- ASSERT_INVALID_PCI_ADDRESS (Address);
- return MmioBitFieldAndThenOr16 (
- (UINTN)GetPciExpressAddress (Address),
- StartBit,
- EndBit,
- AndData,
- OrData
- );
-}
-
-/**
- Reads a 32-bit PCI configuration register.
-
- Reads and returns the 32-bit PCI configuration register specified by Address.
- This function must guarantee that all PCI read and write operations are
- serialized.
-
- If Address > 0x0FFFFFFF, then ASSERT().
- If Address is not aligned on a 32-bit boundary, then ASSERT().
-
- @param Address The address that encodes the PCI Bus, Device, Function and
- Register.
-
- @return The read value from the PCI configuration register.
-
-**/
-UINT32
-EFIAPI
-PciExpressRead32 (
- IN UINTN Address
- )
-{
- ASSERT_INVALID_PCI_ADDRESS (Address);
- return MmioRead32 ((UINTN)GetPciExpressAddress (Address));
-}
-
-/**
- Writes a 32-bit PCI configuration register.
-
- Writes the 32-bit PCI configuration register specified by Address with the
- value specified by Value. Value is returned. This function must guarantee
- that all PCI read and write operations are serialized.
-
- If Address > 0x0FFFFFFF, then ASSERT().
- If Address is not aligned on a 32-bit boundary, then ASSERT().
-
- @param Address The address that encodes the PCI Bus, Device, Function and
- Register.
- @param Value The value to write.
-
- @return The value written to the PCI configuration register.
-
-**/
-UINT32
-EFIAPI
-PciExpressWrite32 (
- IN UINTN Address,
- IN UINT32 Value
- )
-{
- ASSERT_INVALID_PCI_ADDRESS (Address);
- return MmioWrite32 ((UINTN)GetPciExpressAddress (Address), Value);
-}
-
-/**
- Performs a bitwise OR of a 32-bit PCI configuration register with
- a 32-bit value.
-
- Reads the 32-bit PCI configuration register specified by Address, performs a
- bitwise OR between the read result and the value specified by
- OrData, and writes the result to the 32-bit PCI configuration register
- specified by Address. The value written to the PCI configuration register is
- returned. This function must guarantee that all PCI read and write operations
- are serialized.
-
- If Address > 0x0FFFFFFF, then ASSERT().
- If Address is not aligned on a 32-bit boundary, then ASSERT().
-
- @param Address The address that encodes the PCI Bus, Device, Function and
- Register.
- @param OrData The value to OR with the PCI configuration register.
-
- @return The value written back to the PCI configuration register.
-
-**/
-UINT32
-EFIAPI
-PciExpressOr32 (
- IN UINTN Address,
- IN UINT32 OrData
- )
-{
- ASSERT_INVALID_PCI_ADDRESS (Address);
- return MmioOr32 ((UINTN)GetPciExpressAddress (Address), OrData);
-}
-
-/**
- Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
- value.
-
- Reads the 32-bit PCI configuration register specified by Address, performs a
- bitwise AND between the read result and the value specified by AndData, and
- writes the result to the 32-bit PCI configuration register specified by
- Address. The value written to the PCI configuration register is returned.
- This function must guarantee that all PCI read and write operations are
- serialized.
-
- If Address > 0x0FFFFFFF, then ASSERT().
- If Address is not aligned on a 32-bit boundary, then ASSERT().
-
- @param Address The address that encodes the PCI Bus, Device, Function and
- Register.
- @param AndData The value to AND with the PCI configuration register.
-
- @return The value written back to the PCI configuration register.
-
-**/
-UINT32
-EFIAPI
-PciExpressAnd32 (
- IN UINTN Address,
- IN UINT32 AndData
- )
-{
- ASSERT_INVALID_PCI_ADDRESS (Address);
- return MmioAnd32 ((UINTN)GetPciExpressAddress (Address), AndData);
-}
-
-/**
- Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
- value, followed a bitwise OR with another 32-bit value.
-
- Reads the 32-bit PCI configuration register specified by Address, performs a
- bitwise AND between the read result and the value specified by AndData,
- performs a bitwise OR between the result of the AND operation and
- the value specified by OrData, and writes the result to the 32-bit PCI
- configuration register specified by Address. The value written to the PCI
- configuration register is returned. This function must guarantee that all PCI
- read and write operations are serialized.
-
- If Address > 0x0FFFFFFF, then ASSERT().
- If Address is not aligned on a 32-bit boundary, then ASSERT().
-
- @param Address The address that encodes the PCI Bus, Device, Function and
- Register.
- @param AndData The value to AND with the PCI configuration register.
- @param OrData The value to OR with the result of the AND operation.
-
- @return The value written back to the PCI configuration register.
-
-**/
-UINT32
-EFIAPI
-PciExpressAndThenOr32 (
- IN UINTN Address,
- IN UINT32 AndData,
- IN UINT32 OrData
- )
-{
- ASSERT_INVALID_PCI_ADDRESS (Address);
- return MmioAndThenOr32 (
- (UINTN)GetPciExpressAddress (Address),
- AndData,
- OrData
- );
-}
-
-/**
- Reads a bit field of a PCI configuration register.
-
- Reads the bit field in a 32-bit PCI configuration register. The bit field is
- specified by the StartBit and the EndBit. The value of the bit field is
- returned.
-
- If Address > 0x0FFFFFFF, then ASSERT().
- If Address is not aligned on a 32-bit boundary, then ASSERT().
- If StartBit is greater than 31, then ASSERT().
- If EndBit is greater than 31, then ASSERT().
- If EndBit is less than StartBit, then ASSERT().
-
- @param Address The PCI configuration register to read.
- @param StartBit The ordinal of the least significant bit in the bit field.
- Range 0..31.
- @param EndBit The ordinal of the most significant bit in the bit field.
- Range 0..31.
-
- @return The value of the bit field read from the PCI configuration register.
-
-**/
-UINT32
-EFIAPI
-PciExpressBitFieldRead32 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit
- )
-{
- ASSERT_INVALID_PCI_ADDRESS (Address);
- return MmioBitFieldRead32 (
- (UINTN)GetPciExpressAddress (Address),
- StartBit,
- EndBit
- );
-}
-
-/**
- Writes a bit field to a PCI configuration register.
-
- Writes Value to the bit field of the PCI configuration register. The bit
- field is specified by the StartBit and the EndBit. All other bits in the
- destination PCI configuration register are preserved. The new value of the
- 32-bit register is returned.
-
- If Address > 0x0FFFFFFF, then ASSERT().
- If Address is not aligned on a 32-bit boundary, then ASSERT().
- If StartBit is greater than 31, then ASSERT().
- If EndBit is greater than 31, then ASSERT().
- If EndBit is less than StartBit, then ASSERT().
- If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
-
- @param Address The PCI configuration register to write.
- @param StartBit The ordinal of the least significant bit in the bit field.
- Range 0..31.
- @param EndBit The ordinal of the most significant bit in the bit field.
- Range 0..31.
- @param Value The new value of the bit field.
-
- @return The value written back to the PCI configuration register.
-
-**/
-UINT32
-EFIAPI
-PciExpressBitFieldWrite32 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT32 Value
- )
-{
- ASSERT_INVALID_PCI_ADDRESS (Address);
- return MmioBitFieldWrite32 (
- (UINTN)GetPciExpressAddress (Address),
- StartBit,
- EndBit,
- Value
- );
-}
-
-/**
- Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and
- writes the result back to the bit field in the 32-bit port.
-
- Reads the 32-bit PCI configuration register specified by Address, performs a
- bitwise OR between the read result and the value specified by
- OrData, and writes the result to the 32-bit PCI configuration register
- specified by Address. The value written to the PCI configuration register is
- returned. This function must guarantee that all PCI read and write operations
- are serialized. Extra left bits in OrData are stripped.
-
- If Address > 0x0FFFFFFF, then ASSERT().
- If Address is not aligned on a 32-bit boundary, then ASSERT().
- If StartBit is greater than 31, then ASSERT().
- If EndBit is greater than 31, then ASSERT().
- If EndBit is less than StartBit, then ASSERT().
- If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
-
- @param Address The PCI configuration register to write.
- @param StartBit The ordinal of the least significant bit in the bit field.
- Range 0..31.
- @param EndBit The ordinal of the most significant bit in the bit field.
- Range 0..31.
- @param OrData The value to OR with the PCI configuration register.
-
- @return The value written back to the PCI configuration register.
-
-**/
-UINT32
-EFIAPI
-PciExpressBitFieldOr32 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT32 OrData
- )
-{
- ASSERT_INVALID_PCI_ADDRESS (Address);
- return MmioBitFieldOr32 (
- (UINTN)GetPciExpressAddress (Address),
- StartBit,
- EndBit,
- OrData
- );
-}
-
-/**
- Reads a bit field in a 32-bit PCI configuration register, performs a bitwise
- AND, and writes the result back to the bit field in the 32-bit register.
-
- Reads the 32-bit PCI configuration register specified by Address, performs a
- bitwise AND between the read result and the value specified by AndData, and
- writes the result to the 32-bit PCI configuration register specified by
- Address. The value written to the PCI configuration register is returned.
- This function must guarantee that all PCI read and write operations are
- serialized. Extra left bits in AndData are stripped.
-
- If Address > 0x0FFFFFFF, then ASSERT().
- If Address is not aligned on a 32-bit boundary, then ASSERT().
- If StartBit is greater than 31, then ASSERT().
- If EndBit is greater than 31, then ASSERT().
- If EndBit is less than StartBit, then ASSERT().
- If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
-
- @param Address The PCI configuration register to write.
- @param StartBit The ordinal of the least significant bit in the bit field.
- Range 0..31.
- @param EndBit The ordinal of the most significant bit in the bit field.
- Range 0..31.
- @param AndData The value to AND with the PCI configuration register.
-
- @return The value written back to the PCI configuration register.
-
-**/
-UINT32
-EFIAPI
-PciExpressBitFieldAnd32 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT32 AndData
- )
-{
- ASSERT_INVALID_PCI_ADDRESS (Address);
- return MmioBitFieldAnd32 (
- (UINTN)GetPciExpressAddress (Address),
- StartBit,
- EndBit,
- AndData
- );
-}
-
-/**
- Reads a bit field in a 32-bit port, performs a bitwise AND followed by a
- bitwise OR, and writes the result back to the bit field in the
- 32-bit port.
-
- Reads the 32-bit PCI configuration register specified by Address, performs a
- bitwise AND followed by a bitwise OR between the read result and
- the value specified by AndData, and writes the result to the 32-bit PCI
- configuration register specified by Address. The value written to the PCI
- configuration register is returned. This function must guarantee that all PCI
- read and write operations are serialized. Extra left bits in both AndData and
- OrData are stripped.
-
- If Address > 0x0FFFFFFF, then ASSERT().
- If Address is not aligned on a 32-bit boundary, then ASSERT().
- If StartBit is greater than 31, then ASSERT().
- If EndBit is greater than 31, then ASSERT().
- If EndBit is less than StartBit, then ASSERT().
- If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
- If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
-
- @param Address The PCI configuration register to write.
- @param StartBit The ordinal of the least significant bit in the bit field.
- Range 0..31.
- @param EndBit The ordinal of the most significant bit in the bit field.
- Range 0..31.
- @param AndData The value to AND with the PCI configuration register.
- @param OrData The value to OR with the result of the AND operation.
-
- @return The value written back to the PCI configuration register.
-
-**/
-UINT32
-EFIAPI
-PciExpressBitFieldAndThenOr32 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT32 AndData,
- IN UINT32 OrData
- )
-{
- ASSERT_INVALID_PCI_ADDRESS (Address);
- return MmioBitFieldAndThenOr32 (
- (UINTN)GetPciExpressAddress (Address),
- StartBit,
- EndBit,
- AndData,
- OrData
- );
-}
-
-/**
- Reads a range of PCI configuration registers into a caller supplied buffer.
-
- Reads the range of PCI configuration registers specified by StartAddress and
- Size into the buffer specified by Buffer. This function only allows the PCI
- configuration registers from a single PCI function to be read. Size is
- returned. When possible 32-bit PCI configuration read cycles are used to read
- from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit
- and 16-bit PCI configuration read cycles may be used at the beginning and the
- end of the range.
-
- If StartAddress > 0x0FFFFFFF, then ASSERT().
- If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
- If Size > 0 and Buffer is NULL, then ASSERT().
-
- @param StartAddress The starting address that encodes the PCI Bus, Device,
- Function and Register.
- @param Size The size in bytes of the transfer.
- @param Buffer The pointer to a buffer receiving the data read.
-
- @return Size read data from StartAddress.
-
-**/
-UINTN
-EFIAPI
-PciExpressReadBuffer (
- IN UINTN StartAddress,
- IN UINTN Size,
- OUT VOID *Buffer
- )
-{
- UINTN ReturnValue;
-
- ASSERT_INVALID_PCI_ADDRESS (StartAddress);
- ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);
-
- if (Size == 0) {
- return Size;
- }
-
- ASSERT (Buffer != NULL);
-
- //
- // Save Size for return
- //
- ReturnValue = Size;
-
- if ((StartAddress & 1) != 0) {
- //
- // Read a byte if StartAddress is byte aligned
- //
- *(volatile UINT8 *)Buffer = PciExpressRead8 (StartAddress);
- StartAddress += sizeof (UINT8);
- Size -= sizeof (UINT8);
- Buffer = (UINT8*)Buffer + 1;
- }
-
- if (Size >= sizeof (UINT16) && (StartAddress & 2) != 0) {
- //
- // Read a word if StartAddress is word aligned
- //
- WriteUnaligned16 ((UINT16 *) Buffer, (UINT16) PciExpressRead16 (StartAddress));
-
- StartAddress += sizeof (UINT16);
- Size -= sizeof (UINT16);
- Buffer = (UINT16*)Buffer + 1;
- }
-
- while (Size >= sizeof (UINT32)) {
- //
- // Read as many double words as possible
- //
- WriteUnaligned32 ((UINT32 *) Buffer, (UINT32) PciExpressRead32 (StartAddress));
-
- StartAddress += sizeof (UINT32);
- Size -= sizeof (UINT32);
- Buffer = (UINT32*)Buffer + 1;
- }
-
- if (Size >= sizeof (UINT16)) {
- //
- // Read the last remaining word if exist
- //
- WriteUnaligned16 ((UINT16 *) Buffer, (UINT16) PciExpressRead16 (StartAddress));
- StartAddress += sizeof (UINT16);
- Size -= sizeof (UINT16);
- Buffer = (UINT16*)Buffer + 1;
- }
-
- if (Size >= sizeof (UINT8)) {
- //
- // Read the last remaining byte if exist
- //
- *(volatile UINT8 *)Buffer = PciExpressRead8 (StartAddress);
- }
-
- return ReturnValue;
-}
-
-/**
- Copies the data in a caller supplied buffer to a specified range of PCI
- configuration space.
-
- Writes the range of PCI configuration registers specified by StartAddress and
- Size from the buffer specified by Buffer. This function only allows the PCI
- configuration registers from a single PCI function to be written. Size is
- returned. When possible 32-bit PCI configuration write cycles are used to
- write from StartAdress to StartAddress + Size. Due to alignment restrictions,
- 8-bit and 16-bit PCI configuration write cycles may be used at the beginning
- and the end of the range.
-
- If StartAddress > 0x0FFFFFFF, then ASSERT().
- If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
- If Size > 0 and Buffer is NULL, then ASSERT().
-
- @param StartAddress The starting address that encodes the PCI Bus, Device,
- Function and Register.
- @param Size The size in bytes of the transfer.
- @param Buffer The pointer to a buffer containing the data to write.
-
- @return Size written to StartAddress.
-
-**/
-UINTN
-EFIAPI
-PciExpressWriteBuffer (
- IN UINTN StartAddress,
- IN UINTN Size,
- IN VOID *Buffer
- )
-{
- UINTN ReturnValue;
-
- ASSERT_INVALID_PCI_ADDRESS (StartAddress);
- ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);
-
- if (Size == 0) {
- return 0;
- }
-
- ASSERT (Buffer != NULL);
-
- //
- // Save Size for return
- //
- ReturnValue = Size;
-
- if ((StartAddress & 1) != 0) {
- //
- // Write a byte if StartAddress is byte aligned
- //
- PciExpressWrite8 (StartAddress, *(UINT8*)Buffer);
- StartAddress += sizeof (UINT8);
- Size -= sizeof (UINT8);
- Buffer = (UINT8*)Buffer + 1;
- }
-
- if (Size >= sizeof (UINT16) && (StartAddress & 2) != 0) {
- //
- // Write a word if StartAddress is word aligned
- //
- PciExpressWrite16 (StartAddress, ReadUnaligned16 ((UINT16*)Buffer));
- StartAddress += sizeof (UINT16);
- Size -= sizeof (UINT16);
- Buffer = (UINT16*)Buffer + 1;
- }
-
- while (Size >= sizeof (UINT32)) {
- //
- // Write as many double words as possible
- //
- PciExpressWrite32 (StartAddress, ReadUnaligned32 ((UINT32*)Buffer));
- StartAddress += sizeof (UINT32);
- Size -= sizeof (UINT32);
- Buffer = (UINT32*)Buffer + 1;
- }
-
- if (Size >= sizeof (UINT16)) {
- //
- // Write the last remaining word if exist
- //
- PciExpressWrite16 (StartAddress, ReadUnaligned16 ((UINT16*)Buffer));
- StartAddress += sizeof (UINT16);
- Size -= sizeof (UINT16);
- Buffer = (UINT16*)Buffer + 1;
- }
-
- if (Size >= sizeof (UINT8)) {
- //
- // Write the last remaining byte if exist
- //
- PciExpressWrite8 (StartAddress, *(UINT8*)Buffer);
- }
-
- return ReturnValue;
-}
diff --git a/Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciExpressLib/PciExpressLib.inf b/Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciExpressLib/PciExpressLib.inf
deleted file mode 100644
index acb6fb6219..0000000000
--- a/Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciExpressLib/PciExpressLib.inf
+++ /dev/null
@@ -1,56 +0,0 @@
-## @file
-# Instance of PCI Express Library using the 256 MB PCI Express MMIO window.
-#
-# PCI Express Library that uses the 256 MB PCI Express MMIO window to perform
-# PCI Configuration cycles. Layers on top of an I/O Library instance.
-#
-# Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.
-#
-# This library is inherited from MdePkg/Library/BasePciExpressLib. On
-# NeoverseN1 SoC, with the unmodified version of this library, a slave error is
-# generated when host accesses the config space of a non-available device or
-# unimplemented function on a given bus. In order to resolve this for
-# NeoverseN1 SoC, a modified version of the MdePkg/Library/BasePciExpressLib
-# library is used. The modification includes a check to determine whether the
-# incoming PCI address can be safely accessed.
-#
-# In addition to this, the NeoverseN1 SoC has two other limitations which
-# affect the access to the PCIe root port:
-# 1. ECAM space is not contiguous, root port ECAM (BDF = 0:0:0) is isolated
-# from rest of the downstream hierarchy ECAM space.
-# 2. Root port ECAM space is not capable of 8bit/16bit writes.
-# This library includes workaround for these limitations as well.
-#
-# Copyright (c) 2020, ARM Limited. All rights reserved.
-#
-# SPDX-License-Identifier: BSD-2-Clause-Patent
-#
-##
-
-[Defines]
- INF_VERSION = 0x0001001A
- BASE_NAME = BasePciExpressLib
- FILE_GUID = b378dd06-de7f-4e8c-8fb0-5126adfb34bf
- MODULE_TYPE = BASE
- VERSION_STRING = 1.0
- LIBRARY_CLASS = PciExpressLib
-
-[Sources]
- PciExpressLib.c
-
-[Packages]
- MdePkg/MdePkg.dec
- Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec
-
-[FixedPcd]
- gArmNeoverseN1SocTokenSpaceGuid.PcdPcieRootPortConfigBaseAddress
- gArmNeoverseN1SocTokenSpaceGuid.PcdPcieRootPortConfigBaseSize
-
-[LibraryClasses]
- BaseLib
- DebugLib
- IoLib
- PcdLib
-
-[Pcd]
- gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## CONSUMES
--
2.17.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [edk2-devel] [PATCH v5 4/4] Silicon/ARM/NeoverseN1Soc: Remove PciExpressLib use PciSegmentLib instead
2021-12-22 1:14 ` [PATCH v5 4/4] Silicon/ARM/NeoverseN1Soc: Remove PciExpressLib use PciSegmentLib instead Khasim Mohammed
@ 2021-12-22 8:51 ` PierreGondois
2022-01-19 15:02 ` Sami Mujawar
1 sibling, 0 replies; 13+ messages in thread
From: PierreGondois @ 2021-12-22 8:51 UTC (permalink / raw)
To: devel, khasim.mohammed; +Cc: nd, Deepak Pandey, Sami Mujawar
Hi Khasim,
Everything looks good to me:
Reviewed-by: Pierre Gondois <pierre.gondois@arm.com>
Regards,
Pierre
On 12/22/21 2:14 AM, Khasim Mohammed via groups.io wrote:
> The patch removes PciExpressLib implementation for N1Sdp as:
>
> a) The PciSegmentLib implementation for N1Sdp makes MmioRead() calls
> instead of PciRead() which makes the PciExpressLib redundant.
>
> b) Since N1Sdp requires multiple segments to be supported, PciExpressLib
> and PciLib cannot be used, PciSegmentLib should be used instead as it
> supports multiple segments.
>
> Signed-off-by: Deepak Pandey <Deepak.Pandey@arm.com>
> Signed-off-by: Khasim Syed Mohammed <khasim.mohammed@arm.com>
> ---
> Platform/ARM/N1Sdp/N1SdpPlatform.dsc | 4 +-
> .../PciExpressLib.c | 1589 -----------------
> .../PciExpressLib.inf | 56 -
> 3 files changed, 1 insertion(+), 1648 deletions(-)
> delete mode 100644 Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciExpressLib/PciExpressLib.c
> delete mode 100644 Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciExpressLib/PciExpressLib.inf
>
> diff --git a/Platform/ARM/N1Sdp/N1SdpPlatform.dsc b/Platform/ARM/N1Sdp/N1SdpPlatform.dsc
> index cb2049966c..8dac1bc54c 100644
> --- a/Platform/ARM/N1Sdp/N1SdpPlatform.dsc
> +++ b/Platform/ARM/N1Sdp/N1SdpPlatform.dsc
> @@ -75,9 +75,7 @@
> [LibraryClasses.common.DXE_DRIVER]
> FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib.inf
> PciHostBridgeLib|Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.inf
> - PciSegmentLib|MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf
> - PciLib|MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf
> - PciExpressLib|Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciExpressLib/PciExpressLib.inf
> + PciSegmentLib|Silicon/ARM/NeoverseN1Soc/Library/PciSegmentLib/PciSegmentLib.inf
>
> [LibraryClasses.common.DXE_RUNTIME_DRIVER]
> BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
> diff --git a/Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciExpressLib/PciExpressLib.c b/Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciExpressLib/PciExpressLib.c
> deleted file mode 100644
> index bb0246b4a9..0000000000
> --- a/Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciExpressLib/PciExpressLib.c
> +++ /dev/null
> @@ -1,1589 +0,0 @@
> -/** @file
> - Functions in this library instance make use of MMIO functions in IoLib to
> - access memory mapped PCI configuration space.
> -
> - All assertions for I/O operations are handled in MMIO functions in the IoLib
> - Library.
> -
> - Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
> -
> - On the NeoverseN1Soc, a slave error is generated when host accesses the
> - configuration space of non-available device or unimplemented function on a
> - given bus. So this library introduces a workaround using IsBdfValid(),
> - to return 0xFFFFFFFF for all such access.
> -
> - In addition to this, the hardware has two other limitations which affect
> - access to the PCIe root port:
> - 1. ECAM space is not contiguous, root port ECAM (BDF = 0:0:0) is isolated
> - from rest of the downstream hierarchy ECAM space.
> - 2. Root port ECAM space is not capable of 8bit/16bit writes.
> - The description of the workarounds included for these limitations can
> - be found in the comments below.
> -
> - Copyright (c) 2020, ARM Limited. All rights reserved.
> -
> - SPDX-License-Identifier: BSD-2-Clause-Patent
> -
> -**/
> -
> -
> -#include <Base.h>
> -
> -#include <Library/BaseLib.h>
> -#include <Library/PciExpressLib.h>
> -#include <Library/IoLib.h>
> -#include <Library/DebugLib.h>
> -#include <Library/PcdLib.h>
> -#include <NeoverseN1Soc.h>
> -
> -/**
> - Assert the validity of a PCI address. A valid PCI address should contain 1's
> - only in the low 28 bits.
> -
> - @param A The address to validate.
> -
> -**/
> -#define ASSERT_INVALID_PCI_ADDRESS(A) \
> - ASSERT (((A) & ~0xfffffff) == 0)
> -
> -/* Root port Entry, BDF Entries Count */
> -#define BDF_TABLE_ENTRY_SIZE 4
> -#define BDF_TABLE_HEADER_COUNT 2
> -#define BDF_TABLE_HEADER_SIZE 8
> -
> -/* BDF table offsets for PCIe */
> -#define PCIE_BDF_TABLE_OFFSET 0
> -
> -#define GET_BUS_NUM(Address) (((Address) >> 20) & 0x7F)
> -#define GET_DEV_NUM(Address) (((Address) >> 15) & 0x1F)
> -#define GET_FUNC_NUM(Address) (((Address) >> 12) & 0x07)
> -#define GET_REG_NUM(Address) ((Address) & 0xFFF)
> -
> -/**
> - BDF Table structure : (Header + BDF Entries)
> - --------------------------------------------
> - [Offset 0x00] ROOT PORT ADDRESS
> - [Offset 0x04] BDF ENTRIES COUNT
> - [Offset 0x08] BDF ENTRY 0
> - [Offset 0x0C] BDF ENTRY 1
> - [Offset 0x10] BDF ENTRY 2
> - [Offset 0x14] BDF ENTRY 3
> - [Offset 0x18] BDF ENTRY 4
> - ...
> - [Offset 0x--] BDF ENTRY N
> - --------------------------------------------
> -**/
> -
> -/**
> - Value returned for reads on configuration space of unimplemented
> - device functions.
> -**/
> -STATIC UINTN mDummyConfigData = 0xFFFFFFFF;
> -
> -/**
> - Registers a PCI device so PCI configuration registers may be accessed after
> - SetVirtualAddressMap().
> -
> - Registers the PCI device specified by Address so all the PCI configuration
> - registers associated with that PCI device may be accessed after SetVirtualAddressMap()
> - is called.
> -
> - If Address > 0x0FFFFFFF, then ASSERT().
> -
> - @param Address The address that encodes the PCI Bus, Device, Function and
> - Register.
> -
> - @retval RETURN_SUCCESS The PCI device was registered for runtime access.
> - @retval RETURN_UNSUPPORTED An attempt was made to call this function
> - after ExitBootServices().
> - @retval RETURN_UNSUPPORTED The resources required to access the PCI device
> - at runtime could not be mapped.
> - @retval RETURN_OUT_OF_RESOURCES There are not enough resources available to
> - complete the registration.
> -
> -**/
> -RETURN_STATUS
> -EFIAPI
> -PciExpressRegisterForRuntimeAccess (
> - IN UINTN Address
> - )
> -{
> - ASSERT_INVALID_PCI_ADDRESS (Address);
> - return RETURN_UNSUPPORTED;
> -}
> -
> -/**
> - Check if the requested PCI address can be safely accessed.
> -
> - SCP performs the initial bus scan, prepares a table of valid BDF addresses
> - and shares them through non-trusted SRAM. This function validates if the
> - requested PCI address belongs to a valid BDF by checking the table of valid
> - entries. If not, this function will return false. This is a workaround to
> - avoid bus fault that occurs when accessing unavailable PCI device due to
> - hardware bug.
> -
> - @param Address The address that encodes the PCI Bus, Device, Function and
> - Register.
> -
> - @return TRUE BDF can be accessed, valid.
> - @return FALSE BDF should not be accessed, invalid.
> -
> -**/
> -STATIC
> -BOOLEAN
> -IsBdfValid (
> - IN UINTN Address
> - )
> -{
> - UINTN BdfCount;
> - UINTN BdfValue;
> - UINTN BdfEntry;
> - UINTN Count;
> - UINTN TableBase;
> - UINTN ConfigBase;
> -
> - ConfigBase = Address & ~0xFFF;
> - TableBase = NEOVERSEN1SOC_NON_SECURE_SRAM_BASE + PCIE_BDF_TABLE_OFFSET;
> - BdfCount = MmioRead32 (TableBase + BDF_TABLE_ENTRY_SIZE);
> - BdfEntry = TableBase + BDF_TABLE_HEADER_SIZE;
> -
> - /* Skip the header & check remaining entry */
> - for (Count = 0; Count < BdfCount; Count++, BdfEntry += BDF_TABLE_ENTRY_SIZE) {
> - BdfValue = MmioRead32 (BdfEntry);
> - if (BdfValue == ConfigBase) {
> - return TRUE;
> - }
> - }
> -
> - return FALSE;
> -}
> -
> -/**
> - Get the physical address of a configuration space register.
> -
> - Implement a workaround to avoid generation of slave errors from the bus. That
> - is, retrieve the PCI Express Base Address via a PCD entry, add the incomming
> - address with that base address and check whether this converted address
> - points to a accessible BDF. If it is not accessible, return the address
> - of a dummy location so that a read from it does not cause a slave error.
> -
> - In addition to this, implement a workaround for accessing the root port's
> - configuration space. The root port configuration space is not contiguous
> - with the rest of the downstream hierarchy configuration space. So determine
> - whether the specified address is for the root port and use a different base
> - address for it.
> -
> - @param Address The address that encodes the PCI Bus, Device, Function and
> - Register.
> -
> - @return Physical address of the configuration register that corresponds to the
> - PCI configuration register specified by input parameter 'Address'.
> -
> -**/
> -STATIC
> -VOID*
> -GetPciExpressAddress (
> - IN UINTN Address
> - )
> -{
> - UINT8 Bus, Device, Function;
> - UINTN ConfigAddress;
> -
> - Bus = GET_BUS_NUM (Address);
> - Device = GET_DEV_NUM (Address);
> - Function = GET_FUNC_NUM (Address);
> -
> - if ((Bus == 0) && (Device == 0) && (Function == 0)) {
> - ConfigAddress = PcdGet32 (PcdPcieRootPortConfigBaseAddress) + Address;
> - } else {
> - ConfigAddress = PcdGet64 (PcdPciExpressBaseAddress) + Address;
> - if (!IsBdfValid(Address)) {
> - ConfigAddress = (UINTN)&mDummyConfigData;
> - }
> - }
> -
> - return (VOID *)ConfigAddress;
> -}
> -
> -/**
> - Reads an 8-bit PCI configuration register.
> -
> - Reads and returns the 8-bit PCI configuration register specified by Address.
> - This function must guarantee that all PCI read and write operations are
> - serialized.
> -
> - If Address > 0x0FFFFFFF, then ASSERT().
> -
> - @param Address The address that encodes the PCI Bus, Device, Function and
> - Register.
> -
> - @return The read value from the PCI configuration register.
> -
> -**/
> -UINT8
> -EFIAPI
> -PciExpressRead8 (
> - IN UINTN Address
> - )
> -{
> - ASSERT_INVALID_PCI_ADDRESS (Address);
> - return MmioRead8 ((UINTN)GetPciExpressAddress (Address));
> -}
> -
> -/**
> - Writes an 8-bit PCI configuration register.
> -
> - Writes the 8-bit PCI configuration register specified by Address with the
> - value specified by Value. Value is returned. This function must guarantee
> - that all PCI read and write operations are serialized.
> -
> - If Address > 0x0FFFFFFF, then ASSERT().
> -
> - @param Address The address that encodes the PCI Bus, Device, Function and
> - Register.
> - @param Value The value to write.
> -
> - @return The value written to the PCI configuration register.
> -
> -**/
> -UINT8
> -EFIAPI
> -PciExpressWrite8 (
> - IN UINTN Address,
> - IN UINT8 Value
> - )
> -{
> - UINT8 Bus, Device, Function;
> - UINT8 Offset;
> - UINT32 Data;
> -
> - ASSERT_INVALID_PCI_ADDRESS (Address);
> -
> - Bus = GET_BUS_NUM (Address);
> - Device = GET_DEV_NUM (Address);
> - Function = GET_FUNC_NUM (Address);
> -
> - //
> - // 8-bit and 16-bit writes to root port config space is not supported due to
> - // a hardware limitation. As a workaround, perform a read-update-write
> - // sequence on the whole 32-bit word of the root port config register such
> - // that only the specified 8-bits of that word are updated.
> - //
> - if ((Bus == 0) && (Device == 0) && (Function == 0)) {
> - Offset = Address & 0x3;
> - Address &= 0xFFFFFFFC;
> - Data = MmioRead32 ((UINTN)GetPciExpressAddress (Address));
> - Data &= ~(0xFF << (8 * Offset));
> - Data |= (Value << (8 * Offset));
> - MmioWrite32 ((UINTN)GetPciExpressAddress (Address), Data);
> - return Value;
> - }
> -
> - return MmioWrite8 ((UINTN)GetPciExpressAddress (Address), Value);
> -}
> -
> -/**
> - Performs a bitwise OR of an 8-bit PCI configuration register with
> - an 8-bit value.
> -
> - Reads the 8-bit PCI configuration register specified by Address, performs a
> - bitwise OR between the read result and the value specified by
> - OrData, and writes the result to the 8-bit PCI configuration register
> - specified by Address. The value written to the PCI configuration register is
> - returned. This function must guarantee that all PCI read and write operations
> - are serialized.
> -
> - If Address > 0x0FFFFFFF, then ASSERT().
> -
> - @param Address The address that encodes the PCI Bus, Device, Function and
> - Register.
> - @param OrData The value to OR with the PCI configuration register.
> -
> - @return The value written back to the PCI configuration register.
> -
> -**/
> -UINT8
> -EFIAPI
> -PciExpressOr8 (
> - IN UINTN Address,
> - IN UINT8 OrData
> - )
> -{
> - ASSERT_INVALID_PCI_ADDRESS (Address);
> - return MmioOr8 ((UINTN)GetPciExpressAddress (Address), OrData);
> -}
> -
> -/**
> - Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
> - value.
> -
> - Reads the 8-bit PCI configuration register specified by Address, performs a
> - bitwise AND between the read result and the value specified by AndData, and
> - writes the result to the 8-bit PCI configuration register specified by
> - Address. The value written to the PCI configuration register is returned.
> - This function must guarantee that all PCI read and write operations are
> - serialized.
> -
> - If Address > 0x0FFFFFFF, then ASSERT().
> -
> - @param Address The address that encodes the PCI Bus, Device, Function and
> - Register.
> - @param AndData The value to AND with the PCI configuration register.
> -
> - @return The value written back to the PCI configuration register.
> -
> -**/
> -UINT8
> -EFIAPI
> -PciExpressAnd8 (
> - IN UINTN Address,
> - IN UINT8 AndData
> - )
> -{
> - ASSERT_INVALID_PCI_ADDRESS (Address);
> - return MmioAnd8 ((UINTN)GetPciExpressAddress (Address), AndData);
> -}
> -
> -/**
> - Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
> - value, followed a bitwise OR with another 8-bit value.
> -
> - Reads the 8-bit PCI configuration register specified by Address, performs a
> - bitwise AND between the read result and the value specified by AndData,
> - performs a bitwise OR between the result of the AND operation and
> - the value specified by OrData, and writes the result to the 8-bit PCI
> - configuration register specified by Address. The value written to the PCI
> - configuration register is returned. This function must guarantee that all PCI
> - read and write operations are serialized.
> -
> - If Address > 0x0FFFFFFF, then ASSERT().
> -
> - @param Address The address that encodes the PCI Bus, Device, Function and
> - Register.
> - @param AndData The value to AND with the PCI configuration register.
> - @param OrData The value to OR with the result of the AND operation.
> -
> - @return The value written back to the PCI configuration register.
> -
> -**/
> -UINT8
> -EFIAPI
> -PciExpressAndThenOr8 (
> - IN UINTN Address,
> - IN UINT8 AndData,
> - IN UINT8 OrData
> - )
> -{
> - ASSERT_INVALID_PCI_ADDRESS (Address);
> - return MmioAndThenOr8 (
> - (UINTN)GetPciExpressAddress (Address),
> - AndData,
> - OrData
> - );
> -}
> -
> -/**
> - Reads a bit field of a PCI configuration register.
> -
> - Reads the bit field in an 8-bit PCI configuration register. The bit field is
> - specified by the StartBit and the EndBit. The value of the bit field is
> - returned.
> -
> - If Address > 0x0FFFFFFF, then ASSERT().
> - If StartBit is greater than 7, then ASSERT().
> - If EndBit is greater than 7, then ASSERT().
> - If EndBit is less than StartBit, then ASSERT().
> -
> - @param Address The PCI configuration register to read.
> - @param StartBit The ordinal of the least significant bit in the bit field.
> - Range 0..7.
> - @param EndBit The ordinal of the most significant bit in the bit field.
> - Range 0..7.
> -
> - @return The value of the bit field read from the PCI configuration register.
> -
> -**/
> -UINT8
> -EFIAPI
> -PciExpressBitFieldRead8 (
> - IN UINTN Address,
> - IN UINTN StartBit,
> - IN UINTN EndBit
> - )
> -{
> - ASSERT_INVALID_PCI_ADDRESS (Address);
> - return MmioBitFieldRead8 (
> - (UINTN)GetPciExpressAddress (Address),
> - StartBit,
> - EndBit
> - );
> -}
> -
> -/**
> - Writes a bit field to a PCI configuration register.
> -
> - Writes Value to the bit field of the PCI configuration register. The bit
> - field is specified by the StartBit and the EndBit. All other bits in the
> - destination PCI configuration register are preserved. The new value of the
> - 8-bit register is returned.
> -
> - If Address > 0x0FFFFFFF, then ASSERT().
> - If StartBit is greater than 7, then ASSERT().
> - If EndBit is greater than 7, then ASSERT().
> - If EndBit is less than StartBit, then ASSERT().
> - If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
> -
> - @param Address The PCI configuration register to write.
> - @param StartBit The ordinal of the least significant bit in the bit field.
> - Range 0..7.
> - @param EndBit The ordinal of the most significant bit in the bit field.
> - Range 0..7.
> - @param Value The new value of the bit field.
> -
> - @return The value written back to the PCI configuration register.
> -
> -**/
> -UINT8
> -EFIAPI
> -PciExpressBitFieldWrite8 (
> - IN UINTN Address,
> - IN UINTN StartBit,
> - IN UINTN EndBit,
> - IN UINT8 Value
> - )
> -{
> - ASSERT_INVALID_PCI_ADDRESS (Address);
> - return MmioBitFieldWrite8 (
> - (UINTN)GetPciExpressAddress (Address),
> - StartBit,
> - EndBit,
> - Value
> - );
> -}
> -
> -/**
> - Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and
> - writes the result back to the bit field in the 8-bit port.
> -
> - Reads the 8-bit PCI configuration register specified by Address, performs a
> - bitwise OR between the read result and the value specified by
> - OrData, and writes the result to the 8-bit PCI configuration register
> - specified by Address. The value written to the PCI configuration register is
> - returned. This function must guarantee that all PCI read and write operations
> - are serialized. Extra left bits in OrData are stripped.
> -
> - If Address > 0x0FFFFFFF, then ASSERT().
> - If StartBit is greater than 7, then ASSERT().
> - If EndBit is greater than 7, then ASSERT().
> - If EndBit is less than StartBit, then ASSERT().
> - If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
> -
> - @param Address The PCI configuration register to write.
> - @param StartBit The ordinal of the least significant bit in the bit field.
> - Range 0..7.
> - @param EndBit The ordinal of the most significant bit in the bit field.
> - Range 0..7.
> - @param OrData The value to OR with the PCI configuration register.
> -
> - @return The value written back to the PCI configuration register.
> -
> -**/
> -UINT8
> -EFIAPI
> -PciExpressBitFieldOr8 (
> - IN UINTN Address,
> - IN UINTN StartBit,
> - IN UINTN EndBit,
> - IN UINT8 OrData
> - )
> -{
> - ASSERT_INVALID_PCI_ADDRESS (Address);
> - return MmioBitFieldOr8 (
> - (UINTN)GetPciExpressAddress (Address),
> - StartBit,
> - EndBit,
> - OrData
> - );
> -}
> -
> -/**
> - Reads a bit field in an 8-bit PCI configuration register, performs a bitwise
> - AND, and writes the result back to the bit field in the 8-bit register.
> -
> - Reads the 8-bit PCI configuration register specified by Address, performs a
> - bitwise AND between the read result and the value specified by AndData, and
> - writes the result to the 8-bit PCI configuration register specified by
> - Address. The value written to the PCI configuration register is returned.
> - This function must guarantee that all PCI read and write operations are
> - serialized. Extra left bits in AndData are stripped.
> -
> - If Address > 0x0FFFFFFF, then ASSERT().
> - If StartBit is greater than 7, then ASSERT().
> - If EndBit is greater than 7, then ASSERT().
> - If EndBit is less than StartBit, then ASSERT().
> - If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
> -
> - @param Address The PCI configuration register to write.
> - @param StartBit The ordinal of the least significant bit in the bit field.
> - Range 0..7.
> - @param EndBit The ordinal of the most significant bit in the bit field.
> - Range 0..7.
> - @param AndData The value to AND with the PCI configuration register.
> -
> - @return The value written back to the PCI configuration register.
> -
> -**/
> -UINT8
> -EFIAPI
> -PciExpressBitFieldAnd8 (
> - IN UINTN Address,
> - IN UINTN StartBit,
> - IN UINTN EndBit,
> - IN UINT8 AndData
> - )
> -{
> - ASSERT_INVALID_PCI_ADDRESS (Address);
> - return MmioBitFieldAnd8 (
> - (UINTN)GetPciExpressAddress (Address),
> - StartBit,
> - EndBit,
> - AndData
> - );
> -}
> -
> -/**
> - Reads a bit field in an 8-bit port, performs a bitwise AND followed by a
> - bitwise OR, and writes the result back to the bit field in the
> - 8-bit port.
> -
> - Reads the 8-bit PCI configuration register specified by Address, performs a
> - bitwise AND followed by a bitwise OR between the read result and
> - the value specified by AndData, and writes the result to the 8-bit PCI
> - configuration register specified by Address. The value written to the PCI
> - configuration register is returned. This function must guarantee that all PCI
> - read and write operations are serialized. Extra left bits in both AndData and
> - OrData are stripped.
> -
> - If Address > 0x0FFFFFFF, then ASSERT().
> - If StartBit is greater than 7, then ASSERT().
> - If EndBit is greater than 7, then ASSERT().
> - If EndBit is less than StartBit, then ASSERT().
> - If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
> - If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
> -
> - @param Address The PCI configuration register to write.
> - @param StartBit The ordinal of the least significant bit in the bit field.
> - Range 0..7.
> - @param EndBit The ordinal of the most significant bit in the bit field.
> - Range 0..7.
> - @param AndData The value to AND with the PCI configuration register.
> - @param OrData The value to OR with the result of the AND operation.
> -
> - @return The value written back to the PCI configuration register.
> -
> -**/
> -UINT8
> -EFIAPI
> -PciExpressBitFieldAndThenOr8 (
> - IN UINTN Address,
> - IN UINTN StartBit,
> - IN UINTN EndBit,
> - IN UINT8 AndData,
> - IN UINT8 OrData
> - )
> -{
> - ASSERT_INVALID_PCI_ADDRESS (Address);
> - return MmioBitFieldAndThenOr8 (
> - (UINTN)GetPciExpressAddress (Address),
> - StartBit,
> - EndBit,
> - AndData,
> - OrData
> - );
> -}
> -
> -/**
> - Reads a 16-bit PCI configuration register.
> -
> - Reads and returns the 16-bit PCI configuration register specified by Address.
> - This function must guarantee that all PCI read and write operations are
> - serialized.
> -
> - If Address > 0x0FFFFFFF, then ASSERT().
> - If Address is not aligned on a 16-bit boundary, then ASSERT().
> -
> - @param Address The address that encodes the PCI Bus, Device, Function and
> - Register.
> -
> - @return The read value from the PCI configuration register.
> -
> -**/
> -UINT16
> -EFIAPI
> -PciExpressRead16 (
> - IN UINTN Address
> - )
> -{
> - ASSERT_INVALID_PCI_ADDRESS (Address);
> - return MmioRead16 ((UINTN)GetPciExpressAddress (Address));
> -}
> -
> -/**
> - Writes a 16-bit PCI configuration register.
> -
> - Writes the 16-bit PCI configuration register specified by Address with the
> - value specified by Value. Value is returned. This function must guarantee
> - that all PCI read and write operations are serialized.
> -
> - If Address > 0x0FFFFFFF, then ASSERT().
> - If Address is not aligned on a 16-bit boundary, then ASSERT().
> -
> - @param Address The address that encodes the PCI Bus, Device, Function and
> - Register.
> - @param Value The value to write.
> -
> - @return The value written to the PCI configuration register.
> -
> -**/
> -UINT16
> -EFIAPI
> -PciExpressWrite16 (
> - IN UINTN Address,
> - IN UINT16 Value
> - )
> -{
> - UINT8 Bus, Device, Function;
> - UINT8 Offset;
> - UINT32 Data;
> -
> - ASSERT_INVALID_PCI_ADDRESS (Address);
> -
> - Bus = GET_BUS_NUM (Address);
> - Device = GET_DEV_NUM (Address);
> - Function = GET_FUNC_NUM (Address);
> -
> - //
> - // 8-bit and 16-bit writes to root port config space is not supported due to
> - // a hardware limitation. As a workaround, perform a read-update-write
> - // sequence on the whole 32-bit word of the root port config register such
> - // that only the specified 16-bits of that word are updated.
> - //
> - if ((Bus == 0) && (Device == 0) && (Function == 0)) {
> - Offset = Address & 0x3;
> - Address &= 0xFFFFFFFC;
> - Data = MmioRead32 ((UINTN)GetPciExpressAddress (Address));
> - Data &= ~(0xFFFF << (8 * Offset));
> - Data |= (Value << (8 * Offset));
> - MmioWrite32 ((UINTN)GetPciExpressAddress (Address), Data);
> - return Value;
> - }
> -
> - return MmioWrite16 ((UINTN)GetPciExpressAddress (Address), Value);
> -}
> -
> -/**
> - Performs a bitwise OR of a 16-bit PCI configuration register with
> - a 16-bit value.
> -
> - Reads the 16-bit PCI configuration register specified by Address, performs a
> - bitwise OR between the read result and the value specified by
> - OrData, and writes the result to the 16-bit PCI configuration register
> - specified by Address. The value written to the PCI configuration register is
> - returned. This function must guarantee that all PCI read and write operations
> - are serialized.
> -
> - If Address > 0x0FFFFFFF, then ASSERT().
> - If Address is not aligned on a 16-bit boundary, then ASSERT().
> -
> - @param Address The address that encodes the PCI Bus, Device, Function and
> - Register.
> - @param OrData The value to OR with the PCI configuration register.
> -
> - @return The value written back to the PCI configuration register.
> -
> -**/
> -UINT16
> -EFIAPI
> -PciExpressOr16 (
> - IN UINTN Address,
> - IN UINT16 OrData
> - )
> -{
> - ASSERT_INVALID_PCI_ADDRESS (Address);
> - return MmioOr16 ((UINTN)GetPciExpressAddress (Address), OrData);
> -}
> -
> -/**
> - Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
> - value.
> -
> - Reads the 16-bit PCI configuration register specified by Address, performs a
> - bitwise AND between the read result and the value specified by AndData, and
> - writes the result to the 16-bit PCI configuration register specified by
> - Address. The value written to the PCI configuration register is returned.
> - This function must guarantee that all PCI read and write operations are
> - serialized.
> -
> - If Address > 0x0FFFFFFF, then ASSERT().
> - If Address is not aligned on a 16-bit boundary, then ASSERT().
> -
> - @param Address The address that encodes the PCI Bus, Device, Function and
> - Register.
> - @param AndData The value to AND with the PCI configuration register.
> -
> - @return The value written back to the PCI configuration register.
> -
> -**/
> -UINT16
> -EFIAPI
> -PciExpressAnd16 (
> - IN UINTN Address,
> - IN UINT16 AndData
> - )
> -{
> - ASSERT_INVALID_PCI_ADDRESS (Address);
> - return MmioAnd16 ((UINTN)GetPciExpressAddress (Address), AndData);
> -}
> -
> -/**
> - Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
> - value, followed a bitwise OR with another 16-bit value.
> -
> - Reads the 16-bit PCI configuration register specified by Address, performs a
> - bitwise AND between the read result and the value specified by AndData,
> - performs a bitwise OR between the result of the AND operation and
> - the value specified by OrData, and writes the result to the 16-bit PCI
> - configuration register specified by Address. The value written to the PCI
> - configuration register is returned. This function must guarantee that all PCI
> - read and write operations are serialized.
> -
> - If Address > 0x0FFFFFFF, then ASSERT().
> - If Address is not aligned on a 16-bit boundary, then ASSERT().
> -
> - @param Address The address that encodes the PCI Bus, Device, Function and
> - Register.
> - @param AndData The value to AND with the PCI configuration register.
> - @param OrData The value to OR with the result of the AND operation.
> -
> - @return The value written back to the PCI configuration register.
> -
> -**/
> -UINT16
> -EFIAPI
> -PciExpressAndThenOr16 (
> - IN UINTN Address,
> - IN UINT16 AndData,
> - IN UINT16 OrData
> - )
> -{
> - ASSERT_INVALID_PCI_ADDRESS (Address);
> - return MmioAndThenOr16 (
> - (UINTN)GetPciExpressAddress (Address),
> - AndData,
> - OrData
> - );
> -}
> -
> -/**
> - Reads a bit field of a PCI configuration register.
> -
> - Reads the bit field in a 16-bit PCI configuration register. The bit field is
> - specified by the StartBit and the EndBit. The value of the bit field is
> - returned.
> -
> - If Address > 0x0FFFFFFF, then ASSERT().
> - If Address is not aligned on a 16-bit boundary, then ASSERT().
> - If StartBit is greater than 15, then ASSERT().
> - If EndBit is greater than 15, then ASSERT().
> - If EndBit is less than StartBit, then ASSERT().
> -
> - @param Address The PCI configuration register to read.
> - @param StartBit The ordinal of the least significant bit in the bit field.
> - Range 0..15.
> - @param EndBit The ordinal of the most significant bit in the bit field.
> - Range 0..15.
> -
> - @return The value of the bit field read from the PCI configuration register.
> -
> -**/
> -UINT16
> -EFIAPI
> -PciExpressBitFieldRead16 (
> - IN UINTN Address,
> - IN UINTN StartBit,
> - IN UINTN EndBit
> - )
> -{
> - ASSERT_INVALID_PCI_ADDRESS (Address);
> - return MmioBitFieldRead16 (
> - (UINTN)GetPciExpressAddress (Address),
> - StartBit,
> - EndBit
> - );
> -}
> -
> -/**
> - Writes a bit field to a PCI configuration register.
> -
> - Writes Value to the bit field of the PCI configuration register. The bit
> - field is specified by the StartBit and the EndBit. All other bits in the
> - destination PCI configuration register are preserved. The new value of the
> - 16-bit register is returned.
> -
> - If Address > 0x0FFFFFFF, then ASSERT().
> - If Address is not aligned on a 16-bit boundary, then ASSERT().
> - If StartBit is greater than 15, then ASSERT().
> - If EndBit is greater than 15, then ASSERT().
> - If EndBit is less than StartBit, then ASSERT().
> - If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
> -
> - @param Address The PCI configuration register to write.
> - @param StartBit The ordinal of the least significant bit in the bit field.
> - Range 0..15.
> - @param EndBit The ordinal of the most significant bit in the bit field.
> - Range 0..15.
> - @param Value The new value of the bit field.
> -
> - @return The value written back to the PCI configuration register.
> -
> -**/
> -UINT16
> -EFIAPI
> -PciExpressBitFieldWrite16 (
> - IN UINTN Address,
> - IN UINTN StartBit,
> - IN UINTN EndBit,
> - IN UINT16 Value
> - )
> -{
> - ASSERT_INVALID_PCI_ADDRESS (Address);
> - return MmioBitFieldWrite16 (
> - (UINTN)GetPciExpressAddress (Address),
> - StartBit,
> - EndBit,
> - Value
> - );
> -}
> -
> -/**
> - Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and
> - writes the result back to the bit field in the 16-bit port.
> -
> - Reads the 16-bit PCI configuration register specified by Address, performs a
> - bitwise OR between the read result and the value specified by
> - OrData, and writes the result to the 16-bit PCI configuration register
> - specified by Address. The value written to the PCI configuration register is
> - returned. This function must guarantee that all PCI read and write operations
> - are serialized. Extra left bits in OrData are stripped.
> -
> - If Address > 0x0FFFFFFF, then ASSERT().
> - If Address is not aligned on a 16-bit boundary, then ASSERT().
> - If StartBit is greater than 15, then ASSERT().
> - If EndBit is greater than 15, then ASSERT().
> - If EndBit is less than StartBit, then ASSERT().
> - If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
> -
> - @param Address The PCI configuration register to write.
> - @param StartBit The ordinal of the least significant bit in the bit field.
> - Range 0..15.
> - @param EndBit The ordinal of the most significant bit in the bit field.
> - Range 0..15.
> - @param OrData The value to OR with the PCI configuration register.
> -
> - @return The value written back to the PCI configuration register.
> -
> -**/
> -UINT16
> -EFIAPI
> -PciExpressBitFieldOr16 (
> - IN UINTN Address,
> - IN UINTN StartBit,
> - IN UINTN EndBit,
> - IN UINT16 OrData
> - )
> -{
> - ASSERT_INVALID_PCI_ADDRESS (Address);
> - return MmioBitFieldOr16 (
> - (UINTN)GetPciExpressAddress (Address),
> - StartBit,
> - EndBit,
> - OrData
> - );
> -}
> -
> -/**
> - Reads a bit field in a 16-bit PCI configuration register, performs a bitwise
> - AND, and writes the result back to the bit field in the 16-bit register.
> -
> - Reads the 16-bit PCI configuration register specified by Address, performs a
> - bitwise AND between the read result and the value specified by AndData, and
> - writes the result to the 16-bit PCI configuration register specified by
> - Address. The value written to the PCI configuration register is returned.
> - This function must guarantee that all PCI read and write operations are
> - serialized. Extra left bits in AndData are stripped.
> -
> - If Address > 0x0FFFFFFF, then ASSERT().
> - If Address is not aligned on a 16-bit boundary, then ASSERT().
> - If StartBit is greater than 15, then ASSERT().
> - If EndBit is greater than 15, then ASSERT().
> - If EndBit is less than StartBit, then ASSERT().
> - If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
> -
> - @param Address The PCI configuration register to write.
> - @param StartBit The ordinal of the least significant bit in the bit field.
> - Range 0..15.
> - @param EndBit The ordinal of the most significant bit in the bit field.
> - Range 0..15.
> - @param AndData The value to AND with the PCI configuration register.
> -
> - @return The value written back to the PCI configuration register.
> -
> -**/
> -UINT16
> -EFIAPI
> -PciExpressBitFieldAnd16 (
> - IN UINTN Address,
> - IN UINTN StartBit,
> - IN UINTN EndBit,
> - IN UINT16 AndData
> - )
> -{
> - ASSERT_INVALID_PCI_ADDRESS (Address);
> - return MmioBitFieldAnd16 (
> - (UINTN)GetPciExpressAddress (Address),
> - StartBit,
> - EndBit,
> - AndData
> - );
> -}
> -
> -/**
> - Reads a bit field in a 16-bit port, performs a bitwise AND followed by a
> - bitwise OR, and writes the result back to the bit field in the
> - 16-bit port.
> -
> - Reads the 16-bit PCI configuration register specified by Address, performs a
> - bitwise AND followed by a bitwise OR between the read result and
> - the value specified by AndData, and writes the result to the 16-bit PCI
> - configuration register specified by Address. The value written to the PCI
> - configuration register is returned. This function must guarantee that all PCI
> - read and write operations are serialized. Extra left bits in both AndData and
> - OrData are stripped.
> -
> - If Address > 0x0FFFFFFF, then ASSERT().
> - If Address is not aligned on a 16-bit boundary, then ASSERT().
> - If StartBit is greater than 15, then ASSERT().
> - If EndBit is greater than 15, then ASSERT().
> - If EndBit is less than StartBit, then ASSERT().
> - If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
> - If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
> -
> - @param Address The PCI configuration register to write.
> - @param StartBit The ordinal of the least significant bit in the bit field.
> - Range 0..15.
> - @param EndBit The ordinal of the most significant bit in the bit field.
> - Range 0..15.
> - @param AndData The value to AND with the PCI configuration register.
> - @param OrData The value to OR with the result of the AND operation.
> -
> - @return The value written back to the PCI configuration register.
> -
> -**/
> -UINT16
> -EFIAPI
> -PciExpressBitFieldAndThenOr16 (
> - IN UINTN Address,
> - IN UINTN StartBit,
> - IN UINTN EndBit,
> - IN UINT16 AndData,
> - IN UINT16 OrData
> - )
> -{
> - ASSERT_INVALID_PCI_ADDRESS (Address);
> - return MmioBitFieldAndThenOr16 (
> - (UINTN)GetPciExpressAddress (Address),
> - StartBit,
> - EndBit,
> - AndData,
> - OrData
> - );
> -}
> -
> -/**
> - Reads a 32-bit PCI configuration register.
> -
> - Reads and returns the 32-bit PCI configuration register specified by Address.
> - This function must guarantee that all PCI read and write operations are
> - serialized.
> -
> - If Address > 0x0FFFFFFF, then ASSERT().
> - If Address is not aligned on a 32-bit boundary, then ASSERT().
> -
> - @param Address The address that encodes the PCI Bus, Device, Function and
> - Register.
> -
> - @return The read value from the PCI configuration register.
> -
> -**/
> -UINT32
> -EFIAPI
> -PciExpressRead32 (
> - IN UINTN Address
> - )
> -{
> - ASSERT_INVALID_PCI_ADDRESS (Address);
> - return MmioRead32 ((UINTN)GetPciExpressAddress (Address));
> -}
> -
> -/**
> - Writes a 32-bit PCI configuration register.
> -
> - Writes the 32-bit PCI configuration register specified by Address with the
> - value specified by Value. Value is returned. This function must guarantee
> - that all PCI read and write operations are serialized.
> -
> - If Address > 0x0FFFFFFF, then ASSERT().
> - If Address is not aligned on a 32-bit boundary, then ASSERT().
> -
> - @param Address The address that encodes the PCI Bus, Device, Function and
> - Register.
> - @param Value The value to write.
> -
> - @return The value written to the PCI configuration register.
> -
> -**/
> -UINT32
> -EFIAPI
> -PciExpressWrite32 (
> - IN UINTN Address,
> - IN UINT32 Value
> - )
> -{
> - ASSERT_INVALID_PCI_ADDRESS (Address);
> - return MmioWrite32 ((UINTN)GetPciExpressAddress (Address), Value);
> -}
> -
> -/**
> - Performs a bitwise OR of a 32-bit PCI configuration register with
> - a 32-bit value.
> -
> - Reads the 32-bit PCI configuration register specified by Address, performs a
> - bitwise OR between the read result and the value specified by
> - OrData, and writes the result to the 32-bit PCI configuration register
> - specified by Address. The value written to the PCI configuration register is
> - returned. This function must guarantee that all PCI read and write operations
> - are serialized.
> -
> - If Address > 0x0FFFFFFF, then ASSERT().
> - If Address is not aligned on a 32-bit boundary, then ASSERT().
> -
> - @param Address The address that encodes the PCI Bus, Device, Function and
> - Register.
> - @param OrData The value to OR with the PCI configuration register.
> -
> - @return The value written back to the PCI configuration register.
> -
> -**/
> -UINT32
> -EFIAPI
> -PciExpressOr32 (
> - IN UINTN Address,
> - IN UINT32 OrData
> - )
> -{
> - ASSERT_INVALID_PCI_ADDRESS (Address);
> - return MmioOr32 ((UINTN)GetPciExpressAddress (Address), OrData);
> -}
> -
> -/**
> - Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
> - value.
> -
> - Reads the 32-bit PCI configuration register specified by Address, performs a
> - bitwise AND between the read result and the value specified by AndData, and
> - writes the result to the 32-bit PCI configuration register specified by
> - Address. The value written to the PCI configuration register is returned.
> - This function must guarantee that all PCI read and write operations are
> - serialized.
> -
> - If Address > 0x0FFFFFFF, then ASSERT().
> - If Address is not aligned on a 32-bit boundary, then ASSERT().
> -
> - @param Address The address that encodes the PCI Bus, Device, Function and
> - Register.
> - @param AndData The value to AND with the PCI configuration register.
> -
> - @return The value written back to the PCI configuration register.
> -
> -**/
> -UINT32
> -EFIAPI
> -PciExpressAnd32 (
> - IN UINTN Address,
> - IN UINT32 AndData
> - )
> -{
> - ASSERT_INVALID_PCI_ADDRESS (Address);
> - return MmioAnd32 ((UINTN)GetPciExpressAddress (Address), AndData);
> -}
> -
> -/**
> - Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
> - value, followed a bitwise OR with another 32-bit value.
> -
> - Reads the 32-bit PCI configuration register specified by Address, performs a
> - bitwise AND between the read result and the value specified by AndData,
> - performs a bitwise OR between the result of the AND operation and
> - the value specified by OrData, and writes the result to the 32-bit PCI
> - configuration register specified by Address. The value written to the PCI
> - configuration register is returned. This function must guarantee that all PCI
> - read and write operations are serialized.
> -
> - If Address > 0x0FFFFFFF, then ASSERT().
> - If Address is not aligned on a 32-bit boundary, then ASSERT().
> -
> - @param Address The address that encodes the PCI Bus, Device, Function and
> - Register.
> - @param AndData The value to AND with the PCI configuration register.
> - @param OrData The value to OR with the result of the AND operation.
> -
> - @return The value written back to the PCI configuration register.
> -
> -**/
> -UINT32
> -EFIAPI
> -PciExpressAndThenOr32 (
> - IN UINTN Address,
> - IN UINT32 AndData,
> - IN UINT32 OrData
> - )
> -{
> - ASSERT_INVALID_PCI_ADDRESS (Address);
> - return MmioAndThenOr32 (
> - (UINTN)GetPciExpressAddress (Address),
> - AndData,
> - OrData
> - );
> -}
> -
> -/**
> - Reads a bit field of a PCI configuration register.
> -
> - Reads the bit field in a 32-bit PCI configuration register. The bit field is
> - specified by the StartBit and the EndBit. The value of the bit field is
> - returned.
> -
> - If Address > 0x0FFFFFFF, then ASSERT().
> - If Address is not aligned on a 32-bit boundary, then ASSERT().
> - If StartBit is greater than 31, then ASSERT().
> - If EndBit is greater than 31, then ASSERT().
> - If EndBit is less than StartBit, then ASSERT().
> -
> - @param Address The PCI configuration register to read.
> - @param StartBit The ordinal of the least significant bit in the bit field.
> - Range 0..31.
> - @param EndBit The ordinal of the most significant bit in the bit field.
> - Range 0..31.
> -
> - @return The value of the bit field read from the PCI configuration register.
> -
> -**/
> -UINT32
> -EFIAPI
> -PciExpressBitFieldRead32 (
> - IN UINTN Address,
> - IN UINTN StartBit,
> - IN UINTN EndBit
> - )
> -{
> - ASSERT_INVALID_PCI_ADDRESS (Address);
> - return MmioBitFieldRead32 (
> - (UINTN)GetPciExpressAddress (Address),
> - StartBit,
> - EndBit
> - );
> -}
> -
> -/**
> - Writes a bit field to a PCI configuration register.
> -
> - Writes Value to the bit field of the PCI configuration register. The bit
> - field is specified by the StartBit and the EndBit. All other bits in the
> - destination PCI configuration register are preserved. The new value of the
> - 32-bit register is returned.
> -
> - If Address > 0x0FFFFFFF, then ASSERT().
> - If Address is not aligned on a 32-bit boundary, then ASSERT().
> - If StartBit is greater than 31, then ASSERT().
> - If EndBit is greater than 31, then ASSERT().
> - If EndBit is less than StartBit, then ASSERT().
> - If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
> -
> - @param Address The PCI configuration register to write.
> - @param StartBit The ordinal of the least significant bit in the bit field.
> - Range 0..31.
> - @param EndBit The ordinal of the most significant bit in the bit field.
> - Range 0..31.
> - @param Value The new value of the bit field.
> -
> - @return The value written back to the PCI configuration register.
> -
> -**/
> -UINT32
> -EFIAPI
> -PciExpressBitFieldWrite32 (
> - IN UINTN Address,
> - IN UINTN StartBit,
> - IN UINTN EndBit,
> - IN UINT32 Value
> - )
> -{
> - ASSERT_INVALID_PCI_ADDRESS (Address);
> - return MmioBitFieldWrite32 (
> - (UINTN)GetPciExpressAddress (Address),
> - StartBit,
> - EndBit,
> - Value
> - );
> -}
> -
> -/**
> - Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and
> - writes the result back to the bit field in the 32-bit port.
> -
> - Reads the 32-bit PCI configuration register specified by Address, performs a
> - bitwise OR between the read result and the value specified by
> - OrData, and writes the result to the 32-bit PCI configuration register
> - specified by Address. The value written to the PCI configuration register is
> - returned. This function must guarantee that all PCI read and write operations
> - are serialized. Extra left bits in OrData are stripped.
> -
> - If Address > 0x0FFFFFFF, then ASSERT().
> - If Address is not aligned on a 32-bit boundary, then ASSERT().
> - If StartBit is greater than 31, then ASSERT().
> - If EndBit is greater than 31, then ASSERT().
> - If EndBit is less than StartBit, then ASSERT().
> - If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
> -
> - @param Address The PCI configuration register to write.
> - @param StartBit The ordinal of the least significant bit in the bit field.
> - Range 0..31.
> - @param EndBit The ordinal of the most significant bit in the bit field.
> - Range 0..31.
> - @param OrData The value to OR with the PCI configuration register.
> -
> - @return The value written back to the PCI configuration register.
> -
> -**/
> -UINT32
> -EFIAPI
> -PciExpressBitFieldOr32 (
> - IN UINTN Address,
> - IN UINTN StartBit,
> - IN UINTN EndBit,
> - IN UINT32 OrData
> - )
> -{
> - ASSERT_INVALID_PCI_ADDRESS (Address);
> - return MmioBitFieldOr32 (
> - (UINTN)GetPciExpressAddress (Address),
> - StartBit,
> - EndBit,
> - OrData
> - );
> -}
> -
> -/**
> - Reads a bit field in a 32-bit PCI configuration register, performs a bitwise
> - AND, and writes the result back to the bit field in the 32-bit register.
> -
> - Reads the 32-bit PCI configuration register specified by Address, performs a
> - bitwise AND between the read result and the value specified by AndData, and
> - writes the result to the 32-bit PCI configuration register specified by
> - Address. The value written to the PCI configuration register is returned.
> - This function must guarantee that all PCI read and write operations are
> - serialized. Extra left bits in AndData are stripped.
> -
> - If Address > 0x0FFFFFFF, then ASSERT().
> - If Address is not aligned on a 32-bit boundary, then ASSERT().
> - If StartBit is greater than 31, then ASSERT().
> - If EndBit is greater than 31, then ASSERT().
> - If EndBit is less than StartBit, then ASSERT().
> - If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
> -
> - @param Address The PCI configuration register to write.
> - @param StartBit The ordinal of the least significant bit in the bit field.
> - Range 0..31.
> - @param EndBit The ordinal of the most significant bit in the bit field.
> - Range 0..31.
> - @param AndData The value to AND with the PCI configuration register.
> -
> - @return The value written back to the PCI configuration register.
> -
> -**/
> -UINT32
> -EFIAPI
> -PciExpressBitFieldAnd32 (
> - IN UINTN Address,
> - IN UINTN StartBit,
> - IN UINTN EndBit,
> - IN UINT32 AndData
> - )
> -{
> - ASSERT_INVALID_PCI_ADDRESS (Address);
> - return MmioBitFieldAnd32 (
> - (UINTN)GetPciExpressAddress (Address),
> - StartBit,
> - EndBit,
> - AndData
> - );
> -}
> -
> -/**
> - Reads a bit field in a 32-bit port, performs a bitwise AND followed by a
> - bitwise OR, and writes the result back to the bit field in the
> - 32-bit port.
> -
> - Reads the 32-bit PCI configuration register specified by Address, performs a
> - bitwise AND followed by a bitwise OR between the read result and
> - the value specified by AndData, and writes the result to the 32-bit PCI
> - configuration register specified by Address. The value written to the PCI
> - configuration register is returned. This function must guarantee that all PCI
> - read and write operations are serialized. Extra left bits in both AndData and
> - OrData are stripped.
> -
> - If Address > 0x0FFFFFFF, then ASSERT().
> - If Address is not aligned on a 32-bit boundary, then ASSERT().
> - If StartBit is greater than 31, then ASSERT().
> - If EndBit is greater than 31, then ASSERT().
> - If EndBit is less than StartBit, then ASSERT().
> - If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
> - If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
> -
> - @param Address The PCI configuration register to write.
> - @param StartBit The ordinal of the least significant bit in the bit field.
> - Range 0..31.
> - @param EndBit The ordinal of the most significant bit in the bit field.
> - Range 0..31.
> - @param AndData The value to AND with the PCI configuration register.
> - @param OrData The value to OR with the result of the AND operation.
> -
> - @return The value written back to the PCI configuration register.
> -
> -**/
> -UINT32
> -EFIAPI
> -PciExpressBitFieldAndThenOr32 (
> - IN UINTN Address,
> - IN UINTN StartBit,
> - IN UINTN EndBit,
> - IN UINT32 AndData,
> - IN UINT32 OrData
> - )
> -{
> - ASSERT_INVALID_PCI_ADDRESS (Address);
> - return MmioBitFieldAndThenOr32 (
> - (UINTN)GetPciExpressAddress (Address),
> - StartBit,
> - EndBit,
> - AndData,
> - OrData
> - );
> -}
> -
> -/**
> - Reads a range of PCI configuration registers into a caller supplied buffer.
> -
> - Reads the range of PCI configuration registers specified by StartAddress and
> - Size into the buffer specified by Buffer. This function only allows the PCI
> - configuration registers from a single PCI function to be read. Size is
> - returned. When possible 32-bit PCI configuration read cycles are used to read
> - from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit
> - and 16-bit PCI configuration read cycles may be used at the beginning and the
> - end of the range.
> -
> - If StartAddress > 0x0FFFFFFF, then ASSERT().
> - If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
> - If Size > 0 and Buffer is NULL, then ASSERT().
> -
> - @param StartAddress The starting address that encodes the PCI Bus, Device,
> - Function and Register.
> - @param Size The size in bytes of the transfer.
> - @param Buffer The pointer to a buffer receiving the data read.
> -
> - @return Size read data from StartAddress.
> -
> -**/
> -UINTN
> -EFIAPI
> -PciExpressReadBuffer (
> - IN UINTN StartAddress,
> - IN UINTN Size,
> - OUT VOID *Buffer
> - )
> -{
> - UINTN ReturnValue;
> -
> - ASSERT_INVALID_PCI_ADDRESS (StartAddress);
> - ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);
> -
> - if (Size == 0) {
> - return Size;
> - }
> -
> - ASSERT (Buffer != NULL);
> -
> - //
> - // Save Size for return
> - //
> - ReturnValue = Size;
> -
> - if ((StartAddress & 1) != 0) {
> - //
> - // Read a byte if StartAddress is byte aligned
> - //
> - *(volatile UINT8 *)Buffer = PciExpressRead8 (StartAddress);
> - StartAddress += sizeof (UINT8);
> - Size -= sizeof (UINT8);
> - Buffer = (UINT8*)Buffer + 1;
> - }
> -
> - if (Size >= sizeof (UINT16) && (StartAddress & 2) != 0) {
> - //
> - // Read a word if StartAddress is word aligned
> - //
> - WriteUnaligned16 ((UINT16 *) Buffer, (UINT16) PciExpressRead16 (StartAddress));
> -
> - StartAddress += sizeof (UINT16);
> - Size -= sizeof (UINT16);
> - Buffer = (UINT16*)Buffer + 1;
> - }
> -
> - while (Size >= sizeof (UINT32)) {
> - //
> - // Read as many double words as possible
> - //
> - WriteUnaligned32 ((UINT32 *) Buffer, (UINT32) PciExpressRead32 (StartAddress));
> -
> - StartAddress += sizeof (UINT32);
> - Size -= sizeof (UINT32);
> - Buffer = (UINT32*)Buffer + 1;
> - }
> -
> - if (Size >= sizeof (UINT16)) {
> - //
> - // Read the last remaining word if exist
> - //
> - WriteUnaligned16 ((UINT16 *) Buffer, (UINT16) PciExpressRead16 (StartAddress));
> - StartAddress += sizeof (UINT16);
> - Size -= sizeof (UINT16);
> - Buffer = (UINT16*)Buffer + 1;
> - }
> -
> - if (Size >= sizeof (UINT8)) {
> - //
> - // Read the last remaining byte if exist
> - //
> - *(volatile UINT8 *)Buffer = PciExpressRead8 (StartAddress);
> - }
> -
> - return ReturnValue;
> -}
> -
> -/**
> - Copies the data in a caller supplied buffer to a specified range of PCI
> - configuration space.
> -
> - Writes the range of PCI configuration registers specified by StartAddress and
> - Size from the buffer specified by Buffer. This function only allows the PCI
> - configuration registers from a single PCI function to be written. Size is
> - returned. When possible 32-bit PCI configuration write cycles are used to
> - write from StartAdress to StartAddress + Size. Due to alignment restrictions,
> - 8-bit and 16-bit PCI configuration write cycles may be used at the beginning
> - and the end of the range.
> -
> - If StartAddress > 0x0FFFFFFF, then ASSERT().
> - If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
> - If Size > 0 and Buffer is NULL, then ASSERT().
> -
> - @param StartAddress The starting address that encodes the PCI Bus, Device,
> - Function and Register.
> - @param Size The size in bytes of the transfer.
> - @param Buffer The pointer to a buffer containing the data to write.
> -
> - @return Size written to StartAddress.
> -
> -**/
> -UINTN
> -EFIAPI
> -PciExpressWriteBuffer (
> - IN UINTN StartAddress,
> - IN UINTN Size,
> - IN VOID *Buffer
> - )
> -{
> - UINTN ReturnValue;
> -
> - ASSERT_INVALID_PCI_ADDRESS (StartAddress);
> - ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);
> -
> - if (Size == 0) {
> - return 0;
> - }
> -
> - ASSERT (Buffer != NULL);
> -
> - //
> - // Save Size for return
> - //
> - ReturnValue = Size;
> -
> - if ((StartAddress & 1) != 0) {
> - //
> - // Write a byte if StartAddress is byte aligned
> - //
> - PciExpressWrite8 (StartAddress, *(UINT8*)Buffer);
> - StartAddress += sizeof (UINT8);
> - Size -= sizeof (UINT8);
> - Buffer = (UINT8*)Buffer + 1;
> - }
> -
> - if (Size >= sizeof (UINT16) && (StartAddress & 2) != 0) {
> - //
> - // Write a word if StartAddress is word aligned
> - //
> - PciExpressWrite16 (StartAddress, ReadUnaligned16 ((UINT16*)Buffer));
> - StartAddress += sizeof (UINT16);
> - Size -= sizeof (UINT16);
> - Buffer = (UINT16*)Buffer + 1;
> - }
> -
> - while (Size >= sizeof (UINT32)) {
> - //
> - // Write as many double words as possible
> - //
> - PciExpressWrite32 (StartAddress, ReadUnaligned32 ((UINT32*)Buffer));
> - StartAddress += sizeof (UINT32);
> - Size -= sizeof (UINT32);
> - Buffer = (UINT32*)Buffer + 1;
> - }
> -
> - if (Size >= sizeof (UINT16)) {
> - //
> - // Write the last remaining word if exist
> - //
> - PciExpressWrite16 (StartAddress, ReadUnaligned16 ((UINT16*)Buffer));
> - StartAddress += sizeof (UINT16);
> - Size -= sizeof (UINT16);
> - Buffer = (UINT16*)Buffer + 1;
> - }
> -
> - if (Size >= sizeof (UINT8)) {
> - //
> - // Write the last remaining byte if exist
> - //
> - PciExpressWrite8 (StartAddress, *(UINT8*)Buffer);
> - }
> -
> - return ReturnValue;
> -}
> diff --git a/Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciExpressLib/PciExpressLib.inf b/Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciExpressLib/PciExpressLib.inf
> deleted file mode 100644
> index acb6fb6219..0000000000
> --- a/Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciExpressLib/PciExpressLib.inf
> +++ /dev/null
> @@ -1,56 +0,0 @@
> -## @file
> -# Instance of PCI Express Library using the 256 MB PCI Express MMIO window.
> -#
> -# PCI Express Library that uses the 256 MB PCI Express MMIO window to perform
> -# PCI Configuration cycles. Layers on top of an I/O Library instance.
> -#
> -# Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.
> -#
> -# This library is inherited from MdePkg/Library/BasePciExpressLib. On
> -# NeoverseN1 SoC, with the unmodified version of this library, a slave error is
> -# generated when host accesses the config space of a non-available device or
> -# unimplemented function on a given bus. In order to resolve this for
> -# NeoverseN1 SoC, a modified version of the MdePkg/Library/BasePciExpressLib
> -# library is used. The modification includes a check to determine whether the
> -# incoming PCI address can be safely accessed.
> -#
> -# In addition to this, the NeoverseN1 SoC has two other limitations which
> -# affect the access to the PCIe root port:
> -# 1. ECAM space is not contiguous, root port ECAM (BDF = 0:0:0) is isolated
> -# from rest of the downstream hierarchy ECAM space.
> -# 2. Root port ECAM space is not capable of 8bit/16bit writes.
> -# This library includes workaround for these limitations as well.
> -#
> -# Copyright (c) 2020, ARM Limited. All rights reserved.
> -#
> -# SPDX-License-Identifier: BSD-2-Clause-Patent
> -#
> -##
> -
> -[Defines]
> - INF_VERSION = 0x0001001A
> - BASE_NAME = BasePciExpressLib
> - FILE_GUID = b378dd06-de7f-4e8c-8fb0-5126adfb34bf
> - MODULE_TYPE = BASE
> - VERSION_STRING = 1.0
> - LIBRARY_CLASS = PciExpressLib
> -
> -[Sources]
> - PciExpressLib.c
> -
> -[Packages]
> - MdePkg/MdePkg.dec
> - Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec
> -
> -[FixedPcd]
> - gArmNeoverseN1SocTokenSpaceGuid.PcdPcieRootPortConfigBaseAddress
> - gArmNeoverseN1SocTokenSpaceGuid.PcdPcieRootPortConfigBaseSize
> -
> -[LibraryClasses]
> - BaseLib
> - DebugLib
> - IoLib
> - PcdLib
> -
> -[Pcd]
> - gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## CONSUMES
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [edk2-devel] [PATCH v5 3/4] Silicon/ARM/NeoverseN1Soc: Add CCIX root complex support
2021-12-22 1:14 ` [PATCH v5 3/4] Silicon/ARM/NeoverseN1Soc: Add CCIX root complex support Khasim Mohammed
@ 2021-12-22 8:52 ` PierreGondois
2022-01-19 15:02 ` Sami Mujawar
1 sibling, 0 replies; 13+ messages in thread
From: PierreGondois @ 2021-12-22 8:52 UTC (permalink / raw)
To: devel, khasim.mohammed; +Cc: nd, Sami Mujawar
Hi Khasim,
Everything looks good to me:
Reviewed-by: Pierre Gondois <pierre.gondois@arm.com>
Regards,
Pierre
On 12/22/21 2:14 AM, Khasim Mohammed via groups.io wrote:
> This patch enables CCIX root complex support by updating
> the root complex node info in PciHostBridge library.
>
> Signed-off-by: Khasim Syed Mohammed <khasim.mohammed@arm.com>
> ---
> .../PciHostBridgeLib/PciHostBridgeLib.c | 71 +++++++++++++++++--
> .../PciHostBridgeLib/PciHostBridgeLib.inf | 11 ++-
> 2 files changed, 76 insertions(+), 6 deletions(-)
>
> diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.c b/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.c
> index 9332939f63..c3a14a6c17 100644
> --- a/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.c
> +++ b/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.c
> @@ -1,7 +1,7 @@
> /** @file
> * PCI Host Bridge Library instance for ARM Neoverse N1 platform
> *
> -* Copyright (c) 2019 - 2020, ARM Limited. All rights reserved.
> +* Copyright (c) 2019 - 2021, ARM Limited. All rights reserved.<BR>
> *
> * SPDX-License-Identifier: BSD-2-Clause-Patent
> *
> @@ -16,6 +16,8 @@
> #include <Protocol/PciHostBridgeResourceAllocation.h>
> #include <Protocol/PciRootBridgeIo.h>
>
> +#define ROOT_COMPLEX_NUM 2
> +
> GLOBAL_REMOVE_IF_UNREFERENCED
> STATIC CHAR16 CONST * CONST mPciHostBridgeLibAcpiAddressSpaceTypeStr[] = {
> L"Mem", L"I/O", L"Bus"
> @@ -28,7 +30,7 @@ typedef struct {
> } EFI_PCI_ROOT_BRIDGE_DEVICE_PATH;
> #pragma pack ()
>
> -STATIC EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath[] = {
> +STATIC EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath[ROOT_COMPLEX_NUM] = {
> // PCIe
> {
> {
> @@ -51,10 +53,33 @@ STATIC EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath[] = {
> 0
> }
> }
> - }
> + },
> + //CCIX
> + {
> + {
> + {
> + ACPI_DEVICE_PATH,
> + ACPI_DP,
> + {
> + (UINT8)sizeof (ACPI_HID_DEVICE_PATH),
> + (UINT8)(sizeof (ACPI_HID_DEVICE_PATH) >> 8)
> + }
> + },
> + EISA_PNP_ID(0x0A09), // CCIX
> + 0
> + },
> + {
> + END_DEVICE_PATH_TYPE,
> + END_ENTIRE_DEVICE_PATH_SUBTYPE,
> + {
> + END_DEVICE_PATH_LENGTH,
> + 0
> + }
> + }
> + },
> };
>
> -STATIC PCI_ROOT_BRIDGE mPciRootBridge[] = {
> +STATIC PCI_ROOT_BRIDGE mPciRootBridge[ROOT_COMPLEX_NUM] = {
> {
> 0, // Segment
> 0, // Supports
> @@ -90,7 +115,43 @@ STATIC PCI_ROOT_BRIDGE mPciRootBridge[] = {
> 0
> },
> (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath[0]
> - }
> + },
> + {
> + 1, // Segment
> + 0, // Supports
> + 0, // Attributes
> + TRUE, // DmaAbove4G
> + FALSE, // NoExtendedConfigSpace
> + FALSE, // ResourceAssigned
> + EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM | // AllocationAttributes
> + EFI_PCI_HOST_BRIDGE_MEM64_DECODE,
> + {
> + // Bus
> + FixedPcdGet32 (PcdCcixBusMin),
> + FixedPcdGet32 (PcdCcixBusMax)
> + }, {
> + // Io
> + FixedPcdGet64 (PcdCcixIoBase),
> + FixedPcdGet64 (PcdCcixIoBase) + FixedPcdGet64 (PcdCcixIoSize) - 1
> + }, {
> + // Mem
> + FixedPcdGet32 (PcdCcixMmio32Base),
> + FixedPcdGet32 (PcdCcixMmio32Base) + FixedPcdGet32 (PcdCcixMmio32Size) - 1
> + }, {
> + // MemAbove4G
> + FixedPcdGet64 (PcdCcixMmio64Base),
> + FixedPcdGet64 (PcdCcixMmio64Base) + FixedPcdGet64 (PcdCcixMmio64Size) - 1
> + }, {
> + // PMem
> + MAX_UINT64,
> + 0
> + }, {
> + // PMemAbove4G
> + MAX_UINT64,
> + 0
> + },
> + (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath[1]
> + },
> };
>
> /**
> diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.inf b/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.inf
> index 3ff1c592f2..3356c3ad35 100644
> --- a/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.inf
> +++ b/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.inf
> @@ -1,7 +1,7 @@
> ## @file
> # PCI Host Bridge Library instance for ARM Neoverse N1 platform.
> #
> -# Copyright (c) 2019 - 2020, ARM Limited. All rights reserved.
> +# Copyright (c) 2019 - 2021, ARM Limited. All rights reserved.<BR>
> #
> # SPDX-License-Identifier: BSD-2-Clause-Patent
> #
> @@ -42,6 +42,15 @@
> gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio64Base
> gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio64Size
>
> + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixBusMin
> + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixBusMax
> + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixIoBase
> + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixIoSize
> + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio32Base
> + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio32Size
> + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio64Base
> + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio64Size
> +
> [Protocols]
> gEfiCpuIo2ProtocolGuid
>
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [edk2-devel] [PATCH v5 2/4] Silicon/ARM/NeoverseN1Soc: Update PCDs to support multiple PCI root ports
2021-12-22 1:14 ` [PATCH v5 2/4] Silicon/ARM/NeoverseN1Soc: Update PCDs to support multiple PCI root ports Khasim Mohammed
@ 2021-12-22 8:52 ` PierreGondois
2022-01-19 15:01 ` Sami Mujawar
1 sibling, 0 replies; 13+ messages in thread
From: PierreGondois @ 2021-12-22 8:52 UTC (permalink / raw)
To: devel, khasim.mohammed; +Cc: nd, Sami Mujawar
Hi Khasim,
Everything looks good to me:
Reviewed-by: Pierre Gondois <pierre.gondois@arm.com>
Regards,
Pierre
On 12/22/21 2:14 AM, Khasim Mohammed via groups.io wrote:
> PCD entries are updated to remove the hardcoded assignments and to
> add support for multiple PCI root ports.
>
> Signed-off-by: Khasim Syed Mohammed <khasim.mohammed@arm.com>
> ---
> .../AslTables/SsdtPci.asl | 8 +--
> .../AslTables/SsdtRemotePci.asl | 4 +-
> .../ConfigurationManager.c | 24 ++++----
> .../ConfigurationManagerDxe.inf | 18 ++++--
> Platform/ARM/N1Sdp/N1SdpPlatform.dec | 8 ---
> Platform/ARM/N1Sdp/N1SdpPlatform.dsc | 1 -
> .../Library/PlatformLib/PlatformLib.inf | 1 +
> .../Library/PlatformLib/PlatformLibMem.c | 4 +-
> Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec | 58 +++++++++++--------
> 9 files changed, 68 insertions(+), 58 deletions(-)
>
> diff --git a/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/AslTables/SsdtPci.asl b/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/AslTables/SsdtPci.asl
> index cdbd42c154..9922673d0d 100644
> --- a/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/AslTables/SsdtPci.asl
> +++ b/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/AslTables/SsdtPci.asl
> @@ -80,8 +80,8 @@ DefinitionBlock("SsdtPci.aml", "SSDT", 1, "ARMLTD", "N1Sdp",
> Device(PCI0) {
> Name (_HID, EISAID("PNP0A08")) // PCI Express Root Bridge
> Name (_CID, EISAID("PNP0A03")) // Compatible PCI Root Bridge
> - Name (_SEG, Zero) // PCI Segment Group number
> - Name (_BBN, Zero) // PCI Base Bus Number
> + Name (_SEG, FixedPcdGet32 (PcdPcieSegmentNumber)) // Segment Number
> + Name (_BBN, FixedPcdGet32 (PcdPcieBusBaseNumber)) // Bus Base Number
> Name (_CCA, 1) // Cache Coherency Attribute
>
> // Root Complex 0
> @@ -166,8 +166,8 @@ DefinitionBlock("SsdtPci.aml", "SSDT", 1, "ARMLTD", "N1Sdp",
> Device(PCI1) {
> Name (_HID, EISAID("PNP0A08")) // PCI Express Root Bridge
> Name (_CID, EISAID("PNP0A03")) // Compatible PCI Root Bridge
> - Name (_SEG, 1) // PCI Segment Group number
> - Name (_BBN, Zero) // PCI Base Bus Number
> + Name (_SEG, FixedPcdGet32 (PcdCcixSegmentNumber)) // Segment Number
> + Name (_BBN, FixedPcdGet32 (PcdCcixBusBaseNumber)) // Bus Base Number
> Name (_CCA, 1) // Cache Coherency Attribute
>
> // Root Complex 1
> diff --git a/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/AslTables/SsdtRemotePci.asl b/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/AslTables/SsdtRemotePci.asl
> index b6bec7c106..4c6e0c762f 100644
> --- a/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/AslTables/SsdtRemotePci.asl
> +++ b/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/AslTables/SsdtRemotePci.asl
> @@ -76,8 +76,8 @@ DefinitionBlock("SsdtRemotePci.aml", "SSDT", 1, "ARMLTD", "N1Sdp",
> Device(PCI2) {
> Name (_HID, EISAID("PNP0A08")) // PCI Express Root Bridge
> Name (_CID, EISAID("PNP0A03")) // Compatible PCI Root Bridge
> - Name (_SEG, 2) // PCI Segment Group number
> - Name (_BBN, Zero) // PCI Base Bus Number
> + Name (_SEG, FixedPcdGet32 (PcdRemotePcieSegmentNumber)) // Segment Number
> + Name (_BBN, FixedPcdGet32 (PcdRemotePcieBusBaseNumber)) // BusBase Number
> Name (_CCA, 1) // Cache Coherency Attribute
>
> // Remote Root Complex 0
> diff --git a/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c b/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c
> index 9c91372c11..f50623ae3f 100644
> --- a/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c
> +++ b/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c
> @@ -1047,24 +1047,24 @@ EDKII_PLATFORM_REPOSITORY_INFO N1sdpRepositoryInfo = {
> {
> // PCIe ECAM
> {
> - 0x70000000, // Base Address
> - 0x0, // Segment Group Number
> - 0x0, // Start Bus Number
> - 17 // End Bus Number
> + FixedPcdGet64 (PcdPcieExpressBaseAddress), // Base Address
> + FixedPcdGet32 (PcdPcieSegmentNumber), // Segment Group Number
> + FixedPcdGet32 (PcdPcieBusMin), // Start Bus Number
> + FixedPcdGet32 (PcdPcieBusMax) // End Bus Number
> },
> // CCIX ECAM
> {
> - 0x68000000, // Base Address
> - 0x1, // Segment Group Number
> - 0x0, // Start Bus Number
> - 17 // End Bus Number
> + FixedPcdGet32 (PcdCcixExpressBaseAddress), // Base Address
> + FixedPcdGet32 (PcdCcixSegmentNumber), // Segment Group Number
> + FixedPcdGet32 (PcdCcixBusMin), // Start Bus Number
> + FixedPcdGet32 (PcdCcixBusMax) // End Bus Number
> },
> //Remote Chip PCIe ECAM
> {
> - 0x40070000000, // Base Address
> - 0x2, // Segment Group Number
> - 0x0, // Start Bus Number
> - 17 // End Bus Number
> + FixedPcdGet64 (PcdRemotePcieBaseAddress), // Base Address
> + FixedPcdGet32 (PcdRemotePcieSegmentNumber), // Segment Group Number
> + FixedPcdGet32 (PcdRemotePcieBusMin), // Start Bus Number
> + FixedPcdGet32 (PcdRemotePcieBusMax) // End Bus Number
> }
> },
>
> diff --git a/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerDxe.inf b/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerDxe.inf
> index 027a4202ff..3a8711c6f1 100644
> --- a/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerDxe.inf
> +++ b/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerDxe.inf
> @@ -76,8 +76,6 @@
> gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase
> gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate
>
> - gArmN1SdpTokenSpaceGuid.PcdPcieExpressBaseAddress
> -
> gArmNeoverseN1SocTokenSpaceGuid.PcdExtMemorySpace
> gArmNeoverseN1SocTokenSpaceGuid.PcdDramBlock2Base
>
> @@ -91,6 +89,8 @@
> gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusCount
> gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusMax
> gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusMin
> + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusBaseNumber
> + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieExpressBaseAddress
> gArmNeoverseN1SocTokenSpaceGuid.PcdPcieIoBase
> gArmNeoverseN1SocTokenSpaceGuid.PcdPcieIoMaxBase
> gArmNeoverseN1SocTokenSpaceGuid.PcdPcieIoSize
> @@ -105,11 +105,13 @@
> gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio64Translation
> gArmNeoverseN1SocTokenSpaceGuid.PcdPcieRootPortConfigBaseAddress
> gArmNeoverseN1SocTokenSpaceGuid.PcdPcieRootPortConfigBaseSize
> + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieSegmentNumber
>
> # CCIX
> gArmNeoverseN1SocTokenSpaceGuid.PcdCcixBusCount
> gArmNeoverseN1SocTokenSpaceGuid.PcdCcixBusMax
> gArmNeoverseN1SocTokenSpaceGuid.PcdCcixBusMin
> + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixBusBaseNumber
> gArmNeoverseN1SocTokenSpaceGuid.PcdCcixExpressBaseAddress
> gArmNeoverseN1SocTokenSpaceGuid.PcdCcixIoBase
> gArmNeoverseN1SocTokenSpaceGuid.PcdCcixIoMaxBase
> @@ -125,6 +127,7 @@
> gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio64Translation
> gArmNeoverseN1SocTokenSpaceGuid.PcdCcixRootPortConfigBaseAddress
> gArmNeoverseN1SocTokenSpaceGuid.PcdCcixRootPortConfigBaseSize
> + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixSegmentNumber
>
> # Coresight
> gArmN1SdpTokenSpaceGuid.PcdCsComponentSize
> @@ -158,9 +161,14 @@
> gArmN1SdpTokenSpaceGuid.PcdCsTpiuMaxBase
>
> # Remote PCIe
> - gArmN1SdpTokenSpaceGuid.PcdRemotePcieIoTranslation
> - gArmN1SdpTokenSpaceGuid.PcdRemotePcieMmio32Translation
> - gArmN1SdpTokenSpaceGuid.PcdRemotePcieMmio64Translation
> + gArmNeoverseN1SocTokenSpaceGuid.PcdRemotePcieBaseAddress
> + gArmNeoverseN1SocTokenSpaceGuid.PcdRemotePcieBusBaseNumber
> + gArmNeoverseN1SocTokenSpaceGuid.PcdRemotePcieBusMax
> + gArmNeoverseN1SocTokenSpaceGuid.PcdRemotePcieBusMin
> + gArmNeoverseN1SocTokenSpaceGuid.PcdRemotePcieIoTranslation
> + gArmNeoverseN1SocTokenSpaceGuid.PcdRemotePcieMmio32Translation
> + gArmNeoverseN1SocTokenSpaceGuid.PcdRemotePcieMmio64Translation
> + gArmNeoverseN1SocTokenSpaceGuid.PcdRemotePcieSegmentNumber
>
> [Depex]
> TRUE
> diff --git a/Platform/ARM/N1Sdp/N1SdpPlatform.dec b/Platform/ARM/N1Sdp/N1SdpPlatform.dec
> index 2ab6c20dcc..16937197b8 100644
> --- a/Platform/ARM/N1Sdp/N1SdpPlatform.dec
> +++ b/Platform/ARM/N1Sdp/N1SdpPlatform.dec
> @@ -34,9 +34,6 @@
> gArmN1SdpTokenSpaceGuid.PcdRamDiskBase|0x88000000|UINT32|0x00000001
> gArmN1SdpTokenSpaceGuid.PcdRamDiskSize|0x18000000|UINT32|0x00000002
>
> - # PCIe
> - gArmN1SdpTokenSpaceGuid.PcdPcieExpressBaseAddress|0x70000000|UINT32|0x00000007
> -
> # External memory
> gArmNeoverseN1SocTokenSpaceGuid.PcdExtMemorySpace|0|UINT64|0x00000029
>
> @@ -92,8 +89,3 @@
> # unmapped reserved region results in a DECERR response.
> #
> gArmN1SdpTokenSpaceGuid.PcdCsComponentSize|0x1000|UINT32|0x00000049
> -
> - # Remote Chip PCIe
> - gArmN1SdpTokenSpaceGuid.PcdRemotePcieIoTranslation|0x40075200000|UINT64|0x0000004A
> - gArmN1SdpTokenSpaceGuid.PcdRemotePcieMmio32Translation|0x40000000000|UINT64|0x0000004B
> - gArmN1SdpTokenSpaceGuid.PcdRemotePcieMmio64Translation|0x40000000000|UINT64|0x0000004C
> diff --git a/Platform/ARM/N1Sdp/N1SdpPlatform.dsc b/Platform/ARM/N1Sdp/N1SdpPlatform.dsc
> index 7488bdc036..cb2049966c 100644
> --- a/Platform/ARM/N1Sdp/N1SdpPlatform.dsc
> +++ b/Platform/ARM/N1Sdp/N1SdpPlatform.dsc
> @@ -127,7 +127,6 @@
> gArmTokenSpaceGuid.PcdGicRedistributorsBase|0x300C0000
>
> # PCIe
> - gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x70000000
> gEmbeddedTokenSpaceGuid.PcdPrePiCpuIoSize|24
> gEfiMdeModulePkgTokenSpaceGuid.PcdSrIovSupport|FALSE
>
> diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf
> index 8e2154aadf..96e590cdd8 100644
> --- a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf
> +++ b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf
> @@ -43,6 +43,7 @@
> gArmNeoverseN1SocTokenSpaceGuid.PcdExtMemorySpace
> gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusMax
> gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusMin
> + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieExpressBaseAddress
> gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio32Base
> gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio32Size
> gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio64Base
> diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c
> index 1c4a445c5e..339fa07b32 100644
> --- a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c
> +++ b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c
> @@ -115,8 +115,8 @@ ArmPlatformGetVirtualMemoryMap (
> VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
>
> // PCIe ECAM Configuration Space
> - VirtualMemoryTable[++Index].PhysicalBase = PcdGet64 (PcdPciExpressBaseAddress);
> - VirtualMemoryTable[Index].VirtualBase = PcdGet64 (PcdPciExpressBaseAddress);
> + VirtualMemoryTable[++Index].PhysicalBase = PcdGet64 (PcdPcieExpressBaseAddress);
> + VirtualMemoryTable[Index].VirtualBase = PcdGet64 (PcdPcieExpressBaseAddress);
> VirtualMemoryTable[Index].Length = (FixedPcdGet32 (PcdPcieBusMax) -
> FixedPcdGet32 (PcdPcieBusMin) + 1) *
> SIZE_1MB;
> diff --git a/Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec b/Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec
> index eea2d58402..d91ed28319 100644
> --- a/Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec
> +++ b/Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec
> @@ -29,11 +29,11 @@
> gArmNeoverseN1SocTokenSpaceGuid.PcdDramBlock2Base|0|UINT64|0x00000001
>
> #PCIe
> - gArmNeoverseN1SocTokenSpaceGuid.PcdPcieRootPortConfigBaseAddress|0x60000000|UINT32|0x00000002
> - gArmNeoverseN1SocTokenSpaceGuid.PcdPcieRootPortConfigBaseSize|0x00001000|UINT32|0x00000003
> - gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusCount|18|UINT32|0x00000004
> - gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusMax|17|UINT32|0x00000005
> - gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusMin|0|UINT32|0x00000006
> + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusCount|18|UINT32|0x00000002
> + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusMax|17|UINT32|0x00000003
> + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusMin|0|UINT32|0x00000004
> + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusBaseNumber|0|UINT32|0x00000005
> + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieExpressBaseAddress|0x70000000|UINT64|0x00000006
> gArmNeoverseN1SocTokenSpaceGuid.PcdPcieIoBase|0x0|UINT32|0x00000007
> gArmNeoverseN1SocTokenSpaceGuid.PcdPcieIoMaxBase|0x001FFFF|UINT32|0x00000008
> gArmNeoverseN1SocTokenSpaceGuid.PcdPcieIoSize|0x020000|UINT32|0x00000009
> @@ -46,30 +46,40 @@
> gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio64MaxBase|0x28FFFFFFFF|UINT64|0x00000010
> gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio64Size|0x2000000000|UINT64|0x00000011
> gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio64Translation|0x0|UINT64|0x00000012
> + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieRootPortConfigBaseAddress|0x60000000|UINT32|0x00000013
> + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieRootPortConfigBaseSize|0x00001000|UINT32|0x00000014
> + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieSegmentNumber|0|UINT32|0x00000015
>
> # CCIX
> gArmNeoverseN1SocTokenSpaceGuid.PcdCcixBusCount|18|UINT32|0x00000016
> gArmNeoverseN1SocTokenSpaceGuid.PcdCcixBusMax|17|UINT32|0x00000017
> gArmNeoverseN1SocTokenSpaceGuid.PcdCcixBusMin|0|UINT32|0x00000018
> - gArmNeoverseN1SocTokenSpaceGuid.PcdCcixExpressBaseAddress|0x68000000|UINT32|0x00000019
> - gArmNeoverseN1SocTokenSpaceGuid.PcdCcixIoBase|0x0|UINT32|0x0000001A
> - gArmNeoverseN1SocTokenSpaceGuid.PcdCcixIoMaxBase|0x01FFFF|UINT32|0x0000001B
> - gArmNeoverseN1SocTokenSpaceGuid.PcdCcixIoSize|0x020000|UINT32|0x0000001C
> - gArmNeoverseN1SocTokenSpaceGuid.PcdCcixIoTranslation|0x6D200000|UINT32|0x00000001D
> - gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio32Base|0x69200000|UINT32|0x0000001E
> - gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio32MaxBase|0x6D1FFFFF|UINT32|0x00000001F
> - gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio32Size|0x04000000|UINT32|0x00000020
> - gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio32Translation|0x0|UINT32|0x00000021
> - gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio64Base|0x2900000000|UINT64|0x00000022
> - gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio64MaxBase|0x48FFFFFFFF|UINT64|0x00000023
> - gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio64Size|0x2000000000|UINT64|0x00000024
> - gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio64Translation|0x0|UINT64|0x00000025
> - gArmNeoverseN1SocTokenSpaceGuid.PcdCcixRootPortConfigBaseAddress|0x62000000|UINT32|0x00000026
> - gArmNeoverseN1SocTokenSpaceGuid.PcdCcixRootPortConfigBaseSize|0x00001000|UINT32|0x00000027
> + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixBusBaseNumber|0|UINT32|0x00000019
> + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixExpressBaseAddress|0x68000000|UINT32|0x0000001A
> + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixIoBase|0x0|UINT32|0x0000001B
> + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixIoMaxBase|0x00FFFFFF|UINT32|0x0000001C
> + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixIoSize|0x01000000|UINT32|0x0000001D
> + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixIoTranslation|0x6D200000|UINT32|0x00000001E
> + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio32Base|0x69200000|UINT32|0x0000001F
> + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio32MaxBase|0x6D1FFFFF|UINT32|0x000000020
> + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio32Size|0x04000000|UINT32|0x00000021
> + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio32Translation|0x0|UINT32|0x00000022
> + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio64Base|0x2900000000|UINT64|0x00000023
> + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio64MaxBase|0x48FFFFFFFF|UINT64|0x00000024
> + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio64Size|0x2000000000|UINT64|0x00000025
> + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio64Translation|0x0|UINT64|0x00000026
> + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixRootPortConfigBaseAddress|0x62000000|UINT32|0x00000027
> + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixRootPortConfigBaseSize|0x00001000|UINT32|0x00000028
> + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixSegmentNumber|1|UINT32|0x00000029
>
> - gArmNeoverseN1SocTokenSpaceGuid.PcdExtMemorySpace|0x40000000000|UINT64|0x00000029
> + gArmNeoverseN1SocTokenSpaceGuid.PcdExtMemorySpace|0x40000000000|UINT64|0x00000030
>
> # Remote Chip PCIe
> - gArmNeoverseN1SocTokenSpaceGuid.PcdRemotePcieIoTranslation|0x40075200000|UINT64|0x0000004A
> - gArmNeoverseN1SocTokenSpaceGuid.PcdRemotePcieMmio32Translation|0x40000000000|UINT64|0x0000004B
> - gArmNeoverseN1SocTokenSpaceGuid.PcdRemotePcieMmio64Translation|0x40000000000|UINT64|0x0000004C
> + gArmNeoverseN1SocTokenSpaceGuid.PcdRemotePcieBaseAddress|0x40070000000|UINT64|0x0000004A
> + gArmNeoverseN1SocTokenSpaceGuid.PcdRemotePcieBusBaseNumber|0|UINT32|0x0000004B
> + gArmNeoverseN1SocTokenSpaceGuid.PcdRemotePcieBusMax|17|UINT32|0x0000004C
> + gArmNeoverseN1SocTokenSpaceGuid.PcdRemotePcieBusMin|0|UINT32|0x0000004D
> + gArmNeoverseN1SocTokenSpaceGuid.PcdRemotePcieIoTranslation|0x40075200000|UINT64|0x0000004E
> + gArmNeoverseN1SocTokenSpaceGuid.PcdRemotePcieMmio32Translation|0x40000000000|UINT64|0x0000004F
> + gArmNeoverseN1SocTokenSpaceGuid.PcdRemotePcieMmio64Translation|0x40000000000|UINT64|0x00000050
> + gArmNeoverseN1SocTokenSpaceGuid.PcdRemotePcieSegmentNumber|2|UINT32|0x00000051
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [edk2-devel] [PATCH v5 1/4] Silicon/ARM/NeoverseN1Soc: Port PCI Segment Library
2021-12-22 1:14 ` [PATCH v5 1/4] Silicon/ARM/NeoverseN1Soc: Port PCI Segment Library Khasim Mohammed
@ 2021-12-22 8:52 ` PierreGondois
2022-01-19 15:01 ` Sami Mujawar
1 sibling, 0 replies; 13+ messages in thread
From: PierreGondois @ 2021-12-22 8:52 UTC (permalink / raw)
To: devel, khasim.mohammed; +Cc: nd, Sami Mujawar
Hi Khasim,
Everything looks good to me:
Reviewed-by: Pierre Gondois <pierre.gondois@arm.com>
Regards,
Pierre
On 12/22/21 2:14 AM, Khasim Mohammed via groups.io wrote:
> The BasePCISegment Library in MdePkg doesn't allow configuring
> multiple segments required for PCIe and CCIX root port
> enumeration. Therefore, a custom PCI Segment library is adapted
> from SynQuacerPciSegmentLib and ported for N1Sdp.
>
> In addition to this, the hardware has few other limitations which affects
> the access to the PCIe root port:
> 1. ECAM space is not contiguous, root port ECAM (BDF = 0:0:0) is isolated
> from rest of the downstream hierarchy ECAM space.
> 2. Root port ECAM space is not capable of 8bit/16bit writes.
> 3. A slave error is generated when host accesses the configuration
> space of non-available device or unimplemented function on a
> given bus.
>
> The description of the workarounds included for these limitations can
> be found in the corresponding files of this patch.
>
> Signed-off-by: Khasim Syed Mohammed <khasim.mohammed@arm.com>
> ---
> .../Library/PciSegmentLib/PciSegmentLib.c | 1602 +++++++++++++++++
> .../Library/PciSegmentLib/PciSegmentLib.inf | 38 +
> 2 files changed, 1640 insertions(+)
> create mode 100644 Silicon/ARM/NeoverseN1Soc/Library/PciSegmentLib/PciSegmentLib.c
> create mode 100644 Silicon/ARM/NeoverseN1Soc/Library/PciSegmentLib/PciSegmentLib.inf
>
> diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PciSegmentLib/PciSegmentLib.c b/Silicon/ARM/NeoverseN1Soc/Library/PciSegmentLib/PciSegmentLib.c
> new file mode 100644
> index 0000000000..a39a414044
> --- /dev/null
> +++ b/Silicon/ARM/NeoverseN1Soc/Library/PciSegmentLib/PciSegmentLib.c
> @@ -0,0 +1,1602 @@
> +/** @file
> + PCI Segment Library for N1SDP SoC with multiple RCs
> +
> + Having two distinct root complexes is not supported by the standard
> + set of PciLib/PciExpressLib/PciSegmentLib, this PciSegmentLib
> + reimplements the functionality to support multiple root ports on
> + different segment numbers.
> +
> + On the NeoverseN1Soc, a slave error is generated when host accesses the
> + configuration space of non-available device or unimplemented function on a
> + given bus. So this library introduces a workaround using IsBdfValid(),
> + to return 0xFFFFFFFF for all such access.
> +
> + In addition to this, the hardware has two other limitations which affect
> + access to the PCIe root port:
> + 1. ECAM space is not contiguous, root port ECAM (BDF = 0:0:0) is isolated
> + from rest of the downstream hierarchy ECAM space.
> + 2. Root port ECAM space is not capable of 8bit/16bit writes.
> + The description of the workarounds included for these limitations can
> + be found in the comments below.
> +
> + Copyright (c) 2007 - 2012, Intel Corporation. All rights reserved.<BR>
> + Copyright (c) 2021, ARM Limited. All rights reserved.<BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +
> +#include <Base.h>
> +
> +#include <Library/BaseLib.h>
> +#include <Library/DebugLib.h>
> +#include <Library/IoLib.h>
> +#include <Library/PcdLib.h>
> +#include <Library/PciSegmentLib.h>
> +#include <NeoverseN1Soc.h>
> +
> +typedef enum {
> + PciCfgWidthUint8 = 0,
> + PciCfgWidthUint16,
> + PciCfgWidthUint32,
> + PciCfgWidthMax
> +} PCI_CFG_WIDTH;
> +
> +/**
> + Assert the validity of a PCI Segment address.
> + A valid PCI Segment address should not contain 1's in bits 28..31 and 48..63
> +
> + @param A The address to validate.
> + @param M Additional bits to assert to be zero.
> +**/
> +#define ASSERT_INVALID_PCI_SEGMENT_ADDRESS(A,M) \
> + ASSERT (((A) & (0xffff0000f0000000ULL | (M))) == 0)
> +
> +#define BUS_OFFSET 20
> +#define DEV_OFFSET 15
> +#define FUNC_OFFSET 12
> +#define REG_OFFSET 4096
> +
> +#define EFI_PCIE_ADDRESS(bus, dev, func, reg) \
> + (UINT64) ( \
> + (((UINTN) bus) << BUS_OFFSET) | \
> + (((UINTN) dev) << DEV_OFFSET) | \
> + (((UINTN) func) << FUNC_OFFSET) | \
> + (((UINTN) (reg)) < REG_OFFSET ? \
> + ((UINTN) (reg)) : (UINT64) (LShiftU64 ((UINT64) (reg), 32))))
> +
> +#define GET_PCIE_BASE_ADDRESS(Address) (Address & 0xF8000000)
> +
> +/* Root port Entry, BDF Entries Count */
> +#define BDF_TABLE_ENTRY_SIZE 4
> +#define BDF_TABLE_HEADER_COUNT 2
> +#define BDF_TABLE_HEADER_SIZE 8
> +
> +/* BDF table offsets for PCIe */
> +#define PCIE_BDF_TABLE_OFFSET 0
> +#define CCIX_BDF_TABLE_OFFSET (16 * 1024)
> +
> +#define GET_BUS_NUM(Address) (((Address) >> 20) & 0x7F)
> +#define GET_DEV_NUM(Address) (((Address) >> 15) & 0x1F)
> +#define GET_FUNC_NUM(Address) (((Address) >> 12) & 0x07)
> +#define GET_REG_NUM(Address) ((Address) & 0xFFF)
> +#define GET_SEG_NUM(Address) (((Address) >> 32) & 0xFFFF)
> +
> +CONST STATIC UINTN mDummyConfigData = 0xFFFFFFFF;
> +
> +/**
> + Check if the requested PCI address is a valid BDF address.
> +
> + SCP performs the initial bus scan and prepares a table of valid BDF addresses
> + and shares them through non-trusted SRAM. This function validates if the PCI
> + address from any PCI request falls within the table of valid entries. If not,
> + this function will return 0xFFFFFFFF. This is a workaround to avoid bus fault
> + that happens when accessing unavailable PCI device due to RTL bug.
> +
> + @param Address The address that encodes the PCI Bus, Device, Function and
> + Register.
> +
> + @return The base address of PCI Express.
> +
> +**/
> +STATIC
> +UINTN
> +IsBdfValid (
> + IN UINTN Address
> + )
> +{
> + UINT16 Segment;
> + UINTN BdfCount;
> + UINTN BdfValue;
> + UINTN Count;
> + UINTN TableBase;
> + UINTN PciAddress;
> +
> + Segment = GET_SEG_NUM (Address);
> + ASSERT ((Segment == 0) || (Segment == 1));
> +
> + // Keep the Bus, Device, Function bits. Clear the rest.
> + PciAddress = Address & 0xFFFF000;
> +
> + if (Segment == 0) {
> + TableBase = NEOVERSEN1SOC_NON_SECURE_SRAM_BASE + PCIE_BDF_TABLE_OFFSET;
> + } else {
> + TableBase = NEOVERSEN1SOC_NON_SECURE_SRAM_BASE + CCIX_BDF_TABLE_OFFSET;
> + }
> +
> + BdfCount = MmioRead32 (TableBase + BDF_TABLE_ENTRY_SIZE);
> +
> + /* Start from the second entry */
> + for (Count = BDF_TABLE_HEADER_COUNT;
> + Count < (BdfCount + BDF_TABLE_HEADER_COUNT);
> + Count++) {
> + BdfValue = MmioRead32 (TableBase + (Count * BDF_TABLE_ENTRY_SIZE));
> + if (BdfValue == PciAddress)
> + break;
> + }
> +
> + if (Count == (BdfCount + BDF_TABLE_HEADER_COUNT)) {
> + return mDummyConfigData;
> + } else {
> + return PciAddress;
> + }
> +}
> +
> +/**
> + Get the physical address of a configuration space register.
> +
> + Implement a workaround to avoid generation of slave errors from the bus. That
> + is, retrieve the PCI Express Base Address via a PCD entry, add the incomming
> + address with that base address and check whether this converted address
> + points to a accessible BDF. If it is not accessible, return the address
> + of a dummy location so that a read from it does not cause a slave error.
> +
> + In addition to this, implement a workaround for accessing the root port's
> + configuration space. The root port configuration space is not contiguous
> + with the rest of the downstream hierarchy configuration space. So determine
> + whether the specified address is for the root port and use a different base
> + address for it.
> +
> + @param Address The address that encodes the PCI Bus, Device, Function and
> + Register.
> +
> + @return Physical address of the configuration register that corresponds to the
> + PCI configuration register specified by input parameter 'Address'.
> +
> +**/
> +STATIC
> +VOID*
> +GetPciExpressAddress (
> + IN UINTN Address
> + )
> +{
> + BOOLEAN CheckRootPort;
> + UINT16 Segment;
> + UINT8 Bus;
> + UINT8 Device;
> + UINT8 Function;
> + UINT16 Register;
> + UINTN ConfigAddress;
> +
> + Segment = GET_SEG_NUM (Address);
> + ASSERT ((Segment == 0) || (Segment == 1));
> +
> + Bus = GET_BUS_NUM (Address);
> + Device = GET_DEV_NUM (Address);
> + Function = GET_FUNC_NUM (Address);
> + Register = GET_REG_NUM (Address);
> +
> +
> + CheckRootPort = (BOOLEAN) (Bus == 0) && (Device == 0) && (Function == 0);
> +
> + if (CheckRootPort == FALSE) {
> + if (IsBdfValid (Address) == mDummyConfigData) {
> + return (VOID*) &mDummyConfigData;
> + }
> + }
> +
> + if (Segment == 0) {
> + if (CheckRootPort == TRUE) {
> + ConfigAddress = (UINTN) PcdGet32 (PcdPcieRootPortConfigBaseAddress);
> + } else {
> + ConfigAddress = (UINTN) PcdGet64 (PcdPcieExpressBaseAddress);
> + }
> + } else {
> + if (CheckRootPort == TRUE) {
> + ConfigAddress = (UINTN) PcdGet32 (PcdCcixRootPortConfigBaseAddress);
> + } else {
> + ConfigAddress = (UINTN) PcdGet32 (PcdCcixExpressBaseAddress);
> + }
> + }
> +
> + ConfigAddress += EFI_PCIE_ADDRESS (Bus, Device, Function, Register);
> + return (VOID *)ConfigAddress;
> +}
> +
> +/**
> + Internal worker function to read a PCI configuration register.
> +
> + @param Address The address that encodes the PCI Bus, Device, Function
> + and Register.
> + @param Width The width of data to read
> +
> + @return The value read from the PCI configuration register.
> +**/
> +STATIC
> +UINT32
> +PciSegmentLibReadWorker (
> + IN UINT64 Address,
> + IN PCI_CFG_WIDTH Width
> + )
> +{
> + UINTN PciAddress;
> +
> + PciAddress = (UINTN) GetPciExpressAddress ((UINTN) Address);
> +
> + switch (Width) {
> + case PciCfgWidthUint8:
> + return MmioRead8 (PciAddress);
> + case PciCfgWidthUint16:
> + return MmioRead16 (PciAddress);
> + case PciCfgWidthUint32:
> + return MmioRead32 (PciAddress);
> + default:
> + ASSERT (FALSE);
> + }
> +
> + return 0;
> +}
> +
> +/**
> + Internal worker function to write to a PCI configuration register.
> +
> + @param Address The address that encodes the PCI Bus, Device, Function
> + and Register.
> + @param Width The width of data to write
> + @param Data The value to write.
> +
> + @return The value written to the PCI configuration register.
> +**/
> +STATIC
> +UINT32
> +PciSegmentLibWriteWorker (
> + IN UINT64 Address,
> + IN PCI_CFG_WIDTH Width,
> + IN UINT32 Data
> + )
> +{
> + UINT8 Offset;
> + UINT32 WData;
> + UINT64 AlignedAddress;
> + BOOLEAN CheckRootPort;
> +
> + CheckRootPort = (GET_BUS_NUM (Address) == 0) &&
> + (GET_DEV_NUM (Address) == 0) &&
> + (GET_FUNC_NUM (Address) == 0);
> +
> + // 8-bit and 16-bit writes to root port config space is not supported due to
> + // a hardware limitation. As a workaround, perform a read-update-write
> + // sequence on the whole 32-bit word of the root port config register such
> + // that only the specified 8-bits of that word are updated.
> +
> + switch (Width) {
> + case PciCfgWidthUint8:
> + if (CheckRootPort == TRUE) {
> + Offset = Address & 0x3;
> + AlignedAddress = Address & ~(0x3);
> + WData = MmioRead32 ((UINTN) GetPciExpressAddress (AlignedAddress));
> + WData &= ~(0xFF << (8 * Offset));
> + WData |= (Data << (8 * Offset));
> + MmioWrite32 ((UINTN) GetPciExpressAddress (AlignedAddress), WData);
> + return Data;
> + } else {
> + MmioWrite8 ((UINTN) GetPciExpressAddress (Address), Data);
> + }
> + break;
> + case PciCfgWidthUint16:
> + if (CheckRootPort == TRUE) {
> + Offset = Address & 0x3;
> + AlignedAddress = Address & ~(0x3);
> + WData = MmioRead32 ((UINTN) GetPciExpressAddress (AlignedAddress));
> + WData &= ~(0xFFFF << (8 * Offset));
> + WData |= (Data << (8 * Offset));
> + MmioWrite32 ((UINTN) GetPciExpressAddress (AlignedAddress), WData);
> + return Data;
> + } else {
> + MmioWrite16 ((UINTN) GetPciExpressAddress (Address), Data);
> + }
> + break;
> + case PciCfgWidthUint32:
> + MmioWrite32 ((UINTN) GetPciExpressAddress (Address), Data);
> + break;
> + default:
> + ASSERT (FALSE);
> + }
> +
> + return Data;
> +}
> +
> +/**
> + Reads an 8-bit PCI configuration register.
> +
> + Reads and returns the 8-bit PCI configuration register specified by Address.
> + This function must guarantee that all PCI read and write operations are
> + serialized.
> +
> + If any reserved bits in Address are set, then ASSERT().
> +
> + @param Address The address that encodes the PCI Segment, Bus,
> + Device, Function and Register.
> +
> + @return The 8-bit PCI configuration register specified by the Address.
> +**/
> +UINT8
> +EFIAPI
> +PciSegmentRead8 (
> + IN UINT64 Address
> + )
> +{
> + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 0);
> +
> + return (UINT8) PciSegmentLibReadWorker (Address, PciCfgWidthUint8);
> +}
> +
> +/**
> + Writes an 8-bit PCI configuration register.
> +
> + Writes the 8-bit Value in the PCI configuration register specified by the
> + Address. This function must guarantee that all PCI read and write operations
> + are serialized.
> +
> + If any reserved bits in Address are set, then ASSERT().
> +
> + @param Address The address that encodes the PCI Segment, Bus,
> + Device, Function, and Register.
> + @param Value The value to write.
> +
> + @return The value written to the PCI configuration register.
> +**/
> +UINT8
> +EFIAPI
> +PciSegmentWrite8 (
> + IN UINT64 Address,
> + IN UINT8 Value
> + )
> +{
> + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 0);
> +
> + return (UINT8) PciSegmentLibWriteWorker (Address, PciCfgWidthUint8, Value);
> +}
> +
> +/**
> + Performs a bitwise OR of an 8-bit PCI configuration register with
> + an 8-bit value.
> +
> + Reads the 8-bit PCI configuration register specified by Address,
> + performs a bitwise OR between the read result and the value specified by
> + OrData, and writes the result to the 8-bit PCI configuration register
> + specified by Address.
> +
> + The value written to the PCI configuration register is returned.
> + This function must guarantee that all PCI read and write operations
> + are serialized.
> +
> + If any reserved bits in Address are set, then ASSERT().
> +
> + @param Address The address that encodes the PCI Segment, Bus, Device,
> + Function, and Register.
> + @param OrData The value to OR with the PCI configuration register.
> +
> + @return The value written to the PCI configuration register.
> +**/
> +UINT8
> +EFIAPI
> +PciSegmentOr8 (
> + IN UINT64 Address,
> + IN UINT8 OrData
> + )
> +{
> + return PciSegmentWrite8 (Address,
> + (UINT8) (PciSegmentRead8 (Address) | OrData));
> +}
> +
> +/**
> + Performs a bitwise AND of an 8-bit PCI configuration register with
> + an 8-bit value.
> +
> + Reads the 8-bit PCI configuration register specified by Address,
> + performs a bitwise AND between the read result and the value specified by
> + AndData, and writes the result to the 8-bit PCI configuration register
> + specified by Address.
> +
> + The value written to the PCI configuration register is returned.
> + This function must guarantee that all PCI read and write operations
> + are serialized. If any reserved bits in Address are set, then ASSERT().
> +
> + @param Address The address that encodes the PCI Segment, Bus, Device,
> + Function, and Register.
> + @param AndData The value to AND with the PCI configuration register.
> +
> + @return The value written to the PCI configuration register.
> +**/
> +UINT8
> +EFIAPI
> +PciSegmentAnd8 (
> + IN UINT64 Address,
> + IN UINT8 AndData
> + )
> +{
> + return PciSegmentWrite8 (Address,
> + (UINT8) (PciSegmentRead8 (Address) & AndData));
> +}
> +
> +/**
> + Performs a bitwise AND of an 8-bit PCI configuration register with
> + an 8-bit value, followed by a bitwise OR with another 8-bit value.
> +
> + Reads the 8-bit PCI configuration register specified by Address,
> + performs a bitwise AND between the read result and the value specified
> + by AndData, performs a bitwise OR between the result of the AND operation
> + and the value specified by OrData, and writes the result to the 8-bit
> + PCI configuration register specified by Address.
> +
> + The value written to the PCI configuration register is returned.
> + This function must guarantee that all PCI read and write operations
> + are serialized.
> +
> + If any reserved bits in Address are set, then ASSERT().
> +
> + @param Address The address that encodes the PCI Segment, Bus, Device,
> + Function, and Register.
> + @param AndData The value to AND with the PCI configuration register.
> + @param OrData The value to OR with the PCI configuration register.
> +
> + @return The value written to the PCI configuration register.
> +
> +**/
> +UINT8
> +EFIAPI
> +PciSegmentAndThenOr8 (
> + IN UINT64 Address,
> + IN UINT8 AndData,
> + IN UINT8 OrData
> + )
> +{
> + return PciSegmentWrite8 (Address,
> + (UINT8) ((PciSegmentRead8 (Address) & AndData)
> + | OrData));
> +}
> +
> +/**
> + Reads a bit field of a PCI configuration register.
> +
> + Reads the bit field in an 8-bit PCI configuration register. The bit field is
> + specified by the StartBit and the EndBit. The value of the bit field is
> + returned.
> +
> + If any reserved bits in Address are set, then ASSERT().
> + If StartBit is greater than 7, then ASSERT().
> + If EndBit is greater than 7, then ASSERT().
> + If EndBit is less than StartBit, then ASSERT().
> +
> + @param Address The PCI configuration register to read.
> + @param StartBit The ordinal of the least significant bit in the bit field.
> + Range 0..7.
> + @param EndBit The ordinal of the most significant bit in the bit field.
> + Range 0..7.
> +
> + @return The value of the bit field read from the PCI configuration register.
> +
> +**/
> +UINT8
> +EFIAPI
> +PciSegmentBitFieldRead8 (
> + IN UINT64 Address,
> + IN UINTN StartBit,
> + IN UINTN EndBit
> + )
> +{
> + return BitFieldRead8 (PciSegmentRead8 (Address), StartBit, EndBit);
> +}
> +
> +/**
> + Writes a bit field to a PCI configuration register.
> +
> + Writes Value to the bit field of the PCI configuration register. The bit
> + field is specified by the StartBit and the EndBit. All other bits in the
> + destination PCI configuration register are preserved. The new value of the
> + 8-bit register is returned.
> +
> + If any reserved bits in Address are set, then ASSERT().
> + If StartBit is greater than 7, then ASSERT().
> + If EndBit is greater than 7, then ASSERT().
> + If EndBit is less than StartBit, then ASSERT().
> + If Value is larger than the bitmask value range specified by StartBit
> + and EndBit, then ASSERT().
> +
> + @param Address The PCI configuration register to write.
> + @param StartBit The ordinal of the least significant bit in the bit field.
> + Range 0..7.
> + @param EndBit The ordinal of the most significant bit in the bit field.
> + Range 0..7.
> + @param Value The new value of the bit field.
> +
> + @return The value written back to the PCI configuration register.
> +
> +**/
> +UINT8
> +EFIAPI
> +PciSegmentBitFieldWrite8 (
> + IN UINT64 Address,
> + IN UINTN StartBit,
> + IN UINTN EndBit,
> + IN UINT8 Value
> + )
> +{
> + return PciSegmentWrite8 (Address,
> + BitFieldWrite8 (PciSegmentRead8 (Address),
> + StartBit,
> + EndBit,
> + Value));
> +}
> +
> +/**
> + Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and
> + writes the result back to the bit field in the 8-bit port.
> +
> + Reads the 8-bit PCI configuration register specified by Address, performs a
> + bitwise OR between the read result and the value specified by
> + OrData, and writes the result to the 8-bit PCI configuration register
> + specified by Address. The value written to the PCI configuration register is
> + returned. This function must guarantee that all PCI read and write operations
> + are serialized. Extra left bits in OrData are stripped.
> +
> + If any reserved bits in Address are set, then ASSERT().
> + If StartBit is greater than 7, then ASSERT().
> + If EndBit is greater than 7, then ASSERT().
> + If EndBit is less than StartBit, then ASSERT().
> + If OrData is larger than the bitmask value range specified by StartBit and
> + EndBit, then ASSERT().
> +
> + @param Address The PCI configuration register to write.
> + @param StartBit The ordinal of the least significant bit in the bit field.
> + Range 0..7.
> + @param EndBit The ordinal of the most significant bit in the bit field.
> + Range 0..7.
> + @param OrData The value to OR with the PCI configuration register.
> +
> + @return The value written back to the PCI configuration register.
> +
> +**/
> +UINT8
> +EFIAPI
> +PciSegmentBitFieldOr8 (
> + IN UINT64 Address,
> + IN UINTN StartBit,
> + IN UINTN EndBit,
> + IN UINT8 OrData
> + )
> +{
> + return PciSegmentWrite8 (Address,
> + BitFieldOr8 (PciSegmentRead8 (Address),
> + StartBit,
> + EndBit,
> + OrData));
> +}
> +
> +/**
> + Reads a bit field in an 8-bit PCI configuration register, performs a bitwise
> + AND, and writes the result back to the bit field in the 8-bit register.
> +
> + Reads the 8-bit PCI configuration register specified by Address, performs a
> + bitwise AND between the read result and the value specified by AndData, and
> + writes the result to the 8-bit PCI configuration register specified by
> + Address. The value written to the PCI configuration register is returned.
> + This function must guarantee that all PCI read and write operations are
> + serialized. Extra left bits in AndData are stripped.
> +
> + If any reserved bits in Address are set, then ASSERT().
> + If StartBit is greater than 7, then ASSERT().
> + If EndBit is greater than 7, then ASSERT().
> + If EndBit is less than StartBit, then ASSERT().
> + If AndData is larger than the bitmask value range specified by StartBit and
> + EndBit, then ASSERT().
> +
> + @param Address The PCI configuration register to write.
> + @param StartBit The ordinal of the least significant bit in the bit field.
> + Range 0..7.
> + @param EndBit The ordinal of the most significant bit in the bit field.
> + Range 0..7.
> + @param AndData The value to AND with the PCI configuration register.
> +
> + @return The value written back to the PCI configuration register.
> +
> +**/
> +UINT8
> +EFIAPI
> +PciSegmentBitFieldAnd8 (
> + IN UINT64 Address,
> + IN UINTN StartBit,
> + IN UINTN EndBit,
> + IN UINT8 AndData
> + )
> +{
> + return PciSegmentWrite8 (Address,
> + BitFieldAnd8 (PciSegmentRead8 (Address),
> + StartBit,
> + EndBit,
> + AndData));
> +}
> +
> +/**
> + Reads a bit field in an 8-bit port, performs a bitwise AND followed by a
> + bitwise OR, and writes the result back to the bit field in the
> + 8-bit port.
> +
> + Reads the 8-bit PCI configuration register specified by Address, performs a
> + bitwise AND followed by a bitwise OR between the read result and
> + the value specified by AndData, and writes the result to the 8-bit PCI
> + configuration register specified by Address. The value written to the PCI
> + configuration register is returned. This function must guarantee that all PCI
> + read and write operations are serialized. Extra left bits in both AndData and
> + OrData are stripped.
> +
> + If any reserved bits in Address are set, then ASSERT().
> + If StartBit is greater than 7, then ASSERT().
> + If EndBit is greater than 7, then ASSERT().
> + If EndBit is less than StartBit, then ASSERT().
> + If AndData is larger than the bitmask value range specified by StartBit
> + and EndBit, then ASSERT().
> + If OrData is larger than the bitmask value range specified by StartBit
> + and EndBit, then ASSERT().
> +
> + @param Address The PCI configuration register to write.
> + @param StartBit The ordinal of the least significant bit in the bit field.
> + Range 0..7.
> + @param EndBit The ordinal of the most significant bit in the bit field.
> + Range 0..7.
> + @param AndData The value to AND with the PCI configuration register.
> + @param OrData The value to OR with the result of the AND operation.
> +
> + @return The value written back to the PCI configuration register.
> +
> +**/
> +UINT8
> +EFIAPI
> +PciSegmentBitFieldAndThenOr8 (
> + IN UINT64 Address,
> + IN UINTN StartBit,
> + IN UINTN EndBit,
> + IN UINT8 AndData,
> + IN UINT8 OrData
> + )
> +{
> + return PciSegmentWrite8 (Address,
> + BitFieldAndThenOr8 (PciSegmentRead8 (Address),
> + StartBit,
> + EndBit,
> + AndData,
> + OrData));
> +}
> +
> +/**
> + Reads a 16-bit PCI configuration register.
> +
> + Reads and returns the 16-bit PCI configuration register specified by Address.
> + This function must guarantee that all PCI read and write operations
> + are serialized.
> +
> + If any reserved bits in Address are set, then ASSERT().
> + If Address is not aligned on a 16-bit boundary, then ASSERT().
> +
> + @param Address The address that encodes the PCI Segment, Bus, Device,
> + Function, and Register.
> +
> + @return The 16-bit PCI configuration register specified by Address.
> +
> +**/
> +UINT16
> +EFIAPI
> +PciSegmentRead16 (
> + IN UINT64 Address
> + )
> +{
> + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 1);
> +
> + return (UINT16) PciSegmentLibReadWorker (Address, PciCfgWidthUint16);
> +}
> +
> +/**
> + Writes a 16-bit PCI configuration register.
> +
> + Writes the 16-bit PCI configuration register specified by Address with the
> + value specified by Value. Value is returned.
> + This function must guarantee that all PCI read and write operations
> + are serialized.
> +
> + If any reserved bits in Address are set, then ASSERT().
> + If Address is not aligned on a 16-bit boundary, then ASSERT().
> +
> + @param Address The address that encodes the PCI Segment, Bus, Device,
> + Function, and Register.
> + @param Value The value to write.
> +
> + @return The Value written is returned.
> +
> +**/
> +UINT16
> +EFIAPI
> +PciSegmentWrite16 (
> + IN UINT64 Address,
> + IN UINT16 Value
> + )
> +{
> + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 1);
> +
> + return (UINT16) PciSegmentLibWriteWorker (Address, PciCfgWidthUint16, Value);
> +}
> +
> +/**
> + Performs a bitwise OR of a 16-bit PCI configuration register with
> + a 16-bit value.
> +
> + Reads the 16-bit PCI configuration register specified by Address, performs a
> + bitwise OR between the read result and the value specified by
> + OrData, and writes the result to the 16-bit PCI configuration register
> + specified by Address. The value written to the PCI configuration register is
> + returned. This function must guarantee that all PCI read and write operations
> + are serialized.
> +
> + If any reserved bits in Address are set, then ASSERT().
> + If Address is not aligned on a 16-bit boundary, then ASSERT().
> +
> + @param Address The address that encodes the PCI Segment, Bus, Device,
> + Function and Register.
> + @param OrData The value to OR with the PCI configuration register.
> +
> + @return The value written back to the PCI configuration register.
> +
> +**/
> +UINT16
> +EFIAPI
> +PciSegmentOr16 (
> + IN UINT64 Address,
> + IN UINT16 OrData
> + )
> +{
> + return PciSegmentWrite16 (Address,
> + (UINT16) (PciSegmentRead16 (Address) | OrData));
> +}
> +
> +/**
> + Performs a bitwise AND of a 16-bit PCI configuration register with
> + a 16-bit value.
> +
> + Reads the 16-bit PCI configuration register specified by Address,
> + performs a bitwise AND between the read result and the value specified
> + by AndData, and writes the result to the 16-bit PCI configuration register
> + specified by the Address.
> +
> + The value written to the PCI configuration register is returned.
> + This function must guarantee that all PCI read and write operations
> + are serialized.
> +
> + If any reserved bits in Address are set, then ASSERT().
> + If Address is not aligned on a 16-bit boundary, then ASSERT().
> +
> + @param Address The address that encodes the PCI Segment, Bus, Device,
> + Function, and Register.
> + @param AndData The value to AND with the PCI configuration register.
> +
> + @return The value written to the PCI configuration register.
> +
> +**/
> +UINT16
> +EFIAPI
> +PciSegmentAnd16 (
> + IN UINT64 Address,
> + IN UINT16 AndData
> + )
> +{
> + return PciSegmentWrite16 (Address,
> + (UINT16) (PciSegmentRead16 (Address) & AndData));
> +}
> +
> +/**
> + Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
> + value, followed a bitwise OR with another 16-bit value.
> +
> + Reads the 16-bit PCI configuration register specified by Address,
> + performs a bitwise AND between the read result and the value specified by
> + AndData, performs a bitwise OR between the result of the AND operation and
> + the value specified by OrData, and writes the result to the 16-bit PCI
> + configuration register specified by the Address.
> +
> + The value written to the PCI configuration register is returned.
> + This function must guarantee that all PCI read and write operations
> + are serialized.
> +
> + If any reserved bits in Address are set, then ASSERT().
> + If Address is not aligned on a 16-bit boundary, then ASSERT().
> +
> + @param Address The address that encodes the PCI Segment, Bus, Device,
> + Function, and Register.
> + @param AndData The value to AND with the PCI configuration register.
> + @param OrData The value to OR with the PCI configuration register.
> +
> + @return The value written to the PCI configuration register.
> +
> +**/
> +UINT16
> +EFIAPI
> +PciSegmentAndThenOr16 (
> + IN UINT64 Address,
> + IN UINT16 AndData,
> + IN UINT16 OrData
> + )
> +{
> + return PciSegmentWrite16 (Address,
> + (UINT16) ((PciSegmentRead16 (Address) & AndData)
> + | OrData));
> +}
> +
> +/**
> + Reads a bit field of a PCI configuration register.
> +
> + Reads the bit field in a 16-bit PCI configuration register. The bit field is
> + specified by the StartBit and the EndBit. The value of the bit field is
> + returned.
> +
> + If any reserved bits in Address are set, then ASSERT().
> + If Address is not aligned on a 16-bit boundary, then ASSERT().
> + If StartBit is greater than 15, then ASSERT().
> + If EndBit is greater than 15, then ASSERT().
> + If EndBit is less than StartBit, then ASSERT().
> +
> + @param Address The PCI configuration register to read.
> + @param StartBit The ordinal of the least significant bit in the bit field.
> + Range 0..15.
> + @param EndBit The ordinal of the most significant bit in the bit field.
> + Range 0..15.
> +
> + @return The value of the bit field read from the PCI configuration register.
> +
> +**/
> +UINT16
> +EFIAPI
> +PciSegmentBitFieldRead16 (
> + IN UINT64 Address,
> + IN UINTN StartBit,
> + IN UINTN EndBit
> + )
> +{
> + return BitFieldRead16 (PciSegmentRead16 (Address), StartBit, EndBit);
> +}
> +
> +/**
> + Writes a bit field to a PCI configuration register.
> +
> + Writes Value to the bit field of the PCI configuration register. The bit
> + field is specified by the StartBit and the EndBit. All other bits in the
> + destination PCI configuration register are preserved. The new value of the
> + 16-bit register is returned.
> +
> + If any reserved bits in Address are set, then ASSERT().
> + If Address is not aligned on a 16-bit boundary, then ASSERT().
> + If StartBit is greater than 15, then ASSERT().
> + If EndBit is greater than 15, then ASSERT().
> + If EndBit is less than StartBit, then ASSERT().
> + If Value is larger than the bitmask value range specified by StartBit and
> + EndBit, then ASSERT().
> +
> + @param Address The PCI configuration register to write.
> + @param StartBit The ordinal of the least significant bit in the bit field.
> + Range 0..15.
> + @param EndBit The ordinal of the most significant bit in the bit field.
> + Range 0..15.
> + @param Value The new value of the bit field.
> +
> + @return The value written back to the PCI configuration register.
> +
> +**/
> +UINT16
> +EFIAPI
> +PciSegmentBitFieldWrite16 (
> + IN UINT64 Address,
> + IN UINTN StartBit,
> + IN UINTN EndBit,
> + IN UINT16 Value
> + )
> +{
> + return PciSegmentWrite16 (Address,
> + BitFieldWrite16 (PciSegmentRead16 (Address),
> + StartBit,
> + EndBit,
> + Value));
> +}
> +
> +/**
> + Reads the 16-bit PCI configuration register specified by Address,
> + performs a bitwise OR between the read result and the value specified
> + by OrData, and writes the result to the 16-bit PCI configuration register
> + specified by the Address.
> +
> + If any reserved bits in Address are set, then ASSERT().
> + If Address is not aligned on a 16-bit boundary, then ASSERT().
> + If StartBit is greater than 15, then ASSERT().
> + If EndBit is greater than 15, then ASSERT().
> + If EndBit is less than StartBit, then ASSERT().
> + If OrData is larger than the bitmask value range specified by StartBit and
> + EndBit, then ASSERT().
> +
> + @param Address The PCI configuration register to write.
> + @param StartBit The ordinal of the least significant bit in the bit field.
> + Range 0..15.
> + @param EndBit The ordinal of the most significant bit in the bit field.
> + Range 0..15.
> + @param OrData The value to OR with the PCI configuration register.
> +
> + @return The value written back to the PCI configuration register.
> +
> +**/
> +UINT16
> +EFIAPI
> +PciSegmentBitFieldOr16 (
> + IN UINT64 Address,
> + IN UINTN StartBit,
> + IN UINTN EndBit,
> + IN UINT16 OrData
> + )
> +{
> + return PciSegmentWrite16 (Address,
> + BitFieldOr16 (PciSegmentRead16 (Address),
> + StartBit,
> + EndBit,
> + OrData));
> +}
> +
> +/**
> + Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR,
> + and writes the result back to the bit field in the 16-bit port.
> +
> + Reads the 16-bit PCI configuration register specified by Address,
> + performs a bitwise OR between the read result and the value specified by
> + OrData, and writes the result to the 16-bit PCI configuration register
> + specified by the Address.
> +
> + The value written to the PCI configuration register is returned.
> + This function must guarantee that all PCI read and write operations are
> + serialized. Extra left bits in OrData are stripped.
> +
> + If any reserved bits in Address are set, then ASSERT().
> + If Address is not aligned on a 16-bit boundary, then ASSERT().
> + If StartBit is greater than 7, then ASSERT().
> + If EndBit is greater than 7, then ASSERT().
> + If EndBit is less than StartBit, then ASSERT().
> + If AndData is larger than the bitmask value range specified by StartBit and
> + EndBit, then ASSERT().
> +
> + @param Address The address that encodes the PCI Segment, Bus, Device,
> + Function, and Register.
> + @param StartBit The ordinal of the least significant bit in the bit field.
> + The ordinal of the least significant bit in a byte is
> + bit 0.
> + @param EndBit The ordinal of the most significant bit in the bit field.
> + The ordinal of the most significant bit in a byte is bit 7.
> + @param AndData The value to AND with the read value from the PCI
> + configuration register.
> +
> + @return The value written to the PCI configuration register.
> +
> +**/
> +UINT16
> +EFIAPI
> +PciSegmentBitFieldAnd16 (
> + IN UINT64 Address,
> + IN UINTN StartBit,
> + IN UINTN EndBit,
> + IN UINT16 AndData
> + )
> +{
> + return PciSegmentWrite16 (Address,
> + BitFieldAnd16 (PciSegmentRead16 (Address),
> + StartBit,
> + EndBit,
> + AndData));
> +}
> +
> +/**
> + Reads a bit field in a 16-bit port, performs a bitwise AND followed by a
> + bitwise OR, and writes the result back to the bit field in the
> + 16-bit port.
> +
> + Reads the 16-bit PCI configuration register specified by Address, performs a
> + bitwise AND followed by a bitwise OR between the read result and
> + the value specified by AndData, and writes the result to the 16-bit PCI
> + configuration register specified by Address. The value written to the PCI
> + configuration register is returned. This function must guarantee that all PCI
> + read and write operations are serialized. Extra left bits in both AndData and
> + OrData are stripped.
> +
> + If any reserved bits in Address are set, then ASSERT().
> + If StartBit is greater than 15, then ASSERT().
> + If EndBit is greater than 15, then ASSERT().
> + If EndBit is less than StartBit, then ASSERT().
> + If AndData is larger than the bitmask value range specified by StartBit and
> + EndBit, then ASSERT().
> + If OrData is larger than the bitmask value range specified by StartBit and
> + EndBit, then ASSERT().
> +
> + @param Address The PCI configuration register to write.
> + @param StartBit The ordinal of the least significant bit in the bit field.
> + Range 0..15.
> + @param EndBit The ordinal of the most significant bit in the bit field.
> + Range 0..15.
> + @param AndData The value to AND with the PCI configuration register.
> + @param OrData The value to OR with the result of the AND operation.
> +
> + @return The value written back to the PCI configuration register.
> +
> +**/
> +UINT16
> +EFIAPI
> +PciSegmentBitFieldAndThenOr16 (
> + IN UINT64 Address,
> + IN UINTN StartBit,
> + IN UINTN EndBit,
> + IN UINT16 AndData,
> + IN UINT16 OrData
> + )
> +{
> + return PciSegmentWrite16 (Address,
> + BitFieldAndThenOr16 (PciSegmentRead16 (Address),
> + StartBit,
> + EndBit,
> + AndData,
> + OrData));
> +}
> +
> +/**
> + Reads a 32-bit PCI configuration register.
> +
> + Reads and returns the 32-bit PCI configuration register specified by Address.
> + This function must guarantee that all PCI read and write operations
> + are serialized.
> +
> + If any reserved bits in Address are set, then ASSERT().
> + If Address is not aligned on a 32-bit boundary, then ASSERT().
> +
> + @param Address The address that encodes the PCI Segment, Bus,
> + Device, Function and Register.
> +
> + @return The 32-bit PCI configuration register specified by Address.
> +
> +**/
> +UINT32
> +EFIAPI
> +PciSegmentRead32 (
> + IN UINT64 Address
> + )
> +{
> + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 3);
> +
> + return PciSegmentLibReadWorker (Address, PciCfgWidthUint32);
> +}
> +
> +/**
> + Writes a 32-bit PCI configuration register.
> +
> + Writes the 32-bit PCI configuration register specified by Address with the
> + value specified by Value. Value is returned. This function must guarantee
> + that all PCI read and write operations are serialized.
> +
> + If any reserved bits in Address are set, then ASSERT().
> + If Address is not aligned on a 32-bit boundary, then ASSERT().
> +
> + @param Address The address that encodes the PCI Segment, Bus, Device,
> + Function, and Register.
> + @param Value The value to write.
> +
> + @return The parameter of Value.
> +
> +**/
> +UINT32
> +EFIAPI
> +PciSegmentWrite32 (
> + IN UINT64 Address,
> + IN UINT32 Value
> + )
> +{
> + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 3);
> +
> + return PciSegmentLibWriteWorker (Address, PciCfgWidthUint32, Value);
> +}
> +
> +/**
> + Performs a bitwise OR of a 32-bit PCI configuration register with a
> + 32-bit value.
> +
> + Reads the 32-bit PCI configuration register specified by Address,
> + performs a bitwise OR between the read result and the value specified
> + by OrData, and writes the result to the 32-bit PCI configuration register
> + specified by Address.
> +
> + The value written to the PCI configuration register is returned.
> + This function must guarantee that all PCI read and write operations
> + are serialized.
> +
> + If any reserved bits in Address are set, then ASSERT().
> + If Address is not aligned on a 32-bit boundary, then ASSERT().
> +
> + @param Address The address that encodes the PCI Segment, Bus, Device,
> + Function, and Register.
> + @param OrData The value to OR with the PCI configuration register.
> +
> + @return The value written to the PCI configuration register.
> +
> +**/
> +UINT32
> +EFIAPI
> +PciSegmentOr32 (
> + IN UINT64 Address,
> + IN UINT32 OrData
> + )
> +{
> + return PciSegmentWrite32 (Address, PciSegmentRead32 (Address) | OrData);
> +}
> +
> +/**
> + Performs a bitwise AND of a 32-bit PCI configuration register with
> + a 32-bit value.
> +
> + Reads the 32-bit PCI configuration register specified by Address,
> + performs a bitwise AND between the read result and the value specified
> + by AndData, and writes the result to the 32-bit PCI configuration register
> + specified by Address.
> + The value written to the PCI configuration register is returned.
> + This function must guarantee that all PCI read and write operations
> + are serialized.
> +
> + If any reserved bits in Address are set, then ASSERT().
> + If Address is not aligned on a 32-bit boundary, then ASSERT().
> +
> + @param Address The address that encodes the PCI Segment, Bus,
> + Device, Function and Register.
> + @param AndData The value to AND with the PCI configuration register.
> +
> + @return The value written to the PCI configuration register.
> +
> +**/
> +UINT32
> +EFIAPI
> +PciSegmentAnd32 (
> + IN UINT64 Address,
> + IN UINT32 AndData
> + )
> +{
> + return PciSegmentWrite32 (Address, PciSegmentRead32 (Address) & AndData);
> +}
> +
> +/**
> + Performs a bitwise AND of a 32-bit PCI configuration register with
> + a 32-bit value, followed by a bitwise OR with another 32-bit value.
> +
> + Reads the 32-bit PCI configuration register specified by Address,
> + performs a bitwise AND between the read result and the value specified
> + by AndData, performs a bitwise OR between the result of the AND operation
> + and the value specified by OrData, and writes the result to the 32-bit
> + PCI configuration register specified by Address.
> +
> + The value written to the PCI configuration register is returned.
> + This function must guarantee that all PCI read and write operations
> + are serialized.
> +
> + If any reserved bits in Address are set, then ASSERT().
> + If Address is not aligned on a 32-bit boundary, then ASSERT().
> +
> + @param Address The address that encodes the PCI Segment, Bus, Device,
> + Function and Register.
> + @param AndData The value to AND with the PCI configuration register.
> + @param OrData The value to OR with the PCI configuration register.
> +
> + @return The value written to the PCI configuration register.
> +
> +**/
> +UINT32
> +EFIAPI
> +PciSegmentAndThenOr32 (
> + IN UINT64 Address,
> + IN UINT32 AndData,
> + IN UINT32 OrData
> + )
> +{
> + return PciSegmentWrite32 (Address,
> + (PciSegmentRead32 (Address) & AndData) | OrData);
> +}
> +
> +/**
> + Reads a bit field of a PCI configuration register.
> +
> + Reads the bit field in a 32-bit PCI configuration register. The bit field is
> + specified by the StartBit and the EndBit. The value of the bit field is
> + returned.
> +
> + If any reserved bits in Address are set, then ASSERT().
> + If Address is not aligned on a 32-bit boundary, then ASSERT().
> + If StartBit is greater than 31, then ASSERT().
> + If EndBit is greater than 31, then ASSERT().
> + If EndBit is less than StartBit, then ASSERT().
> +
> + @param Address The PCI configuration register to read.
> + @param StartBit The ordinal of the least significant bit in the bit field.
> + Range 0..31.
> + @param EndBit The ordinal of the most significant bit in the bit field.
> + Range 0..31.
> +
> + @return The value of the bit field read from the PCI configuration register.
> +
> +**/
> +UINT32
> +EFIAPI
> +PciSegmentBitFieldRead32 (
> + IN UINT64 Address,
> + IN UINTN StartBit,
> + IN UINTN EndBit
> + )
> +{
> + return BitFieldRead32 (PciSegmentRead32 (Address), StartBit, EndBit);
> +}
> +
> +/**
> + Writes a bit field to a PCI configuration register.
> +
> + Writes Value to the bit field of the PCI configuration register. The bit
> + field is specified by the StartBit and the EndBit. All other bits in the
> + destination PCI configuration register are preserved. The new value of the
> + 32-bit register is returned.
> +
> + If any reserved bits in Address are set, then ASSERT().
> + If Address is not aligned on a 32-bit boundary, then ASSERT().
> + If StartBit is greater than 31, then ASSERT().
> + If EndBit is greater than 31, then ASSERT().
> + If EndBit is less than StartBit, then ASSERT().
> + If Value is larger than the bitmask value range specified by StartBit
> + and EndBit, then ASSERT().
> +
> + @param Address The PCI configuration register to write.
> + @param StartBit The ordinal of the least significant bit in the bit field.
> + Range 0..31.
> + @param EndBit The ordinal of the most significant bit in the bit field.
> + Range 0..31.
> + @param Value The new value of the bit field.
> +
> + @return The value written back to the PCI configuration register.
> +
> +**/
> +UINT32
> +EFIAPI
> +PciSegmentBitFieldWrite32 (
> + IN UINT64 Address,
> + IN UINTN StartBit,
> + IN UINTN EndBit,
> + IN UINT32 Value
> + )
> +{
> + return PciSegmentWrite32 (Address,
> + BitFieldWrite32 (PciSegmentRead32 (Address),
> + StartBit,
> + EndBit,
> + Value));
> +}
> +
> +/**
> + Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and
> + writes the result back to the bit field in the 32-bit port.
> +
> + Reads the 32-bit PCI configuration register specified by Address, performs a
> + bitwise OR between the read result and the value specified by
> + OrData, and writes the result to the 32-bit PCI configuration register
> + specified by Address. The value written to the PCI configuration register is
> + returned. This function must guarantee that all PCI read and write operations
> + are serialized. Extra left bits in OrData are stripped.
> +
> + If any reserved bits in Address are set, then ASSERT().
> + If StartBit is greater than 31, then ASSERT().
> + If EndBit is greater than 31, then ASSERT().
> + If EndBit is less than StartBit, then ASSERT().
> + If OrData is larger than the bitmask value range specified by StartBit and
> + EndBit, then ASSERT().
> +
> + @param Address The PCI configuration register to write.
> + @param StartBit The ordinal of the least significant bit in the bit field.
> + Range 0..31.
> + @param EndBit The ordinal of the most significant bit in the bit field.
> + Range 0..31.
> + @param OrData The value to OR with the PCI configuration register.
> +
> + @return The value written back to the PCI configuration register.
> +
> +**/
> +UINT32
> +EFIAPI
> +PciSegmentBitFieldOr32 (
> + IN UINT64 Address,
> + IN UINTN StartBit,
> + IN UINTN EndBit,
> + IN UINT32 OrData
> + )
> +{
> + return PciSegmentWrite32 (Address,
> + BitFieldOr32 (PciSegmentRead32 (Address),
> + StartBit,
> + EndBit,
> + OrData));
> +}
> +
> +/**
> + Reads a bit field in a 32-bit PCI configuration register, performs a bitwise
> + AND, and writes the result back to the bit field in the 32-bit register.
> +
> + Reads the 32-bit PCI configuration register specified by Address,
> + performs a bitwise AND between the read result and the value specified
> + by AndData, and writes the result to the 32-bit PCI configuration register
> + specified by Address. The value written to the PCI configuration register
> + is returned. This function must guarantee that all PCI read and write
> + operations are serialized. Extra left bits in AndData are stripped.
> +
> + If any reserved bits in Address are set, then ASSERT().
> + If Address is not aligned on a 32-bit boundary, then ASSERT().
> + If StartBit is greater than 31, then ASSERT().
> + If EndBit is greater than 31, then ASSERT().
> + If EndBit is less than StartBit, then ASSERT().
> + If AndData is larger than the bitmask value range specified by StartBit and
> + EndBit, then ASSERT().
> +
> + @param Address The PCI configuration register to write.
> + @param StartBit The ordinal of the least significant bit in the bit field.
> + Range 0..31.
> + @param EndBit The ordinal of the most significant bit in the bit field.
> + Range 0..31.
> + @param AndData The value to AND with the PCI configuration register.
> +
> + @return The value written back to the PCI configuration register.
> +
> +**/
> +UINT32
> +EFIAPI
> +PciSegmentBitFieldAnd32 (
> + IN UINT64 Address,
> + IN UINTN StartBit,
> + IN UINTN EndBit,
> + IN UINT32 AndData
> + )
> +{
> + return PciSegmentWrite32 (Address,
> + BitFieldAnd32 (PciSegmentRead32 (Address),
> + StartBit,
> + EndBit,
> + AndData));
> +}
> +
> +/**
> + Reads a bit field in a 32-bit port, performs a bitwise AND followed by a
> + bitwise OR, and writes the result back to the bit field in the
> + 32-bit port.
> +
> + Reads the 32-bit PCI configuration register specified by Address, performs a
> + bitwise AND followed by a bitwise OR between the read result and
> + the value specified by AndData, and writes the result to the 32-bit PCI
> + configuration register specified by Address. The value written to the PCI
> + configuration register is returned. This function must guarantee that all PCI
> + read and write operations are serialized. Extra left bits in both AndData and
> + OrData are stripped.
> +
> + If any reserved bits in Address are set, then ASSERT().
> + If StartBit is greater than 31, then ASSERT().
> + If EndBit is greater than 31, then ASSERT().
> + If EndBit is less than StartBit, then ASSERT().
> + If AndData is larger than the bitmask value range specified by StartBit
> + and EndBit, then ASSERT().
> + If OrData is larger than the bitmask value range specified by StartBit
> + and EndBit, then ASSERT().
> +
> + @param Address The PCI configuration register to write.
> + @param StartBit The ordinal of the least significant bit in the bit field.
> + Range 0..31.
> + @param EndBit The ordinal of the most significant bit in the bit field.
> + Range 0..31.
> + @param AndData The value to AND with the PCI configuration register.
> + @param OrData The value to OR with the result of the AND operation.
> +
> + @return The value written back to the PCI configuration register.
> +
> +**/
> +UINT32
> +EFIAPI
> +PciSegmentBitFieldAndThenOr32 (
> + IN UINT64 Address,
> + IN UINTN StartBit,
> + IN UINTN EndBit,
> + IN UINT32 AndData,
> + IN UINT32 OrData
> + )
> +{
> + return PciSegmentWrite32 (
> + Address,
> + BitFieldAndThenOr32 (PciSegmentRead32 (Address),
> + StartBit,
> + EndBit,
> + AndData,
> + OrData));
> +}
> +
> +/**
> + Reads a range of PCI configuration registers into a caller supplied buffer.
> +
> + Reads the range of PCI configuration registers specified by StartAddress and
> + Size into the buffer specified by Buffer. This function only allows the PCI
> + configuration registers from a single PCI function to be read. Size is
> + returned. When possible 32-bit PCI configuration read cycles are used to read
> + from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit
> + and 16-bit PCI configuration read cycles may be used at the beginning and the
> + end of the range.
> +
> + If any reserved bits in StartAddress are set, then ASSERT().
> + If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
> + If Size > 0 and Buffer is NULL, then ASSERT().
> +
> + @param StartAddress The starting address that encodes the PCI Segment, Bus,
> + Device, Function and Register.
> + @param Size The size in bytes of the transfer.
> + @param Buffer The pointer to a buffer receiving the data read.
> +
> + @return Size
> +
> +**/
> +UINTN
> +EFIAPI
> +PciSegmentReadBuffer (
> + IN UINT64 StartAddress,
> + IN UINTN Size,
> + OUT VOID *Buffer
> + )
> +{
> + UINTN ReturnValue;
> +
> + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (StartAddress, 0);
> + ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);
> +
> + if (Size == 0) {
> + return Size;
> + }
> +
> + ASSERT (Buffer != NULL);
> +
> + // Save Size for return
> + ReturnValue = Size;
> +
> + if ((StartAddress & BIT0) != 0) {
> + // Read a byte if StartAddress is byte aligned
> + *(volatile UINT8 *)Buffer = PciSegmentRead8 (StartAddress);
> + StartAddress += sizeof (UINT8);
> + Size -= sizeof (UINT8);
> + Buffer = (UINT8*)Buffer + 1;
> + }
> +
> + if (Size >= sizeof (UINT16) && (StartAddress & BIT1) != 0) {
> + // Read a word if StartAddress is word aligned
> + WriteUnaligned16 (Buffer, PciSegmentRead16 (StartAddress));
> + StartAddress += sizeof (UINT16);
> + Size -= sizeof (UINT16);
> + Buffer = (UINT16*)Buffer + 1;
> + }
> +
> + while (Size >= sizeof (UINT32)) {
> + // Read as many double words as possible
> + WriteUnaligned32 (Buffer, PciSegmentRead32 (StartAddress));
> + StartAddress += sizeof (UINT32);
> + Size -= sizeof (UINT32);
> + Buffer = (UINT32*)Buffer + 1;
> + }
> +
> + if (Size >= sizeof (UINT16)) {
> + // Read the last remaining word if exist
> + WriteUnaligned16 (Buffer, PciSegmentRead16 (StartAddress));
> + StartAddress += sizeof (UINT16);
> + Size -= sizeof (UINT16);
> + Buffer = (UINT16*)Buffer + 1;
> + }
> +
> + if (Size >= sizeof (UINT8)) {
> + // Read the last remaining byte if exist
> + *(volatile UINT8 *)Buffer = PciSegmentRead8 (StartAddress);
> + }
> +
> + return ReturnValue;
> +}
> +
> +/**
> + Copies the data in a caller supplied buffer to a specified range of PCI
> + configuration space.
> +
> + Writes the range of PCI configuration registers specified by StartAddress and
> + Size from the buffer specified by Buffer. This function only allows the PCI
> + configuration registers from a single PCI function to be written. Size is
> + returned. When possible 32-bit PCI configuration write cycles are used to
> + write from StartAdress to StartAddress + Size. Due to alignment restrictions,
> + 8-bit and 16-bit PCI configuration write cycles may be used at the beginning
> + and the end of the range.
> +
> + If any reserved bits in StartAddress are set, then ASSERT().
> + If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
> + If Size > 0 and Buffer is NULL, then ASSERT().
> +
> + @param StartAddress The starting address that encodes the PCI Segment, Bus,
> + Device, Function and Register.
> + @param Size The size in bytes of the transfer.
> + @param Buffer The pointer to a buffer containing the data to write.
> +
> + @return The parameter of Size.
> +
> +**/
> +UINTN
> +EFIAPI
> +PciSegmentWriteBuffer (
> + IN UINT64 StartAddress,
> + IN UINTN Size,
> + IN VOID *Buffer
> + )
> +{
> + UINTN ReturnValue;
> +
> + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (StartAddress, 0);
> + ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);
> +
> + if (Size == 0) {
> + return 0;
> + }
> +
> + ASSERT (Buffer != NULL);
> +
> + // Save Size for return
> + ReturnValue = Size;
> +
> + if ((StartAddress & BIT0) != 0) {
> + // Write a byte if StartAddress is byte aligned
> + PciSegmentWrite8 (StartAddress, *(UINT8*)Buffer);
> + StartAddress += sizeof (UINT8);
> + Size -= sizeof (UINT8);
> + Buffer = (UINT8*)Buffer + 1;
> + }
> +
> + if (Size >= sizeof (UINT16) && (StartAddress & BIT1) != 0) {
> + // Write a word if StartAddress is word aligned
> + PciSegmentWrite16 (StartAddress, ReadUnaligned16 (Buffer));
> + StartAddress += sizeof (UINT16);
> + Size -= sizeof (UINT16);
> + Buffer = (UINT16*)Buffer + 1;
> + }
> +
> + while (Size >= sizeof (UINT32)) {
> + // Write as many double words as possible
> + PciSegmentWrite32 (StartAddress, ReadUnaligned32 (Buffer));
> + StartAddress += sizeof (UINT32);
> + Size -= sizeof (UINT32);
> + Buffer = (UINT32*)Buffer + 1;
> + }
> +
> + if (Size >= sizeof (UINT16)) {
> + // Write the last remaining word if exist
> + PciSegmentWrite16 (StartAddress, ReadUnaligned16 (Buffer));
> + StartAddress += sizeof (UINT16);
> + Size -= sizeof (UINT16);
> + Buffer = (UINT16*)Buffer + 1;
> + }
> +
> + if (Size >= sizeof (UINT8)) {
> + // Write the last remaining byte if exist
> + PciSegmentWrite8 (StartAddress, *(UINT8*)Buffer);
> + }
> +
> + return ReturnValue;
> +}
> diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PciSegmentLib/PciSegmentLib.inf b/Silicon/ARM/NeoverseN1Soc/Library/PciSegmentLib/PciSegmentLib.inf
> new file mode 100644
> index 0000000000..1d15f74faf
> --- /dev/null
> +++ b/Silicon/ARM/NeoverseN1Soc/Library/PciSegmentLib/PciSegmentLib.inf
> @@ -0,0 +1,38 @@
> +## @file
> +# PCI Segment Library for N1Sdp SoC with multiple RCs
> +#
> +# Copyright (c) 2007 - 2014, Intel Corporation. All rights reserved.<BR>
> +# Copyright (c) 2021, ARM Limited. All rights reserved.<BR>
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +##
> +
> +[Defines]
> + INF_VERSION = 0x00010019
> + BASE_NAME = PciSegmentLib
> + FILE_GUID = b5ecc9c3-6b30-4f72-8a06-889b4ea8427e
> + MODULE_TYPE = BASE
> + VERSION_STRING = 1.0
> + LIBRARY_CLASS = PciSegmentLib
> +
> +[Sources]
> + PciSegmentLib.c
> +
> +[Packages]
> + MdePkg/MdePkg.dec
> + Platform/ARM/N1Sdp/N1SdpPlatform.dec
> + Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec
> +
> +[LibraryClasses]
> + BaseLib
> + DebugLib
> + IoLib
> +
> +[FixedPcd]
> + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixExpressBaseAddress
> + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieExpressBaseAddress
> + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixRootPortConfigBaseAddress
> + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixRootPortConfigBaseSize
> + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieRootPortConfigBaseAddress
> + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieRootPortConfigBaseSize
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [edk2-devel] [PATCH v5 1/4] Silicon/ARM/NeoverseN1Soc: Port PCI Segment Library
2021-12-22 1:14 ` [PATCH v5 1/4] Silicon/ARM/NeoverseN1Soc: Port PCI Segment Library Khasim Mohammed
2021-12-22 8:52 ` [edk2-devel] " PierreGondois
@ 2022-01-19 15:01 ` Sami Mujawar
1 sibling, 0 replies; 13+ messages in thread
From: Sami Mujawar @ 2022-01-19 15:01 UTC (permalink / raw)
To: devel, khasim.mohammed; +Cc: nd
Hi Khasim,
Thank you for this patch.
Please find my feedback marked inline as [SAMI].
Regards,
Sami Mujawar
On 22/12/2021 01:14 AM, Khasim Mohammed via groups.io wrote:
> The BasePCISegment Library in MdePkg doesn't allow configuring
> multiple segments required for PCIe and CCIX root port
> enumeration. Therefore, a custom PCI Segment library is adapted
> from SynQuacerPciSegmentLib and ported for N1Sdp.
>
> In addition to this, the hardware has few other limitations which affects
> the access to the PCIe root port:
> 1. ECAM space is not contiguous, root port ECAM (BDF = 0:0:0) is isolated
> from rest of the downstream hierarchy ECAM space.
> 2. Root port ECAM space is not capable of 8bit/16bit writes.
> 3. A slave error is generated when host accesses the configuration
> space of non-available device or unimplemented function on a
> given bus.
>
> The description of the workarounds included for these limitations can
> be found in the corresponding files of this patch.
>
> Signed-off-by: Khasim Syed Mohammed <khasim.mohammed@arm.com>
> ---
> .../Library/PciSegmentLib/PciSegmentLib.c | 1602 +++++++++++++++++
> .../Library/PciSegmentLib/PciSegmentLib.inf | 38 +
> 2 files changed, 1640 insertions(+)
> create mode 100644 Silicon/ARM/NeoverseN1Soc/Library/PciSegmentLib/PciSegmentLib.c
> create mode 100644 Silicon/ARM/NeoverseN1Soc/Library/PciSegmentLib/PciSegmentLib.inf
>
> diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PciSegmentLib/PciSegmentLib.c b/Silicon/ARM/NeoverseN1Soc/Library/PciSegmentLib/PciSegmentLib.c
> new file mode 100644
> index 0000000000..a39a414044
> --- /dev/null
> +++ b/Silicon/ARM/NeoverseN1Soc/Library/PciSegmentLib/PciSegmentLib.c
> @@ -0,0 +1,1602 @@
> +/** @file
> + PCI Segment Library for N1SDP SoC with multiple RCs
> +
> + Having two distinct root complexes is not supported by the standard
> + set of PciLib/PciExpressLib/PciSegmentLib, this PciSegmentLib
> + reimplements the functionality to support multiple root ports on
> + different segment numbers.
> +
> + On the NeoverseN1Soc, a slave error is generated when host accesses the
> + configuration space of non-available device or unimplemented function on a
> + given bus. So this library introduces a workaround using IsBdfValid(),
> + to return 0xFFFFFFFF for all such access.
> +
> + In addition to this, the hardware has two other limitations which affect
> + access to the PCIe root port:
> + 1. ECAM space is not contiguous, root port ECAM (BDF = 0:0:0) is isolated
> + from rest of the downstream hierarchy ECAM space.
> + 2. Root port ECAM space is not capable of 8bit/16bit writes.
> + The description of the workarounds included for these limitations can
> + be found in the comments below.
> +
> + Copyright (c) 2007 - 2012, Intel Corporation. All rights reserved.<BR>
> + Copyright (c) 2021, ARM Limited. All rights reserved.<BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +
> +#include <Base.h>
> +
> +#include <Library/BaseLib.h>
> +#include <Library/DebugLib.h>
> +#include <Library/IoLib.h>
> +#include <Library/PcdLib.h>
> +#include <Library/PciSegmentLib.h>
> +#include <NeoverseN1Soc.h>
> +
> +typedef enum {
> + PciCfgWidthUint8 = 0,
> + PciCfgWidthUint16,
> + PciCfgWidthUint32,
> + PciCfgWidthMax
> +} PCI_CFG_WIDTH;
> +
> +/**
> + Assert the validity of a PCI Segment address.
> + A valid PCI Segment address should not contain 1's in bits 28..31 and 48..63
> +
> + @param A The address to validate.
> + @param M Additional bits to assert to be zero.
> +**/
> +#define ASSERT_INVALID_PCI_SEGMENT_ADDRESS(A,M) \
> + ASSERT (((A) & (0xffff0000f0000000ULL | (M))) == 0)
> +
> +#define BUS_OFFSET 20
> +#define DEV_OFFSET 15
> +#define FUNC_OFFSET 12
> +#define REG_OFFSET 4096
> +
> +#define EFI_PCIE_ADDRESS(bus, dev, func, reg) \
> + (UINT64) ( \
> + (((UINTN) bus) << BUS_OFFSET) | \
> + (((UINTN) dev) << DEV_OFFSET) | \
> + (((UINTN) func) << FUNC_OFFSET) | \
> + (((UINTN) (reg)) < REG_OFFSET ? \
> + ((UINTN) (reg)) : (UINT64) (LShiftU64 ((UINT64) (reg), 32))))
> +
> +#define GET_PCIE_BASE_ADDRESS(Address) (Address & 0xF8000000)
> +
> +/* Root port Entry, BDF Entries Count */
> +#define BDF_TABLE_ENTRY_SIZE 4
> +#define BDF_TABLE_HEADER_COUNT 2
> +#define BDF_TABLE_HEADER_SIZE 8
> +
> +/* BDF table offsets for PCIe */
> +#define PCIE_BDF_TABLE_OFFSET 0
> +#define CCIX_BDF_TABLE_OFFSET (16 * 1024)
> +
> +#define GET_BUS_NUM(Address) (((Address) >> 20) & 0x7F)
[SAMI] Can BUS_OFFSET be used here instead of 20. Similar comment for
the macros, below.
> +#define GET_DEV_NUM(Address) (((Address) >> 15) & 0x1F)
> +#define GET_FUNC_NUM(Address) (((Address) >> 12) & 0x07)
> +#define GET_REG_NUM(Address) ((Address) & 0xFFF)
> +#define GET_SEG_NUM(Address) (((Address) >> 32) & 0xFFFF)
[SAMI] Would it be possible to define a macro for the segment offset?
> +
> +CONST STATIC UINTN mDummyConfigData = 0xFFFFFFFF;
> +
> +/**
> + Check if the requested PCI address is a valid BDF address.
> +
> + SCP performs the initial bus scan and prepares a table of valid BDF addresses
> + and shares them through non-trusted SRAM. This function validates if the PCI
> + address from any PCI request falls within the table of valid entries. If not,
> + this function will return 0xFFFFFFFF. This is a workaround to avoid bus fault
> + that happens when accessing unavailable PCI device due to RTL bug.
> +
> + @param Address The address that encodes the PCI Bus, Device, Function and
> + Register.
> +
> + @return The base address of PCI Express.
[SAMI] or 0xFFFFFFFF if the address is not valid?
> +
> +**/
> +STATIC
> +UINTN
> +IsBdfValid (
> + IN UINTN Address
> + )
> +{
> + UINT16 Segment;
> + UINTN BdfCount;
> + UINTN BdfValue;
> + UINTN Count;
> + UINTN TableBase;
> + UINTN PciAddress;
> +
> + Segment = GET_SEG_NUM (Address);
> + ASSERT ((Segment == 0) || (Segment == 1));
[SAMI] For release builds, what happens if Segment is not 0 or 1? Also,
the if condition below will set the TableBase as if it were Segment 1.
> +
> + // Keep the Bus, Device, Function bits. Clear the rest.
> + PciAddress = Address & 0xFFFF000;
> +
> + if (Segment == 0) {
> + TableBase = NEOVERSEN1SOC_NON_SECURE_SRAM_BASE + PCIE_BDF_TABLE_OFFSET;
> + } else {
> + TableBase = NEOVERSEN1SOC_NON_SECURE_SRAM_BASE + CCIX_BDF_TABLE_OFFSET;
[SAMI] Should this else be an else if (Segment == 1), and a following
else should add ASSERT (0). This would also mean that the earlier assert
can be removed.
> + }
> +
> + BdfCount = MmioRead32 (TableBase + BDF_TABLE_ENTRY_SIZE);
> +
> + /* Start from the second entry */
> + for (Count = BDF_TABLE_HEADER_COUNT;
> + Count < (BdfCount + BDF_TABLE_HEADER_COUNT);
> + Count++) {
> + BdfValue = MmioRead32 (TableBase + (Count * BDF_TABLE_ENTRY_SIZE));
> + if (BdfValue == PciAddress)
> + break;
[SAMI] Can you run uncrustif on this code, please? The edk2 coding
standard requires if conditions to use curly braces for enclosing
statements.
> + }
> +
> + if (Count == (BdfCount + BDF_TABLE_HEADER_COUNT)) {
> + return mDummyConfigData;
> + } else {
> + return PciAddress;
> + }
> +}
> +
> +/**
> + Get the physical address of a configuration space register.
> +
> + Implement a workaround to avoid generation of slave errors from the bus. That
> + is, retrieve the PCI Express Base Address via a PCD entry, add the incomming
> + address with that base address and check whether this converted address
> + points to a accessible BDF. If it is not accessible, return the address
> + of a dummy location so that a read from it does not cause a slave error.
> +
> + In addition to this, implement a workaround for accessing the root port's
> + configuration space. The root port configuration space is not contiguous
> + with the rest of the downstream hierarchy configuration space. So determine
> + whether the specified address is for the root port and use a different base
> + address for it.
> +
> + @param Address The address that encodes the PCI Bus, Device, Function and
> + Register.
> +
> + @return Physical address of the configuration register that corresponds to the
> + PCI configuration register specified by input parameter 'Address'.
> +
> +**/
> +STATIC
> +VOID*
> +GetPciExpressAddress (
> + IN UINTN Address
> + )
> +{
> + BOOLEAN CheckRootPort;
> + UINT16 Segment;
> + UINT8 Bus;
> + UINT8 Device;
> + UINT8 Function;
> + UINT16 Register;
> + UINTN ConfigAddress;
> +
> + Segment = GET_SEG_NUM (Address);
> + ASSERT ((Segment == 0) || (Segment == 1));
[SAMI] Same question about this assert as above.
> +
> + Bus = GET_BUS_NUM (Address);
> + Device = GET_DEV_NUM (Address);
> + Function = GET_FUNC_NUM (Address);
> + Register = GET_REG_NUM (Address);
> +
> +
> + CheckRootPort = (BOOLEAN) (Bus == 0) && (Device == 0) && (Function == 0);
[SAMI] Is the type cast to BOOLEAN required?
> +
> + if (CheckRootPort == FALSE) {
> + if (IsBdfValid (Address) == mDummyConfigData) {
> + return (VOID*) &mDummyConfigData;
> + }
> + }
> +
> + if (Segment == 0) {
> + if (CheckRootPort == TRUE) {
> + ConfigAddress = (UINTN) PcdGet32 (PcdPcieRootPortConfigBaseAddress);
> + } else {
> + ConfigAddress = (UINTN) PcdGet64 (PcdPcieExpressBaseAddress);
> + }
> + } else {
> + if (CheckRootPort == TRUE) {
> + ConfigAddress = (UINTN) PcdGet32 (PcdCcixRootPortConfigBaseAddress);
> + } else {
> + ConfigAddress = (UINTN) PcdGet32 (PcdCcixExpressBaseAddress);
> + }
> + }
> +
> + ConfigAddress += EFI_PCIE_ADDRESS (Bus, Device, Function, Register);
> + return (VOID *)ConfigAddress;
> +}
> +
> +/**
> + Internal worker function to read a PCI configuration register.
> +
> + @param Address The address that encodes the PCI Bus, Device, Function
> + and Register.
> + @param Width The width of data to read
> +
> + @return The value read from the PCI configuration register.
> +**/
> +STATIC
> +UINT32
> +PciSegmentLibReadWorker (
> + IN UINT64 Address,
> + IN PCI_CFG_WIDTH Width
> + )
> +{
> + UINTN PciAddress;
> +
> + PciAddress = (UINTN) GetPciExpressAddress ((UINTN) Address);
> +
> + switch (Width) {
> + case PciCfgWidthUint8:
> + return MmioRead8 (PciAddress);
> + case PciCfgWidthUint16:
> + return MmioRead16 (PciAddress);
> + case PciCfgWidthUint32:
> + return MmioRead32 (PciAddress);
> + default:
> + ASSERT (FALSE);
> + }
> +
> + return 0;
> +}
> +
> +/**
> + Internal worker function to write to a PCI configuration register.
> +
> + @param Address The address that encodes the PCI Bus, Device, Function
> + and Register.
> + @param Width The width of data to write
> + @param Data The value to write.
> +
> + @return The value written to the PCI configuration register.
> +**/
> +STATIC
> +UINT32
> +PciSegmentLibWriteWorker (
> + IN UINT64 Address,
> + IN PCI_CFG_WIDTH Width,
> + IN UINT32 Data
> + )
> +{
> + UINT8 Offset;
> + UINT32 WData;
> + UINT64 AlignedAddress;
> + BOOLEAN CheckRootPort;
> +
> + CheckRootPort = (GET_BUS_NUM (Address) == 0) &&
> + (GET_DEV_NUM (Address) == 0) &&
> + (GET_FUNC_NUM (Address) == 0);
> +
> + // 8-bit and 16-bit writes to root port config space is not supported due to
> + // a hardware limitation. As a workaround, perform a read-update-write
> + // sequence on the whole 32-bit word of the root port config register such
> + // that only the specified 8-bits of that word are updated.
> +
> + switch (Width) {
> + case PciCfgWidthUint8:
> + if (CheckRootPort == TRUE) {
> + Offset = Address & 0x3;
> + AlignedAddress = Address & ~(0x3);
> + WData = MmioRead32 ((UINTN) GetPciExpressAddress (AlignedAddress));
> + WData &= ~(0xFF << (8 * Offset));
> + WData |= (Data << (8 * Offset));
> + MmioWrite32 ((UINTN) GetPciExpressAddress (AlignedAddress), WData);
> + return Data;
> + } else {
> + MmioWrite8 ((UINTN) GetPciExpressAddress (Address), Data);
> + }
> + break;
> + case PciCfgWidthUint16:
> + if (CheckRootPort == TRUE) {
> + Offset = Address & 0x3;
> + AlignedAddress = Address & ~(0x3);
> + WData = MmioRead32 ((UINTN) GetPciExpressAddress (AlignedAddress));
> + WData &= ~(0xFFFF << (8 * Offset));
> + WData |= (Data << (8 * Offset));
> + MmioWrite32 ((UINTN) GetPciExpressAddress (AlignedAddress), WData);
> + return Data;
> + } else {
> + MmioWrite16 ((UINTN) GetPciExpressAddress (Address), Data);
> + }
> + break;
> + case PciCfgWidthUint32:
> + MmioWrite32 ((UINTN) GetPciExpressAddress (Address), Data);
> + break;
> + default:
> + ASSERT (FALSE);
[SAMI] Should 0 be returned in this case to indicate an error?
> + }
> +
> + return Data;
> +}
> +
> +/**
> + Reads an 8-bit PCI configuration register.
> +
> + Reads and returns the 8-bit PCI configuration register specified by Address.
> + This function must guarantee that all PCI read and write operations are
> + serialized.
> +
> + If any reserved bits in Address are set, then ASSERT().
> +
> + @param Address The address that encodes the PCI Segment, Bus,
> + Device, Function and Register.
> +
> + @return The 8-bit PCI configuration register specified by the Address.
> +**/
> +UINT8
> +EFIAPI
> +PciSegmentRead8 (
> + IN UINT64 Address
> + )
> +{
> + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 0);
> +
> + return (UINT8) PciSegmentLibReadWorker (Address, PciCfgWidthUint8);
> +}
> +
> +/**
> + Writes an 8-bit PCI configuration register.
> +
> + Writes the 8-bit Value in the PCI configuration register specified by the
> + Address. This function must guarantee that all PCI read and write operations
> + are serialized.
> +
> + If any reserved bits in Address are set, then ASSERT().
> +
> + @param Address The address that encodes the PCI Segment, Bus,
> + Device, Function, and Register.
> + @param Value The value to write.
> +
> + @return The value written to the PCI configuration register.
> +**/
> +UINT8
> +EFIAPI
> +PciSegmentWrite8 (
> + IN UINT64 Address,
> + IN UINT8 Value
> + )
> +{
> + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 0);
> +
> + return (UINT8) PciSegmentLibWriteWorker (Address, PciCfgWidthUint8, Value);
> +}
> +
> +/**
> + Performs a bitwise OR of an 8-bit PCI configuration register with
> + an 8-bit value.
> +
> + Reads the 8-bit PCI configuration register specified by Address,
> + performs a bitwise OR between the read result and the value specified by
> + OrData, and writes the result to the 8-bit PCI configuration register
> + specified by Address.
> +
> + The value written to the PCI configuration register is returned.
> + This function must guarantee that all PCI read and write operations
> + are serialized.
> +
> + If any reserved bits in Address are set, then ASSERT().
> +
> + @param Address The address that encodes the PCI Segment, Bus, Device,
> + Function, and Register.
> + @param OrData The value to OR with the PCI configuration register.
> +
> + @return The value written to the PCI configuration register.
> +**/
> +UINT8
> +EFIAPI
> +PciSegmentOr8 (
> + IN UINT64 Address,
> + IN UINT8 OrData
> + )
> +{
> + return PciSegmentWrite8 (Address,
> + (UINT8) (PciSegmentRead8 (Address) | OrData));
> +}
> +
> +/**
> + Performs a bitwise AND of an 8-bit PCI configuration register with
> + an 8-bit value.
> +
> + Reads the 8-bit PCI configuration register specified by Address,
> + performs a bitwise AND between the read result and the value specified by
> + AndData, and writes the result to the 8-bit PCI configuration register
> + specified by Address.
> +
> + The value written to the PCI configuration register is returned.
> + This function must guarantee that all PCI read and write operations
> + are serialized. If any reserved bits in Address are set, then ASSERT().
> +
> + @param Address The address that encodes the PCI Segment, Bus, Device,
> + Function, and Register.
> + @param AndData The value to AND with the PCI configuration register.
> +
> + @return The value written to the PCI configuration register.
> +**/
> +UINT8
> +EFIAPI
> +PciSegmentAnd8 (
> + IN UINT64 Address,
> + IN UINT8 AndData
> + )
> +{
> + return PciSegmentWrite8 (Address,
> + (UINT8) (PciSegmentRead8 (Address) & AndData));
> +}
> +
> +/**
> + Performs a bitwise AND of an 8-bit PCI configuration register with
> + an 8-bit value, followed by a bitwise OR with another 8-bit value.
> +
> + Reads the 8-bit PCI configuration register specified by Address,
> + performs a bitwise AND between the read result and the value specified
> + by AndData, performs a bitwise OR between the result of the AND operation
> + and the value specified by OrData, and writes the result to the 8-bit
> + PCI configuration register specified by Address.
> +
> + The value written to the PCI configuration register is returned.
> + This function must guarantee that all PCI read and write operations
> + are serialized.
> +
> + If any reserved bits in Address are set, then ASSERT().
> +
> + @param Address The address that encodes the PCI Segment, Bus, Device,
> + Function, and Register.
> + @param AndData The value to AND with the PCI configuration register.
> + @param OrData The value to OR with the PCI configuration register.
> +
> + @return The value written to the PCI configuration register.
> +
> +**/
> +UINT8
> +EFIAPI
> +PciSegmentAndThenOr8 (
> + IN UINT64 Address,
> + IN UINT8 AndData,
> + IN UINT8 OrData
> + )
> +{
> + return PciSegmentWrite8 (Address,
> + (UINT8) ((PciSegmentRead8 (Address) & AndData)
> + | OrData));
> +}
> +
> +/**
> + Reads a bit field of a PCI configuration register.
> +
> + Reads the bit field in an 8-bit PCI configuration register. The bit field is
> + specified by the StartBit and the EndBit. The value of the bit field is
> + returned.
> +
> + If any reserved bits in Address are set, then ASSERT().
> + If StartBit is greater than 7, then ASSERT().
> + If EndBit is greater than 7, then ASSERT().
> + If EndBit is less than StartBit, then ASSERT().
> +
> + @param Address The PCI configuration register to read.
> + @param StartBit The ordinal of the least significant bit in the bit field.
> + Range 0..7.
> + @param EndBit The ordinal of the most significant bit in the bit field.
> + Range 0..7.
> +
> + @return The value of the bit field read from the PCI configuration register.
> +
> +**/
> +UINT8
> +EFIAPI
> +PciSegmentBitFieldRead8 (
> + IN UINT64 Address,
> + IN UINTN StartBit,
> + IN UINTN EndBit
> + )
> +{
> + return BitFieldRead8 (PciSegmentRead8 (Address), StartBit, EndBit);
> +}
> +
> +/**
> + Writes a bit field to a PCI configuration register.
> +
> + Writes Value to the bit field of the PCI configuration register. The bit
> + field is specified by the StartBit and the EndBit. All other bits in the
> + destination PCI configuration register are preserved. The new value of the
> + 8-bit register is returned.
> +
> + If any reserved bits in Address are set, then ASSERT().
> + If StartBit is greater than 7, then ASSERT().
> + If EndBit is greater than 7, then ASSERT().
> + If EndBit is less than StartBit, then ASSERT().
> + If Value is larger than the bitmask value range specified by StartBit
> + and EndBit, then ASSERT().
> +
> + @param Address The PCI configuration register to write.
> + @param StartBit The ordinal of the least significant bit in the bit field.
> + Range 0..7.
> + @param EndBit The ordinal of the most significant bit in the bit field.
> + Range 0..7.
> + @param Value The new value of the bit field.
> +
> + @return The value written back to the PCI configuration register.
> +
> +**/
> +UINT8
> +EFIAPI
> +PciSegmentBitFieldWrite8 (
> + IN UINT64 Address,
> + IN UINTN StartBit,
> + IN UINTN EndBit,
> + IN UINT8 Value
> + )
> +{
> + return PciSegmentWrite8 (Address,
> + BitFieldWrite8 (PciSegmentRead8 (Address),
> + StartBit,
> + EndBit,
> + Value));
> +}
> +
> +/**
> + Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and
> + writes the result back to the bit field in the 8-bit port.
> +
> + Reads the 8-bit PCI configuration register specified by Address, performs a
> + bitwise OR between the read result and the value specified by
> + OrData, and writes the result to the 8-bit PCI configuration register
> + specified by Address. The value written to the PCI configuration register is
> + returned. This function must guarantee that all PCI read and write operations
> + are serialized. Extra left bits in OrData are stripped.
> +
> + If any reserved bits in Address are set, then ASSERT().
> + If StartBit is greater than 7, then ASSERT().
> + If EndBit is greater than 7, then ASSERT().
> + If EndBit is less than StartBit, then ASSERT().
> + If OrData is larger than the bitmask value range specified by StartBit and
> + EndBit, then ASSERT().
> +
> + @param Address The PCI configuration register to write.
> + @param StartBit The ordinal of the least significant bit in the bit field.
> + Range 0..7.
> + @param EndBit The ordinal of the most significant bit in the bit field.
> + Range 0..7.
> + @param OrData The value to OR with the PCI configuration register.
> +
> + @return The value written back to the PCI configuration register.
> +
> +**/
> +UINT8
> +EFIAPI
> +PciSegmentBitFieldOr8 (
> + IN UINT64 Address,
> + IN UINTN StartBit,
> + IN UINTN EndBit,
> + IN UINT8 OrData
> + )
> +{
> + return PciSegmentWrite8 (Address,
> + BitFieldOr8 (PciSegmentRead8 (Address),
> + StartBit,
> + EndBit,
> + OrData));
> +}
> +
> +/**
> + Reads a bit field in an 8-bit PCI configuration register, performs a bitwise
> + AND, and writes the result back to the bit field in the 8-bit register.
> +
> + Reads the 8-bit PCI configuration register specified by Address, performs a
> + bitwise AND between the read result and the value specified by AndData, and
> + writes the result to the 8-bit PCI configuration register specified by
> + Address. The value written to the PCI configuration register is returned.
> + This function must guarantee that all PCI read and write operations are
> + serialized. Extra left bits in AndData are stripped.
> +
> + If any reserved bits in Address are set, then ASSERT().
> + If StartBit is greater than 7, then ASSERT().
> + If EndBit is greater than 7, then ASSERT().
> + If EndBit is less than StartBit, then ASSERT().
> + If AndData is larger than the bitmask value range specified by StartBit and
> + EndBit, then ASSERT().
> +
> + @param Address The PCI configuration register to write.
> + @param StartBit The ordinal of the least significant bit in the bit field.
> + Range 0..7.
> + @param EndBit The ordinal of the most significant bit in the bit field.
> + Range 0..7.
> + @param AndData The value to AND with the PCI configuration register.
> +
> + @return The value written back to the PCI configuration register.
> +
> +**/
> +UINT8
> +EFIAPI
> +PciSegmentBitFieldAnd8 (
> + IN UINT64 Address,
> + IN UINTN StartBit,
> + IN UINTN EndBit,
> + IN UINT8 AndData
> + )
> +{
> + return PciSegmentWrite8 (Address,
> + BitFieldAnd8 (PciSegmentRead8 (Address),
> + StartBit,
> + EndBit,
> + AndData));
> +}
> +
> +/**
> + Reads a bit field in an 8-bit port, performs a bitwise AND followed by a
> + bitwise OR, and writes the result back to the bit field in the
> + 8-bit port.
> +
> + Reads the 8-bit PCI configuration register specified by Address, performs a
> + bitwise AND followed by a bitwise OR between the read result and
> + the value specified by AndData, and writes the result to the 8-bit PCI
> + configuration register specified by Address. The value written to the PCI
> + configuration register is returned. This function must guarantee that all PCI
> + read and write operations are serialized. Extra left bits in both AndData and
> + OrData are stripped.
> +
> + If any reserved bits in Address are set, then ASSERT().
> + If StartBit is greater than 7, then ASSERT().
> + If EndBit is greater than 7, then ASSERT().
> + If EndBit is less than StartBit, then ASSERT().
> + If AndData is larger than the bitmask value range specified by StartBit
> + and EndBit, then ASSERT().
> + If OrData is larger than the bitmask value range specified by StartBit
> + and EndBit, then ASSERT().
> +
> + @param Address The PCI configuration register to write.
> + @param StartBit The ordinal of the least significant bit in the bit field.
> + Range 0..7.
> + @param EndBit The ordinal of the most significant bit in the bit field.
> + Range 0..7.
> + @param AndData The value to AND with the PCI configuration register.
> + @param OrData The value to OR with the result of the AND operation.
> +
> + @return The value written back to the PCI configuration register.
> +
> +**/
> +UINT8
> +EFIAPI
> +PciSegmentBitFieldAndThenOr8 (
> + IN UINT64 Address,
> + IN UINTN StartBit,
> + IN UINTN EndBit,
> + IN UINT8 AndData,
> + IN UINT8 OrData
> + )
> +{
> + return PciSegmentWrite8 (Address,
> + BitFieldAndThenOr8 (PciSegmentRead8 (Address),
> + StartBit,
> + EndBit,
> + AndData,
> + OrData));
> +}
> +
> +/**
> + Reads a 16-bit PCI configuration register.
> +
> + Reads and returns the 16-bit PCI configuration register specified by Address.
> + This function must guarantee that all PCI read and write operations
> + are serialized.
> +
> + If any reserved bits in Address are set, then ASSERT().
> + If Address is not aligned on a 16-bit boundary, then ASSERT().
> +
> + @param Address The address that encodes the PCI Segment, Bus, Device,
> + Function, and Register.
> +
> + @return The 16-bit PCI configuration register specified by Address.
> +
> +**/
> +UINT16
> +EFIAPI
> +PciSegmentRead16 (
> + IN UINT64 Address
> + )
> +{
> + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 1);
> +
> + return (UINT16) PciSegmentLibReadWorker (Address, PciCfgWidthUint16);
> +}
> +
> +/**
> + Writes a 16-bit PCI configuration register.
> +
> + Writes the 16-bit PCI configuration register specified by Address with the
> + value specified by Value. Value is returned.
> + This function must guarantee that all PCI read and write operations
> + are serialized.
> +
> + If any reserved bits in Address are set, then ASSERT().
> + If Address is not aligned on a 16-bit boundary, then ASSERT().
> +
> + @param Address The address that encodes the PCI Segment, Bus, Device,
> + Function, and Register.
> + @param Value The value to write.
> +
> + @return The Value written is returned.
> +
> +**/
> +UINT16
> +EFIAPI
> +PciSegmentWrite16 (
> + IN UINT64 Address,
> + IN UINT16 Value
> + )
> +{
> + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 1);
> +
> + return (UINT16) PciSegmentLibWriteWorker (Address, PciCfgWidthUint16, Value);
> +}
> +
> +/**
> + Performs a bitwise OR of a 16-bit PCI configuration register with
> + a 16-bit value.
> +
> + Reads the 16-bit PCI configuration register specified by Address, performs a
> + bitwise OR between the read result and the value specified by
> + OrData, and writes the result to the 16-bit PCI configuration register
> + specified by Address. The value written to the PCI configuration register is
> + returned. This function must guarantee that all PCI read and write operations
> + are serialized.
> +
> + If any reserved bits in Address are set, then ASSERT().
> + If Address is not aligned on a 16-bit boundary, then ASSERT().
> +
> + @param Address The address that encodes the PCI Segment, Bus, Device,
> + Function and Register.
> + @param OrData The value to OR with the PCI configuration register.
> +
> + @return The value written back to the PCI configuration register.
> +
> +**/
> +UINT16
> +EFIAPI
> +PciSegmentOr16 (
> + IN UINT64 Address,
> + IN UINT16 OrData
> + )
> +{
> + return PciSegmentWrite16 (Address,
> + (UINT16) (PciSegmentRead16 (Address) | OrData));
> +}
> +
> +/**
> + Performs a bitwise AND of a 16-bit PCI configuration register with
> + a 16-bit value.
> +
> + Reads the 16-bit PCI configuration register specified by Address,
> + performs a bitwise AND between the read result and the value specified
> + by AndData, and writes the result to the 16-bit PCI configuration register
> + specified by the Address.
> +
> + The value written to the PCI configuration register is returned.
> + This function must guarantee that all PCI read and write operations
> + are serialized.
> +
> + If any reserved bits in Address are set, then ASSERT().
> + If Address is not aligned on a 16-bit boundary, then ASSERT().
> +
> + @param Address The address that encodes the PCI Segment, Bus, Device,
> + Function, and Register.
> + @param AndData The value to AND with the PCI configuration register.
> +
> + @return The value written to the PCI configuration register.
> +
> +**/
> +UINT16
> +EFIAPI
> +PciSegmentAnd16 (
> + IN UINT64 Address,
> + IN UINT16 AndData
> + )
> +{
> + return PciSegmentWrite16 (Address,
> + (UINT16) (PciSegmentRead16 (Address) & AndData));
> +}
> +
> +/**
> + Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
> + value, followed a bitwise OR with another 16-bit value.
> +
> + Reads the 16-bit PCI configuration register specified by Address,
> + performs a bitwise AND between the read result and the value specified by
> + AndData, performs a bitwise OR between the result of the AND operation and
> + the value specified by OrData, and writes the result to the 16-bit PCI
> + configuration register specified by the Address.
> +
> + The value written to the PCI configuration register is returned.
> + This function must guarantee that all PCI read and write operations
> + are serialized.
> +
> + If any reserved bits in Address are set, then ASSERT().
> + If Address is not aligned on a 16-bit boundary, then ASSERT().
> +
> + @param Address The address that encodes the PCI Segment, Bus, Device,
> + Function, and Register.
> + @param AndData The value to AND with the PCI configuration register.
> + @param OrData The value to OR with the PCI configuration register.
> +
> + @return The value written to the PCI configuration register.
> +
> +**/
> +UINT16
> +EFIAPI
> +PciSegmentAndThenOr16 (
> + IN UINT64 Address,
> + IN UINT16 AndData,
> + IN UINT16 OrData
> + )
> +{
> + return PciSegmentWrite16 (Address,
> + (UINT16) ((PciSegmentRead16 (Address) & AndData)
> + | OrData));
> +}
> +
> +/**
> + Reads a bit field of a PCI configuration register.
> +
> + Reads the bit field in a 16-bit PCI configuration register. The bit field is
> + specified by the StartBit and the EndBit. The value of the bit field is
> + returned.
> +
> + If any reserved bits in Address are set, then ASSERT().
> + If Address is not aligned on a 16-bit boundary, then ASSERT().
> + If StartBit is greater than 15, then ASSERT().
> + If EndBit is greater than 15, then ASSERT().
> + If EndBit is less than StartBit, then ASSERT().
> +
> + @param Address The PCI configuration register to read.
> + @param StartBit The ordinal of the least significant bit in the bit field.
> + Range 0..15.
> + @param EndBit The ordinal of the most significant bit in the bit field.
> + Range 0..15.
> +
> + @return The value of the bit field read from the PCI configuration register.
> +
> +**/
> +UINT16
> +EFIAPI
> +PciSegmentBitFieldRead16 (
> + IN UINT64 Address,
> + IN UINTN StartBit,
> + IN UINTN EndBit
> + )
> +{
> + return BitFieldRead16 (PciSegmentRead16 (Address), StartBit, EndBit);
> +}
> +
> +/**
> + Writes a bit field to a PCI configuration register.
> +
> + Writes Value to the bit field of the PCI configuration register. The bit
> + field is specified by the StartBit and the EndBit. All other bits in the
> + destination PCI configuration register are preserved. The new value of the
> + 16-bit register is returned.
> +
> + If any reserved bits in Address are set, then ASSERT().
> + If Address is not aligned on a 16-bit boundary, then ASSERT().
> + If StartBit is greater than 15, then ASSERT().
> + If EndBit is greater than 15, then ASSERT().
> + If EndBit is less than StartBit, then ASSERT().
> + If Value is larger than the bitmask value range specified by StartBit and
> + EndBit, then ASSERT().
> +
> + @param Address The PCI configuration register to write.
> + @param StartBit The ordinal of the least significant bit in the bit field.
> + Range 0..15.
> + @param EndBit The ordinal of the most significant bit in the bit field.
> + Range 0..15.
> + @param Value The new value of the bit field.
> +
> + @return The value written back to the PCI configuration register.
> +
> +**/
> +UINT16
> +EFIAPI
> +PciSegmentBitFieldWrite16 (
> + IN UINT64 Address,
> + IN UINTN StartBit,
> + IN UINTN EndBit,
> + IN UINT16 Value
> + )
> +{
> + return PciSegmentWrite16 (Address,
> + BitFieldWrite16 (PciSegmentRead16 (Address),
> + StartBit,
> + EndBit,
> + Value));
> +}
> +
> +/**
> + Reads the 16-bit PCI configuration register specified by Address,
> + performs a bitwise OR between the read result and the value specified
> + by OrData, and writes the result to the 16-bit PCI configuration register
> + specified by the Address.
> +
> + If any reserved bits in Address are set, then ASSERT().
> + If Address is not aligned on a 16-bit boundary, then ASSERT().
> + If StartBit is greater than 15, then ASSERT().
> + If EndBit is greater than 15, then ASSERT().
> + If EndBit is less than StartBit, then ASSERT().
> + If OrData is larger than the bitmask value range specified by StartBit and
> + EndBit, then ASSERT().
> +
> + @param Address The PCI configuration register to write.
> + @param StartBit The ordinal of the least significant bit in the bit field.
> + Range 0..15.
> + @param EndBit The ordinal of the most significant bit in the bit field.
> + Range 0..15.
> + @param OrData The value to OR with the PCI configuration register.
> +
> + @return The value written back to the PCI configuration register.
> +
> +**/
> +UINT16
> +EFIAPI
> +PciSegmentBitFieldOr16 (
> + IN UINT64 Address,
> + IN UINTN StartBit,
> + IN UINTN EndBit,
> + IN UINT16 OrData
> + )
> +{
> + return PciSegmentWrite16 (Address,
> + BitFieldOr16 (PciSegmentRead16 (Address),
> + StartBit,
> + EndBit,
> + OrData));
> +}
> +
> +/**
> + Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR,
> + and writes the result back to the bit field in the 16-bit port.
> +
> + Reads the 16-bit PCI configuration register specified by Address,
> + performs a bitwise OR between the read result and the value specified by
> + OrData, and writes the result to the 16-bit PCI configuration register
> + specified by the Address.
> +
> + The value written to the PCI configuration register is returned.
> + This function must guarantee that all PCI read and write operations are
> + serialized. Extra left bits in OrData are stripped.
> +
> + If any reserved bits in Address are set, then ASSERT().
> + If Address is not aligned on a 16-bit boundary, then ASSERT().
> + If StartBit is greater than 7, then ASSERT().
> + If EndBit is greater than 7, then ASSERT().
> + If EndBit is less than StartBit, then ASSERT().
> + If AndData is larger than the bitmask value range specified by StartBit and
> + EndBit, then ASSERT().
> +
> + @param Address The address that encodes the PCI Segment, Bus, Device,
> + Function, and Register.
> + @param StartBit The ordinal of the least significant bit in the bit field.
> + The ordinal of the least significant bit in a byte is
> + bit 0.
> + @param EndBit The ordinal of the most significant bit in the bit field.
> + The ordinal of the most significant bit in a byte is bit 7.
> + @param AndData The value to AND with the read value from the PCI
> + configuration register.
> +
> + @return The value written to the PCI configuration register.
> +
> +**/
> +UINT16
> +EFIAPI
> +PciSegmentBitFieldAnd16 (
> + IN UINT64 Address,
> + IN UINTN StartBit,
> + IN UINTN EndBit,
> + IN UINT16 AndData
> + )
> +{
> + return PciSegmentWrite16 (Address,
> + BitFieldAnd16 (PciSegmentRead16 (Address),
> + StartBit,
> + EndBit,
> + AndData));
> +}
> +
> +/**
> + Reads a bit field in a 16-bit port, performs a bitwise AND followed by a
> + bitwise OR, and writes the result back to the bit field in the
> + 16-bit port.
> +
> + Reads the 16-bit PCI configuration register specified by Address, performs a
> + bitwise AND followed by a bitwise OR between the read result and
> + the value specified by AndData, and writes the result to the 16-bit PCI
> + configuration register specified by Address. The value written to the PCI
> + configuration register is returned. This function must guarantee that all PCI
> + read and write operations are serialized. Extra left bits in both AndData and
> + OrData are stripped.
> +
> + If any reserved bits in Address are set, then ASSERT().
> + If StartBit is greater than 15, then ASSERT().
> + If EndBit is greater than 15, then ASSERT().
> + If EndBit is less than StartBit, then ASSERT().
> + If AndData is larger than the bitmask value range specified by StartBit and
> + EndBit, then ASSERT().
> + If OrData is larger than the bitmask value range specified by StartBit and
> + EndBit, then ASSERT().
> +
> + @param Address The PCI configuration register to write.
> + @param StartBit The ordinal of the least significant bit in the bit field.
> + Range 0..15.
> + @param EndBit The ordinal of the most significant bit in the bit field.
> + Range 0..15.
> + @param AndData The value to AND with the PCI configuration register.
> + @param OrData The value to OR with the result of the AND operation.
> +
> + @return The value written back to the PCI configuration register.
> +
> +**/
> +UINT16
> +EFIAPI
> +PciSegmentBitFieldAndThenOr16 (
> + IN UINT64 Address,
> + IN UINTN StartBit,
> + IN UINTN EndBit,
> + IN UINT16 AndData,
> + IN UINT16 OrData
> + )
> +{
> + return PciSegmentWrite16 (Address,
> + BitFieldAndThenOr16 (PciSegmentRead16 (Address),
> + StartBit,
> + EndBit,
> + AndData,
> + OrData));
> +}
> +
> +/**
> + Reads a 32-bit PCI configuration register.
> +
> + Reads and returns the 32-bit PCI configuration register specified by Address.
> + This function must guarantee that all PCI read and write operations
> + are serialized.
> +
> + If any reserved bits in Address are set, then ASSERT().
> + If Address is not aligned on a 32-bit boundary, then ASSERT().
> +
> + @param Address The address that encodes the PCI Segment, Bus,
> + Device, Function and Register.
> +
> + @return The 32-bit PCI configuration register specified by Address.
> +
> +**/
> +UINT32
> +EFIAPI
> +PciSegmentRead32 (
> + IN UINT64 Address
> + )
> +{
> + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 3);
> +
> + return PciSegmentLibReadWorker (Address, PciCfgWidthUint32);
> +}
> +
> +/**
> + Writes a 32-bit PCI configuration register.
> +
> + Writes the 32-bit PCI configuration register specified by Address with the
> + value specified by Value. Value is returned. This function must guarantee
> + that all PCI read and write operations are serialized.
> +
> + If any reserved bits in Address are set, then ASSERT().
> + If Address is not aligned on a 32-bit boundary, then ASSERT().
> +
> + @param Address The address that encodes the PCI Segment, Bus, Device,
> + Function, and Register.
> + @param Value The value to write.
> +
> + @return The parameter of Value.
> +
> +**/
> +UINT32
> +EFIAPI
> +PciSegmentWrite32 (
> + IN UINT64 Address,
> + IN UINT32 Value
> + )
> +{
> + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 3);
> +
> + return PciSegmentLibWriteWorker (Address, PciCfgWidthUint32, Value);
> +}
> +
> +/**
> + Performs a bitwise OR of a 32-bit PCI configuration register with a
> + 32-bit value.
> +
> + Reads the 32-bit PCI configuration register specified by Address,
> + performs a bitwise OR between the read result and the value specified
> + by OrData, and writes the result to the 32-bit PCI configuration register
> + specified by Address.
> +
> + The value written to the PCI configuration register is returned.
> + This function must guarantee that all PCI read and write operations
> + are serialized.
> +
> + If any reserved bits in Address are set, then ASSERT().
> + If Address is not aligned on a 32-bit boundary, then ASSERT().
> +
> + @param Address The address that encodes the PCI Segment, Bus, Device,
> + Function, and Register.
> + @param OrData The value to OR with the PCI configuration register.
> +
> + @return The value written to the PCI configuration register.
> +
> +**/
> +UINT32
> +EFIAPI
> +PciSegmentOr32 (
> + IN UINT64 Address,
> + IN UINT32 OrData
> + )
> +{
> + return PciSegmentWrite32 (Address, PciSegmentRead32 (Address) | OrData);
> +}
> +
> +/**
> + Performs a bitwise AND of a 32-bit PCI configuration register with
> + a 32-bit value.
> +
> + Reads the 32-bit PCI configuration register specified by Address,
> + performs a bitwise AND between the read result and the value specified
> + by AndData, and writes the result to the 32-bit PCI configuration register
> + specified by Address.
> + The value written to the PCI configuration register is returned.
> + This function must guarantee that all PCI read and write operations
> + are serialized.
> +
> + If any reserved bits in Address are set, then ASSERT().
> + If Address is not aligned on a 32-bit boundary, then ASSERT().
> +
> + @param Address The address that encodes the PCI Segment, Bus,
> + Device, Function and Register.
> + @param AndData The value to AND with the PCI configuration register.
> +
> + @return The value written to the PCI configuration register.
> +
> +**/
> +UINT32
> +EFIAPI
> +PciSegmentAnd32 (
> + IN UINT64 Address,
> + IN UINT32 AndData
> + )
> +{
> + return PciSegmentWrite32 (Address, PciSegmentRead32 (Address) & AndData);
> +}
> +
> +/**
> + Performs a bitwise AND of a 32-bit PCI configuration register with
> + a 32-bit value, followed by a bitwise OR with another 32-bit value.
> +
> + Reads the 32-bit PCI configuration register specified by Address,
> + performs a bitwise AND between the read result and the value specified
> + by AndData, performs a bitwise OR between the result of the AND operation
> + and the value specified by OrData, and writes the result to the 32-bit
> + PCI configuration register specified by Address.
> +
> + The value written to the PCI configuration register is returned.
> + This function must guarantee that all PCI read and write operations
> + are serialized.
> +
> + If any reserved bits in Address are set, then ASSERT().
> + If Address is not aligned on a 32-bit boundary, then ASSERT().
> +
> + @param Address The address that encodes the PCI Segment, Bus, Device,
> + Function and Register.
> + @param AndData The value to AND with the PCI configuration register.
> + @param OrData The value to OR with the PCI configuration register.
> +
> + @return The value written to the PCI configuration register.
> +
> +**/
> +UINT32
> +EFIAPI
> +PciSegmentAndThenOr32 (
> + IN UINT64 Address,
> + IN UINT32 AndData,
> + IN UINT32 OrData
> + )
> +{
> + return PciSegmentWrite32 (Address,
> + (PciSegmentRead32 (Address) & AndData) | OrData);
> +}
> +
> +/**
> + Reads a bit field of a PCI configuration register.
> +
> + Reads the bit field in a 32-bit PCI configuration register. The bit field is
> + specified by the StartBit and the EndBit. The value of the bit field is
> + returned.
> +
> + If any reserved bits in Address are set, then ASSERT().
> + If Address is not aligned on a 32-bit boundary, then ASSERT().
> + If StartBit is greater than 31, then ASSERT().
> + If EndBit is greater than 31, then ASSERT().
> + If EndBit is less than StartBit, then ASSERT().
> +
> + @param Address The PCI configuration register to read.
> + @param StartBit The ordinal of the least significant bit in the bit field.
> + Range 0..31.
> + @param EndBit The ordinal of the most significant bit in the bit field.
> + Range 0..31.
> +
> + @return The value of the bit field read from the PCI configuration register.
> +
> +**/
> +UINT32
> +EFIAPI
> +PciSegmentBitFieldRead32 (
> + IN UINT64 Address,
> + IN UINTN StartBit,
> + IN UINTN EndBit
> + )
> +{
> + return BitFieldRead32 (PciSegmentRead32 (Address), StartBit, EndBit);
> +}
> +
> +/**
> + Writes a bit field to a PCI configuration register.
> +
> + Writes Value to the bit field of the PCI configuration register. The bit
> + field is specified by the StartBit and the EndBit. All other bits in the
> + destination PCI configuration register are preserved. The new value of the
> + 32-bit register is returned.
> +
> + If any reserved bits in Address are set, then ASSERT().
> + If Address is not aligned on a 32-bit boundary, then ASSERT().
> + If StartBit is greater than 31, then ASSERT().
> + If EndBit is greater than 31, then ASSERT().
> + If EndBit is less than StartBit, then ASSERT().
> + If Value is larger than the bitmask value range specified by StartBit
> + and EndBit, then ASSERT().
> +
> + @param Address The PCI configuration register to write.
> + @param StartBit The ordinal of the least significant bit in the bit field.
> + Range 0..31.
> + @param EndBit The ordinal of the most significant bit in the bit field.
> + Range 0..31.
> + @param Value The new value of the bit field.
> +
> + @return The value written back to the PCI configuration register.
> +
> +**/
> +UINT32
> +EFIAPI
> +PciSegmentBitFieldWrite32 (
> + IN UINT64 Address,
> + IN UINTN StartBit,
> + IN UINTN EndBit,
> + IN UINT32 Value
> + )
> +{
> + return PciSegmentWrite32 (Address,
> + BitFieldWrite32 (PciSegmentRead32 (Address),
> + StartBit,
> + EndBit,
> + Value));
> +}
> +
> +/**
> + Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and
> + writes the result back to the bit field in the 32-bit port.
> +
> + Reads the 32-bit PCI configuration register specified by Address, performs a
> + bitwise OR between the read result and the value specified by
> + OrData, and writes the result to the 32-bit PCI configuration register
> + specified by Address. The value written to the PCI configuration register is
> + returned. This function must guarantee that all PCI read and write operations
> + are serialized. Extra left bits in OrData are stripped.
> +
> + If any reserved bits in Address are set, then ASSERT().
> + If StartBit is greater than 31, then ASSERT().
> + If EndBit is greater than 31, then ASSERT().
> + If EndBit is less than StartBit, then ASSERT().
> + If OrData is larger than the bitmask value range specified by StartBit and
> + EndBit, then ASSERT().
> +
> + @param Address The PCI configuration register to write.
> + @param StartBit The ordinal of the least significant bit in the bit field.
> + Range 0..31.
> + @param EndBit The ordinal of the most significant bit in the bit field.
> + Range 0..31.
> + @param OrData The value to OR with the PCI configuration register.
> +
> + @return The value written back to the PCI configuration register.
> +
> +**/
> +UINT32
> +EFIAPI
> +PciSegmentBitFieldOr32 (
> + IN UINT64 Address,
> + IN UINTN StartBit,
> + IN UINTN EndBit,
> + IN UINT32 OrData
> + )
> +{
> + return PciSegmentWrite32 (Address,
> + BitFieldOr32 (PciSegmentRead32 (Address),
> + StartBit,
> + EndBit,
> + OrData));
> +}
> +
> +/**
> + Reads a bit field in a 32-bit PCI configuration register, performs a bitwise
> + AND, and writes the result back to the bit field in the 32-bit register.
> +
> + Reads the 32-bit PCI configuration register specified by Address,
> + performs a bitwise AND between the read result and the value specified
> + by AndData, and writes the result to the 32-bit PCI configuration register
> + specified by Address. The value written to the PCI configuration register
> + is returned. This function must guarantee that all PCI read and write
> + operations are serialized. Extra left bits in AndData are stripped.
> +
> + If any reserved bits in Address are set, then ASSERT().
> + If Address is not aligned on a 32-bit boundary, then ASSERT().
> + If StartBit is greater than 31, then ASSERT().
> + If EndBit is greater than 31, then ASSERT().
> + If EndBit is less than StartBit, then ASSERT().
> + If AndData is larger than the bitmask value range specified by StartBit and
> + EndBit, then ASSERT().
> +
> + @param Address The PCI configuration register to write.
> + @param StartBit The ordinal of the least significant bit in the bit field.
> + Range 0..31.
> + @param EndBit The ordinal of the most significant bit in the bit field.
> + Range 0..31.
> + @param AndData The value to AND with the PCI configuration register.
> +
> + @return The value written back to the PCI configuration register.
> +
> +**/
> +UINT32
> +EFIAPI
> +PciSegmentBitFieldAnd32 (
> + IN UINT64 Address,
> + IN UINTN StartBit,
> + IN UINTN EndBit,
> + IN UINT32 AndData
> + )
> +{
> + return PciSegmentWrite32 (Address,
> + BitFieldAnd32 (PciSegmentRead32 (Address),
> + StartBit,
> + EndBit,
> + AndData));
> +}
> +
> +/**
> + Reads a bit field in a 32-bit port, performs a bitwise AND followed by a
> + bitwise OR, and writes the result back to the bit field in the
> + 32-bit port.
> +
> + Reads the 32-bit PCI configuration register specified by Address, performs a
> + bitwise AND followed by a bitwise OR between the read result and
> + the value specified by AndData, and writes the result to the 32-bit PCI
> + configuration register specified by Address. The value written to the PCI
> + configuration register is returned. This function must guarantee that all PCI
> + read and write operations are serialized. Extra left bits in both AndData and
> + OrData are stripped.
> +
> + If any reserved bits in Address are set, then ASSERT().
> + If StartBit is greater than 31, then ASSERT().
> + If EndBit is greater than 31, then ASSERT().
> + If EndBit is less than StartBit, then ASSERT().
> + If AndData is larger than the bitmask value range specified by StartBit
> + and EndBit, then ASSERT().
> + If OrData is larger than the bitmask value range specified by StartBit
> + and EndBit, then ASSERT().
> +
> + @param Address The PCI configuration register to write.
> + @param StartBit The ordinal of the least significant bit in the bit field.
> + Range 0..31.
> + @param EndBit The ordinal of the most significant bit in the bit field.
> + Range 0..31.
> + @param AndData The value to AND with the PCI configuration register.
> + @param OrData The value to OR with the result of the AND operation.
> +
> + @return The value written back to the PCI configuration register.
> +
> +**/
> +UINT32
> +EFIAPI
> +PciSegmentBitFieldAndThenOr32 (
> + IN UINT64 Address,
> + IN UINTN StartBit,
> + IN UINTN EndBit,
> + IN UINT32 AndData,
> + IN UINT32 OrData
> + )
> +{
> + return PciSegmentWrite32 (
> + Address,
> + BitFieldAndThenOr32 (PciSegmentRead32 (Address),
> + StartBit,
> + EndBit,
> + AndData,
> + OrData));
> +}
> +
> +/**
> + Reads a range of PCI configuration registers into a caller supplied buffer.
> +
> + Reads the range of PCI configuration registers specified by StartAddress and
> + Size into the buffer specified by Buffer. This function only allows the PCI
> + configuration registers from a single PCI function to be read. Size is
> + returned. When possible 32-bit PCI configuration read cycles are used to read
> + from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit
> + and 16-bit PCI configuration read cycles may be used at the beginning and the
> + end of the range.
> +
> + If any reserved bits in StartAddress are set, then ASSERT().
> + If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
> + If Size > 0 and Buffer is NULL, then ASSERT().
> +
> + @param StartAddress The starting address that encodes the PCI Segment, Bus,
> + Device, Function and Register.
> + @param Size The size in bytes of the transfer.
> + @param Buffer The pointer to a buffer receiving the data read.
> +
> + @return Size
> +
> +**/
> +UINTN
> +EFIAPI
> +PciSegmentReadBuffer (
> + IN UINT64 StartAddress,
> + IN UINTN Size,
> + OUT VOID *Buffer
> + )
> +{
> + UINTN ReturnValue;
> +
> + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (StartAddress, 0);
> + ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);
[SAMI] What happens in release build if any of the above conditions
fail? Should this function continue to execute?
> +
> + if (Size == 0) {
> + return Size;
> + }
> +
> + ASSERT (Buffer != NULL);
[SAMI] For Release build, if Buffer is NULL, it will still be
dereferenced a few lines below.
> +
> + // Save Size for return
> + ReturnValue = Size;
> +
> + if ((StartAddress & BIT0) != 0) {
> + // Read a byte if StartAddress is byte aligned
> + *(volatile UINT8 *)Buffer = PciSegmentRead8 (StartAddress);
> + StartAddress += sizeof (UINT8);
> + Size -= sizeof (UINT8);
> + Buffer = (UINT8*)Buffer + 1;
> + }
> +
> + if (Size >= sizeof (UINT16) && (StartAddress & BIT1) != 0) {
> + // Read a word if StartAddress is word aligned
> + WriteUnaligned16 (Buffer, PciSegmentRead16 (StartAddress));
> + StartAddress += sizeof (UINT16);
> + Size -= sizeof (UINT16);
> + Buffer = (UINT16*)Buffer + 1;
> + }
> +
> + while (Size >= sizeof (UINT32)) {
> + // Read as many double words as possible
> + WriteUnaligned32 (Buffer, PciSegmentRead32 (StartAddress));
> + StartAddress += sizeof (UINT32);
> + Size -= sizeof (UINT32);
> + Buffer = (UINT32*)Buffer + 1;
> + }
> +
> + if (Size >= sizeof (UINT16)) {
> + // Read the last remaining word if exist
> + WriteUnaligned16 (Buffer, PciSegmentRead16 (StartAddress));
> + StartAddress += sizeof (UINT16);
> + Size -= sizeof (UINT16);
> + Buffer = (UINT16*)Buffer + 1;
> + }
> +
> + if (Size >= sizeof (UINT8)) {
> + // Read the last remaining byte if exist
> + *(volatile UINT8 *)Buffer = PciSegmentRead8 (StartAddress);
> + }
> +
> + return ReturnValue;
> +}
> +
> +/**
> + Copies the data in a caller supplied buffer to a specified range of PCI
> + configuration space.
> +
> + Writes the range of PCI configuration registers specified by StartAddress and
> + Size from the buffer specified by Buffer. This function only allows the PCI
> + configuration registers from a single PCI function to be written. Size is
> + returned. When possible 32-bit PCI configuration write cycles are used to
> + write from StartAdress to StartAddress + Size. Due to alignment restrictions,
> + 8-bit and 16-bit PCI configuration write cycles may be used at the beginning
> + and the end of the range.
> +
> + If any reserved bits in StartAddress are set, then ASSERT().
> + If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
> + If Size > 0 and Buffer is NULL, then ASSERT().
> +
> + @param StartAddress The starting address that encodes the PCI Segment, Bus,
> + Device, Function and Register.
> + @param Size The size in bytes of the transfer.
> + @param Buffer The pointer to a buffer containing the data to write.
> +
> + @return The parameter of Size.
> +
> +**/
> +UINTN
> +EFIAPI
> +PciSegmentWriteBuffer (
> + IN UINT64 StartAddress,
> + IN UINTN Size,
> + IN VOID *Buffer
> + )
> +{
> + UINTN ReturnValue;
> +
> + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (StartAddress, 0);
> + ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);
[SAMI] Same comment as in PciSegmentReadBuffer.
> +
> + if (Size == 0) {
> + return 0;
> + }
> +
> + ASSERT (Buffer != NULL);
[SAMI] Same comment as in PciSegmentReadBuffer.
> +
> + // Save Size for return
> + ReturnValue = Size;
> +
> + if ((StartAddress & BIT0) != 0) {
> + // Write a byte if StartAddress is byte aligned
> + PciSegmentWrite8 (StartAddress, *(UINT8*)Buffer);
> + StartAddress += sizeof (UINT8);
> + Size -= sizeof (UINT8);
> + Buffer = (UINT8*)Buffer + 1;
> + }
> +
> + if (Size >= sizeof (UINT16) && (StartAddress & BIT1) != 0) {
> + // Write a word if StartAddress is word aligned
> + PciSegmentWrite16 (StartAddress, ReadUnaligned16 (Buffer));
> + StartAddress += sizeof (UINT16);
> + Size -= sizeof (UINT16);
> + Buffer = (UINT16*)Buffer + 1;
> + }
> +
> + while (Size >= sizeof (UINT32)) {
> + // Write as many double words as possible
> + PciSegmentWrite32 (StartAddress, ReadUnaligned32 (Buffer));
> + StartAddress += sizeof (UINT32);
> + Size -= sizeof (UINT32);
> + Buffer = (UINT32*)Buffer + 1;
> + }
> +
> + if (Size >= sizeof (UINT16)) {
> + // Write the last remaining word if exist
> + PciSegmentWrite16 (StartAddress, ReadUnaligned16 (Buffer));
> + StartAddress += sizeof (UINT16);
> + Size -= sizeof (UINT16);
> + Buffer = (UINT16*)Buffer + 1;
> + }
> +
> + if (Size >= sizeof (UINT8)) {
> + // Write the last remaining byte if exist
> + PciSegmentWrite8 (StartAddress, *(UINT8*)Buffer);
> + }
> +
> + return ReturnValue;
> +}
> diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PciSegmentLib/PciSegmentLib.inf b/Silicon/ARM/NeoverseN1Soc/Library/PciSegmentLib/PciSegmentLib.inf
> new file mode 100644
> index 0000000000..1d15f74faf
> --- /dev/null
> +++ b/Silicon/ARM/NeoverseN1Soc/Library/PciSegmentLib/PciSegmentLib.inf
> @@ -0,0 +1,38 @@
> +## @file
> +# PCI Segment Library for N1Sdp SoC with multiple RCs
> +#
> +# Copyright (c) 2007 - 2014, Intel Corporation. All rights reserved.<BR>
> +# Copyright (c) 2021, ARM Limited. All rights reserved.<BR>
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +##
> +
> +[Defines]
> + INF_VERSION = 0x00010019
[SAMI] Can you update the INF_VERSION to match as defined by the latest
specification, please? See
https://edk2-docs.gitbook.io/edk-ii-inf-specification/2_inf_overview/24_-defines-_section
> + BASE_NAME = PciSegmentLib
> + FILE_GUID = b5ecc9c3-6b30-4f72-8a06-889b4ea8427e
> + MODULE_TYPE = BASE
> + VERSION_STRING = 1.0
> + LIBRARY_CLASS = PciSegmentLib
> +
> +[Sources]
> + PciSegmentLib.c
> +
> +[Packages]
> + MdePkg/MdePkg.dec
> + Platform/ARM/N1Sdp/N1SdpPlatform.dec
> + Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec
> +
> +[LibraryClasses]
> + BaseLib
> + DebugLib
> + IoLib
> +
> +[FixedPcd]
> + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixExpressBaseAddress
> + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieExpressBaseAddress
> + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixRootPortConfigBaseAddress
> + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixRootPortConfigBaseSize
> + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieRootPortConfigBaseAddress
> + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieRootPortConfigBaseSize
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [edk2-devel] [PATCH v5 2/4] Silicon/ARM/NeoverseN1Soc: Update PCDs to support multiple PCI root ports
2021-12-22 1:14 ` [PATCH v5 2/4] Silicon/ARM/NeoverseN1Soc: Update PCDs to support multiple PCI root ports Khasim Mohammed
2021-12-22 8:52 ` [edk2-devel] " PierreGondois
@ 2022-01-19 15:01 ` Sami Mujawar
1 sibling, 0 replies; 13+ messages in thread
From: Sami Mujawar @ 2022-01-19 15:01 UTC (permalink / raw)
To: devel, khasim.mohammed; +Cc: nd
Hi Khasim,
Thank you for this patch.
I have a minor suggestion marked inline as [SAMI]. Otherwise this patch
looks good to me.
With that changed,
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
Regards,
Sami Mujawar
On 22/12/2021 01:14 AM, Khasim Mohammed via groups.io wrote:
> PCD entries are updated to remove the hardcoded assignments and to
> add support for multiple PCI root ports.
>
> Signed-off-by: Khasim Syed Mohammed <khasim.mohammed@arm.com>
> ---
> .../AslTables/SsdtPci.asl | 8 +--
> .../AslTables/SsdtRemotePci.asl | 4 +-
> .../ConfigurationManager.c | 24 ++++----
> .../ConfigurationManagerDxe.inf | 18 ++++--
> Platform/ARM/N1Sdp/N1SdpPlatform.dec | 8 ---
> Platform/ARM/N1Sdp/N1SdpPlatform.dsc | 1 -
> .../Library/PlatformLib/PlatformLib.inf | 1 +
> .../Library/PlatformLib/PlatformLibMem.c | 4 +-
> Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec | 58 +++++++++++--------
> 9 files changed, 68 insertions(+), 58 deletions(-)
>
> diff --git a/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/AslTables/SsdtPci.asl b/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/AslTables/SsdtPci.asl
> index cdbd42c154..9922673d0d 100644
> --- a/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/AslTables/SsdtPci.asl
> +++ b/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/AslTables/SsdtPci.asl
> @@ -80,8 +80,8 @@ DefinitionBlock("SsdtPci.aml", "SSDT", 1, "ARMLTD", "N1Sdp",
> Device(PCI0) {
> Name (_HID, EISAID("PNP0A08")) // PCI Express Root Bridge
> Name (_CID, EISAID("PNP0A03")) // Compatible PCI Root Bridge
> - Name (_SEG, Zero) // PCI Segment Group number
> - Name (_BBN, Zero) // PCI Base Bus Number
> + Name (_SEG, FixedPcdGet32 (PcdPcieSegmentNumber)) // Segment Number
> + Name (_BBN, FixedPcdGet32 (PcdPcieBusBaseNumber)) // Bus Base Number
> Name (_CCA, 1) // Cache Coherency Attribute
>
> // Root Complex 0
> @@ -166,8 +166,8 @@ DefinitionBlock("SsdtPci.aml", "SSDT", 1, "ARMLTD", "N1Sdp",
> Device(PCI1) {
> Name (_HID, EISAID("PNP0A08")) // PCI Express Root Bridge
> Name (_CID, EISAID("PNP0A03")) // Compatible PCI Root Bridge
> - Name (_SEG, 1) // PCI Segment Group number
> - Name (_BBN, Zero) // PCI Base Bus Number
> + Name (_SEG, FixedPcdGet32 (PcdCcixSegmentNumber)) // Segment Number
> + Name (_BBN, FixedPcdGet32 (PcdCcixBusBaseNumber)) // Bus Base Number
> Name (_CCA, 1) // Cache Coherency Attribute
>
> // Root Complex 1
> diff --git a/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/AslTables/SsdtRemotePci.asl b/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/AslTables/SsdtRemotePci.asl
> index b6bec7c106..4c6e0c762f 100644
> --- a/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/AslTables/SsdtRemotePci.asl
> +++ b/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/AslTables/SsdtRemotePci.asl
> @@ -76,8 +76,8 @@ DefinitionBlock("SsdtRemotePci.aml", "SSDT", 1, "ARMLTD", "N1Sdp",
> Device(PCI2) {
> Name (_HID, EISAID("PNP0A08")) // PCI Express Root Bridge
> Name (_CID, EISAID("PNP0A03")) // Compatible PCI Root Bridge
> - Name (_SEG, 2) // PCI Segment Group number
> - Name (_BBN, Zero) // PCI Base Bus Number
> + Name (_SEG, FixedPcdGet32 (PcdRemotePcieSegmentNumber)) // Segment Number
> + Name (_BBN, FixedPcdGet32 (PcdRemotePcieBusBaseNumber)) // BusBase Number
> Name (_CCA, 1) // Cache Coherency Attribute
>
> // Remote Root Complex 0
> diff --git a/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c b/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c
> index 9c91372c11..f50623ae3f 100644
> --- a/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c
> +++ b/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c
> @@ -1047,24 +1047,24 @@ EDKII_PLATFORM_REPOSITORY_INFO N1sdpRepositoryInfo = {
> {
> // PCIe ECAM
> {
> - 0x70000000, // Base Address
> - 0x0, // Segment Group Number
> - 0x0, // Start Bus Number
> - 17 // End Bus Number
> + FixedPcdGet64 (PcdPcieExpressBaseAddress), // Base Address
> + FixedPcdGet32 (PcdPcieSegmentNumber), // Segment Group Number
> + FixedPcdGet32 (PcdPcieBusMin), // Start Bus Number
> + FixedPcdGet32 (PcdPcieBusMax) // End Bus Number
> },
> // CCIX ECAM
> {
> - 0x68000000, // Base Address
> - 0x1, // Segment Group Number
> - 0x0, // Start Bus Number
> - 17 // End Bus Number
> + FixedPcdGet32 (PcdCcixExpressBaseAddress), // Base Address
> + FixedPcdGet32 (PcdCcixSegmentNumber), // Segment Group Number
> + FixedPcdGet32 (PcdCcixBusMin), // Start Bus Number
> + FixedPcdGet32 (PcdCcixBusMax) // End Bus Number
> },
> //Remote Chip PCIe ECAM
> {
> - 0x40070000000, // Base Address
> - 0x2, // Segment Group Number
> - 0x0, // Start Bus Number
> - 17 // End Bus Number
> + FixedPcdGet64 (PcdRemotePcieBaseAddress), // Base Address
> + FixedPcdGet32 (PcdRemotePcieSegmentNumber), // Segment Group Number
> + FixedPcdGet32 (PcdRemotePcieBusMin), // Start Bus Number
> + FixedPcdGet32 (PcdRemotePcieBusMax) // End Bus Number
> }
> },
>
> diff --git a/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerDxe.inf b/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerDxe.inf
> index 027a4202ff..3a8711c6f1 100644
> --- a/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerDxe.inf
> +++ b/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerDxe.inf
> @@ -76,8 +76,6 @@
> gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase
> gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate
>
> - gArmN1SdpTokenSpaceGuid.PcdPcieExpressBaseAddress
> -
> gArmNeoverseN1SocTokenSpaceGuid.PcdExtMemorySpace
> gArmNeoverseN1SocTokenSpaceGuid.PcdDramBlock2Base
>
> @@ -91,6 +89,8 @@
> gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusCount
> gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusMax
> gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusMin
> + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusBaseNumber
[SAMI] Please arrange in alphsbetical order. Same comment for other
locations where PCDs are added in this patch (also in the dec files).
> + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieExpressBaseAddress
> gArmNeoverseN1SocTokenSpaceGuid.PcdPcieIoBase
> gArmNeoverseN1SocTokenSpaceGuid.PcdPcieIoMaxBase
> gArmNeoverseN1SocTokenSpaceGuid.PcdPcieIoSize
> @@ -105,11 +105,13 @@
> gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio64Translation
> gArmNeoverseN1SocTokenSpaceGuid.PcdPcieRootPortConfigBaseAddress
> gArmNeoverseN1SocTokenSpaceGuid.PcdPcieRootPortConfigBaseSize
> + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieSegmentNumber
>
> # CCIX
> gArmNeoverseN1SocTokenSpaceGuid.PcdCcixBusCount
> gArmNeoverseN1SocTokenSpaceGuid.PcdCcixBusMax
> gArmNeoverseN1SocTokenSpaceGuid.PcdCcixBusMin
> + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixBusBaseNumber
> gArmNeoverseN1SocTokenSpaceGuid.PcdCcixExpressBaseAddress
> gArmNeoverseN1SocTokenSpaceGuid.PcdCcixIoBase
> gArmNeoverseN1SocTokenSpaceGuid.PcdCcixIoMaxBase
> @@ -125,6 +127,7 @@
> gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio64Translation
> gArmNeoverseN1SocTokenSpaceGuid.PcdCcixRootPortConfigBaseAddress
> gArmNeoverseN1SocTokenSpaceGuid.PcdCcixRootPortConfigBaseSize
> + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixSegmentNumber
>
> # Coresight
> gArmN1SdpTokenSpaceGuid.PcdCsComponentSize
> @@ -158,9 +161,14 @@
> gArmN1SdpTokenSpaceGuid.PcdCsTpiuMaxBase
>
> # Remote PCIe
> - gArmN1SdpTokenSpaceGuid.PcdRemotePcieIoTranslation
> - gArmN1SdpTokenSpaceGuid.PcdRemotePcieMmio32Translation
> - gArmN1SdpTokenSpaceGuid.PcdRemotePcieMmio64Translation
> + gArmNeoverseN1SocTokenSpaceGuid.PcdRemotePcieBaseAddress
> + gArmNeoverseN1SocTokenSpaceGuid.PcdRemotePcieBusBaseNumber
> + gArmNeoverseN1SocTokenSpaceGuid.PcdRemotePcieBusMax
> + gArmNeoverseN1SocTokenSpaceGuid.PcdRemotePcieBusMin
> + gArmNeoverseN1SocTokenSpaceGuid.PcdRemotePcieIoTranslation
> + gArmNeoverseN1SocTokenSpaceGuid.PcdRemotePcieMmio32Translation
> + gArmNeoverseN1SocTokenSpaceGuid.PcdRemotePcieMmio64Translation
> + gArmNeoverseN1SocTokenSpaceGuid.PcdRemotePcieSegmentNumber
>
> [Depex]
> TRUE
> diff --git a/Platform/ARM/N1Sdp/N1SdpPlatform.dec b/Platform/ARM/N1Sdp/N1SdpPlatform.dec
> index 2ab6c20dcc..16937197b8 100644
> --- a/Platform/ARM/N1Sdp/N1SdpPlatform.dec
> +++ b/Platform/ARM/N1Sdp/N1SdpPlatform.dec
> @@ -34,9 +34,6 @@
> gArmN1SdpTokenSpaceGuid.PcdRamDiskBase|0x88000000|UINT32|0x00000001
> gArmN1SdpTokenSpaceGuid.PcdRamDiskSize|0x18000000|UINT32|0x00000002
>
> - # PCIe
> - gArmN1SdpTokenSpaceGuid.PcdPcieExpressBaseAddress|0x70000000|UINT32|0x00000007
> -
> # External memory
> gArmNeoverseN1SocTokenSpaceGuid.PcdExtMemorySpace|0|UINT64|0x00000029
>
> @@ -92,8 +89,3 @@
> # unmapped reserved region results in a DECERR response.
> #
> gArmN1SdpTokenSpaceGuid.PcdCsComponentSize|0x1000|UINT32|0x00000049
> -
> - # Remote Chip PCIe
> - gArmN1SdpTokenSpaceGuid.PcdRemotePcieIoTranslation|0x40075200000|UINT64|0x0000004A
> - gArmN1SdpTokenSpaceGuid.PcdRemotePcieMmio32Translation|0x40000000000|UINT64|0x0000004B
> - gArmN1SdpTokenSpaceGuid.PcdRemotePcieMmio64Translation|0x40000000000|UINT64|0x0000004C
> diff --git a/Platform/ARM/N1Sdp/N1SdpPlatform.dsc b/Platform/ARM/N1Sdp/N1SdpPlatform.dsc
> index 7488bdc036..cb2049966c 100644
> --- a/Platform/ARM/N1Sdp/N1SdpPlatform.dsc
> +++ b/Platform/ARM/N1Sdp/N1SdpPlatform.dsc
> @@ -127,7 +127,6 @@
> gArmTokenSpaceGuid.PcdGicRedistributorsBase|0x300C0000
>
> # PCIe
> - gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x70000000
> gEmbeddedTokenSpaceGuid.PcdPrePiCpuIoSize|24
> gEfiMdeModulePkgTokenSpaceGuid.PcdSrIovSupport|FALSE
>
> diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf
> index 8e2154aadf..96e590cdd8 100644
> --- a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf
> +++ b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf
> @@ -43,6 +43,7 @@
> gArmNeoverseN1SocTokenSpaceGuid.PcdExtMemorySpace
> gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusMax
> gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusMin
> + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieExpressBaseAddress
> gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio32Base
> gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio32Size
> gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio64Base
> diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c
> index 1c4a445c5e..339fa07b32 100644
> --- a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c
> +++ b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c
> @@ -115,8 +115,8 @@ ArmPlatformGetVirtualMemoryMap (
> VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
>
> // PCIe ECAM Configuration Space
> - VirtualMemoryTable[++Index].PhysicalBase = PcdGet64 (PcdPciExpressBaseAddress);
> - VirtualMemoryTable[Index].VirtualBase = PcdGet64 (PcdPciExpressBaseAddress);
> + VirtualMemoryTable[++Index].PhysicalBase = PcdGet64 (PcdPcieExpressBaseAddress);
> + VirtualMemoryTable[Index].VirtualBase = PcdGet64 (PcdPcieExpressBaseAddress);
> VirtualMemoryTable[Index].Length = (FixedPcdGet32 (PcdPcieBusMax) -
> FixedPcdGet32 (PcdPcieBusMin) + 1) *
> SIZE_1MB;
> diff --git a/Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec b/Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec
> index eea2d58402..d91ed28319 100644
> --- a/Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec
> +++ b/Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec
> @@ -29,11 +29,11 @@
> gArmNeoverseN1SocTokenSpaceGuid.PcdDramBlock2Base|0|UINT64|0x00000001
>
> #PCIe
> - gArmNeoverseN1SocTokenSpaceGuid.PcdPcieRootPortConfigBaseAddress|0x60000000|UINT32|0x00000002
> - gArmNeoverseN1SocTokenSpaceGuid.PcdPcieRootPortConfigBaseSize|0x00001000|UINT32|0x00000003
> - gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusCount|18|UINT32|0x00000004
> - gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusMax|17|UINT32|0x00000005
> - gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusMin|0|UINT32|0x00000006
> + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusCount|18|UINT32|0x00000002
> + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusMax|17|UINT32|0x00000003
> + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusMin|0|UINT32|0x00000004
> + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusBaseNumber|0|UINT32|0x00000005
> + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieExpressBaseAddress|0x70000000|UINT64|0x00000006
> gArmNeoverseN1SocTokenSpaceGuid.PcdPcieIoBase|0x0|UINT32|0x00000007
> gArmNeoverseN1SocTokenSpaceGuid.PcdPcieIoMaxBase|0x001FFFF|UINT32|0x00000008
> gArmNeoverseN1SocTokenSpaceGuid.PcdPcieIoSize|0x020000|UINT32|0x00000009
> @@ -46,30 +46,40 @@
> gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio64MaxBase|0x28FFFFFFFF|UINT64|0x00000010
> gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio64Size|0x2000000000|UINT64|0x00000011
> gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio64Translation|0x0|UINT64|0x00000012
> + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieRootPortConfigBaseAddress|0x60000000|UINT32|0x00000013
> + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieRootPortConfigBaseSize|0x00001000|UINT32|0x00000014
> + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieSegmentNumber|0|UINT32|0x00000015
>
> # CCIX
> gArmNeoverseN1SocTokenSpaceGuid.PcdCcixBusCount|18|UINT32|0x00000016
> gArmNeoverseN1SocTokenSpaceGuid.PcdCcixBusMax|17|UINT32|0x00000017
> gArmNeoverseN1SocTokenSpaceGuid.PcdCcixBusMin|0|UINT32|0x00000018
> - gArmNeoverseN1SocTokenSpaceGuid.PcdCcixExpressBaseAddress|0x68000000|UINT32|0x00000019
> - gArmNeoverseN1SocTokenSpaceGuid.PcdCcixIoBase|0x0|UINT32|0x0000001A
> - gArmNeoverseN1SocTokenSpaceGuid.PcdCcixIoMaxBase|0x01FFFF|UINT32|0x0000001B
> - gArmNeoverseN1SocTokenSpaceGuid.PcdCcixIoSize|0x020000|UINT32|0x0000001C
> - gArmNeoverseN1SocTokenSpaceGuid.PcdCcixIoTranslation|0x6D200000|UINT32|0x00000001D
> - gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio32Base|0x69200000|UINT32|0x0000001E
> - gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio32MaxBase|0x6D1FFFFF|UINT32|0x00000001F
> - gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio32Size|0x04000000|UINT32|0x00000020
> - gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio32Translation|0x0|UINT32|0x00000021
> - gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio64Base|0x2900000000|UINT64|0x00000022
> - gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio64MaxBase|0x48FFFFFFFF|UINT64|0x00000023
> - gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio64Size|0x2000000000|UINT64|0x00000024
> - gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio64Translation|0x0|UINT64|0x00000025
> - gArmNeoverseN1SocTokenSpaceGuid.PcdCcixRootPortConfigBaseAddress|0x62000000|UINT32|0x00000026
> - gArmNeoverseN1SocTokenSpaceGuid.PcdCcixRootPortConfigBaseSize|0x00001000|UINT32|0x00000027
> + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixBusBaseNumber|0|UINT32|0x00000019
> + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixExpressBaseAddress|0x68000000|UINT32|0x0000001A
> + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixIoBase|0x0|UINT32|0x0000001B
> + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixIoMaxBase|0x00FFFFFF|UINT32|0x0000001C
> + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixIoSize|0x01000000|UINT32|0x0000001D
> + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixIoTranslation|0x6D200000|UINT32|0x00000001E
> + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio32Base|0x69200000|UINT32|0x0000001F
> + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio32MaxBase|0x6D1FFFFF|UINT32|0x000000020
> + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio32Size|0x04000000|UINT32|0x00000021
> + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio32Translation|0x0|UINT32|0x00000022
> + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio64Base|0x2900000000|UINT64|0x00000023
> + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio64MaxBase|0x48FFFFFFFF|UINT64|0x00000024
> + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio64Size|0x2000000000|UINT64|0x00000025
> + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio64Translation|0x0|UINT64|0x00000026
> + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixRootPortConfigBaseAddress|0x62000000|UINT32|0x00000027
> + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixRootPortConfigBaseSize|0x00001000|UINT32|0x00000028
> + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixSegmentNumber|1|UINT32|0x00000029
>
> - gArmNeoverseN1SocTokenSpaceGuid.PcdExtMemorySpace|0x40000000000|UINT64|0x00000029
> + gArmNeoverseN1SocTokenSpaceGuid.PcdExtMemorySpace|0x40000000000|UINT64|0x00000030
>
> # Remote Chip PCIe
> - gArmNeoverseN1SocTokenSpaceGuid.PcdRemotePcieIoTranslation|0x40075200000|UINT64|0x0000004A
> - gArmNeoverseN1SocTokenSpaceGuid.PcdRemotePcieMmio32Translation|0x40000000000|UINT64|0x0000004B
> - gArmNeoverseN1SocTokenSpaceGuid.PcdRemotePcieMmio64Translation|0x40000000000|UINT64|0x0000004C
> + gArmNeoverseN1SocTokenSpaceGuid.PcdRemotePcieBaseAddress|0x40070000000|UINT64|0x0000004A
> + gArmNeoverseN1SocTokenSpaceGuid.PcdRemotePcieBusBaseNumber|0|UINT32|0x0000004B
> + gArmNeoverseN1SocTokenSpaceGuid.PcdRemotePcieBusMax|17|UINT32|0x0000004C
> + gArmNeoverseN1SocTokenSpaceGuid.PcdRemotePcieBusMin|0|UINT32|0x0000004D
> + gArmNeoverseN1SocTokenSpaceGuid.PcdRemotePcieIoTranslation|0x40075200000|UINT64|0x0000004E
> + gArmNeoverseN1SocTokenSpaceGuid.PcdRemotePcieMmio32Translation|0x40000000000|UINT64|0x0000004F
> + gArmNeoverseN1SocTokenSpaceGuid.PcdRemotePcieMmio64Translation|0x40000000000|UINT64|0x00000050
> + gArmNeoverseN1SocTokenSpaceGuid.PcdRemotePcieSegmentNumber|2|UINT32|0x00000051
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [edk2-devel] [PATCH v5 3/4] Silicon/ARM/NeoverseN1Soc: Add CCIX root complex support
2021-12-22 1:14 ` [PATCH v5 3/4] Silicon/ARM/NeoverseN1Soc: Add CCIX root complex support Khasim Mohammed
2021-12-22 8:52 ` [edk2-devel] " PierreGondois
@ 2022-01-19 15:02 ` Sami Mujawar
1 sibling, 0 replies; 13+ messages in thread
From: Sami Mujawar @ 2022-01-19 15:02 UTC (permalink / raw)
To: devel, khasim.mohammed; +Cc: nd
Hi Khasim,
Thank you for this patch.
These changes look good to me.
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
Regards,
Sami Mujawar
On 22/12/2021 01:14 AM, Khasim Mohammed via groups.io wrote:
> This patch enables CCIX root complex support by updating
> the root complex node info in PciHostBridge library.
>
> Signed-off-by: Khasim Syed Mohammed <khasim.mohammed@arm.com>
> ---
> .../PciHostBridgeLib/PciHostBridgeLib.c | 71 +++++++++++++++++--
> .../PciHostBridgeLib/PciHostBridgeLib.inf | 11 ++-
> 2 files changed, 76 insertions(+), 6 deletions(-)
>
> diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.c b/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.c
> index 9332939f63..c3a14a6c17 100644
> --- a/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.c
> +++ b/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.c
> @@ -1,7 +1,7 @@
> /** @file
> * PCI Host Bridge Library instance for ARM Neoverse N1 platform
> *
> -* Copyright (c) 2019 - 2020, ARM Limited. All rights reserved.
> +* Copyright (c) 2019 - 2021, ARM Limited. All rights reserved.<BR>
> *
> * SPDX-License-Identifier: BSD-2-Clause-Patent
> *
> @@ -16,6 +16,8 @@
> #include <Protocol/PciHostBridgeResourceAllocation.h>
> #include <Protocol/PciRootBridgeIo.h>
>
> +#define ROOT_COMPLEX_NUM 2
> +
> GLOBAL_REMOVE_IF_UNREFERENCED
> STATIC CHAR16 CONST * CONST mPciHostBridgeLibAcpiAddressSpaceTypeStr[] = {
> L"Mem", L"I/O", L"Bus"
> @@ -28,7 +30,7 @@ typedef struct {
> } EFI_PCI_ROOT_BRIDGE_DEVICE_PATH;
> #pragma pack ()
>
> -STATIC EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath[] = {
> +STATIC EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath[ROOT_COMPLEX_NUM] = {
> // PCIe
> {
> {
> @@ -51,10 +53,33 @@ STATIC EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath[] = {
> 0
> }
> }
> - }
> + },
> + //CCIX
> + {
> + {
> + {
> + ACPI_DEVICE_PATH,
> + ACPI_DP,
> + {
> + (UINT8)sizeof (ACPI_HID_DEVICE_PATH),
> + (UINT8)(sizeof (ACPI_HID_DEVICE_PATH) >> 8)
> + }
> + },
> + EISA_PNP_ID(0x0A09), // CCIX
> + 0
> + },
> + {
> + END_DEVICE_PATH_TYPE,
> + END_ENTIRE_DEVICE_PATH_SUBTYPE,
> + {
> + END_DEVICE_PATH_LENGTH,
> + 0
> + }
> + }
> + },
> };
>
> -STATIC PCI_ROOT_BRIDGE mPciRootBridge[] = {
> +STATIC PCI_ROOT_BRIDGE mPciRootBridge[ROOT_COMPLEX_NUM] = {
> {
> 0, // Segment
> 0, // Supports
> @@ -90,7 +115,43 @@ STATIC PCI_ROOT_BRIDGE mPciRootBridge[] = {
> 0
> },
> (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath[0]
> - }
> + },
> + {
> + 1, // Segment
> + 0, // Supports
> + 0, // Attributes
> + TRUE, // DmaAbove4G
> + FALSE, // NoExtendedConfigSpace
> + FALSE, // ResourceAssigned
> + EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM | // AllocationAttributes
> + EFI_PCI_HOST_BRIDGE_MEM64_DECODE,
> + {
> + // Bus
> + FixedPcdGet32 (PcdCcixBusMin),
> + FixedPcdGet32 (PcdCcixBusMax)
> + }, {
> + // Io
> + FixedPcdGet64 (PcdCcixIoBase),
> + FixedPcdGet64 (PcdCcixIoBase) + FixedPcdGet64 (PcdCcixIoSize) - 1
> + }, {
> + // Mem
> + FixedPcdGet32 (PcdCcixMmio32Base),
> + FixedPcdGet32 (PcdCcixMmio32Base) + FixedPcdGet32 (PcdCcixMmio32Size) - 1
> + }, {
> + // MemAbove4G
> + FixedPcdGet64 (PcdCcixMmio64Base),
> + FixedPcdGet64 (PcdCcixMmio64Base) + FixedPcdGet64 (PcdCcixMmio64Size) - 1
> + }, {
> + // PMem
> + MAX_UINT64,
> + 0
> + }, {
> + // PMemAbove4G
> + MAX_UINT64,
> + 0
> + },
> + (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath[1]
> + },
> };
>
> /**
> diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.inf b/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.inf
> index 3ff1c592f2..3356c3ad35 100644
> --- a/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.inf
> +++ b/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.inf
> @@ -1,7 +1,7 @@
> ## @file
> # PCI Host Bridge Library instance for ARM Neoverse N1 platform.
> #
> -# Copyright (c) 2019 - 2020, ARM Limited. All rights reserved.
> +# Copyright (c) 2019 - 2021, ARM Limited. All rights reserved.<BR>
> #
> # SPDX-License-Identifier: BSD-2-Clause-Patent
> #
> @@ -42,6 +42,15 @@
> gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio64Base
> gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio64Size
>
> + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixBusMin
> + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixBusMax
> + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixIoBase
> + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixIoSize
> + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio32Base
> + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio32Size
> + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio64Base
> + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio64Size
> +
> [Protocols]
> gEfiCpuIo2ProtocolGuid
>
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [edk2-devel] [PATCH v5 4/4] Silicon/ARM/NeoverseN1Soc: Remove PciExpressLib use PciSegmentLib instead
2021-12-22 1:14 ` [PATCH v5 4/4] Silicon/ARM/NeoverseN1Soc: Remove PciExpressLib use PciSegmentLib instead Khasim Mohammed
2021-12-22 8:51 ` [edk2-devel] " PierreGondois
@ 2022-01-19 15:02 ` Sami Mujawar
1 sibling, 0 replies; 13+ messages in thread
From: Sami Mujawar @ 2022-01-19 15:02 UTC (permalink / raw)
To: devel, khasim.mohammed; +Cc: nd, Deepak Pandey
Hi Khasim,
Thank you for this patch.
These changes look good to me.
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
Regards,
Sami Mujawar
On 22/12/2021 01:14 AM, Khasim Mohammed via groups.io wrote:
> The patch removes PciExpressLib implementation for N1Sdp as:
>
> a) The PciSegmentLib implementation for N1Sdp makes MmioRead() calls
> instead of PciRead() which makes the PciExpressLib redundant.
>
> b) Since N1Sdp requires multiple segments to be supported, PciExpressLib
> and PciLib cannot be used, PciSegmentLib should be used instead as it
> supports multiple segments.
>
> Signed-off-by: Deepak Pandey <Deepak.Pandey@arm.com>
> Signed-off-by: Khasim Syed Mohammed <khasim.mohammed@arm.com>
> ---
> Platform/ARM/N1Sdp/N1SdpPlatform.dsc | 4 +-
> .../PciExpressLib.c | 1589 -----------------
> .../PciExpressLib.inf | 56 -
> 3 files changed, 1 insertion(+), 1648 deletions(-)
> delete mode 100644 Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciExpressLib/PciExpressLib.c
> delete mode 100644 Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciExpressLib/PciExpressLib.inf
>
> diff --git a/Platform/ARM/N1Sdp/N1SdpPlatform.dsc b/Platform/ARM/N1Sdp/N1SdpPlatform.dsc
> index cb2049966c..8dac1bc54c 100644
> --- a/Platform/ARM/N1Sdp/N1SdpPlatform.dsc
> +++ b/Platform/ARM/N1Sdp/N1SdpPlatform.dsc
> @@ -75,9 +75,7 @@
> [LibraryClasses.common.DXE_DRIVER]
> FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib.inf
> PciHostBridgeLib|Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.inf
> - PciSegmentLib|MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf
> - PciLib|MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf
> - PciExpressLib|Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciExpressLib/PciExpressLib.inf
> + PciSegmentLib|Silicon/ARM/NeoverseN1Soc/Library/PciSegmentLib/PciSegmentLib.inf
>
> [LibraryClasses.common.DXE_RUNTIME_DRIVER]
> BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
> diff --git a/Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciExpressLib/PciExpressLib.c b/Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciExpressLib/PciExpressLib.c
> deleted file mode 100644
> index bb0246b4a9..0000000000
> --- a/Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciExpressLib/PciExpressLib.c
> +++ /dev/null
> @@ -1,1589 +0,0 @@
> -/** @file
> - Functions in this library instance make use of MMIO functions in IoLib to
> - access memory mapped PCI configuration space.
> -
> - All assertions for I/O operations are handled in MMIO functions in the IoLib
> - Library.
> -
> - Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
> -
> - On the NeoverseN1Soc, a slave error is generated when host accesses the
> - configuration space of non-available device or unimplemented function on a
> - given bus. So this library introduces a workaround using IsBdfValid(),
> - to return 0xFFFFFFFF for all such access.
> -
> - In addition to this, the hardware has two other limitations which affect
> - access to the PCIe root port:
> - 1. ECAM space is not contiguous, root port ECAM (BDF = 0:0:0) is isolated
> - from rest of the downstream hierarchy ECAM space.
> - 2. Root port ECAM space is not capable of 8bit/16bit writes.
> - The description of the workarounds included for these limitations can
> - be found in the comments below.
> -
> - Copyright (c) 2020, ARM Limited. All rights reserved.
> -
> - SPDX-License-Identifier: BSD-2-Clause-Patent
> -
> -**/
> -
> -
> -#include <Base.h>
> -
> -#include <Library/BaseLib.h>
> -#include <Library/PciExpressLib.h>
> -#include <Library/IoLib.h>
> -#include <Library/DebugLib.h>
> -#include <Library/PcdLib.h>
> -#include <NeoverseN1Soc.h>
> -
> -/**
> - Assert the validity of a PCI address. A valid PCI address should contain 1's
> - only in the low 28 bits.
> -
> - @param A The address to validate.
> -
> -**/
> -#define ASSERT_INVALID_PCI_ADDRESS(A) \
> - ASSERT (((A) & ~0xfffffff) == 0)
> -
> -/* Root port Entry, BDF Entries Count */
> -#define BDF_TABLE_ENTRY_SIZE 4
> -#define BDF_TABLE_HEADER_COUNT 2
> -#define BDF_TABLE_HEADER_SIZE 8
> -
> -/* BDF table offsets for PCIe */
> -#define PCIE_BDF_TABLE_OFFSET 0
> -
> -#define GET_BUS_NUM(Address) (((Address) >> 20) & 0x7F)
> -#define GET_DEV_NUM(Address) (((Address) >> 15) & 0x1F)
> -#define GET_FUNC_NUM(Address) (((Address) >> 12) & 0x07)
> -#define GET_REG_NUM(Address) ((Address) & 0xFFF)
> -
> -/**
> - BDF Table structure : (Header + BDF Entries)
> - --------------------------------------------
> - [Offset 0x00] ROOT PORT ADDRESS
> - [Offset 0x04] BDF ENTRIES COUNT
> - [Offset 0x08] BDF ENTRY 0
> - [Offset 0x0C] BDF ENTRY 1
> - [Offset 0x10] BDF ENTRY 2
> - [Offset 0x14] BDF ENTRY 3
> - [Offset 0x18] BDF ENTRY 4
> - ...
> - [Offset 0x--] BDF ENTRY N
> - --------------------------------------------
> -**/
> -
> -/**
> - Value returned for reads on configuration space of unimplemented
> - device functions.
> -**/
> -STATIC UINTN mDummyConfigData = 0xFFFFFFFF;
> -
> -/**
> - Registers a PCI device so PCI configuration registers may be accessed after
> - SetVirtualAddressMap().
> -
> - Registers the PCI device specified by Address so all the PCI configuration
> - registers associated with that PCI device may be accessed after SetVirtualAddressMap()
> - is called.
> -
> - If Address > 0x0FFFFFFF, then ASSERT().
> -
> - @param Address The address that encodes the PCI Bus, Device, Function and
> - Register.
> -
> - @retval RETURN_SUCCESS The PCI device was registered for runtime access.
> - @retval RETURN_UNSUPPORTED An attempt was made to call this function
> - after ExitBootServices().
> - @retval RETURN_UNSUPPORTED The resources required to access the PCI device
> - at runtime could not be mapped.
> - @retval RETURN_OUT_OF_RESOURCES There are not enough resources available to
> - complete the registration.
> -
> -**/
> -RETURN_STATUS
> -EFIAPI
> -PciExpressRegisterForRuntimeAccess (
> - IN UINTN Address
> - )
> -{
> - ASSERT_INVALID_PCI_ADDRESS (Address);
> - return RETURN_UNSUPPORTED;
> -}
> -
> -/**
> - Check if the requested PCI address can be safely accessed.
> -
> - SCP performs the initial bus scan, prepares a table of valid BDF addresses
> - and shares them through non-trusted SRAM. This function validates if the
> - requested PCI address belongs to a valid BDF by checking the table of valid
> - entries. If not, this function will return false. This is a workaround to
> - avoid bus fault that occurs when accessing unavailable PCI device due to
> - hardware bug.
> -
> - @param Address The address that encodes the PCI Bus, Device, Function and
> - Register.
> -
> - @return TRUE BDF can be accessed, valid.
> - @return FALSE BDF should not be accessed, invalid.
> -
> -**/
> -STATIC
> -BOOLEAN
> -IsBdfValid (
> - IN UINTN Address
> - )
> -{
> - UINTN BdfCount;
> - UINTN BdfValue;
> - UINTN BdfEntry;
> - UINTN Count;
> - UINTN TableBase;
> - UINTN ConfigBase;
> -
> - ConfigBase = Address & ~0xFFF;
> - TableBase = NEOVERSEN1SOC_NON_SECURE_SRAM_BASE + PCIE_BDF_TABLE_OFFSET;
> - BdfCount = MmioRead32 (TableBase + BDF_TABLE_ENTRY_SIZE);
> - BdfEntry = TableBase + BDF_TABLE_HEADER_SIZE;
> -
> - /* Skip the header & check remaining entry */
> - for (Count = 0; Count < BdfCount; Count++, BdfEntry += BDF_TABLE_ENTRY_SIZE) {
> - BdfValue = MmioRead32 (BdfEntry);
> - if (BdfValue == ConfigBase) {
> - return TRUE;
> - }
> - }
> -
> - return FALSE;
> -}
> -
> -/**
> - Get the physical address of a configuration space register.
> -
> - Implement a workaround to avoid generation of slave errors from the bus. That
> - is, retrieve the PCI Express Base Address via a PCD entry, add the incomming
> - address with that base address and check whether this converted address
> - points to a accessible BDF. If it is not accessible, return the address
> - of a dummy location so that a read from it does not cause a slave error.
> -
> - In addition to this, implement a workaround for accessing the root port's
> - configuration space. The root port configuration space is not contiguous
> - with the rest of the downstream hierarchy configuration space. So determine
> - whether the specified address is for the root port and use a different base
> - address for it.
> -
> - @param Address The address that encodes the PCI Bus, Device, Function and
> - Register.
> -
> - @return Physical address of the configuration register that corresponds to the
> - PCI configuration register specified by input parameter 'Address'.
> -
> -**/
> -STATIC
> -VOID*
> -GetPciExpressAddress (
> - IN UINTN Address
> - )
> -{
> - UINT8 Bus, Device, Function;
> - UINTN ConfigAddress;
> -
> - Bus = GET_BUS_NUM (Address);
> - Device = GET_DEV_NUM (Address);
> - Function = GET_FUNC_NUM (Address);
> -
> - if ((Bus == 0) && (Device == 0) && (Function == 0)) {
> - ConfigAddress = PcdGet32 (PcdPcieRootPortConfigBaseAddress) + Address;
> - } else {
> - ConfigAddress = PcdGet64 (PcdPciExpressBaseAddress) + Address;
> - if (!IsBdfValid(Address)) {
> - ConfigAddress = (UINTN)&mDummyConfigData;
> - }
> - }
> -
> - return (VOID *)ConfigAddress;
> -}
> -
> -/**
> - Reads an 8-bit PCI configuration register.
> -
> - Reads and returns the 8-bit PCI configuration register specified by Address.
> - This function must guarantee that all PCI read and write operations are
> - serialized.
> -
> - If Address > 0x0FFFFFFF, then ASSERT().
> -
> - @param Address The address that encodes the PCI Bus, Device, Function and
> - Register.
> -
> - @return The read value from the PCI configuration register.
> -
> -**/
> -UINT8
> -EFIAPI
> -PciExpressRead8 (
> - IN UINTN Address
> - )
> -{
> - ASSERT_INVALID_PCI_ADDRESS (Address);
> - return MmioRead8 ((UINTN)GetPciExpressAddress (Address));
> -}
> -
> -/**
> - Writes an 8-bit PCI configuration register.
> -
> - Writes the 8-bit PCI configuration register specified by Address with the
> - value specified by Value. Value is returned. This function must guarantee
> - that all PCI read and write operations are serialized.
> -
> - If Address > 0x0FFFFFFF, then ASSERT().
> -
> - @param Address The address that encodes the PCI Bus, Device, Function and
> - Register.
> - @param Value The value to write.
> -
> - @return The value written to the PCI configuration register.
> -
> -**/
> -UINT8
> -EFIAPI
> -PciExpressWrite8 (
> - IN UINTN Address,
> - IN UINT8 Value
> - )
> -{
> - UINT8 Bus, Device, Function;
> - UINT8 Offset;
> - UINT32 Data;
> -
> - ASSERT_INVALID_PCI_ADDRESS (Address);
> -
> - Bus = GET_BUS_NUM (Address);
> - Device = GET_DEV_NUM (Address);
> - Function = GET_FUNC_NUM (Address);
> -
> - //
> - // 8-bit and 16-bit writes to root port config space is not supported due to
> - // a hardware limitation. As a workaround, perform a read-update-write
> - // sequence on the whole 32-bit word of the root port config register such
> - // that only the specified 8-bits of that word are updated.
> - //
> - if ((Bus == 0) && (Device == 0) && (Function == 0)) {
> - Offset = Address & 0x3;
> - Address &= 0xFFFFFFFC;
> - Data = MmioRead32 ((UINTN)GetPciExpressAddress (Address));
> - Data &= ~(0xFF << (8 * Offset));
> - Data |= (Value << (8 * Offset));
> - MmioWrite32 ((UINTN)GetPciExpressAddress (Address), Data);
> - return Value;
> - }
> -
> - return MmioWrite8 ((UINTN)GetPciExpressAddress (Address), Value);
> -}
> -
> -/**
> - Performs a bitwise OR of an 8-bit PCI configuration register with
> - an 8-bit value.
> -
> - Reads the 8-bit PCI configuration register specified by Address, performs a
> - bitwise OR between the read result and the value specified by
> - OrData, and writes the result to the 8-bit PCI configuration register
> - specified by Address. The value written to the PCI configuration register is
> - returned. This function must guarantee that all PCI read and write operations
> - are serialized.
> -
> - If Address > 0x0FFFFFFF, then ASSERT().
> -
> - @param Address The address that encodes the PCI Bus, Device, Function and
> - Register.
> - @param OrData The value to OR with the PCI configuration register.
> -
> - @return The value written back to the PCI configuration register.
> -
> -**/
> -UINT8
> -EFIAPI
> -PciExpressOr8 (
> - IN UINTN Address,
> - IN UINT8 OrData
> - )
> -{
> - ASSERT_INVALID_PCI_ADDRESS (Address);
> - return MmioOr8 ((UINTN)GetPciExpressAddress (Address), OrData);
> -}
> -
> -/**
> - Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
> - value.
> -
> - Reads the 8-bit PCI configuration register specified by Address, performs a
> - bitwise AND between the read result and the value specified by AndData, and
> - writes the result to the 8-bit PCI configuration register specified by
> - Address. The value written to the PCI configuration register is returned.
> - This function must guarantee that all PCI read and write operations are
> - serialized.
> -
> - If Address > 0x0FFFFFFF, then ASSERT().
> -
> - @param Address The address that encodes the PCI Bus, Device, Function and
> - Register.
> - @param AndData The value to AND with the PCI configuration register.
> -
> - @return The value written back to the PCI configuration register.
> -
> -**/
> -UINT8
> -EFIAPI
> -PciExpressAnd8 (
> - IN UINTN Address,
> - IN UINT8 AndData
> - )
> -{
> - ASSERT_INVALID_PCI_ADDRESS (Address);
> - return MmioAnd8 ((UINTN)GetPciExpressAddress (Address), AndData);
> -}
> -
> -/**
> - Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
> - value, followed a bitwise OR with another 8-bit value.
> -
> - Reads the 8-bit PCI configuration register specified by Address, performs a
> - bitwise AND between the read result and the value specified by AndData,
> - performs a bitwise OR between the result of the AND operation and
> - the value specified by OrData, and writes the result to the 8-bit PCI
> - configuration register specified by Address. The value written to the PCI
> - configuration register is returned. This function must guarantee that all PCI
> - read and write operations are serialized.
> -
> - If Address > 0x0FFFFFFF, then ASSERT().
> -
> - @param Address The address that encodes the PCI Bus, Device, Function and
> - Register.
> - @param AndData The value to AND with the PCI configuration register.
> - @param OrData The value to OR with the result of the AND operation.
> -
> - @return The value written back to the PCI configuration register.
> -
> -**/
> -UINT8
> -EFIAPI
> -PciExpressAndThenOr8 (
> - IN UINTN Address,
> - IN UINT8 AndData,
> - IN UINT8 OrData
> - )
> -{
> - ASSERT_INVALID_PCI_ADDRESS (Address);
> - return MmioAndThenOr8 (
> - (UINTN)GetPciExpressAddress (Address),
> - AndData,
> - OrData
> - );
> -}
> -
> -/**
> - Reads a bit field of a PCI configuration register.
> -
> - Reads the bit field in an 8-bit PCI configuration register. The bit field is
> - specified by the StartBit and the EndBit. The value of the bit field is
> - returned.
> -
> - If Address > 0x0FFFFFFF, then ASSERT().
> - If StartBit is greater than 7, then ASSERT().
> - If EndBit is greater than 7, then ASSERT().
> - If EndBit is less than StartBit, then ASSERT().
> -
> - @param Address The PCI configuration register to read.
> - @param StartBit The ordinal of the least significant bit in the bit field.
> - Range 0..7.
> - @param EndBit The ordinal of the most significant bit in the bit field.
> - Range 0..7.
> -
> - @return The value of the bit field read from the PCI configuration register.
> -
> -**/
> -UINT8
> -EFIAPI
> -PciExpressBitFieldRead8 (
> - IN UINTN Address,
> - IN UINTN StartBit,
> - IN UINTN EndBit
> - )
> -{
> - ASSERT_INVALID_PCI_ADDRESS (Address);
> - return MmioBitFieldRead8 (
> - (UINTN)GetPciExpressAddress (Address),
> - StartBit,
> - EndBit
> - );
> -}
> -
> -/**
> - Writes a bit field to a PCI configuration register.
> -
> - Writes Value to the bit field of the PCI configuration register. The bit
> - field is specified by the StartBit and the EndBit. All other bits in the
> - destination PCI configuration register are preserved. The new value of the
> - 8-bit register is returned.
> -
> - If Address > 0x0FFFFFFF, then ASSERT().
> - If StartBit is greater than 7, then ASSERT().
> - If EndBit is greater than 7, then ASSERT().
> - If EndBit is less than StartBit, then ASSERT().
> - If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
> -
> - @param Address The PCI configuration register to write.
> - @param StartBit The ordinal of the least significant bit in the bit field.
> - Range 0..7.
> - @param EndBit The ordinal of the most significant bit in the bit field.
> - Range 0..7.
> - @param Value The new value of the bit field.
> -
> - @return The value written back to the PCI configuration register.
> -
> -**/
> -UINT8
> -EFIAPI
> -PciExpressBitFieldWrite8 (
> - IN UINTN Address,
> - IN UINTN StartBit,
> - IN UINTN EndBit,
> - IN UINT8 Value
> - )
> -{
> - ASSERT_INVALID_PCI_ADDRESS (Address);
> - return MmioBitFieldWrite8 (
> - (UINTN)GetPciExpressAddress (Address),
> - StartBit,
> - EndBit,
> - Value
> - );
> -}
> -
> -/**
> - Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and
> - writes the result back to the bit field in the 8-bit port.
> -
> - Reads the 8-bit PCI configuration register specified by Address, performs a
> - bitwise OR between the read result and the value specified by
> - OrData, and writes the result to the 8-bit PCI configuration register
> - specified by Address. The value written to the PCI configuration register is
> - returned. This function must guarantee that all PCI read and write operations
> - are serialized. Extra left bits in OrData are stripped.
> -
> - If Address > 0x0FFFFFFF, then ASSERT().
> - If StartBit is greater than 7, then ASSERT().
> - If EndBit is greater than 7, then ASSERT().
> - If EndBit is less than StartBit, then ASSERT().
> - If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
> -
> - @param Address The PCI configuration register to write.
> - @param StartBit The ordinal of the least significant bit in the bit field.
> - Range 0..7.
> - @param EndBit The ordinal of the most significant bit in the bit field.
> - Range 0..7.
> - @param OrData The value to OR with the PCI configuration register.
> -
> - @return The value written back to the PCI configuration register.
> -
> -**/
> -UINT8
> -EFIAPI
> -PciExpressBitFieldOr8 (
> - IN UINTN Address,
> - IN UINTN StartBit,
> - IN UINTN EndBit,
> - IN UINT8 OrData
> - )
> -{
> - ASSERT_INVALID_PCI_ADDRESS (Address);
> - return MmioBitFieldOr8 (
> - (UINTN)GetPciExpressAddress (Address),
> - StartBit,
> - EndBit,
> - OrData
> - );
> -}
> -
> -/**
> - Reads a bit field in an 8-bit PCI configuration register, performs a bitwise
> - AND, and writes the result back to the bit field in the 8-bit register.
> -
> - Reads the 8-bit PCI configuration register specified by Address, performs a
> - bitwise AND between the read result and the value specified by AndData, and
> - writes the result to the 8-bit PCI configuration register specified by
> - Address. The value written to the PCI configuration register is returned.
> - This function must guarantee that all PCI read and write operations are
> - serialized. Extra left bits in AndData are stripped.
> -
> - If Address > 0x0FFFFFFF, then ASSERT().
> - If StartBit is greater than 7, then ASSERT().
> - If EndBit is greater than 7, then ASSERT().
> - If EndBit is less than StartBit, then ASSERT().
> - If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
> -
> - @param Address The PCI configuration register to write.
> - @param StartBit The ordinal of the least significant bit in the bit field.
> - Range 0..7.
> - @param EndBit The ordinal of the most significant bit in the bit field.
> - Range 0..7.
> - @param AndData The value to AND with the PCI configuration register.
> -
> - @return The value written back to the PCI configuration register.
> -
> -**/
> -UINT8
> -EFIAPI
> -PciExpressBitFieldAnd8 (
> - IN UINTN Address,
> - IN UINTN StartBit,
> - IN UINTN EndBit,
> - IN UINT8 AndData
> - )
> -{
> - ASSERT_INVALID_PCI_ADDRESS (Address);
> - return MmioBitFieldAnd8 (
> - (UINTN)GetPciExpressAddress (Address),
> - StartBit,
> - EndBit,
> - AndData
> - );
> -}
> -
> -/**
> - Reads a bit field in an 8-bit port, performs a bitwise AND followed by a
> - bitwise OR, and writes the result back to the bit field in the
> - 8-bit port.
> -
> - Reads the 8-bit PCI configuration register specified by Address, performs a
> - bitwise AND followed by a bitwise OR between the read result and
> - the value specified by AndData, and writes the result to the 8-bit PCI
> - configuration register specified by Address. The value written to the PCI
> - configuration register is returned. This function must guarantee that all PCI
> - read and write operations are serialized. Extra left bits in both AndData and
> - OrData are stripped.
> -
> - If Address > 0x0FFFFFFF, then ASSERT().
> - If StartBit is greater than 7, then ASSERT().
> - If EndBit is greater than 7, then ASSERT().
> - If EndBit is less than StartBit, then ASSERT().
> - If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
> - If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
> -
> - @param Address The PCI configuration register to write.
> - @param StartBit The ordinal of the least significant bit in the bit field.
> - Range 0..7.
> - @param EndBit The ordinal of the most significant bit in the bit field.
> - Range 0..7.
> - @param AndData The value to AND with the PCI configuration register.
> - @param OrData The value to OR with the result of the AND operation.
> -
> - @return The value written back to the PCI configuration register.
> -
> -**/
> -UINT8
> -EFIAPI
> -PciExpressBitFieldAndThenOr8 (
> - IN UINTN Address,
> - IN UINTN StartBit,
> - IN UINTN EndBit,
> - IN UINT8 AndData,
> - IN UINT8 OrData
> - )
> -{
> - ASSERT_INVALID_PCI_ADDRESS (Address);
> - return MmioBitFieldAndThenOr8 (
> - (UINTN)GetPciExpressAddress (Address),
> - StartBit,
> - EndBit,
> - AndData,
> - OrData
> - );
> -}
> -
> -/**
> - Reads a 16-bit PCI configuration register.
> -
> - Reads and returns the 16-bit PCI configuration register specified by Address.
> - This function must guarantee that all PCI read and write operations are
> - serialized.
> -
> - If Address > 0x0FFFFFFF, then ASSERT().
> - If Address is not aligned on a 16-bit boundary, then ASSERT().
> -
> - @param Address The address that encodes the PCI Bus, Device, Function and
> - Register.
> -
> - @return The read value from the PCI configuration register.
> -
> -**/
> -UINT16
> -EFIAPI
> -PciExpressRead16 (
> - IN UINTN Address
> - )
> -{
> - ASSERT_INVALID_PCI_ADDRESS (Address);
> - return MmioRead16 ((UINTN)GetPciExpressAddress (Address));
> -}
> -
> -/**
> - Writes a 16-bit PCI configuration register.
> -
> - Writes the 16-bit PCI configuration register specified by Address with the
> - value specified by Value. Value is returned. This function must guarantee
> - that all PCI read and write operations are serialized.
> -
> - If Address > 0x0FFFFFFF, then ASSERT().
> - If Address is not aligned on a 16-bit boundary, then ASSERT().
> -
> - @param Address The address that encodes the PCI Bus, Device, Function and
> - Register.
> - @param Value The value to write.
> -
> - @return The value written to the PCI configuration register.
> -
> -**/
> -UINT16
> -EFIAPI
> -PciExpressWrite16 (
> - IN UINTN Address,
> - IN UINT16 Value
> - )
> -{
> - UINT8 Bus, Device, Function;
> - UINT8 Offset;
> - UINT32 Data;
> -
> - ASSERT_INVALID_PCI_ADDRESS (Address);
> -
> - Bus = GET_BUS_NUM (Address);
> - Device = GET_DEV_NUM (Address);
> - Function = GET_FUNC_NUM (Address);
> -
> - //
> - // 8-bit and 16-bit writes to root port config space is not supported due to
> - // a hardware limitation. As a workaround, perform a read-update-write
> - // sequence on the whole 32-bit word of the root port config register such
> - // that only the specified 16-bits of that word are updated.
> - //
> - if ((Bus == 0) && (Device == 0) && (Function == 0)) {
> - Offset = Address & 0x3;
> - Address &= 0xFFFFFFFC;
> - Data = MmioRead32 ((UINTN)GetPciExpressAddress (Address));
> - Data &= ~(0xFFFF << (8 * Offset));
> - Data |= (Value << (8 * Offset));
> - MmioWrite32 ((UINTN)GetPciExpressAddress (Address), Data);
> - return Value;
> - }
> -
> - return MmioWrite16 ((UINTN)GetPciExpressAddress (Address), Value);
> -}
> -
> -/**
> - Performs a bitwise OR of a 16-bit PCI configuration register with
> - a 16-bit value.
> -
> - Reads the 16-bit PCI configuration register specified by Address, performs a
> - bitwise OR between the read result and the value specified by
> - OrData, and writes the result to the 16-bit PCI configuration register
> - specified by Address. The value written to the PCI configuration register is
> - returned. This function must guarantee that all PCI read and write operations
> - are serialized.
> -
> - If Address > 0x0FFFFFFF, then ASSERT().
> - If Address is not aligned on a 16-bit boundary, then ASSERT().
> -
> - @param Address The address that encodes the PCI Bus, Device, Function and
> - Register.
> - @param OrData The value to OR with the PCI configuration register.
> -
> - @return The value written back to the PCI configuration register.
> -
> -**/
> -UINT16
> -EFIAPI
> -PciExpressOr16 (
> - IN UINTN Address,
> - IN UINT16 OrData
> - )
> -{
> - ASSERT_INVALID_PCI_ADDRESS (Address);
> - return MmioOr16 ((UINTN)GetPciExpressAddress (Address), OrData);
> -}
> -
> -/**
> - Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
> - value.
> -
> - Reads the 16-bit PCI configuration register specified by Address, performs a
> - bitwise AND between the read result and the value specified by AndData, and
> - writes the result to the 16-bit PCI configuration register specified by
> - Address. The value written to the PCI configuration register is returned.
> - This function must guarantee that all PCI read and write operations are
> - serialized.
> -
> - If Address > 0x0FFFFFFF, then ASSERT().
> - If Address is not aligned on a 16-bit boundary, then ASSERT().
> -
> - @param Address The address that encodes the PCI Bus, Device, Function and
> - Register.
> - @param AndData The value to AND with the PCI configuration register.
> -
> - @return The value written back to the PCI configuration register.
> -
> -**/
> -UINT16
> -EFIAPI
> -PciExpressAnd16 (
> - IN UINTN Address,
> - IN UINT16 AndData
> - )
> -{
> - ASSERT_INVALID_PCI_ADDRESS (Address);
> - return MmioAnd16 ((UINTN)GetPciExpressAddress (Address), AndData);
> -}
> -
> -/**
> - Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
> - value, followed a bitwise OR with another 16-bit value.
> -
> - Reads the 16-bit PCI configuration register specified by Address, performs a
> - bitwise AND between the read result and the value specified by AndData,
> - performs a bitwise OR between the result of the AND operation and
> - the value specified by OrData, and writes the result to the 16-bit PCI
> - configuration register specified by Address. The value written to the PCI
> - configuration register is returned. This function must guarantee that all PCI
> - read and write operations are serialized.
> -
> - If Address > 0x0FFFFFFF, then ASSERT().
> - If Address is not aligned on a 16-bit boundary, then ASSERT().
> -
> - @param Address The address that encodes the PCI Bus, Device, Function and
> - Register.
> - @param AndData The value to AND with the PCI configuration register.
> - @param OrData The value to OR with the result of the AND operation.
> -
> - @return The value written back to the PCI configuration register.
> -
> -**/
> -UINT16
> -EFIAPI
> -PciExpressAndThenOr16 (
> - IN UINTN Address,
> - IN UINT16 AndData,
> - IN UINT16 OrData
> - )
> -{
> - ASSERT_INVALID_PCI_ADDRESS (Address);
> - return MmioAndThenOr16 (
> - (UINTN)GetPciExpressAddress (Address),
> - AndData,
> - OrData
> - );
> -}
> -
> -/**
> - Reads a bit field of a PCI configuration register.
> -
> - Reads the bit field in a 16-bit PCI configuration register. The bit field is
> - specified by the StartBit and the EndBit. The value of the bit field is
> - returned.
> -
> - If Address > 0x0FFFFFFF, then ASSERT().
> - If Address is not aligned on a 16-bit boundary, then ASSERT().
> - If StartBit is greater than 15, then ASSERT().
> - If EndBit is greater than 15, then ASSERT().
> - If EndBit is less than StartBit, then ASSERT().
> -
> - @param Address The PCI configuration register to read.
> - @param StartBit The ordinal of the least significant bit in the bit field.
> - Range 0..15.
> - @param EndBit The ordinal of the most significant bit in the bit field.
> - Range 0..15.
> -
> - @return The value of the bit field read from the PCI configuration register.
> -
> -**/
> -UINT16
> -EFIAPI
> -PciExpressBitFieldRead16 (
> - IN UINTN Address,
> - IN UINTN StartBit,
> - IN UINTN EndBit
> - )
> -{
> - ASSERT_INVALID_PCI_ADDRESS (Address);
> - return MmioBitFieldRead16 (
> - (UINTN)GetPciExpressAddress (Address),
> - StartBit,
> - EndBit
> - );
> -}
> -
> -/**
> - Writes a bit field to a PCI configuration register.
> -
> - Writes Value to the bit field of the PCI configuration register. The bit
> - field is specified by the StartBit and the EndBit. All other bits in the
> - destination PCI configuration register are preserved. The new value of the
> - 16-bit register is returned.
> -
> - If Address > 0x0FFFFFFF, then ASSERT().
> - If Address is not aligned on a 16-bit boundary, then ASSERT().
> - If StartBit is greater than 15, then ASSERT().
> - If EndBit is greater than 15, then ASSERT().
> - If EndBit is less than StartBit, then ASSERT().
> - If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
> -
> - @param Address The PCI configuration register to write.
> - @param StartBit The ordinal of the least significant bit in the bit field.
> - Range 0..15.
> - @param EndBit The ordinal of the most significant bit in the bit field.
> - Range 0..15.
> - @param Value The new value of the bit field.
> -
> - @return The value written back to the PCI configuration register.
> -
> -**/
> -UINT16
> -EFIAPI
> -PciExpressBitFieldWrite16 (
> - IN UINTN Address,
> - IN UINTN StartBit,
> - IN UINTN EndBit,
> - IN UINT16 Value
> - )
> -{
> - ASSERT_INVALID_PCI_ADDRESS (Address);
> - return MmioBitFieldWrite16 (
> - (UINTN)GetPciExpressAddress (Address),
> - StartBit,
> - EndBit,
> - Value
> - );
> -}
> -
> -/**
> - Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and
> - writes the result back to the bit field in the 16-bit port.
> -
> - Reads the 16-bit PCI configuration register specified by Address, performs a
> - bitwise OR between the read result and the value specified by
> - OrData, and writes the result to the 16-bit PCI configuration register
> - specified by Address. The value written to the PCI configuration register is
> - returned. This function must guarantee that all PCI read and write operations
> - are serialized. Extra left bits in OrData are stripped.
> -
> - If Address > 0x0FFFFFFF, then ASSERT().
> - If Address is not aligned on a 16-bit boundary, then ASSERT().
> - If StartBit is greater than 15, then ASSERT().
> - If EndBit is greater than 15, then ASSERT().
> - If EndBit is less than StartBit, then ASSERT().
> - If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
> -
> - @param Address The PCI configuration register to write.
> - @param StartBit The ordinal of the least significant bit in the bit field.
> - Range 0..15.
> - @param EndBit The ordinal of the most significant bit in the bit field.
> - Range 0..15.
> - @param OrData The value to OR with the PCI configuration register.
> -
> - @return The value written back to the PCI configuration register.
> -
> -**/
> -UINT16
> -EFIAPI
> -PciExpressBitFieldOr16 (
> - IN UINTN Address,
> - IN UINTN StartBit,
> - IN UINTN EndBit,
> - IN UINT16 OrData
> - )
> -{
> - ASSERT_INVALID_PCI_ADDRESS (Address);
> - return MmioBitFieldOr16 (
> - (UINTN)GetPciExpressAddress (Address),
> - StartBit,
> - EndBit,
> - OrData
> - );
> -}
> -
> -/**
> - Reads a bit field in a 16-bit PCI configuration register, performs a bitwise
> - AND, and writes the result back to the bit field in the 16-bit register.
> -
> - Reads the 16-bit PCI configuration register specified by Address, performs a
> - bitwise AND between the read result and the value specified by AndData, and
> - writes the result to the 16-bit PCI configuration register specified by
> - Address. The value written to the PCI configuration register is returned.
> - This function must guarantee that all PCI read and write operations are
> - serialized. Extra left bits in AndData are stripped.
> -
> - If Address > 0x0FFFFFFF, then ASSERT().
> - If Address is not aligned on a 16-bit boundary, then ASSERT().
> - If StartBit is greater than 15, then ASSERT().
> - If EndBit is greater than 15, then ASSERT().
> - If EndBit is less than StartBit, then ASSERT().
> - If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
> -
> - @param Address The PCI configuration register to write.
> - @param StartBit The ordinal of the least significant bit in the bit field.
> - Range 0..15.
> - @param EndBit The ordinal of the most significant bit in the bit field.
> - Range 0..15.
> - @param AndData The value to AND with the PCI configuration register.
> -
> - @return The value written back to the PCI configuration register.
> -
> -**/
> -UINT16
> -EFIAPI
> -PciExpressBitFieldAnd16 (
> - IN UINTN Address,
> - IN UINTN StartBit,
> - IN UINTN EndBit,
> - IN UINT16 AndData
> - )
> -{
> - ASSERT_INVALID_PCI_ADDRESS (Address);
> - return MmioBitFieldAnd16 (
> - (UINTN)GetPciExpressAddress (Address),
> - StartBit,
> - EndBit,
> - AndData
> - );
> -}
> -
> -/**
> - Reads a bit field in a 16-bit port, performs a bitwise AND followed by a
> - bitwise OR, and writes the result back to the bit field in the
> - 16-bit port.
> -
> - Reads the 16-bit PCI configuration register specified by Address, performs a
> - bitwise AND followed by a bitwise OR between the read result and
> - the value specified by AndData, and writes the result to the 16-bit PCI
> - configuration register specified by Address. The value written to the PCI
> - configuration register is returned. This function must guarantee that all PCI
> - read and write operations are serialized. Extra left bits in both AndData and
> - OrData are stripped.
> -
> - If Address > 0x0FFFFFFF, then ASSERT().
> - If Address is not aligned on a 16-bit boundary, then ASSERT().
> - If StartBit is greater than 15, then ASSERT().
> - If EndBit is greater than 15, then ASSERT().
> - If EndBit is less than StartBit, then ASSERT().
> - If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
> - If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
> -
> - @param Address The PCI configuration register to write.
> - @param StartBit The ordinal of the least significant bit in the bit field.
> - Range 0..15.
> - @param EndBit The ordinal of the most significant bit in the bit field.
> - Range 0..15.
> - @param AndData The value to AND with the PCI configuration register.
> - @param OrData The value to OR with the result of the AND operation.
> -
> - @return The value written back to the PCI configuration register.
> -
> -**/
> -UINT16
> -EFIAPI
> -PciExpressBitFieldAndThenOr16 (
> - IN UINTN Address,
> - IN UINTN StartBit,
> - IN UINTN EndBit,
> - IN UINT16 AndData,
> - IN UINT16 OrData
> - )
> -{
> - ASSERT_INVALID_PCI_ADDRESS (Address);
> - return MmioBitFieldAndThenOr16 (
> - (UINTN)GetPciExpressAddress (Address),
> - StartBit,
> - EndBit,
> - AndData,
> - OrData
> - );
> -}
> -
> -/**
> - Reads a 32-bit PCI configuration register.
> -
> - Reads and returns the 32-bit PCI configuration register specified by Address.
> - This function must guarantee that all PCI read and write operations are
> - serialized.
> -
> - If Address > 0x0FFFFFFF, then ASSERT().
> - If Address is not aligned on a 32-bit boundary, then ASSERT().
> -
> - @param Address The address that encodes the PCI Bus, Device, Function and
> - Register.
> -
> - @return The read value from the PCI configuration register.
> -
> -**/
> -UINT32
> -EFIAPI
> -PciExpressRead32 (
> - IN UINTN Address
> - )
> -{
> - ASSERT_INVALID_PCI_ADDRESS (Address);
> - return MmioRead32 ((UINTN)GetPciExpressAddress (Address));
> -}
> -
> -/**
> - Writes a 32-bit PCI configuration register.
> -
> - Writes the 32-bit PCI configuration register specified by Address with the
> - value specified by Value. Value is returned. This function must guarantee
> - that all PCI read and write operations are serialized.
> -
> - If Address > 0x0FFFFFFF, then ASSERT().
> - If Address is not aligned on a 32-bit boundary, then ASSERT().
> -
> - @param Address The address that encodes the PCI Bus, Device, Function and
> - Register.
> - @param Value The value to write.
> -
> - @return The value written to the PCI configuration register.
> -
> -**/
> -UINT32
> -EFIAPI
> -PciExpressWrite32 (
> - IN UINTN Address,
> - IN UINT32 Value
> - )
> -{
> - ASSERT_INVALID_PCI_ADDRESS (Address);
> - return MmioWrite32 ((UINTN)GetPciExpressAddress (Address), Value);
> -}
> -
> -/**
> - Performs a bitwise OR of a 32-bit PCI configuration register with
> - a 32-bit value.
> -
> - Reads the 32-bit PCI configuration register specified by Address, performs a
> - bitwise OR between the read result and the value specified by
> - OrData, and writes the result to the 32-bit PCI configuration register
> - specified by Address. The value written to the PCI configuration register is
> - returned. This function must guarantee that all PCI read and write operations
> - are serialized.
> -
> - If Address > 0x0FFFFFFF, then ASSERT().
> - If Address is not aligned on a 32-bit boundary, then ASSERT().
> -
> - @param Address The address that encodes the PCI Bus, Device, Function and
> - Register.
> - @param OrData The value to OR with the PCI configuration register.
> -
> - @return The value written back to the PCI configuration register.
> -
> -**/
> -UINT32
> -EFIAPI
> -PciExpressOr32 (
> - IN UINTN Address,
> - IN UINT32 OrData
> - )
> -{
> - ASSERT_INVALID_PCI_ADDRESS (Address);
> - return MmioOr32 ((UINTN)GetPciExpressAddress (Address), OrData);
> -}
> -
> -/**
> - Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
> - value.
> -
> - Reads the 32-bit PCI configuration register specified by Address, performs a
> - bitwise AND between the read result and the value specified by AndData, and
> - writes the result to the 32-bit PCI configuration register specified by
> - Address. The value written to the PCI configuration register is returned.
> - This function must guarantee that all PCI read and write operations are
> - serialized.
> -
> - If Address > 0x0FFFFFFF, then ASSERT().
> - If Address is not aligned on a 32-bit boundary, then ASSERT().
> -
> - @param Address The address that encodes the PCI Bus, Device, Function and
> - Register.
> - @param AndData The value to AND with the PCI configuration register.
> -
> - @return The value written back to the PCI configuration register.
> -
> -**/
> -UINT32
> -EFIAPI
> -PciExpressAnd32 (
> - IN UINTN Address,
> - IN UINT32 AndData
> - )
> -{
> - ASSERT_INVALID_PCI_ADDRESS (Address);
> - return MmioAnd32 ((UINTN)GetPciExpressAddress (Address), AndData);
> -}
> -
> -/**
> - Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
> - value, followed a bitwise OR with another 32-bit value.
> -
> - Reads the 32-bit PCI configuration register specified by Address, performs a
> - bitwise AND between the read result and the value specified by AndData,
> - performs a bitwise OR between the result of the AND operation and
> - the value specified by OrData, and writes the result to the 32-bit PCI
> - configuration register specified by Address. The value written to the PCI
> - configuration register is returned. This function must guarantee that all PCI
> - read and write operations are serialized.
> -
> - If Address > 0x0FFFFFFF, then ASSERT().
> - If Address is not aligned on a 32-bit boundary, then ASSERT().
> -
> - @param Address The address that encodes the PCI Bus, Device, Function and
> - Register.
> - @param AndData The value to AND with the PCI configuration register.
> - @param OrData The value to OR with the result of the AND operation.
> -
> - @return The value written back to the PCI configuration register.
> -
> -**/
> -UINT32
> -EFIAPI
> -PciExpressAndThenOr32 (
> - IN UINTN Address,
> - IN UINT32 AndData,
> - IN UINT32 OrData
> - )
> -{
> - ASSERT_INVALID_PCI_ADDRESS (Address);
> - return MmioAndThenOr32 (
> - (UINTN)GetPciExpressAddress (Address),
> - AndData,
> - OrData
> - );
> -}
> -
> -/**
> - Reads a bit field of a PCI configuration register.
> -
> - Reads the bit field in a 32-bit PCI configuration register. The bit field is
> - specified by the StartBit and the EndBit. The value of the bit field is
> - returned.
> -
> - If Address > 0x0FFFFFFF, then ASSERT().
> - If Address is not aligned on a 32-bit boundary, then ASSERT().
> - If StartBit is greater than 31, then ASSERT().
> - If EndBit is greater than 31, then ASSERT().
> - If EndBit is less than StartBit, then ASSERT().
> -
> - @param Address The PCI configuration register to read.
> - @param StartBit The ordinal of the least significant bit in the bit field.
> - Range 0..31.
> - @param EndBit The ordinal of the most significant bit in the bit field.
> - Range 0..31.
> -
> - @return The value of the bit field read from the PCI configuration register.
> -
> -**/
> -UINT32
> -EFIAPI
> -PciExpressBitFieldRead32 (
> - IN UINTN Address,
> - IN UINTN StartBit,
> - IN UINTN EndBit
> - )
> -{
> - ASSERT_INVALID_PCI_ADDRESS (Address);
> - return MmioBitFieldRead32 (
> - (UINTN)GetPciExpressAddress (Address),
> - StartBit,
> - EndBit
> - );
> -}
> -
> -/**
> - Writes a bit field to a PCI configuration register.
> -
> - Writes Value to the bit field of the PCI configuration register. The bit
> - field is specified by the StartBit and the EndBit. All other bits in the
> - destination PCI configuration register are preserved. The new value of the
> - 32-bit register is returned.
> -
> - If Address > 0x0FFFFFFF, then ASSERT().
> - If Address is not aligned on a 32-bit boundary, then ASSERT().
> - If StartBit is greater than 31, then ASSERT().
> - If EndBit is greater than 31, then ASSERT().
> - If EndBit is less than StartBit, then ASSERT().
> - If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
> -
> - @param Address The PCI configuration register to write.
> - @param StartBit The ordinal of the least significant bit in the bit field.
> - Range 0..31.
> - @param EndBit The ordinal of the most significant bit in the bit field.
> - Range 0..31.
> - @param Value The new value of the bit field.
> -
> - @return The value written back to the PCI configuration register.
> -
> -**/
> -UINT32
> -EFIAPI
> -PciExpressBitFieldWrite32 (
> - IN UINTN Address,
> - IN UINTN StartBit,
> - IN UINTN EndBit,
> - IN UINT32 Value
> - )
> -{
> - ASSERT_INVALID_PCI_ADDRESS (Address);
> - return MmioBitFieldWrite32 (
> - (UINTN)GetPciExpressAddress (Address),
> - StartBit,
> - EndBit,
> - Value
> - );
> -}
> -
> -/**
> - Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and
> - writes the result back to the bit field in the 32-bit port.
> -
> - Reads the 32-bit PCI configuration register specified by Address, performs a
> - bitwise OR between the read result and the value specified by
> - OrData, and writes the result to the 32-bit PCI configuration register
> - specified by Address. The value written to the PCI configuration register is
> - returned. This function must guarantee that all PCI read and write operations
> - are serialized. Extra left bits in OrData are stripped.
> -
> - If Address > 0x0FFFFFFF, then ASSERT().
> - If Address is not aligned on a 32-bit boundary, then ASSERT().
> - If StartBit is greater than 31, then ASSERT().
> - If EndBit is greater than 31, then ASSERT().
> - If EndBit is less than StartBit, then ASSERT().
> - If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
> -
> - @param Address The PCI configuration register to write.
> - @param StartBit The ordinal of the least significant bit in the bit field.
> - Range 0..31.
> - @param EndBit The ordinal of the most significant bit in the bit field.
> - Range 0..31.
> - @param OrData The value to OR with the PCI configuration register.
> -
> - @return The value written back to the PCI configuration register.
> -
> -**/
> -UINT32
> -EFIAPI
> -PciExpressBitFieldOr32 (
> - IN UINTN Address,
> - IN UINTN StartBit,
> - IN UINTN EndBit,
> - IN UINT32 OrData
> - )
> -{
> - ASSERT_INVALID_PCI_ADDRESS (Address);
> - return MmioBitFieldOr32 (
> - (UINTN)GetPciExpressAddress (Address),
> - StartBit,
> - EndBit,
> - OrData
> - );
> -}
> -
> -/**
> - Reads a bit field in a 32-bit PCI configuration register, performs a bitwise
> - AND, and writes the result back to the bit field in the 32-bit register.
> -
> - Reads the 32-bit PCI configuration register specified by Address, performs a
> - bitwise AND between the read result and the value specified by AndData, and
> - writes the result to the 32-bit PCI configuration register specified by
> - Address. The value written to the PCI configuration register is returned.
> - This function must guarantee that all PCI read and write operations are
> - serialized. Extra left bits in AndData are stripped.
> -
> - If Address > 0x0FFFFFFF, then ASSERT().
> - If Address is not aligned on a 32-bit boundary, then ASSERT().
> - If StartBit is greater than 31, then ASSERT().
> - If EndBit is greater than 31, then ASSERT().
> - If EndBit is less than StartBit, then ASSERT().
> - If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
> -
> - @param Address The PCI configuration register to write.
> - @param StartBit The ordinal of the least significant bit in the bit field.
> - Range 0..31.
> - @param EndBit The ordinal of the most significant bit in the bit field.
> - Range 0..31.
> - @param AndData The value to AND with the PCI configuration register.
> -
> - @return The value written back to the PCI configuration register.
> -
> -**/
> -UINT32
> -EFIAPI
> -PciExpressBitFieldAnd32 (
> - IN UINTN Address,
> - IN UINTN StartBit,
> - IN UINTN EndBit,
> - IN UINT32 AndData
> - )
> -{
> - ASSERT_INVALID_PCI_ADDRESS (Address);
> - return MmioBitFieldAnd32 (
> - (UINTN)GetPciExpressAddress (Address),
> - StartBit,
> - EndBit,
> - AndData
> - );
> -}
> -
> -/**
> - Reads a bit field in a 32-bit port, performs a bitwise AND followed by a
> - bitwise OR, and writes the result back to the bit field in the
> - 32-bit port.
> -
> - Reads the 32-bit PCI configuration register specified by Address, performs a
> - bitwise AND followed by a bitwise OR between the read result and
> - the value specified by AndData, and writes the result to the 32-bit PCI
> - configuration register specified by Address. The value written to the PCI
> - configuration register is returned. This function must guarantee that all PCI
> - read and write operations are serialized. Extra left bits in both AndData and
> - OrData are stripped.
> -
> - If Address > 0x0FFFFFFF, then ASSERT().
> - If Address is not aligned on a 32-bit boundary, then ASSERT().
> - If StartBit is greater than 31, then ASSERT().
> - If EndBit is greater than 31, then ASSERT().
> - If EndBit is less than StartBit, then ASSERT().
> - If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
> - If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
> -
> - @param Address The PCI configuration register to write.
> - @param StartBit The ordinal of the least significant bit in the bit field.
> - Range 0..31.
> - @param EndBit The ordinal of the most significant bit in the bit field.
> - Range 0..31.
> - @param AndData The value to AND with the PCI configuration register.
> - @param OrData The value to OR with the result of the AND operation.
> -
> - @return The value written back to the PCI configuration register.
> -
> -**/
> -UINT32
> -EFIAPI
> -PciExpressBitFieldAndThenOr32 (
> - IN UINTN Address,
> - IN UINTN StartBit,
> - IN UINTN EndBit,
> - IN UINT32 AndData,
> - IN UINT32 OrData
> - )
> -{
> - ASSERT_INVALID_PCI_ADDRESS (Address);
> - return MmioBitFieldAndThenOr32 (
> - (UINTN)GetPciExpressAddress (Address),
> - StartBit,
> - EndBit,
> - AndData,
> - OrData
> - );
> -}
> -
> -/**
> - Reads a range of PCI configuration registers into a caller supplied buffer.
> -
> - Reads the range of PCI configuration registers specified by StartAddress and
> - Size into the buffer specified by Buffer. This function only allows the PCI
> - configuration registers from a single PCI function to be read. Size is
> - returned. When possible 32-bit PCI configuration read cycles are used to read
> - from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit
> - and 16-bit PCI configuration read cycles may be used at the beginning and the
> - end of the range.
> -
> - If StartAddress > 0x0FFFFFFF, then ASSERT().
> - If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
> - If Size > 0 and Buffer is NULL, then ASSERT().
> -
> - @param StartAddress The starting address that encodes the PCI Bus, Device,
> - Function and Register.
> - @param Size The size in bytes of the transfer.
> - @param Buffer The pointer to a buffer receiving the data read.
> -
> - @return Size read data from StartAddress.
> -
> -**/
> -UINTN
> -EFIAPI
> -PciExpressReadBuffer (
> - IN UINTN StartAddress,
> - IN UINTN Size,
> - OUT VOID *Buffer
> - )
> -{
> - UINTN ReturnValue;
> -
> - ASSERT_INVALID_PCI_ADDRESS (StartAddress);
> - ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);
> -
> - if (Size == 0) {
> - return Size;
> - }
> -
> - ASSERT (Buffer != NULL);
> -
> - //
> - // Save Size for return
> - //
> - ReturnValue = Size;
> -
> - if ((StartAddress & 1) != 0) {
> - //
> - // Read a byte if StartAddress is byte aligned
> - //
> - *(volatile UINT8 *)Buffer = PciExpressRead8 (StartAddress);
> - StartAddress += sizeof (UINT8);
> - Size -= sizeof (UINT8);
> - Buffer = (UINT8*)Buffer + 1;
> - }
> -
> - if (Size >= sizeof (UINT16) && (StartAddress & 2) != 0) {
> - //
> - // Read a word if StartAddress is word aligned
> - //
> - WriteUnaligned16 ((UINT16 *) Buffer, (UINT16) PciExpressRead16 (StartAddress));
> -
> - StartAddress += sizeof (UINT16);
> - Size -= sizeof (UINT16);
> - Buffer = (UINT16*)Buffer + 1;
> - }
> -
> - while (Size >= sizeof (UINT32)) {
> - //
> - // Read as many double words as possible
> - //
> - WriteUnaligned32 ((UINT32 *) Buffer, (UINT32) PciExpressRead32 (StartAddress));
> -
> - StartAddress += sizeof (UINT32);
> - Size -= sizeof (UINT32);
> - Buffer = (UINT32*)Buffer + 1;
> - }
> -
> - if (Size >= sizeof (UINT16)) {
> - //
> - // Read the last remaining word if exist
> - //
> - WriteUnaligned16 ((UINT16 *) Buffer, (UINT16) PciExpressRead16 (StartAddress));
> - StartAddress += sizeof (UINT16);
> - Size -= sizeof (UINT16);
> - Buffer = (UINT16*)Buffer + 1;
> - }
> -
> - if (Size >= sizeof (UINT8)) {
> - //
> - // Read the last remaining byte if exist
> - //
> - *(volatile UINT8 *)Buffer = PciExpressRead8 (StartAddress);
> - }
> -
> - return ReturnValue;
> -}
> -
> -/**
> - Copies the data in a caller supplied buffer to a specified range of PCI
> - configuration space.
> -
> - Writes the range of PCI configuration registers specified by StartAddress and
> - Size from the buffer specified by Buffer. This function only allows the PCI
> - configuration registers from a single PCI function to be written. Size is
> - returned. When possible 32-bit PCI configuration write cycles are used to
> - write from StartAdress to StartAddress + Size. Due to alignment restrictions,
> - 8-bit and 16-bit PCI configuration write cycles may be used at the beginning
> - and the end of the range.
> -
> - If StartAddress > 0x0FFFFFFF, then ASSERT().
> - If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
> - If Size > 0 and Buffer is NULL, then ASSERT().
> -
> - @param StartAddress The starting address that encodes the PCI Bus, Device,
> - Function and Register.
> - @param Size The size in bytes of the transfer.
> - @param Buffer The pointer to a buffer containing the data to write.
> -
> - @return Size written to StartAddress.
> -
> -**/
> -UINTN
> -EFIAPI
> -PciExpressWriteBuffer (
> - IN UINTN StartAddress,
> - IN UINTN Size,
> - IN VOID *Buffer
> - )
> -{
> - UINTN ReturnValue;
> -
> - ASSERT_INVALID_PCI_ADDRESS (StartAddress);
> - ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);
> -
> - if (Size == 0) {
> - return 0;
> - }
> -
> - ASSERT (Buffer != NULL);
> -
> - //
> - // Save Size for return
> - //
> - ReturnValue = Size;
> -
> - if ((StartAddress & 1) != 0) {
> - //
> - // Write a byte if StartAddress is byte aligned
> - //
> - PciExpressWrite8 (StartAddress, *(UINT8*)Buffer);
> - StartAddress += sizeof (UINT8);
> - Size -= sizeof (UINT8);
> - Buffer = (UINT8*)Buffer + 1;
> - }
> -
> - if (Size >= sizeof (UINT16) && (StartAddress & 2) != 0) {
> - //
> - // Write a word if StartAddress is word aligned
> - //
> - PciExpressWrite16 (StartAddress, ReadUnaligned16 ((UINT16*)Buffer));
> - StartAddress += sizeof (UINT16);
> - Size -= sizeof (UINT16);
> - Buffer = (UINT16*)Buffer + 1;
> - }
> -
> - while (Size >= sizeof (UINT32)) {
> - //
> - // Write as many double words as possible
> - //
> - PciExpressWrite32 (StartAddress, ReadUnaligned32 ((UINT32*)Buffer));
> - StartAddress += sizeof (UINT32);
> - Size -= sizeof (UINT32);
> - Buffer = (UINT32*)Buffer + 1;
> - }
> -
> - if (Size >= sizeof (UINT16)) {
> - //
> - // Write the last remaining word if exist
> - //
> - PciExpressWrite16 (StartAddress, ReadUnaligned16 ((UINT16*)Buffer));
> - StartAddress += sizeof (UINT16);
> - Size -= sizeof (UINT16);
> - Buffer = (UINT16*)Buffer + 1;
> - }
> -
> - if (Size >= sizeof (UINT8)) {
> - //
> - // Write the last remaining byte if exist
> - //
> - PciExpressWrite8 (StartAddress, *(UINT8*)Buffer);
> - }
> -
> - return ReturnValue;
> -}
> diff --git a/Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciExpressLib/PciExpressLib.inf b/Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciExpressLib/PciExpressLib.inf
> deleted file mode 100644
> index acb6fb6219..0000000000
> --- a/Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciExpressLib/PciExpressLib.inf
> +++ /dev/null
> @@ -1,56 +0,0 @@
> -## @file
> -# Instance of PCI Express Library using the 256 MB PCI Express MMIO window.
> -#
> -# PCI Express Library that uses the 256 MB PCI Express MMIO window to perform
> -# PCI Configuration cycles. Layers on top of an I/O Library instance.
> -#
> -# Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.
> -#
> -# This library is inherited from MdePkg/Library/BasePciExpressLib. On
> -# NeoverseN1 SoC, with the unmodified version of this library, a slave error is
> -# generated when host accesses the config space of a non-available device or
> -# unimplemented function on a given bus. In order to resolve this for
> -# NeoverseN1 SoC, a modified version of the MdePkg/Library/BasePciExpressLib
> -# library is used. The modification includes a check to determine whether the
> -# incoming PCI address can be safely accessed.
> -#
> -# In addition to this, the NeoverseN1 SoC has two other limitations which
> -# affect the access to the PCIe root port:
> -# 1. ECAM space is not contiguous, root port ECAM (BDF = 0:0:0) is isolated
> -# from rest of the downstream hierarchy ECAM space.
> -# 2. Root port ECAM space is not capable of 8bit/16bit writes.
> -# This library includes workaround for these limitations as well.
> -#
> -# Copyright (c) 2020, ARM Limited. All rights reserved.
> -#
> -# SPDX-License-Identifier: BSD-2-Clause-Patent
> -#
> -##
> -
> -[Defines]
> - INF_VERSION = 0x0001001A
> - BASE_NAME = BasePciExpressLib
> - FILE_GUID = b378dd06-de7f-4e8c-8fb0-5126adfb34bf
> - MODULE_TYPE = BASE
> - VERSION_STRING = 1.0
> - LIBRARY_CLASS = PciExpressLib
> -
> -[Sources]
> - PciExpressLib.c
> -
> -[Packages]
> - MdePkg/MdePkg.dec
> - Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec
> -
> -[FixedPcd]
> - gArmNeoverseN1SocTokenSpaceGuid.PcdPcieRootPortConfigBaseAddress
> - gArmNeoverseN1SocTokenSpaceGuid.PcdPcieRootPortConfigBaseSize
> -
> -[LibraryClasses]
> - BaseLib
> - DebugLib
> - IoLib
> - PcdLib
> -
> -[Pcd]
> - gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## CONSUMES
^ permalink raw reply [flat|nested] 13+ messages in thread
end of thread, other threads:[~2022-01-19 15:02 UTC | newest]
Thread overview: 13+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2021-12-22 1:14 [PATCH v5 0/4] Enable CCIX port as PCIe root host on N1SDP Khasim Mohammed
2021-12-22 1:14 ` [PATCH v5 1/4] Silicon/ARM/NeoverseN1Soc: Port PCI Segment Library Khasim Mohammed
2021-12-22 8:52 ` [edk2-devel] " PierreGondois
2022-01-19 15:01 ` Sami Mujawar
2021-12-22 1:14 ` [PATCH v5 2/4] Silicon/ARM/NeoverseN1Soc: Update PCDs to support multiple PCI root ports Khasim Mohammed
2021-12-22 8:52 ` [edk2-devel] " PierreGondois
2022-01-19 15:01 ` Sami Mujawar
2021-12-22 1:14 ` [PATCH v5 3/4] Silicon/ARM/NeoverseN1Soc: Add CCIX root complex support Khasim Mohammed
2021-12-22 8:52 ` [edk2-devel] " PierreGondois
2022-01-19 15:02 ` Sami Mujawar
2021-12-22 1:14 ` [PATCH v5 4/4] Silicon/ARM/NeoverseN1Soc: Remove PciExpressLib use PciSegmentLib instead Khasim Mohammed
2021-12-22 8:51 ` [edk2-devel] " PierreGondois
2022-01-19 15:02 ` Sami Mujawar
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