From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from EUR05-VI1-obe.outbound.protection.outlook.com (EUR05-VI1-obe.outbound.protection.outlook.com [40.107.21.40]) by mx.groups.io with SMTP id smtpd.web09.13990.1640135801574679718 for ; Tue, 21 Dec 2021 17:16:42 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@armh.onmicrosoft.com header.s=selector2-armh-onmicrosoft-com header.b=ayil75oX; spf=pass (domain: arm.com, ip: 40.107.21.40, mailfrom: khasim.mohammed@arm.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=armh.onmicrosoft.com; s=selector2-armh-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=9dfs71mS9Oz1mB7xQRyqH1YvTUuFfXhlv7vLd7Uhwt0=; b=ayil75oX9LaRM43XfLf2Eq6kVUndL0C5hxX6Ga0sNjzwWPqC3CB6OPpk16dwe7vPdKMOFj4g4COfAvtEZii9YTJye3fl6oVOa40l5E9sCT+ARUr3xpKIsch8kbn3WE1D3OiguBTyzI94wO4366HrTelHnF+qSbp7ExutIYyzogk= Received: from AS9PR06CA0114.eurprd06.prod.outlook.com (2603:10a6:20b:465::12) by PAXPR08MB7247.eurprd08.prod.outlook.com (2603:10a6:102:212::7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4801.17; Wed, 22 Dec 2021 01:16:37 +0000 Received: from VE1EUR03FT017.eop-EUR03.prod.protection.outlook.com (2603:10a6:20b:465:cafe::5e) by AS9PR06CA0114.outlook.office365.com (2603:10a6:20b:465::12) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4801.15 via Frontend Transport; Wed, 22 Dec 2021 01:16:37 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 63.35.35.123) smtp.mailfrom=arm.com; dkim=pass (signature was verified) header.d=armh.onmicrosoft.com;dmarc=pass action=none header.from=arm.com; Received-SPF: Pass (protection.outlook.com: domain of arm.com designates 63.35.35.123 as permitted sender) receiver=protection.outlook.com; client-ip=63.35.35.123; helo=64aa7808-outbound-1.mta.getcheckrecipient.com; Received: from 64aa7808-outbound-1.mta.getcheckrecipient.com (63.35.35.123) by VE1EUR03FT017.mail.protection.outlook.com (10.152.18.90) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4801.14 via Frontend Transport; Wed, 22 Dec 2021 01:16:36 +0000 Received: ("Tessian outbound 9a8c656e7c94:v110"); Wed, 22 Dec 2021 01:16:36 +0000 X-CheckRecipientChecked: true X-CR-MTA-CID: 641294d90f84c39f X-CR-MTA-TID: 64aa7808 Received: from 1fd71113800a.1 by 64aa7808-outbound-1.mta.getcheckrecipient.com id BA5C4912-00FE-4CC7-9848-51BFA2E022E9.1; Wed, 22 Dec 2021 01:16:26 +0000 Received: from EUR03-VE1-obe.outbound.protection.outlook.com by 64aa7808-outbound-1.mta.getcheckrecipient.com with ESMTPS id 1fd71113800a.1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384); Wed, 22 Dec 2021 01:16:26 +0000 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=A86KTIRImAQQyaFoQciekkUSl+zFfKm/VDpsuA5ciHWuEDwDGUcP37S5q+atVo9jQX0c5AtfSFhpyzTLIhYDK/p560EhB3lBvP6BfApF/RttrtsXcL7t/IWQJL7PluXgunrHlsn2BL2O1dNM7InJyNExvLS+eDl4OsuRcS8/nuknBU5iFWG1hejBhKNM3/rTdoLB2r5xGK28USOElBsabETKV1I7R+g5Tn57HR3BoIyppcptWINmnUqmGhAyhd0KvUJcGuweoR2m2gmGYSMx0uSY16XDS6IOKvAsCRgYOq7m9Fm8MNT+i3YeFyNkZr6XOoVV4kb0W+40pWZu1dQ32w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=9dfs71mS9Oz1mB7xQRyqH1YvTUuFfXhlv7vLd7Uhwt0=; b=ftHqKBafRUK+DPTPi1FE8pRNglWCcqUHjlxwKuk8lHJkBtMKckgNOx6zB4qyeaHv6heime4vOkT30wXm/Y70wtEh+smiMLiy2HsiT5nYKKTC+HgSvrd1hQl64OiIkNXK1PZDx1Lqs4dnnzkE2F+SGT5PGoOiksGquTVhlrqj+qPhg6bFg57xjIW/xGSFUMwvwyBaoXtHOpI2BaGlLCku91M8YkCzhusR9gmAr9Sii8FmWSfW2TKy068QcHY2I9sbZfs48x/AUTRn2HvQOenNhVchZT40drWfGLsKTvI1LtS1GJ8tBIAQR3FBrX85yCFPOITIkLKjm0l4jbsYGzOpPg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=arm.com; dmarc=pass action=none header.from=arm.com; dkim=pass header.d=arm.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=armh.onmicrosoft.com; s=selector2-armh-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=9dfs71mS9Oz1mB7xQRyqH1YvTUuFfXhlv7vLd7Uhwt0=; b=ayil75oX9LaRM43XfLf2Eq6kVUndL0C5hxX6Ga0sNjzwWPqC3CB6OPpk16dwe7vPdKMOFj4g4COfAvtEZii9YTJye3fl6oVOa40l5E9sCT+ARUr3xpKIsch8kbn3WE1D3OiguBTyzI94wO4366HrTelHnF+qSbp7ExutIYyzogk= Authentication-Results-Original: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=arm.com; Received: from PA4PR08MB5902.eurprd08.prod.outlook.com (2603:10a6:102:e0::10) by PAXPR08MB7017.eurprd08.prod.outlook.com (2603:10a6:102:1df::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4801.19; Wed, 22 Dec 2021 01:16:23 +0000 Received: from PA4PR08MB5902.eurprd08.prod.outlook.com ([fe80::64a1:69a1:148d:9fa]) by PA4PR08MB5902.eurprd08.prod.outlook.com ([fe80::64a1:69a1:148d:9fa%9]) with mapi id 15.20.4823.018; Wed, 22 Dec 2021 01:16:23 +0000 From: "Khasim Mohammed" To: devel@edk2.groups.io Cc: nd@arm.com, Khasim Syed Mohammed , Deepak Pandey Subject: [PATCH v5 4/4] Silicon/ARM/NeoverseN1Soc: Remove PciExpressLib use PciSegmentLib instead Date: Wed, 22 Dec 2021 06:44:40 +0530 Message-Id: <20211222011440.3687-5-khasim.mohammed@arm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20211222011440.3687-1-khasim.mohammed@arm.com> References: <20211222011440.3687-1-khasim.mohammed@arm.com> X-ClientProxiedBy: PN0PR01CA0046.INDPRD01.PROD.OUTLOOK.COM (2603:1096:c01:49::14) To PA4PR08MB5902.eurprd08.prod.outlook.com (2603:10a6:102:e0::10) MIME-Version: 1.0 X-MS-Office365-Filtering-Correlation-Id: 2eb6d4be-4a81-4bd8-22bf-08d9c4e8b360 X-MS-TrafficTypeDiagnostic: PAXPR08MB7017:EE_|VE1EUR03FT017:EE_|PAXPR08MB7247:EE_ X-Microsoft-Antispam-PRVS: x-checkrecipientrouted: true NoDisclaimer: true X-MS-Oob-TLC-OOBClassifiers: OLM:8882;OLM:8882; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0; X-Microsoft-Antispam-Message-Info-Original: nWdz615RHGPdBFMFlDG/h6EicZ2jx+BZSkieuHDY2VVJAOjFuOV7ubQoXG7y2FxTXKMre4d3A+aAXg8n1bWOfMUbdHLcCnpjnnGjFvJZjCLhsBPO3zVIDRF7gx+ZOBsgJilD5crNtFgPQdbikqnxrCys+f+23pXJZy9Is2vGFyiblN4sQlMbu3sRlLu894nhf5lEfaP5CqOmjk8uWVIE8enHO+3cIcPGLT1DhhJIbEkGuFCYGS6LxvOtYW7D/piA9WToK0JR65RoN3HLFKWUurNKvJMFtKNifNeiWM7lsR57Zzhcc3pCnTmn70dDQMrZw2W3ph4CUdx7tt7OFnIWPXroiM6sqIoOjDw4kyiKsfrJiWPgHD+S4Qr3hHdpfg5sAjuBr52jdy+9UiyEw8i9jtFMf7k73GixN6c1RMEBoRUKQHGX1Dwfy9Pug+SPDmvQzDmZOzHtIRKtFj9vfP9bO0j7T1HdQ2W1EpItzrfzphYFdPYCQ+eU+uewBxWNjxwdQczyXxS0fPZYpOsmSVIFHOyCd9YsEP3Sxh7ZdDvYQctS+KelkrDoKQxuBFYOvnC9IBOfu6+Lqvtqo43pZQiwclBrszF6qEveIf61PWO5MEV5fBExRBKnvQz6i4WSfN3LIwMV3BC58SuCL3lS7GTRGWjL2My2Vvx0PpoSB6A/RAUIoI7B+Sa+/r5uWbXvgvMtif6pe3AlXOHvY0QkE+QMHg== X-Forefront-Antispam-Report-Untrusted: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:PA4PR08MB5902.eurprd08.prod.outlook.com;PTR:;CAT:NONE;SFS:(4636009)(366004)(186003)(2616005)(26005)(508600001)(36756003)(316002)(8936002)(86362001)(4326008)(66476007)(66556008)(38350700002)(38100700002)(66946007)(6486002)(19627235002)(6666004)(2906002)(6512007)(1076003)(6506007)(6916009)(8676002)(5660300002)(54906003)(52116002)(83380400001)(30864003)(579004)(559001);DIR:OUT;SFP:1101; X-MS-Exchange-Transport-CrossTenantHeadersStamped: PAXPR08MB7017 Original-Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=arm.com; Return-Path: Khasim.Mohammed@arm.com X-EOPAttributedMessage: 0 X-MS-Exchange-Transport-CrossTenantHeadersStripped: VE1EUR03FT017.eop-EUR03.prod.protection.outlook.com X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id-Prvs: 3d16edd8-bddf-4aa3-8cac-08d9c4e8ab40 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: FruS83r2aUiZU9RXNkBi2Lo2iJNq3K4VreD8lQzwosWsiAuKQnbTSL/gX+WaiFy6qIDFI8j6svpt76Nazu232DKph0IH7LpTnmOC2wSy1HD/zRJkhjiXIqtgrKT7WuY/BEK81YwPzl4GFK+hqs8Hd+3GRu6aE4fm4AQUwJ0W4RYAJe435DOiXz9ZJkSgpBRH+U8S74zavsExE++NirIygomL7JO6GlvsTqvUJ0x9LQp+QAlejtpGavFmQRJL5bNKjJ05j6mQtKP8HaxsqfnVBawH9d/3TG2p0AzqEEqLpMy5KTbeKl4ukBtxIkl5d/2ZyhLXF26qcwdVuKCJ3pRawABtuZtOLugph3fVhxQc/IXiWvWo2ifzHeEaliVuN16y2GkpcHuy+vOcq6cax7VzR+GaywIDgCIpk0z/JirFLk+Cvko97X0rD1YybQwx8zBAMBtyK7uE00afZ83poFivJ5+Q3xVZsI7nqd6j4FzCWWgTAnn387P+SQuhV5bq1tk9cePJGMiAGGftfYTqKS3xZ+bDEklBRF4VWfxcmVIT+pOqeIvmokK6sZYB3QnfWLAtslWUigdBFi3QC/jku0YwSv1sFt/RiXGv23uJvmM3fhH7eWIRF00YKoNTSw1PGUXX+Jk9gLOBrsnJjLJayYQlvx5nwUorkPYpE4btIG+LGbeNIm7zNZUa0RQhBi2hCG1Ez+BjgToGmybiFgH7TcxbRQ== X-Forefront-Antispam-Report: CIP:63.35.35.123;CTRY:IE;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:64aa7808-outbound-1.mta.getcheckrecipient.com;PTR:ec2-63-35-35-123.eu-west-1.compute.amazonaws.com;CAT:NONE;SFS:(4636009)(46966006)(36840700001)(86362001)(2906002)(81166007)(36860700001)(54906003)(82310400004)(316002)(8936002)(8676002)(186003)(6506007)(2616005)(36756003)(26005)(508600001)(336012)(356005)(83380400001)(30864003)(6486002)(70206006)(5660300002)(1076003)(6916009)(6512007)(6666004)(19627235002)(4326008)(70586007)(47076005)(559001)(579004);DIR:OUT;SFP:1101; X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Dec 2021 01:16:36.9108 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2eb6d4be-4a81-4bd8-22bf-08d9c4e8b360 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[63.35.35.123];Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: VE1EUR03FT017.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PAXPR08MB7247 Content-Type: text/plain The patch removes PciExpressLib implementation for N1Sdp as: a) The PciSegmentLib implementation for N1Sdp makes MmioRead() calls instead of PciRead() which makes the PciExpressLib redundant. b) Since N1Sdp requires multiple segments to be supported, PciExpressLib and PciLib cannot be used, PciSegmentLib should be used instead as it supports multiple segments. Signed-off-by: Deepak Pandey Signed-off-by: Khasim Syed Mohammed --- Platform/ARM/N1Sdp/N1SdpPlatform.dsc | 4 +- .../PciExpressLib.c | 1589 ----------------- .../PciExpressLib.inf | 56 - 3 files changed, 1 insertion(+), 1648 deletions(-) delete mode 100644 Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciExpressLib/PciExpressLib.c delete mode 100644 Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciExpressLib/PciExpressLib.inf diff --git a/Platform/ARM/N1Sdp/N1SdpPlatform.dsc b/Platform/ARM/N1Sdp/N1SdpPlatform.dsc index cb2049966c..8dac1bc54c 100644 --- a/Platform/ARM/N1Sdp/N1SdpPlatform.dsc +++ b/Platform/ARM/N1Sdp/N1SdpPlatform.dsc @@ -75,9 +75,7 @@ [LibraryClasses.common.DXE_DRIVER] FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib.inf PciHostBridgeLib|Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.inf - PciSegmentLib|MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf - PciLib|MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf - PciExpressLib|Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciExpressLib/PciExpressLib.inf + PciSegmentLib|Silicon/ARM/NeoverseN1Soc/Library/PciSegmentLib/PciSegmentLib.inf [LibraryClasses.common.DXE_RUNTIME_DRIVER] BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf diff --git a/Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciExpressLib/PciExpressLib.c b/Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciExpressLib/PciExpressLib.c deleted file mode 100644 index bb0246b4a9..0000000000 --- a/Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciExpressLib/PciExpressLib.c +++ /dev/null @@ -1,1589 +0,0 @@ -/** @file - Functions in this library instance make use of MMIO functions in IoLib to - access memory mapped PCI configuration space. - - All assertions for I/O operations are handled in MMIO functions in the IoLib - Library. - - Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
- - On the NeoverseN1Soc, a slave error is generated when host accesses the - configuration space of non-available device or unimplemented function on a - given bus. So this library introduces a workaround using IsBdfValid(), - to return 0xFFFFFFFF for all such access. - - In addition to this, the hardware has two other limitations which affect - access to the PCIe root port: - 1. ECAM space is not contiguous, root port ECAM (BDF = 0:0:0) is isolated - from rest of the downstream hierarchy ECAM space. - 2. Root port ECAM space is not capable of 8bit/16bit writes. - The description of the workarounds included for these limitations can - be found in the comments below. - - Copyright (c) 2020, ARM Limited. All rights reserved. - - SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ - - -#include - -#include -#include -#include -#include -#include -#include - -/** - Assert the validity of a PCI address. A valid PCI address should contain 1's - only in the low 28 bits. - - @param A The address to validate. - -**/ -#define ASSERT_INVALID_PCI_ADDRESS(A) \ - ASSERT (((A) & ~0xfffffff) == 0) - -/* Root port Entry, BDF Entries Count */ -#define BDF_TABLE_ENTRY_SIZE 4 -#define BDF_TABLE_HEADER_COUNT 2 -#define BDF_TABLE_HEADER_SIZE 8 - -/* BDF table offsets for PCIe */ -#define PCIE_BDF_TABLE_OFFSET 0 - -#define GET_BUS_NUM(Address) (((Address) >> 20) & 0x7F) -#define GET_DEV_NUM(Address) (((Address) >> 15) & 0x1F) -#define GET_FUNC_NUM(Address) (((Address) >> 12) & 0x07) -#define GET_REG_NUM(Address) ((Address) & 0xFFF) - -/** - BDF Table structure : (Header + BDF Entries) - -------------------------------------------- - [Offset 0x00] ROOT PORT ADDRESS - [Offset 0x04] BDF ENTRIES COUNT - [Offset 0x08] BDF ENTRY 0 - [Offset 0x0C] BDF ENTRY 1 - [Offset 0x10] BDF ENTRY 2 - [Offset 0x14] BDF ENTRY 3 - [Offset 0x18] BDF ENTRY 4 - ... - [Offset 0x--] BDF ENTRY N - -------------------------------------------- -**/ - -/** - Value returned for reads on configuration space of unimplemented - device functions. -**/ -STATIC UINTN mDummyConfigData = 0xFFFFFFFF; - -/** - Registers a PCI device so PCI configuration registers may be accessed after - SetVirtualAddressMap(). - - Registers the PCI device specified by Address so all the PCI configuration - registers associated with that PCI device may be accessed after SetVirtualAddressMap() - is called. - - If Address > 0x0FFFFFFF, then ASSERT(). - - @param Address The address that encodes the PCI Bus, Device, Function and - Register. - - @retval RETURN_SUCCESS The PCI device was registered for runtime access. - @retval RETURN_UNSUPPORTED An attempt was made to call this function - after ExitBootServices(). - @retval RETURN_UNSUPPORTED The resources required to access the PCI device - at runtime could not be mapped. - @retval RETURN_OUT_OF_RESOURCES There are not enough resources available to - complete the registration. - -**/ -RETURN_STATUS -EFIAPI -PciExpressRegisterForRuntimeAccess ( - IN UINTN Address - ) -{ - ASSERT_INVALID_PCI_ADDRESS (Address); - return RETURN_UNSUPPORTED; -} - -/** - Check if the requested PCI address can be safely accessed. - - SCP performs the initial bus scan, prepares a table of valid BDF addresses - and shares them through non-trusted SRAM. This function validates if the - requested PCI address belongs to a valid BDF by checking the table of valid - entries. If not, this function will return false. This is a workaround to - avoid bus fault that occurs when accessing unavailable PCI device due to - hardware bug. - - @param Address The address that encodes the PCI Bus, Device, Function and - Register. - - @return TRUE BDF can be accessed, valid. - @return FALSE BDF should not be accessed, invalid. - -**/ -STATIC -BOOLEAN -IsBdfValid ( - IN UINTN Address - ) -{ - UINTN BdfCount; - UINTN BdfValue; - UINTN BdfEntry; - UINTN Count; - UINTN TableBase; - UINTN ConfigBase; - - ConfigBase = Address & ~0xFFF; - TableBase = NEOVERSEN1SOC_NON_SECURE_SRAM_BASE + PCIE_BDF_TABLE_OFFSET; - BdfCount = MmioRead32 (TableBase + BDF_TABLE_ENTRY_SIZE); - BdfEntry = TableBase + BDF_TABLE_HEADER_SIZE; - - /* Skip the header & check remaining entry */ - for (Count = 0; Count < BdfCount; Count++, BdfEntry += BDF_TABLE_ENTRY_SIZE) { - BdfValue = MmioRead32 (BdfEntry); - if (BdfValue == ConfigBase) { - return TRUE; - } - } - - return FALSE; -} - -/** - Get the physical address of a configuration space register. - - Implement a workaround to avoid generation of slave errors from the bus. That - is, retrieve the PCI Express Base Address via a PCD entry, add the incomming - address with that base address and check whether this converted address - points to a accessible BDF. If it is not accessible, return the address - of a dummy location so that a read from it does not cause a slave error. - - In addition to this, implement a workaround for accessing the root port's - configuration space. The root port configuration space is not contiguous - with the rest of the downstream hierarchy configuration space. So determine - whether the specified address is for the root port and use a different base - address for it. - - @param Address The address that encodes the PCI Bus, Device, Function and - Register. - - @return Physical address of the configuration register that corresponds to the - PCI configuration register specified by input parameter 'Address'. - -**/ -STATIC -VOID* -GetPciExpressAddress ( - IN UINTN Address - ) -{ - UINT8 Bus, Device, Function; - UINTN ConfigAddress; - - Bus = GET_BUS_NUM (Address); - Device = GET_DEV_NUM (Address); - Function = GET_FUNC_NUM (Address); - - if ((Bus == 0) && (Device == 0) && (Function == 0)) { - ConfigAddress = PcdGet32 (PcdPcieRootPortConfigBaseAddress) + Address; - } else { - ConfigAddress = PcdGet64 (PcdPciExpressBaseAddress) + Address; - if (!IsBdfValid(Address)) { - ConfigAddress = (UINTN)&mDummyConfigData; - } - } - - return (VOID *)ConfigAddress; -} - -/** - Reads an 8-bit PCI configuration register. - - Reads and returns the 8-bit PCI configuration register specified by Address. - This function must guarantee that all PCI read and write operations are - serialized. - - If Address > 0x0FFFFFFF, then ASSERT(). - - @param Address The address that encodes the PCI Bus, Device, Function and - Register. - - @return The read value from the PCI configuration register. - -**/ -UINT8 -EFIAPI -PciExpressRead8 ( - IN UINTN Address - ) -{ - ASSERT_INVALID_PCI_ADDRESS (Address); - return MmioRead8 ((UINTN)GetPciExpressAddress (Address)); -} - -/** - Writes an 8-bit PCI configuration register. - - Writes the 8-bit PCI configuration register specified by Address with the - value specified by Value. Value is returned. This function must guarantee - that all PCI read and write operations are serialized. - - If Address > 0x0FFFFFFF, then ASSERT(). - - @param Address The address that encodes the PCI Bus, Device, Function and - Register. - @param Value The value to write. - - @return The value written to the PCI configuration register. - -**/ -UINT8 -EFIAPI -PciExpressWrite8 ( - IN UINTN Address, - IN UINT8 Value - ) -{ - UINT8 Bus, Device, Function; - UINT8 Offset; - UINT32 Data; - - ASSERT_INVALID_PCI_ADDRESS (Address); - - Bus = GET_BUS_NUM (Address); - Device = GET_DEV_NUM (Address); - Function = GET_FUNC_NUM (Address); - - // - // 8-bit and 16-bit writes to root port config space is not supported due to - // a hardware limitation. As a workaround, perform a read-update-write - // sequence on the whole 32-bit word of the root port config register such - // that only the specified 8-bits of that word are updated. - // - if ((Bus == 0) && (Device == 0) && (Function == 0)) { - Offset = Address & 0x3; - Address &= 0xFFFFFFFC; - Data = MmioRead32 ((UINTN)GetPciExpressAddress (Address)); - Data &= ~(0xFF << (8 * Offset)); - Data |= (Value << (8 * Offset)); - MmioWrite32 ((UINTN)GetPciExpressAddress (Address), Data); - return Value; - } - - return MmioWrite8 ((UINTN)GetPciExpressAddress (Address), Value); -} - -/** - Performs a bitwise OR of an 8-bit PCI configuration register with - an 8-bit value. - - Reads the 8-bit PCI configuration register specified by Address, performs a - bitwise OR between the read result and the value specified by - OrData, and writes the result to the 8-bit PCI configuration register - specified by Address. The value written to the PCI configuration register is - returned. This function must guarantee that all PCI read and write operations - are serialized. - - If Address > 0x0FFFFFFF, then ASSERT(). - - @param Address The address that encodes the PCI Bus, Device, Function and - Register. - @param OrData The value to OR with the PCI configuration register. - - @return The value written back to the PCI configuration register. - -**/ -UINT8 -EFIAPI -PciExpressOr8 ( - IN UINTN Address, - IN UINT8 OrData - ) -{ - ASSERT_INVALID_PCI_ADDRESS (Address); - return MmioOr8 ((UINTN)GetPciExpressAddress (Address), OrData); -} - -/** - Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit - value. - - Reads the 8-bit PCI configuration register specified by Address, performs a - bitwise AND between the read result and the value specified by AndData, and - writes the result to the 8-bit PCI configuration register specified by - Address. The value written to the PCI configuration register is returned. - This function must guarantee that all PCI read and write operations are - serialized. - - If Address > 0x0FFFFFFF, then ASSERT(). - - @param Address The address that encodes the PCI Bus, Device, Function and - Register. - @param AndData The value to AND with the PCI configuration register. - - @return The value written back to the PCI configuration register. - -**/ -UINT8 -EFIAPI -PciExpressAnd8 ( - IN UINTN Address, - IN UINT8 AndData - ) -{ - ASSERT_INVALID_PCI_ADDRESS (Address); - return MmioAnd8 ((UINTN)GetPciExpressAddress (Address), AndData); -} - -/** - Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit - value, followed a bitwise OR with another 8-bit value. - - Reads the 8-bit PCI configuration register specified by Address, performs a - bitwise AND between the read result and the value specified by AndData, - performs a bitwise OR between the result of the AND operation and - the value specified by OrData, and writes the result to the 8-bit PCI - configuration register specified by Address. The value written to the PCI - configuration register is returned. This function must guarantee that all PCI - read and write operations are serialized. - - If Address > 0x0FFFFFFF, then ASSERT(). - - @param Address The address that encodes the PCI Bus, Device, Function and - Register. - @param AndData The value to AND with the PCI configuration register. - @param OrData The value to OR with the result of the AND operation. - - @return The value written back to the PCI configuration register. - -**/ -UINT8 -EFIAPI -PciExpressAndThenOr8 ( - IN UINTN Address, - IN UINT8 AndData, - IN UINT8 OrData - ) -{ - ASSERT_INVALID_PCI_ADDRESS (Address); - return MmioAndThenOr8 ( - (UINTN)GetPciExpressAddress (Address), - AndData, - OrData - ); -} - -/** - Reads a bit field of a PCI configuration register. - - Reads the bit field in an 8-bit PCI configuration register. The bit field is - specified by the StartBit and the EndBit. The value of the bit field is - returned. - - If Address > 0x0FFFFFFF, then ASSERT(). - If StartBit is greater than 7, then ASSERT(). - If EndBit is greater than 7, then ASSERT(). - If EndBit is less than StartBit, then ASSERT(). - - @param Address The PCI configuration register to read. - @param StartBit The ordinal of the least significant bit in the bit field. - Range 0..7. - @param EndBit The ordinal of the most significant bit in the bit field. - Range 0..7. - - @return The value of the bit field read from the PCI configuration register. - -**/ -UINT8 -EFIAPI -PciExpressBitFieldRead8 ( - IN UINTN Address, - IN UINTN StartBit, - IN UINTN EndBit - ) -{ - ASSERT_INVALID_PCI_ADDRESS (Address); - return MmioBitFieldRead8 ( - (UINTN)GetPciExpressAddress (Address), - StartBit, - EndBit - ); -} - -/** - Writes a bit field to a PCI configuration register. - - Writes Value to the bit field of the PCI configuration register. The bit - field is specified by the StartBit and the EndBit. All other bits in the - destination PCI configuration register are preserved. The new value of the - 8-bit register is returned. - - If Address > 0x0FFFFFFF, then ASSERT(). - If StartBit is greater than 7, then ASSERT(). - If EndBit is greater than 7, then ASSERT(). - If EndBit is less than StartBit, then ASSERT(). - If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). - - @param Address The PCI configuration register to write. - @param StartBit The ordinal of the least significant bit in the bit field. - Range 0..7. - @param EndBit The ordinal of the most significant bit in the bit field. - Range 0..7. - @param Value The new value of the bit field. - - @return The value written back to the PCI configuration register. - -**/ -UINT8 -EFIAPI -PciExpressBitFieldWrite8 ( - IN UINTN Address, - IN UINTN StartBit, - IN UINTN EndBit, - IN UINT8 Value - ) -{ - ASSERT_INVALID_PCI_ADDRESS (Address); - return MmioBitFieldWrite8 ( - (UINTN)GetPciExpressAddress (Address), - StartBit, - EndBit, - Value - ); -} - -/** - Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and - writes the result back to the bit field in the 8-bit port. - - Reads the 8-bit PCI configuration register specified by Address, performs a - bitwise OR between the read result and the value specified by - OrData, and writes the result to the 8-bit PCI configuration register - specified by Address. The value written to the PCI configuration register is - returned. This function must guarantee that all PCI read and write operations - are serialized. Extra left bits in OrData are stripped. - - If Address > 0x0FFFFFFF, then ASSERT(). - If StartBit is greater than 7, then ASSERT(). - If EndBit is greater than 7, then ASSERT(). - If EndBit is less than StartBit, then ASSERT(). - If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). - - @param Address The PCI configuration register to write. - @param StartBit The ordinal of the least significant bit in the bit field. - Range 0..7. - @param EndBit The ordinal of the most significant bit in the bit field. - Range 0..7. - @param OrData The value to OR with the PCI configuration register. - - @return The value written back to the PCI configuration register. - -**/ -UINT8 -EFIAPI -PciExpressBitFieldOr8 ( - IN UINTN Address, - IN UINTN StartBit, - IN UINTN EndBit, - IN UINT8 OrData - ) -{ - ASSERT_INVALID_PCI_ADDRESS (Address); - return MmioBitFieldOr8 ( - (UINTN)GetPciExpressAddress (Address), - StartBit, - EndBit, - OrData - ); -} - -/** - Reads a bit field in an 8-bit PCI configuration register, performs a bitwise - AND, and writes the result back to the bit field in the 8-bit register. - - Reads the 8-bit PCI configuration register specified by Address, performs a - bitwise AND between the read result and the value specified by AndData, and - writes the result to the 8-bit PCI configuration register specified by - Address. The value written to the PCI configuration register is returned. - This function must guarantee that all PCI read and write operations are - serialized. Extra left bits in AndData are stripped. - - If Address > 0x0FFFFFFF, then ASSERT(). - If StartBit is greater than 7, then ASSERT(). - If EndBit is greater than 7, then ASSERT(). - If EndBit is less than StartBit, then ASSERT(). - If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). - - @param Address The PCI configuration register to write. - @param StartBit The ordinal of the least significant bit in the bit field. - Range 0..7. - @param EndBit The ordinal of the most significant bit in the bit field. - Range 0..7. - @param AndData The value to AND with the PCI configuration register. - - @return The value written back to the PCI configuration register. - -**/ -UINT8 -EFIAPI -PciExpressBitFieldAnd8 ( - IN UINTN Address, - IN UINTN StartBit, - IN UINTN EndBit, - IN UINT8 AndData - ) -{ - ASSERT_INVALID_PCI_ADDRESS (Address); - return MmioBitFieldAnd8 ( - (UINTN)GetPciExpressAddress (Address), - StartBit, - EndBit, - AndData - ); -} - -/** - Reads a bit field in an 8-bit port, performs a bitwise AND followed by a - bitwise OR, and writes the result back to the bit field in the - 8-bit port. - - Reads the 8-bit PCI configuration register specified by Address, performs a - bitwise AND followed by a bitwise OR between the read result and - the value specified by AndData, and writes the result to the 8-bit PCI - configuration register specified by Address. The value written to the PCI - configuration register is returned. This function must guarantee that all PCI - read and write operations are serialized. Extra left bits in both AndData and - OrData are stripped. - - If Address > 0x0FFFFFFF, then ASSERT(). - If StartBit is greater than 7, then ASSERT(). - If EndBit is greater than 7, then ASSERT(). - If EndBit is less than StartBit, then ASSERT(). - If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). - If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). - - @param Address The PCI configuration register to write. - @param StartBit The ordinal of the least significant bit in the bit field. - Range 0..7. - @param EndBit The ordinal of the most significant bit in the bit field. - Range 0..7. - @param AndData The value to AND with the PCI configuration register. - @param OrData The value to OR with the result of the AND operation. - - @return The value written back to the PCI configuration register. - -**/ -UINT8 -EFIAPI -PciExpressBitFieldAndThenOr8 ( - IN UINTN Address, - IN UINTN StartBit, - IN UINTN EndBit, - IN UINT8 AndData, - IN UINT8 OrData - ) -{ - ASSERT_INVALID_PCI_ADDRESS (Address); - return MmioBitFieldAndThenOr8 ( - (UINTN)GetPciExpressAddress (Address), - StartBit, - EndBit, - AndData, - OrData - ); -} - -/** - Reads a 16-bit PCI configuration register. - - Reads and returns the 16-bit PCI configuration register specified by Address. - This function must guarantee that all PCI read and write operations are - serialized. - - If Address > 0x0FFFFFFF, then ASSERT(). - If Address is not aligned on a 16-bit boundary, then ASSERT(). - - @param Address The address that encodes the PCI Bus, Device, Function and - Register. - - @return The read value from the PCI configuration register. - -**/ -UINT16 -EFIAPI -PciExpressRead16 ( - IN UINTN Address - ) -{ - ASSERT_INVALID_PCI_ADDRESS (Address); - return MmioRead16 ((UINTN)GetPciExpressAddress (Address)); -} - -/** - Writes a 16-bit PCI configuration register. - - Writes the 16-bit PCI configuration register specified by Address with the - value specified by Value. Value is returned. This function must guarantee - that all PCI read and write operations are serialized. - - If Address > 0x0FFFFFFF, then ASSERT(). - If Address is not aligned on a 16-bit boundary, then ASSERT(). - - @param Address The address that encodes the PCI Bus, Device, Function and - Register. - @param Value The value to write. - - @return The value written to the PCI configuration register. - -**/ -UINT16 -EFIAPI -PciExpressWrite16 ( - IN UINTN Address, - IN UINT16 Value - ) -{ - UINT8 Bus, Device, Function; - UINT8 Offset; - UINT32 Data; - - ASSERT_INVALID_PCI_ADDRESS (Address); - - Bus = GET_BUS_NUM (Address); - Device = GET_DEV_NUM (Address); - Function = GET_FUNC_NUM (Address); - - // - // 8-bit and 16-bit writes to root port config space is not supported due to - // a hardware limitation. As a workaround, perform a read-update-write - // sequence on the whole 32-bit word of the root port config register such - // that only the specified 16-bits of that word are updated. - // - if ((Bus == 0) && (Device == 0) && (Function == 0)) { - Offset = Address & 0x3; - Address &= 0xFFFFFFFC; - Data = MmioRead32 ((UINTN)GetPciExpressAddress (Address)); - Data &= ~(0xFFFF << (8 * Offset)); - Data |= (Value << (8 * Offset)); - MmioWrite32 ((UINTN)GetPciExpressAddress (Address), Data); - return Value; - } - - return MmioWrite16 ((UINTN)GetPciExpressAddress (Address), Value); -} - -/** - Performs a bitwise OR of a 16-bit PCI configuration register with - a 16-bit value. - - Reads the 16-bit PCI configuration register specified by Address, performs a - bitwise OR between the read result and the value specified by - OrData, and writes the result to the 16-bit PCI configuration register - specified by Address. The value written to the PCI configuration register is - returned. This function must guarantee that all PCI read and write operations - are serialized. - - If Address > 0x0FFFFFFF, then ASSERT(). - If Address is not aligned on a 16-bit boundary, then ASSERT(). - - @param Address The address that encodes the PCI Bus, Device, Function and - Register. - @param OrData The value to OR with the PCI configuration register. - - @return The value written back to the PCI configuration register. - -**/ -UINT16 -EFIAPI -PciExpressOr16 ( - IN UINTN Address, - IN UINT16 OrData - ) -{ - ASSERT_INVALID_PCI_ADDRESS (Address); - return MmioOr16 ((UINTN)GetPciExpressAddress (Address), OrData); -} - -/** - Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit - value. - - Reads the 16-bit PCI configuration register specified by Address, performs a - bitwise AND between the read result and the value specified by AndData, and - writes the result to the 16-bit PCI configuration register specified by - Address. The value written to the PCI configuration register is returned. - This function must guarantee that all PCI read and write operations are - serialized. - - If Address > 0x0FFFFFFF, then ASSERT(). - If Address is not aligned on a 16-bit boundary, then ASSERT(). - - @param Address The address that encodes the PCI Bus, Device, Function and - Register. - @param AndData The value to AND with the PCI configuration register. - - @return The value written back to the PCI configuration register. - -**/ -UINT16 -EFIAPI -PciExpressAnd16 ( - IN UINTN Address, - IN UINT16 AndData - ) -{ - ASSERT_INVALID_PCI_ADDRESS (Address); - return MmioAnd16 ((UINTN)GetPciExpressAddress (Address), AndData); -} - -/** - Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit - value, followed a bitwise OR with another 16-bit value. - - Reads the 16-bit PCI configuration register specified by Address, performs a - bitwise AND between the read result and the value specified by AndData, - performs a bitwise OR between the result of the AND operation and - the value specified by OrData, and writes the result to the 16-bit PCI - configuration register specified by Address. The value written to the PCI - configuration register is returned. This function must guarantee that all PCI - read and write operations are serialized. - - If Address > 0x0FFFFFFF, then ASSERT(). - If Address is not aligned on a 16-bit boundary, then ASSERT(). - - @param Address The address that encodes the PCI Bus, Device, Function and - Register. - @param AndData The value to AND with the PCI configuration register. - @param OrData The value to OR with the result of the AND operation. - - @return The value written back to the PCI configuration register. - -**/ -UINT16 -EFIAPI -PciExpressAndThenOr16 ( - IN UINTN Address, - IN UINT16 AndData, - IN UINT16 OrData - ) -{ - ASSERT_INVALID_PCI_ADDRESS (Address); - return MmioAndThenOr16 ( - (UINTN)GetPciExpressAddress (Address), - AndData, - OrData - ); -} - -/** - Reads a bit field of a PCI configuration register. - - Reads the bit field in a 16-bit PCI configuration register. The bit field is - specified by the StartBit and the EndBit. The value of the bit field is - returned. - - If Address > 0x0FFFFFFF, then ASSERT(). - If Address is not aligned on a 16-bit boundary, then ASSERT(). - If StartBit is greater than 15, then ASSERT(). - If EndBit is greater than 15, then ASSERT(). - If EndBit is less than StartBit, then ASSERT(). - - @param Address The PCI configuration register to read. - @param StartBit The ordinal of the least significant bit in the bit field. - Range 0..15. - @param EndBit The ordinal of the most significant bit in the bit field. - Range 0..15. - - @return The value of the bit field read from the PCI configuration register. - -**/ -UINT16 -EFIAPI -PciExpressBitFieldRead16 ( - IN UINTN Address, - IN UINTN StartBit, - IN UINTN EndBit - ) -{ - ASSERT_INVALID_PCI_ADDRESS (Address); - return MmioBitFieldRead16 ( - (UINTN)GetPciExpressAddress (Address), - StartBit, - EndBit - ); -} - -/** - Writes a bit field to a PCI configuration register. - - Writes Value to the bit field of the PCI configuration register. The bit - field is specified by the StartBit and the EndBit. All other bits in the - destination PCI configuration register are preserved. The new value of the - 16-bit register is returned. - - If Address > 0x0FFFFFFF, then ASSERT(). - If Address is not aligned on a 16-bit boundary, then ASSERT(). - If StartBit is greater than 15, then ASSERT(). - If EndBit is greater than 15, then ASSERT(). - If EndBit is less than StartBit, then ASSERT(). - If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). - - @param Address The PCI configuration register to write. - @param StartBit The ordinal of the least significant bit in the bit field. - Range 0..15. - @param EndBit The ordinal of the most significant bit in the bit field. - Range 0..15. - @param Value The new value of the bit field. - - @return The value written back to the PCI configuration register. - -**/ -UINT16 -EFIAPI -PciExpressBitFieldWrite16 ( - IN UINTN Address, - IN UINTN StartBit, - IN UINTN EndBit, - IN UINT16 Value - ) -{ - ASSERT_INVALID_PCI_ADDRESS (Address); - return MmioBitFieldWrite16 ( - (UINTN)GetPciExpressAddress (Address), - StartBit, - EndBit, - Value - ); -} - -/** - Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and - writes the result back to the bit field in the 16-bit port. - - Reads the 16-bit PCI configuration register specified by Address, performs a - bitwise OR between the read result and the value specified by - OrData, and writes the result to the 16-bit PCI configuration register - specified by Address. The value written to the PCI configuration register is - returned. This function must guarantee that all PCI read and write operations - are serialized. Extra left bits in OrData are stripped. - - If Address > 0x0FFFFFFF, then ASSERT(). - If Address is not aligned on a 16-bit boundary, then ASSERT(). - If StartBit is greater than 15, then ASSERT(). - If EndBit is greater than 15, then ASSERT(). - If EndBit is less than StartBit, then ASSERT(). - If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). - - @param Address The PCI configuration register to write. - @param StartBit The ordinal of the least significant bit in the bit field. - Range 0..15. - @param EndBit The ordinal of the most significant bit in the bit field. - Range 0..15. - @param OrData The value to OR with the PCI configuration register. - - @return The value written back to the PCI configuration register. - -**/ -UINT16 -EFIAPI -PciExpressBitFieldOr16 ( - IN UINTN Address, - IN UINTN StartBit, - IN UINTN EndBit, - IN UINT16 OrData - ) -{ - ASSERT_INVALID_PCI_ADDRESS (Address); - return MmioBitFieldOr16 ( - (UINTN)GetPciExpressAddress (Address), - StartBit, - EndBit, - OrData - ); -} - -/** - Reads a bit field in a 16-bit PCI configuration register, performs a bitwise - AND, and writes the result back to the bit field in the 16-bit register. - - Reads the 16-bit PCI configuration register specified by Address, performs a - bitwise AND between the read result and the value specified by AndData, and - writes the result to the 16-bit PCI configuration register specified by - Address. The value written to the PCI configuration register is returned. - This function must guarantee that all PCI read and write operations are - serialized. Extra left bits in AndData are stripped. - - If Address > 0x0FFFFFFF, then ASSERT(). - If Address is not aligned on a 16-bit boundary, then ASSERT(). - If StartBit is greater than 15, then ASSERT(). - If EndBit is greater than 15, then ASSERT(). - If EndBit is less than StartBit, then ASSERT(). - If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). - - @param Address The PCI configuration register to write. - @param StartBit The ordinal of the least significant bit in the bit field. - Range 0..15. - @param EndBit The ordinal of the most significant bit in the bit field. - Range 0..15. - @param AndData The value to AND with the PCI configuration register. - - @return The value written back to the PCI configuration register. - -**/ -UINT16 -EFIAPI -PciExpressBitFieldAnd16 ( - IN UINTN Address, - IN UINTN StartBit, - IN UINTN EndBit, - IN UINT16 AndData - ) -{ - ASSERT_INVALID_PCI_ADDRESS (Address); - return MmioBitFieldAnd16 ( - (UINTN)GetPciExpressAddress (Address), - StartBit, - EndBit, - AndData - ); -} - -/** - Reads a bit field in a 16-bit port, performs a bitwise AND followed by a - bitwise OR, and writes the result back to the bit field in the - 16-bit port. - - Reads the 16-bit PCI configuration register specified by Address, performs a - bitwise AND followed by a bitwise OR between the read result and - the value specified by AndData, and writes the result to the 16-bit PCI - configuration register specified by Address. The value written to the PCI - configuration register is returned. This function must guarantee that all PCI - read and write operations are serialized. Extra left bits in both AndData and - OrData are stripped. - - If Address > 0x0FFFFFFF, then ASSERT(). - If Address is not aligned on a 16-bit boundary, then ASSERT(). - If StartBit is greater than 15, then ASSERT(). - If EndBit is greater than 15, then ASSERT(). - If EndBit is less than StartBit, then ASSERT(). - If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). - If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). - - @param Address The PCI configuration register to write. - @param StartBit The ordinal of the least significant bit in the bit field. - Range 0..15. - @param EndBit The ordinal of the most significant bit in the bit field. - Range 0..15. - @param AndData The value to AND with the PCI configuration register. - @param OrData The value to OR with the result of the AND operation. - - @return The value written back to the PCI configuration register. - -**/ -UINT16 -EFIAPI -PciExpressBitFieldAndThenOr16 ( - IN UINTN Address, - IN UINTN StartBit, - IN UINTN EndBit, - IN UINT16 AndData, - IN UINT16 OrData - ) -{ - ASSERT_INVALID_PCI_ADDRESS (Address); - return MmioBitFieldAndThenOr16 ( - (UINTN)GetPciExpressAddress (Address), - StartBit, - EndBit, - AndData, - OrData - ); -} - -/** - Reads a 32-bit PCI configuration register. - - Reads and returns the 32-bit PCI configuration register specified by Address. - This function must guarantee that all PCI read and write operations are - serialized. - - If Address > 0x0FFFFFFF, then ASSERT(). - If Address is not aligned on a 32-bit boundary, then ASSERT(). - - @param Address The address that encodes the PCI Bus, Device, Function and - Register. - - @return The read value from the PCI configuration register. - -**/ -UINT32 -EFIAPI -PciExpressRead32 ( - IN UINTN Address - ) -{ - ASSERT_INVALID_PCI_ADDRESS (Address); - return MmioRead32 ((UINTN)GetPciExpressAddress (Address)); -} - -/** - Writes a 32-bit PCI configuration register. - - Writes the 32-bit PCI configuration register specified by Address with the - value specified by Value. Value is returned. This function must guarantee - that all PCI read and write operations are serialized. - - If Address > 0x0FFFFFFF, then ASSERT(). - If Address is not aligned on a 32-bit boundary, then ASSERT(). - - @param Address The address that encodes the PCI Bus, Device, Function and - Register. - @param Value The value to write. - - @return The value written to the PCI configuration register. - -**/ -UINT32 -EFIAPI -PciExpressWrite32 ( - IN UINTN Address, - IN UINT32 Value - ) -{ - ASSERT_INVALID_PCI_ADDRESS (Address); - return MmioWrite32 ((UINTN)GetPciExpressAddress (Address), Value); -} - -/** - Performs a bitwise OR of a 32-bit PCI configuration register with - a 32-bit value. - - Reads the 32-bit PCI configuration register specified by Address, performs a - bitwise OR between the read result and the value specified by - OrData, and writes the result to the 32-bit PCI configuration register - specified by Address. The value written to the PCI configuration register is - returned. This function must guarantee that all PCI read and write operations - are serialized. - - If Address > 0x0FFFFFFF, then ASSERT(). - If Address is not aligned on a 32-bit boundary, then ASSERT(). - - @param Address The address that encodes the PCI Bus, Device, Function and - Register. - @param OrData The value to OR with the PCI configuration register. - - @return The value written back to the PCI configuration register. - -**/ -UINT32 -EFIAPI -PciExpressOr32 ( - IN UINTN Address, - IN UINT32 OrData - ) -{ - ASSERT_INVALID_PCI_ADDRESS (Address); - return MmioOr32 ((UINTN)GetPciExpressAddress (Address), OrData); -} - -/** - Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit - value. - - Reads the 32-bit PCI configuration register specified by Address, performs a - bitwise AND between the read result and the value specified by AndData, and - writes the result to the 32-bit PCI configuration register specified by - Address. The value written to the PCI configuration register is returned. - This function must guarantee that all PCI read and write operations are - serialized. - - If Address > 0x0FFFFFFF, then ASSERT(). - If Address is not aligned on a 32-bit boundary, then ASSERT(). - - @param Address The address that encodes the PCI Bus, Device, Function and - Register. - @param AndData The value to AND with the PCI configuration register. - - @return The value written back to the PCI configuration register. - -**/ -UINT32 -EFIAPI -PciExpressAnd32 ( - IN UINTN Address, - IN UINT32 AndData - ) -{ - ASSERT_INVALID_PCI_ADDRESS (Address); - return MmioAnd32 ((UINTN)GetPciExpressAddress (Address), AndData); -} - -/** - Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit - value, followed a bitwise OR with another 32-bit value. - - Reads the 32-bit PCI configuration register specified by Address, performs a - bitwise AND between the read result and the value specified by AndData, - performs a bitwise OR between the result of the AND operation and - the value specified by OrData, and writes the result to the 32-bit PCI - configuration register specified by Address. The value written to the PCI - configuration register is returned. This function must guarantee that all PCI - read and write operations are serialized. - - If Address > 0x0FFFFFFF, then ASSERT(). - If Address is not aligned on a 32-bit boundary, then ASSERT(). - - @param Address The address that encodes the PCI Bus, Device, Function and - Register. - @param AndData The value to AND with the PCI configuration register. - @param OrData The value to OR with the result of the AND operation. - - @return The value written back to the PCI configuration register. - -**/ -UINT32 -EFIAPI -PciExpressAndThenOr32 ( - IN UINTN Address, - IN UINT32 AndData, - IN UINT32 OrData - ) -{ - ASSERT_INVALID_PCI_ADDRESS (Address); - return MmioAndThenOr32 ( - (UINTN)GetPciExpressAddress (Address), - AndData, - OrData - ); -} - -/** - Reads a bit field of a PCI configuration register. - - Reads the bit field in a 32-bit PCI configuration register. The bit field is - specified by the StartBit and the EndBit. The value of the bit field is - returned. - - If Address > 0x0FFFFFFF, then ASSERT(). - If Address is not aligned on a 32-bit boundary, then ASSERT(). - If StartBit is greater than 31, then ASSERT(). - If EndBit is greater than 31, then ASSERT(). - If EndBit is less than StartBit, then ASSERT(). - - @param Address The PCI configuration register to read. - @param StartBit The ordinal of the least significant bit in the bit field. - Range 0..31. - @param EndBit The ordinal of the most significant bit in the bit field. - Range 0..31. - - @return The value of the bit field read from the PCI configuration register. - -**/ -UINT32 -EFIAPI -PciExpressBitFieldRead32 ( - IN UINTN Address, - IN UINTN StartBit, - IN UINTN EndBit - ) -{ - ASSERT_INVALID_PCI_ADDRESS (Address); - return MmioBitFieldRead32 ( - (UINTN)GetPciExpressAddress (Address), - StartBit, - EndBit - ); -} - -/** - Writes a bit field to a PCI configuration register. - - Writes Value to the bit field of the PCI configuration register. The bit - field is specified by the StartBit and the EndBit. All other bits in the - destination PCI configuration register are preserved. The new value of the - 32-bit register is returned. - - If Address > 0x0FFFFFFF, then ASSERT(). - If Address is not aligned on a 32-bit boundary, then ASSERT(). - If StartBit is greater than 31, then ASSERT(). - If EndBit is greater than 31, then ASSERT(). - If EndBit is less than StartBit, then ASSERT(). - If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). - - @param Address The PCI configuration register to write. - @param StartBit The ordinal of the least significant bit in the bit field. - Range 0..31. - @param EndBit The ordinal of the most significant bit in the bit field. - Range 0..31. - @param Value The new value of the bit field. - - @return The value written back to the PCI configuration register. - -**/ -UINT32 -EFIAPI -PciExpressBitFieldWrite32 ( - IN UINTN Address, - IN UINTN StartBit, - IN UINTN EndBit, - IN UINT32 Value - ) -{ - ASSERT_INVALID_PCI_ADDRESS (Address); - return MmioBitFieldWrite32 ( - (UINTN)GetPciExpressAddress (Address), - StartBit, - EndBit, - Value - ); -} - -/** - Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and - writes the result back to the bit field in the 32-bit port. - - Reads the 32-bit PCI configuration register specified by Address, performs a - bitwise OR between the read result and the value specified by - OrData, and writes the result to the 32-bit PCI configuration register - specified by Address. The value written to the PCI configuration register is - returned. This function must guarantee that all PCI read and write operations - are serialized. Extra left bits in OrData are stripped. - - If Address > 0x0FFFFFFF, then ASSERT(). - If Address is not aligned on a 32-bit boundary, then ASSERT(). - If StartBit is greater than 31, then ASSERT(). - If EndBit is greater than 31, then ASSERT(). - If EndBit is less than StartBit, then ASSERT(). - If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). - - @param Address The PCI configuration register to write. - @param StartBit The ordinal of the least significant bit in the bit field. - Range 0..31. - @param EndBit The ordinal of the most significant bit in the bit field. - Range 0..31. - @param OrData The value to OR with the PCI configuration register. - - @return The value written back to the PCI configuration register. - -**/ -UINT32 -EFIAPI -PciExpressBitFieldOr32 ( - IN UINTN Address, - IN UINTN StartBit, - IN UINTN EndBit, - IN UINT32 OrData - ) -{ - ASSERT_INVALID_PCI_ADDRESS (Address); - return MmioBitFieldOr32 ( - (UINTN)GetPciExpressAddress (Address), - StartBit, - EndBit, - OrData - ); -} - -/** - Reads a bit field in a 32-bit PCI configuration register, performs a bitwise - AND, and writes the result back to the bit field in the 32-bit register. - - Reads the 32-bit PCI configuration register specified by Address, performs a - bitwise AND between the read result and the value specified by AndData, and - writes the result to the 32-bit PCI configuration register specified by - Address. The value written to the PCI configuration register is returned. - This function must guarantee that all PCI read and write operations are - serialized. Extra left bits in AndData are stripped. - - If Address > 0x0FFFFFFF, then ASSERT(). - If Address is not aligned on a 32-bit boundary, then ASSERT(). - If StartBit is greater than 31, then ASSERT(). - If EndBit is greater than 31, then ASSERT(). - If EndBit is less than StartBit, then ASSERT(). - If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). - - @param Address The PCI configuration register to write. - @param StartBit The ordinal of the least significant bit in the bit field. - Range 0..31. - @param EndBit The ordinal of the most significant bit in the bit field. - Range 0..31. - @param AndData The value to AND with the PCI configuration register. - - @return The value written back to the PCI configuration register. - -**/ -UINT32 -EFIAPI -PciExpressBitFieldAnd32 ( - IN UINTN Address, - IN UINTN StartBit, - IN UINTN EndBit, - IN UINT32 AndData - ) -{ - ASSERT_INVALID_PCI_ADDRESS (Address); - return MmioBitFieldAnd32 ( - (UINTN)GetPciExpressAddress (Address), - StartBit, - EndBit, - AndData - ); -} - -/** - Reads a bit field in a 32-bit port, performs a bitwise AND followed by a - bitwise OR, and writes the result back to the bit field in the - 32-bit port. - - Reads the 32-bit PCI configuration register specified by Address, performs a - bitwise AND followed by a bitwise OR between the read result and - the value specified by AndData, and writes the result to the 32-bit PCI - configuration register specified by Address. The value written to the PCI - configuration register is returned. This function must guarantee that all PCI - read and write operations are serialized. Extra left bits in both AndData and - OrData are stripped. - - If Address > 0x0FFFFFFF, then ASSERT(). - If Address is not aligned on a 32-bit boundary, then ASSERT(). - If StartBit is greater than 31, then ASSERT(). - If EndBit is greater than 31, then ASSERT(). - If EndBit is less than StartBit, then ASSERT(). - If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). - If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). - - @param Address The PCI configuration register to write. - @param StartBit The ordinal of the least significant bit in the bit field. - Range 0..31. - @param EndBit The ordinal of the most significant bit in the bit field. - Range 0..31. - @param AndData The value to AND with the PCI configuration register. - @param OrData The value to OR with the result of the AND operation. - - @return The value written back to the PCI configuration register. - -**/ -UINT32 -EFIAPI -PciExpressBitFieldAndThenOr32 ( - IN UINTN Address, - IN UINTN StartBit, - IN UINTN EndBit, - IN UINT32 AndData, - IN UINT32 OrData - ) -{ - ASSERT_INVALID_PCI_ADDRESS (Address); - return MmioBitFieldAndThenOr32 ( - (UINTN)GetPciExpressAddress (Address), - StartBit, - EndBit, - AndData, - OrData - ); -} - -/** - Reads a range of PCI configuration registers into a caller supplied buffer. - - Reads the range of PCI configuration registers specified by StartAddress and - Size into the buffer specified by Buffer. This function only allows the PCI - configuration registers from a single PCI function to be read. Size is - returned. When possible 32-bit PCI configuration read cycles are used to read - from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit - and 16-bit PCI configuration read cycles may be used at the beginning and the - end of the range. - - If StartAddress > 0x0FFFFFFF, then ASSERT(). - If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT(). - If Size > 0 and Buffer is NULL, then ASSERT(). - - @param StartAddress The starting address that encodes the PCI Bus, Device, - Function and Register. - @param Size The size in bytes of the transfer. - @param Buffer The pointer to a buffer receiving the data read. - - @return Size read data from StartAddress. - -**/ -UINTN -EFIAPI -PciExpressReadBuffer ( - IN UINTN StartAddress, - IN UINTN Size, - OUT VOID *Buffer - ) -{ - UINTN ReturnValue; - - ASSERT_INVALID_PCI_ADDRESS (StartAddress); - ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000); - - if (Size == 0) { - return Size; - } - - ASSERT (Buffer != NULL); - - // - // Save Size for return - // - ReturnValue = Size; - - if ((StartAddress & 1) != 0) { - // - // Read a byte if StartAddress is byte aligned - // - *(volatile UINT8 *)Buffer = PciExpressRead8 (StartAddress); - StartAddress += sizeof (UINT8); - Size -= sizeof (UINT8); - Buffer = (UINT8*)Buffer + 1; - } - - if (Size >= sizeof (UINT16) && (StartAddress & 2) != 0) { - // - // Read a word if StartAddress is word aligned - // - WriteUnaligned16 ((UINT16 *) Buffer, (UINT16) PciExpressRead16 (StartAddress)); - - StartAddress += sizeof (UINT16); - Size -= sizeof (UINT16); - Buffer = (UINT16*)Buffer + 1; - } - - while (Size >= sizeof (UINT32)) { - // - // Read as many double words as possible - // - WriteUnaligned32 ((UINT32 *) Buffer, (UINT32) PciExpressRead32 (StartAddress)); - - StartAddress += sizeof (UINT32); - Size -= sizeof (UINT32); - Buffer = (UINT32*)Buffer + 1; - } - - if (Size >= sizeof (UINT16)) { - // - // Read the last remaining word if exist - // - WriteUnaligned16 ((UINT16 *) Buffer, (UINT16) PciExpressRead16 (StartAddress)); - StartAddress += sizeof (UINT16); - Size -= sizeof (UINT16); - Buffer = (UINT16*)Buffer + 1; - } - - if (Size >= sizeof (UINT8)) { - // - // Read the last remaining byte if exist - // - *(volatile UINT8 *)Buffer = PciExpressRead8 (StartAddress); - } - - return ReturnValue; -} - -/** - Copies the data in a caller supplied buffer to a specified range of PCI - configuration space. - - Writes the range of PCI configuration registers specified by StartAddress and - Size from the buffer specified by Buffer. This function only allows the PCI - configuration registers from a single PCI function to be written. Size is - returned. When possible 32-bit PCI configuration write cycles are used to - write from StartAdress to StartAddress + Size. Due to alignment restrictions, - 8-bit and 16-bit PCI configuration write cycles may be used at the beginning - and the end of the range. - - If StartAddress > 0x0FFFFFFF, then ASSERT(). - If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT(). - If Size > 0 and Buffer is NULL, then ASSERT(). - - @param StartAddress The starting address that encodes the PCI Bus, Device, - Function and Register. - @param Size The size in bytes of the transfer. - @param Buffer The pointer to a buffer containing the data to write. - - @return Size written to StartAddress. - -**/ -UINTN -EFIAPI -PciExpressWriteBuffer ( - IN UINTN StartAddress, - IN UINTN Size, - IN VOID *Buffer - ) -{ - UINTN ReturnValue; - - ASSERT_INVALID_PCI_ADDRESS (StartAddress); - ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000); - - if (Size == 0) { - return 0; - } - - ASSERT (Buffer != NULL); - - // - // Save Size for return - // - ReturnValue = Size; - - if ((StartAddress & 1) != 0) { - // - // Write a byte if StartAddress is byte aligned - // - PciExpressWrite8 (StartAddress, *(UINT8*)Buffer); - StartAddress += sizeof (UINT8); - Size -= sizeof (UINT8); - Buffer = (UINT8*)Buffer + 1; - } - - if (Size >= sizeof (UINT16) && (StartAddress & 2) != 0) { - // - // Write a word if StartAddress is word aligned - // - PciExpressWrite16 (StartAddress, ReadUnaligned16 ((UINT16*)Buffer)); - StartAddress += sizeof (UINT16); - Size -= sizeof (UINT16); - Buffer = (UINT16*)Buffer + 1; - } - - while (Size >= sizeof (UINT32)) { - // - // Write as many double words as possible - // - PciExpressWrite32 (StartAddress, ReadUnaligned32 ((UINT32*)Buffer)); - StartAddress += sizeof (UINT32); - Size -= sizeof (UINT32); - Buffer = (UINT32*)Buffer + 1; - } - - if (Size >= sizeof (UINT16)) { - // - // Write the last remaining word if exist - // - PciExpressWrite16 (StartAddress, ReadUnaligned16 ((UINT16*)Buffer)); - StartAddress += sizeof (UINT16); - Size -= sizeof (UINT16); - Buffer = (UINT16*)Buffer + 1; - } - - if (Size >= sizeof (UINT8)) { - // - // Write the last remaining byte if exist - // - PciExpressWrite8 (StartAddress, *(UINT8*)Buffer); - } - - return ReturnValue; -} diff --git a/Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciExpressLib/PciExpressLib.inf b/Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciExpressLib/PciExpressLib.inf deleted file mode 100644 index acb6fb6219..0000000000 --- a/Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciExpressLib/PciExpressLib.inf +++ /dev/null @@ -1,56 +0,0 @@ -## @file -# Instance of PCI Express Library using the 256 MB PCI Express MMIO window. -# -# PCI Express Library that uses the 256 MB PCI Express MMIO window to perform -# PCI Configuration cycles. Layers on top of an I/O Library instance. -# -# Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved. -# -# This library is inherited from MdePkg/Library/BasePciExpressLib. On -# NeoverseN1 SoC, with the unmodified version of this library, a slave error is -# generated when host accesses the config space of a non-available device or -# unimplemented function on a given bus. In order to resolve this for -# NeoverseN1 SoC, a modified version of the MdePkg/Library/BasePciExpressLib -# library is used. The modification includes a check to determine whether the -# incoming PCI address can be safely accessed. -# -# In addition to this, the NeoverseN1 SoC has two other limitations which -# affect the access to the PCIe root port: -# 1. ECAM space is not contiguous, root port ECAM (BDF = 0:0:0) is isolated -# from rest of the downstream hierarchy ECAM space. -# 2. Root port ECAM space is not capable of 8bit/16bit writes. -# This library includes workaround for these limitations as well. -# -# Copyright (c) 2020, ARM Limited. All rights reserved. -# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# -## - -[Defines] - INF_VERSION = 0x0001001A - BASE_NAME = BasePciExpressLib - FILE_GUID = b378dd06-de7f-4e8c-8fb0-5126adfb34bf - MODULE_TYPE = BASE - VERSION_STRING = 1.0 - LIBRARY_CLASS = PciExpressLib - -[Sources] - PciExpressLib.c - -[Packages] - MdePkg/MdePkg.dec - Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec - -[FixedPcd] - gArmNeoverseN1SocTokenSpaceGuid.PcdPcieRootPortConfigBaseAddress - gArmNeoverseN1SocTokenSpaceGuid.PcdPcieRootPortConfigBaseSize - -[LibraryClasses] - BaseLib - DebugLib - IoLib - PcdLib - -[Pcd] - gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## CONSUMES -- 2.17.1