From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by mx.groups.io with SMTP id smtpd.web10.46292.1640743855756983953 for ; Tue, 28 Dec 2021 18:10:55 -0800 Authentication-Results: mx.groups.io; dkim=fail reason="unable to parse pub key" header.i=@intel.com header.s=intel header.b=ekWxMnlf; spf=pass (domain: intel.com, ip: 134.134.136.24, mailfrom: yun.lou@intel.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1640743855; x=1672279855; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=+4a1HJq15g93+ze7IXr6rurVXd4cBOHj2xslJBJH8LY=; b=ekWxMnlfP0K6ehbwfq5PzWC7Jnk2Nl7FQxysC+y9fGJ1b+yg423516/1 izlYDrcmNFb1NNfxP28HlCZmaKcRw0BVKq6F2I+1pcwQrAS6tzZnpJg/D j3FxdvPZRaCt1uxajOLCr1fql6HZT7/XUaAURT7FF1cVxHneZJb5eAsoH BtWFwRKG2lMzZEbssfM3HOmw2h//wZkjWyRb5CRgaeDLI2p/wBgAD3WCy 06Xnin3tUVMi/9wiok163UVH8aGnB0psHRJ8a8yF1/V/UOYcdKPypQl0Y FkqWGaIWT6oN3bawhh791O7EXk4G7utBQm/zj7NlIEz9jhljjnrm2TX6p A==; X-IronPort-AV: E=McAfee;i="6200,9189,10211"; a="241251928" X-IronPort-AV: E=Sophos;i="5.88,244,1635231600"; d="scan'208";a="241251928" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Dec 2021 18:10:38 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.88,244,1635231600"; d="scan'208";a="761247335" Received: from shwdeopenlab102.ccr.corp.intel.com ([10.239.56.73]) by fmsmga005.fm.intel.com with ESMTP; 28 Dec 2021 18:10:35 -0800 From: "Jason Lou" To: devel@edk2.groups.io Cc: Jason Lou , Ray Ni , Eric Dong , Laszlo Ersek , Rahul Kumar Subject: [PATCH v1 4/4] UefiCpuPkg: Replace Opcode with the corresponding instructions. Date: Wed, 29 Dec 2021 10:10:26 +0800 Message-Id: <20211229021026.3107-4-yun.lou@intel.com> X-Mailer: git-send-email 2.31.1.windows.1 In-Reply-To: <20211229021026.3107-1-yun.lou@intel.com> References: <20211229021026.3107-1-yun.lou@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable From: Jason Lou REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3790 Replace Opcode with the corresponding instructions. The code changes have been verified with CompareBuild.py tool, which can be used to compare the results of two different EDK II builds to determine if they generate the same binaries. (the tool link: https://github.com/mdkinney/edk2) Signed-off-by: Jason Lou Cc: Ray Ni Cc: Eric Dong Cc: Laszlo Ersek Cc: Rahul Kumar --- UefiCpuPkg/CpuDxe/X64/CpuAsm.nasm = | 4 +-- UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionHandlerAsm.nasm = | 11 +++++---- UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionTssEntryAsm.nasm = | 9 +++---- UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.nasm = | 14 +++++------ UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/Xcode5ExceptionHandlerAsm.na= sm | 26 ++++++++++---------- UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm = | 4 +-- UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/Cet.nasm = | 4 +-- UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm = | 4 +-- UefiCpuPkg/PiSmmCpuDxeSmm/X64/Cet.nasm = | 4 +-- UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm = | 4 +-- 10 files changed, 42 insertions(+), 42 deletions(-) diff --git a/UefiCpuPkg/CpuDxe/X64/CpuAsm.nasm b/UefiCpuPkg/CpuDxe/X64/CpuA= sm.nasm index 66f8857fc0..1bde01c571 100644 --- a/UefiCpuPkg/CpuDxe/X64/CpuAsm.nasm +++ b/UefiCpuPkg/CpuDxe/X64/CpuAsm.nasm @@ -1,6 +1,6 @@ ;-------------------------------------------------------------------------= -----=0D ;*=0D -;* Copyright (c) 2016, Intel Corporation. All rights reserved.
=0D +;* Copyright (c) 2016 - 2021, Intel Corporation. All rights reserved.=0D ;* SPDX-License-Identifier: BSD-2-Clause-Patent=0D ;*=0D ;* CpuAsm.nasm=0D @@ -23,7 +23,7 @@ ASM_PFX(SetCodeSelector): push rcx=0D lea rax, [setCodeSelectorLongJump]=0D push rax=0D - o64 retf=0D + retfq=0D setCodeSelectorLongJump:=0D ret=0D =0D diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionHandle= rAsm.nasm b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionHandler= Asm.nasm index 58d5312899..f3ecb5fed4 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionHandlerAsm.na= sm +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionHandlerAsm.na= sm @@ -1,5 +1,5 @@ ;-------------------------------------------------------------------------= ----- ;=0D -; Copyright (c) 2016, Intel Corporation. All rights reserved.
=0D +; Copyright (c) 2016 - 2021, Intel Corporation. All rights reserved.
=0D ; SPDX-License-Identifier: BSD-2-Clause-Patent=0D ;=0D ; Module Name:=0D @@ -32,12 +32,13 @@ ALIGN 8 ; exception handler stub table=0D ;=0D AsmIdtVectorBegin:=0D +%assign Vector 0=0D %rep 32=0D - db 0x6a ; push #VectorNum=0D - db ($ - AsmIdtVectorBegin) / ((AsmIdtVectorEnd - AsmIdtVectorBegi= n) / 32) ; VectorNum=0D + push byte %[Vector];=0D push eax=0D mov eax, ASM_PFX(CommonInterruptEntry)=0D jmp eax=0D +%assign Vector Vector+1=0D %endrep=0D AsmIdtVectorEnd:=0D =0D @@ -287,7 +288,7 @@ ErrorCodeAndVectorOnStack: test edx, BIT24 ; Test for FXSAVE/FXRESTOR support.=0D ; edx still contains result from CPUID above=0D jz .3=0D - db 0xf, 0xae, 0x7 ;fxsave [edi]=0D + fxsave [edi]=0D .3:=0D =0D ;; UEFI calling convention for IA32 requires that Direction flag in EFLAGs= is clear=0D @@ -320,7 +321,7 @@ ErrorCodeAndVectorOnStack: ; are supported=0D test edx, BIT24 ; Test for FXSAVE/FXRESTOR support=0D jz .4=0D - db 0xf, 0xae, 0xe ; fxrstor [esi]=0D + fxrstor [esi]=0D .4:=0D add esp, 512=0D =0D diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionTssEnt= ryAsm.nasm b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionTssEnt= ryAsm.nasm index dd3f74d2aa..48a6aa4a97 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionTssEntryAsm.n= asm +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionTssEntryAsm.n= asm @@ -1,5 +1,5 @@ ;-------------------------------------------------------------------------= ----- ;=0D -; Copyright (c) 2017, Intel Corporation. All rights reserved.
=0D +; Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.
=0D ; SPDX-License-Identifier: BSD-2-Clause-Patent=0D ;=0D ; Module Name:=0D @@ -79,8 +79,7 @@ AsmExceptionEntryBegin: DoIret%[Vector]:=0D iretd=0D ASM_PFX(ExceptionTaskSwtichEntry%[Vector]):=0D - db 0x6a ; push #VectorNum=0D - db %[Vector]=0D + push byte %[Vector]=0D mov eax, ASM_PFX(CommonTaskSwtichEntryPoint)=0D call eax=0D mov esp, eax ; Restore stack top=0D @@ -244,7 +243,7 @@ ASM_PFX(CommonTaskSwtichEntryPoint): clts=0D sub esp, 512=0D mov edi, esp=0D - db 0xf, 0xae, 0x7 ;fxsave [edi]=0D + fxsave [edi]=0D .3:=0D =0D ;; UINT32 ExceptionData;=0D @@ -277,7 +276,7 @@ ASM_PFX(CommonTaskSwtichEntryPoint): test edx, BIT24 ; Test for FXSAVE/FXRESTOR support=0D jz .4=0D mov esi, esp=0D - db 0xf, 0xae, 0xe ; fxrstor [esi]=0D + fxrstor [esi]=0D .4:=0D add esp, 512=0D =0D diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandler= Asm.nasm b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAs= m.nasm index 2a5545ecfd..fb23d28b13 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.nasm +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.nasm @@ -1,5 +1,5 @@ ;-------------------------------------------------------------------------= ----- ;=0D -; Copyright (c) 2012 - 2018, Intel Corporation. All rights reserved.
=0D +; Copyright (c) 2012 - 2021, Intel Corporation. All rights reserved.
=0D ; SPDX-License-Identifier: BSD-2-Clause-Patent=0D ;=0D ; Module Name:=0D @@ -32,12 +32,13 @@ SECTION .text ALIGN 8=0D =0D AsmIdtVectorBegin:=0D +%assign Vector 0=0D %rep 32=0D - db 0x6a ; push #VectorNum=0D - db ($ - AsmIdtVectorBegin) / ((AsmIdtVectorEnd - AsmIdtVectorBegi= n) / 32) ; VectorNum=0D + push byte %[Vector]=0D push rax=0D mov rax, ASM_PFX(CommonInterruptEntry)=0D jmp rax=0D +%assign Vector Vector+1=0D %endrep=0D AsmIdtVectorEnd:=0D =0D @@ -257,7 +258,7 @@ DrFinish: ;; FX_SAVE_STATE_X64 FxSaveState;=0D sub rsp, 512=0D mov rdi, rsp=0D - db 0xf, 0xae, 0x7 ;fxsave [rdi]=0D + fxsave [rdi]=0D =0D ;; UEFI calling convention for x64 requires that Direction flag in EFLAGs = is clear=0D cld=0D @@ -284,7 +285,7 @@ DrFinish: ;; FX_SAVE_STATE_X64 FxSaveState;=0D =0D mov rsi, rsp=0D - db 0xf, 0xae, 0xE ; fxrstor [rsi]=0D + fxrstor [rsi]=0D add rsp, 512=0D =0D ;; UINT64 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;=0D @@ -371,8 +372,7 @@ DoReturn: push qword [rax + 0x18] ; save EFLAGS in new location=0D mov rax, [rax] ; restore rax=0D popfq ; restore EFLAGS=0D - DB 0x48 ; prefix to composite "retq" with next "ret= f"=0D - retf ; far return=0D + retfq=0D DoIret:=0D iretq=0D =0D diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/Xcode5ExceptionH= andlerAsm.nasm b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/Xcode5Except= ionHandlerAsm.nasm index 84a12ddb88..df720f6c75 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/Xcode5ExceptionHandlerA= sm.nasm +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/Xcode5ExceptionHandlerA= sm.nasm @@ -1,5 +1,5 @@ ;-------------------------------------------------------------------------= ----- ;=0D -; Copyright (c) 2012 - 2018, Intel Corporation. All rights reserved.
=0D +; Copyright (c) 2012 - 2021, Intel Corporation. All rights reserved.
=0D ; SPDX-License-Identifier: BSD-2-Clause-Patent=0D ;=0D ; Module Name:=0D @@ -54,12 +54,13 @@ SECTION .text ALIGN 8=0D =0D AsmIdtVectorBegin:=0D +%assign Vector 0=0D %rep 32=0D - db 0x6a ; push #VectorNum=0D - db ($ - AsmIdtVectorBegin) / ((AsmIdtVectorEnd - AsmIdtVectorBegi= n) / 32) ; VectorNum=0D + push byte %[Vector]=0D push rax=0D mov rax, strict qword 0 ; mov rax, ASM_PFX(CommonInterruptE= ntry)=0D jmp rax=0D +%assign Vector Vector+1=0D %endrep=0D AsmIdtVectorEnd:=0D =0D @@ -280,7 +281,7 @@ DrFinish: ;; FX_SAVE_STATE_X64 FxSaveState;=0D sub rsp, 512=0D mov rdi, rsp=0D - db 0xf, 0xae, 0x7 ;fxsave [rdi]=0D + fxsave [rdi]=0D =0D ;; UEFI calling convention for x64 requires that Direction flag in EFLAGs = is clear=0D cld=0D @@ -335,15 +336,15 @@ DrFinish: jz CetDone=0D ; SSP should be 0xFC0 at this point=0D mov rax, 0x04 ; advance past cs:lip:prevssp;supervisor s= hadow stack token=0D - INCSSP_RAX ; After this SSP should be 0xFE0=0D - SAVEPREVSSP ; now the shadow stack restore token will = be created at 0xFB8=0D - READSSP_RAX ; Read new SSP, SSP should be 0xFE8=0D + incsspq rax ; After this SSP should be 0xFE0=0D + saveprevssp ; now the shadow stack restore token will = be created at 0xFB8=0D + rdsspq rax ; Read new SSP, SSP should be 0xFE8=0D sub rax, 0x10=0D - CLRSSBSY_RAX ; Clear token at 0xFD8, SSP should be 0 af= ter this=0D + clrssbsy [rax] ; Clear token at 0xFD8, SSP should be 0 af= ter this=0D sub rax, 0x20=0D - RSTORSSP_RAX ; Restore to token at 0xFB8, new SSP will = be 0xFB8=0D + rstorssp [rax] ; Restore to token at 0xFB8, new SSP will = be 0xFB8=0D mov rax, 0x01 ; Pop off the new save token created=0D - INCSSP_RAX ; SSP should be 0xFC0 now=0D + incsspq rax ; SSP should be 0xFC0 now=0D CetDone:=0D =0D cli=0D @@ -353,7 +354,7 @@ CetDone: ;; FX_SAVE_STATE_X64 FxSaveState;=0D =0D mov rsi, rsp=0D - db 0xf, 0xae, 0xE ; fxrstor [rsi]=0D + fxrstor [rsi]=0D add rsp, 512=0D =0D ;; UINT64 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;=0D @@ -440,8 +441,7 @@ DoReturn: push qword [rax + 0x18] ; save EFLAGS in new location=0D mov rax, [rax] ; restore rax=0D popfq ; restore EFLAGS=0D - DB 0x48 ; prefix to composite "retq" with next "re= tf"=0D - retf ; far return=0D + retfq=0D DoIret:=0D iretq=0D =0D diff --git a/UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm b/UefiCpuPkg/Lib= rary/MpInitLib/X64/MpFuncs.nasm index f7f2937faf..30ad94d341 100644 --- a/UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm +++ b/UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm @@ -345,7 +345,7 @@ BITS 64 ;=0D ; Far return into 32-bit mode=0D ;=0D -o64 retf=0D + retfq=0D =0D BITS 32=0D CompatMode:=0D @@ -507,7 +507,7 @@ NoSevEs: ;=0D ; Far return into 32-bit mode=0D ;=0D -o64 retf=0D + retfq=0D =0D BITS 32=0D PmEntry:=0D diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/Cet.nasm b/UefiCpuPkg/PiSmmCpuD= xeSmm/Ia32/Cet.nasm index 0919d6d05f..ee604e89a0 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/Cet.nasm +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/Cet.nasm @@ -1,5 +1,5 @@ ;-------------------------------------------------------------------------= ----- ;=0D -; Copyright (c) 2019, Intel Corporation. All rights reserved.
=0D +; Copyright (c) 2019 - 2021, Intel Corporation. All rights reserved.
=0D ; SPDX-License-Identifier: BSD-2-Clause-Patent=0D ;=0D ;-------------------------------------------------------------------------= ------=0D @@ -13,7 +13,7 @@ ASM_PFX(DisableCet): =0D ; Skip the pushed data for call=0D mov eax, 1=0D - INCSSP_EAX=0D + incsspd eax=0D =0D mov eax, cr4=0D btr eax, 23 ; clear CET=0D diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm b/UefiCpuPkg/PiSm= mCpuDxeSmm/Ia32/SmiEntry.nasm index 167f5e14db..5d38c1f55b 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm @@ -1,5 +1,5 @@ ;-------------------------------------------------------------------------= ----- ;=0D -; Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.
=0D +; Copyright (c) 2016 - 2021, Intel Corporation. All rights reserved.
=0D ; Copyright (c) 2020, AMD Incorporated. All rights reserved.
=0D ; SPDX-License-Identifier: BSD-2-Clause-Patent=0D ;=0D @@ -252,7 +252,7 @@ CetInterruptDone: mov eax, 0x668 | CR4_CET=0D mov cr4, eax=0D =0D - SETSSBSY=0D + setssbsy=0D =0D CetDone:=0D =0D diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/Cet.nasm b/UefiCpuPkg/PiSmmCpuDx= eSmm/X64/Cet.nasm index 3240f9d974..f23ad91132 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/Cet.nasm +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/Cet.nasm @@ -1,5 +1,5 @@ ;-------------------------------------------------------------------------= ----- ;=0D -; Copyright (c) 2019, Intel Corporation. All rights reserved.
=0D +; Copyright (c) 2019 - 2021, Intel Corporation. All rights reserved.
=0D ; SPDX-License-Identifier: BSD-2-Clause-Patent=0D ;=0D ;-------------------------------------------------------------------------= ------=0D @@ -14,7 +14,7 @@ ASM_PFX(DisableCet): =0D ; Skip the pushed data for call=0D mov rax, 1=0D - INCSSP_RAX=0D + incsspq rax=0D =0D mov rax, cr4=0D btr eax, 23 ; clear CET=0D diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm b/UefiCpuPkg/PiSmm= CpuDxeSmm/X64/SmiEntry.nasm index 0e154e5db9..f6712ce594 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm @@ -1,5 +1,5 @@ ;-------------------------------------------------------------------------= ----- ;=0D -; Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.
=0D +; Copyright (c) 2016 - 2021, Intel Corporation. All rights reserved.
=0D ; Copyright (c) 2020, AMD Incorporated. All rights reserved.
=0D ; SPDX-License-Identifier: BSD-2-Clause-Patent=0D ;=0D @@ -279,7 +279,7 @@ CetInterruptDone: mov eax, 0x668 | CR4_CET=0D mov cr4, rax=0D =0D - SETSSBSY=0D + setssbsy=0D =0D CetDone:=0D =0D --=20 2.28.0.windows.1