* [PATCH V2 01/10] Platform/RaspberryPi: Cleanup menu visibility
2022-01-02 5:49 [PATCH V2 00/10] Platform/RaspberryPi: Utilize SPI flash for EFI variables Jeremy Linton
@ 2022-01-02 5:49 ` Jeremy Linton
2022-01-02 5:49 ` [PATCH V2 02/10] Platform/RaspberryPi: Give the user control over the XHCI mailbox Jeremy Linton
` (10 subsequent siblings)
11 siblings, 0 replies; 13+ messages in thread
From: Jeremy Linton @ 2022-01-02 5:49 UTC (permalink / raw)
To: devel
Cc: pete, ardb+tianocore, leif, awarkentin, Sunny.Wang,
samer.el-haj-mahmoud, mariobalanica02, Jeremy Linton,
Ard Biesheuvel
Lets allow some of these options to change when the
system is in ACPI+DT mode. Plus the fan temp should
be disabled when ACPI isn't enabled.
Tested-by: Ard Biesheuvel <ardb@kernel.org>
Signed-off-by: Jeremy Linton <jeremy.linton@arm.com>
---
Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxeHii.vfr | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxeHii.vfr b/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxeHii.vfr
index e8bf16312d..f668b7a553 100644
--- a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxeHii.vfr
+++ b/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxeHii.vfr
@@ -196,7 +196,7 @@ formset
endoneof;
#if (RPI_MODEL == 4)
- grayoutif NOT ideqval SystemTableMode.Mode == SYSTEM_TABLE_MODE_ACPI;
+ grayoutif ideqval SystemTableMode.Mode == SYSTEM_TABLE_MODE_DT;
oneof varid = FanOnGpio.Enabled,
prompt = STRING_TOKEN(STR_ADVANCED_FANONGPIO_PROMPT),
help = STRING_TOKEN(STR_ADVANCED_FANONGPIO_HELP),
@@ -207,7 +207,7 @@ formset
endoneof;
endif;
- grayoutif ideqval FanOnGpio.Enabled == 0;
+ grayoutif ideqval FanOnGpio.Enabled == 0 OR ideqval SystemTableMode.Mode == SYSTEM_TABLE_MODE_DT;
numeric varid = FanTemp.Value,
prompt = STRING_TOKEN(STR_ADVANCED_FANTEMP_PROMPT),
help = STRING_TOKEN(STR_ADVANCED_FANTEMP_HELP),
@@ -219,7 +219,7 @@ formset
endif;
suppressif ideqval XhciPci.Value == 2;
- grayoutif NOT ideqval SystemTableMode.Mode == SYSTEM_TABLE_MODE_ACPI;
+ grayoutif ideqval SystemTableMode.Mode == SYSTEM_TABLE_MODE_DT;
oneof varid = XhciPci.Value,
prompt = STRING_TOKEN(STR_ADVANCED_XHCIPCI_PROMPT),
help = STRING_TOKEN(STR_ADVANCED_XHCIPCI_HELP),
--
2.13.7
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH V2 02/10] Platform/RaspberryPi: Give the user control over the XHCI mailbox
2022-01-02 5:49 [PATCH V2 00/10] Platform/RaspberryPi: Utilize SPI flash for EFI variables Jeremy Linton
2022-01-02 5:49 ` [PATCH V2 01/10] Platform/RaspberryPi: Cleanup menu visibility Jeremy Linton
@ 2022-01-02 5:49 ` Jeremy Linton
2022-01-02 5:49 ` [PATCH V2 03/10] Platform/RaspberryPi: Move GPIO/SPI/I2C to SSDT Jeremy Linton
` (9 subsequent siblings)
11 siblings, 0 replies; 13+ messages in thread
From: Jeremy Linton @ 2022-01-02 5:49 UTC (permalink / raw)
To: devel
Cc: pete, ardb+tianocore, leif, awarkentin, Sunny.Wang,
samer.el-haj-mahmoud, mariobalanica02, Jeremy Linton,
Ard Biesheuvel
Its a complete tossup whether removing the mailbox call after we have
set up the XHCI works for a given kernel+distro in DT mode. So lets
give users which want to try DT the option of flipping this on/off.
Users that don't want to have to deal with DT, can use ACPI.
Tested-by: Ard Biesheuvel <ardb@kernel.org>
Signed-off-by: Jeremy Linton <jeremy.linton@arm.com>
---
Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c | 10 ++++++++++
Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.inf | 1 +
Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxeHii.uni | 5 +++++
Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxeHii.vfr | 15 +++++++++++++++
Platform/RaspberryPi/Drivers/FdtDxe/FdtDxe.c | 4 ++++
Platform/RaspberryPi/Drivers/FdtDxe/FdtDxe.inf | 1 +
Platform/RaspberryPi/RPi3/RPi3.dsc | 6 ++++++
Platform/RaspberryPi/RPi4/RPi4.dsc | 7 +++++++
Platform/RaspberryPi/RaspberryPi.dec | 1 +
9 files changed, 50 insertions(+)
diff --git a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c b/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c
index 415d99fadb..bdabdec7a5 100644
--- a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c
+++ b/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c
@@ -297,6 +297,16 @@ SetupVariables (
Status = PcdSet32S (PcdXhciPci, 1);
ASSERT_EFI_ERROR (Status);
}
+
+ Size = sizeof (UINT32);
+ Status = gRT->GetVariable (L"XhciReload",
+ &gConfigDxeFormSetGuid,
+ NULL, &Size, &Var32);
+ if (EFI_ERROR (Status)) {
+ Status = PcdSet32S (PcdXhciReload, PcdGet32 (PcdXhciReload));
+ ASSERT_EFI_ERROR (Status);
+ }
+
}
} else {
/*
diff --git a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.inf b/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.inf
index e6e22ad82e..ff182e831d 100644
--- a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.inf
+++ b/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.inf
@@ -95,6 +95,7 @@
gRaspberryPiTokenSpaceGuid.PcdFanTemp
gRaspberryPiTokenSpaceGuid.PcdUartInUse
gRaspberryPiTokenSpaceGuid.PcdXhciPci
+ gRaspberryPiTokenSpaceGuid.PcdXhciReload
[Depex]
gPcdProtocolGuid AND gRaspberryPiFirmwareProtocolGuid
diff --git a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxeHii.uni b/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxeHii.uni
index 5ec17072c3..8130638876 100644
--- a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxeHii.uni
+++ b/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxeHii.uni
@@ -62,6 +62,11 @@
#string STR_ADVANCED_XHCIPCI_XHCI #language en-US "XHCI"
#string STR_ADVANCED_XHCIPCI_PCIE #language en-US "PCIe"
+#string STR_ADVANCED_XHCIRELOAD_PROMPT #language en-US "DT Reload XHCI firmware"
+#string STR_ADVANCED_XHCIRELOAD_HELP #language en-US "OS should reload XHCI firmware on reset"
+#string STR_ADVANCED_XHCIRELOAD_DISABLE #language en-US "Disabled"
+#string STR_ADVANCED_XHCIRELOAD_RELOAD #language en-US "Reload"
+
#string STR_ADVANCED_ASSET_TAG_PROMPT #language en-US "Asset Tag"
#string STR_ADVANCED_ASSET_TAG_HELP #language en-US "Set the system Asset Tag"
diff --git a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxeHii.vfr b/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxeHii.vfr
index f668b7a553..f13b70711d 100644
--- a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxeHii.vfr
+++ b/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxeHii.vfr
@@ -61,6 +61,11 @@ formset
name = XhciPci,
guid = CONFIGDXE_FORM_SET_GUID;
+ efivarstore ADVANCED_XHCIPCI_VARSTORE_DATA,
+ attribute = EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS | EFI_VARIABLE_NON_VOLATILE,
+ name = XhciReload,
+ guid = CONFIGDXE_FORM_SET_GUID;
+
efivarstore SYSTEM_TABLE_MODE_VARSTORE_DATA,
attribute = EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS | EFI_VARIABLE_NON_VOLATILE,
name = SystemTableMode,
@@ -228,6 +233,16 @@ formset
option text = STRING_TOKEN(STR_ADVANCED_XHCIPCI_PCIE), value = 1, flags = 0;
endoneof;
endif;
+
+ grayoutif ideqval SystemTableMode.Mode == SYSTEM_TABLE_MODE_ACPI;
+ oneof varid = XhciReload.Value,
+ prompt = STRING_TOKEN(STR_ADVANCED_XHCIRELOAD_PROMPT),
+ help = STRING_TOKEN(STR_ADVANCED_XHCIRELOAD_HELP),
+ flags = NUMERIC_SIZE_4 | INTERACTIVE | RESET_REQUIRED,
+ option text = STRING_TOKEN(STR_ADVANCED_XHCIRELOAD_DISABLE), value = 0, flags = DEFAULT;
+ option text = STRING_TOKEN(STR_ADVANCED_XHCIRELOAD_RELOAD), value = 1, flags = 0;
+ endoneof;
+ endif;
endif;
#endif
string varid = AssetTag.AssetTag,
diff --git a/Platform/RaspberryPi/Drivers/FdtDxe/FdtDxe.c b/Platform/RaspberryPi/Drivers/FdtDxe/FdtDxe.c
index e72d132b18..a808b1bf8c 100644
--- a/Platform/RaspberryPi/Drivers/FdtDxe/FdtDxe.c
+++ b/Platform/RaspberryPi/Drivers/FdtDxe/FdtDxe.c
@@ -375,6 +375,10 @@ SyncPcie (
return EFI_NOT_FOUND;
}
+ if (PcdGet32 (PcdXhciReload) != 1) {
+ return EFI_SUCCESS;
+ }
+
/*
* Now that we are always running without DMA translation, and with a 3G
* limit, there shouldn't be a need to reset/reload the XHCI. The
diff --git a/Platform/RaspberryPi/Drivers/FdtDxe/FdtDxe.inf b/Platform/RaspberryPi/Drivers/FdtDxe/FdtDxe.inf
index 26f84e5940..d9fb6ee480 100644
--- a/Platform/RaspberryPi/Drivers/FdtDxe/FdtDxe.inf
+++ b/Platform/RaspberryPi/Drivers/FdtDxe/FdtDxe.inf
@@ -47,3 +47,4 @@
[Pcd]
gRaspberryPiTokenSpaceGuid.PcdSystemTableMode
+ gRaspberryPiTokenSpaceGuid.PcdXhciReload
diff --git a/Platform/RaspberryPi/RPi3/RPi3.dsc b/Platform/RaspberryPi/RPi3/RPi3.dsc
index 6ab5d1ae6d..9b00327002 100644
--- a/Platform/RaspberryPi/RPi3/RPi3.dsc
+++ b/Platform/RaspberryPi/RPi3/RPi3.dsc
@@ -526,6 +526,12 @@
#
gRaspberryPiTokenSpaceGuid.PcdXhciPci|L"XhciPci"|gConfigDxeFormSetGuid|0x0|0
+ # DT contains XHCI quirk node (not valid on rpi3)
+ #
+ # 0 - DISABLED
+ #
+ gRaspberryPiTokenSpaceGuid.PcdXhciReload|L"XhciReload"|gConfigDxeFormSetGuid|0x0|0
+
#
# Common UEFI ones.
#
diff --git a/Platform/RaspberryPi/RPi4/RPi4.dsc b/Platform/RaspberryPi/RPi4/RPi4.dsc
index 44ed60ab2f..6de4407749 100644
--- a/Platform/RaspberryPi/RPi4/RPi4.dsc
+++ b/Platform/RaspberryPi/RPi4/RPi4.dsc
@@ -544,6 +544,13 @@
#
gRaspberryPiTokenSpaceGuid.PcdXhciPci|L"XhciPci"|gConfigDxeFormSetGuid|0x0|0
+ # DT contains XHCI quirk node
+ #
+ # 0 - No reload
+ # 1 - Yes, DT has Reload
+ #
+ gRaspberryPiTokenSpaceGuid.PcdXhciReload|L"XhciReload"|gConfigDxeFormSetGuid|0x0|0
+
#
# Common UEFI ones.
#
diff --git a/Platform/RaspberryPi/RaspberryPi.dec b/Platform/RaspberryPi/RaspberryPi.dec
index 797be59274..c50ebdcf77 100644
--- a/Platform/RaspberryPi/RaspberryPi.dec
+++ b/Platform/RaspberryPi/RaspberryPi.dec
@@ -72,3 +72,4 @@
gRaspberryPiTokenSpaceGuid.PcdMmcEnableDma|0|UINT32|0x0000001F
gRaspberryPiTokenSpaceGuid.PcdUartInUse|1|UINT32|0x00000021
gRaspberryPiTokenSpaceGuid.PcdXhciPci|0|UINT32|0x00000022
+ gRaspberryPiTokenSpaceGuid.PcdXhciReload|0|UINT32|0x00000023
--
2.13.7
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH V2 03/10] Platform/RaspberryPi: Move GPIO/SPI/I2C to SSDT
2022-01-02 5:49 [PATCH V2 00/10] Platform/RaspberryPi: Utilize SPI flash for EFI variables Jeremy Linton
2022-01-02 5:49 ` [PATCH V2 01/10] Platform/RaspberryPi: Cleanup menu visibility Jeremy Linton
2022-01-02 5:49 ` [PATCH V2 02/10] Platform/RaspberryPi: Give the user control over the XHCI mailbox Jeremy Linton
@ 2022-01-02 5:49 ` Jeremy Linton
2022-01-02 5:49 ` [PATCH V2 04/10] Platform/RaspberryPi: Add menu item to enable/disable GPIO Jeremy Linton
` (8 subsequent siblings)
11 siblings, 0 replies; 13+ messages in thread
From: Jeremy Linton @ 2022-01-02 5:49 UTC (permalink / raw)
To: devel
Cc: pete, ardb+tianocore, leif, awarkentin, Sunny.Wang,
samer.el-haj-mahmoud, mariobalanica02, Jeremy Linton,
Ard Biesheuvel
The UEFI firmware uses the GPIO port for the fan and
real soon now the runtime SPI variable store. As such
we need to be able to either isolate those devices from
the OS or we risk clashing with OS's that reconfigure
the GPIO pins. Ideally we would just rip this out
and use _DSM() or just individual device power
on/off methods to adjust the GPIO pins when needed.
For now, lets leave it since windows at least knows
about it. In the future we will decide whether the
firmware is controlling something (SPI!) based on
whether the user has enabled the GPIO block.
Tested-by: Ard Biesheuvel <ardb@kernel.org>
Signed-off-by: Jeremy Linton <jeremy.linton@arm.com>
---
Platform/RaspberryPi/AcpiTables/AcpiTables.inf | 1 +
Platform/RaspberryPi/AcpiTables/Dsdt.asl | 7 -
Platform/RaspberryPi/AcpiTables/GpuDevs.asl | 126 ----------------
Platform/RaspberryPi/AcpiTables/SsdtGpio.asl | 159 +++++++++++++++++++++
Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c | 6 +
5 files changed, 166 insertions(+), 133 deletions(-)
create mode 100644 Platform/RaspberryPi/AcpiTables/SsdtGpio.asl
diff --git a/Platform/RaspberryPi/AcpiTables/AcpiTables.inf b/Platform/RaspberryPi/AcpiTables/AcpiTables.inf
index da2a6db85f..3894d00565 100644
--- a/Platform/RaspberryPi/AcpiTables/AcpiTables.inf
+++ b/Platform/RaspberryPi/AcpiTables/AcpiTables.inf
@@ -40,6 +40,7 @@
SsdtThermal.asl
Xhci.asl
Pci.asl
+ SsdtGpio.asl
[Packages]
ArmPkg/ArmPkg.dec
diff --git a/Platform/RaspberryPi/AcpiTables/Dsdt.asl b/Platform/RaspberryPi/AcpiTables/Dsdt.asl
index b594d50bdf..08acc81d57 100644
--- a/Platform/RaspberryPi/AcpiTables/Dsdt.asl
+++ b/Platform/RaspberryPi/AcpiTables/Dsdt.asl
@@ -21,13 +21,6 @@
#include "AcpiTables.h"
-#define BCM_ALT0 0x4
-#define BCM_ALT1 0x5
-#define BCM_ALT2 0x6
-#define BCM_ALT3 0x7
-#define BCM_ALT4 0x3
-#define BCM_ALT5 0x2
-
//
// The ASL compiler does not support argument arithmetic in functions
// like QWordMemory (). So we need to instantiate dummy qword regions
diff --git a/Platform/RaspberryPi/AcpiTables/GpuDevs.asl b/Platform/RaspberryPi/AcpiTables/GpuDevs.asl
index 9750dc25c0..3399f0fc9a 100644
--- a/Platform/RaspberryPi/AcpiTables/GpuDevs.asl
+++ b/Platform/RaspberryPi/AcpiTables/GpuDevs.asl
@@ -203,56 +203,6 @@ Device (VCSM)
}
}
-// Description: GPIO
-Device (GPI0)
-{
- Name (_HID, "BCM2845")
- Name (_CID, "BCM2845")
- Name (_UID, 0x0)
- Name (_CCA, 0x0)
- Method (_STA)
- {
- Return(0xf)
- }
- Name (RBUF, ResourceTemplate ()
- {
- MEMORY32FIXED (ReadWrite, 0, GPIO_LENGTH, RMEM)
- Interrupt (ResourceConsumer, Level, ActiveHigh, Shared)
- {
- BCM2386_GPIO_INTERRUPT0, BCM2386_GPIO_INTERRUPT1,
- BCM2386_GPIO_INTERRUPT2, BCM2386_GPIO_INTERRUPT3
- }
- })
- Method (_CRS, 0x0, Serialized)
- {
- MEMORY32SETBASE (RBUF, RMEM, RBAS, GPIO_OFFSET)
- Return (^RBUF)
- }
-}
-
-// Description: I2C
-Device (I2C1)
-{
- Name (_HID, "BCM2841")
- Name (_CID, "BCM2841")
- Name (_UID, 0x1)
- Name (_CCA, 0x0)
- Method (_STA)
- {
- Return(0xf)
- }
- Name (RBUF, ResourceTemplate ()
- {
- MEMORY32FIXED (ReadWrite, 0, BCM2836_I2C1_LENGTH, RMEM)
- Interrupt (ResourceConsumer, Level, ActiveHigh, Shared) { BCM2836_I2C1_INTERRUPT }
- PinFunction (Exclusive, PullUp, BCM_ALT0, "\\_SB.GDV0.GPI0", 0, ResourceConsumer, , ) { 2, 3 }
- })
- Method (_CRS, 0x0, Serialized)
- {
- MEMORY32SETBASE (RBUF, RMEM, RBAS, BCM2836_I2C1_OFFSET)
- Return (^RBUF)
- }
-}
// I2C2 is the HDMI DDC connection
Device (I2C2)
@@ -278,81 +228,6 @@ Device (I2C2)
}
}
-// SPI
-Device (SPI0)
-{
- Name (_HID, "BCM2838")
- Name (_CID, "BCM2838")
- Name (_UID, 0x0)
- Name (_CCA, 0x0)
- Method (_STA)
- {
- Return (0xf)
- }
- Name (RBUF, ResourceTemplate ()
- {
- MEMORY32FIXED (ReadWrite, 0, BCM2836_SPI0_LENGTH, RMEM)
- Interrupt (ResourceConsumer, Level, ActiveHigh, Shared) { BCM2836_SPI0_INTERRUPT }
- PinFunction (Exclusive, PullDown, BCM_ALT0, "\\_SB.GDV0.GPI0", 0, ResourceConsumer, , ) { 9, 10, 11 } // MISO, MOSI, SCLK
- PinFunction (Exclusive, PullUp, BCM_ALT0, "\\_SB.GDV0.GPI0", 0, ResourceConsumer, , ) { 8 } // CE0
- PinFunction (Exclusive, PullUp, BCM_ALT0, "\\_SB.GDV0.GPI0", 0, ResourceConsumer, , ) { 7 } // CE1
- })
-
- Method (_CRS, 0x0, Serialized)
- {
- MEMORY32SETBASE (RBUF, RMEM, RBAS, BCM2836_SPI0_OFFSET)
- Return (^RBUF)
- }
-}
-
-Device (SPI1)
-{
- Name (_HID, "BCM2839")
- Name (_CID, "BCM2839")
- Name (_UID, 0x1)
- Name (_CCA, 0x0)
- Name (_DEP, Package() { \_SB.GDV0.RPIQ })
- Method (_STA)
- {
- Return (0xf)
- }
- Name (RBUF, ResourceTemplate ()
- {
- MEMORY32FIXED (ReadWrite, 0, BCM2836_SPI1_LENGTH, RMEM)
- Interrupt (ResourceConsumer, Level, ActiveHigh, Shared,) { BCM2836_SPI1_INTERRUPT }
- PinFunction (Exclusive, PullDown, BCM_ALT4, "\\_SB.GDV0.GPI0", 0, ResourceConsumer, , ) { 19, 20, 21 } // MISO, MOSI, SCLK
- PinFunction (Exclusive, PullDown, BCM_ALT4, "\\_SB.GDV0.GPI0", 0, ResourceConsumer, , ) { 16 } // CE2
- })
-
- Method (_CRS, 0x0, Serialized)
- {
- MEMORY32SETBASE (RBUF, RMEM, RBAS, BCM2836_SPI1_OFFSET)
- Return (^RBUF)
- }
-}
-
-// SPI2 has no pins on GPIO header
-// Device (SPI2)
-// {
-// Name (_HID, "BCM2839")
-// Name (_CID, "BCM2839")
-// Name (_UID, 0x2)
-// Name (_CCA, 0x0)
-// Name (_DEP, Package() { \_SB.GDV0.RPIQ })
-// Method (_STA)
-// {
-// Return (0xf) // Disabled
-// }
-// Method (_CRS, 0x0, Serialized)
-// {
-// Name (RBUF, ResourceTemplate ()
-// {
-// MEMORY32FIXED (ReadWrite, BCM2836_SPI2_BASE_ADDRESS, BCM2836_SPI2_LENGTH, RMEM)
-// Interrupt (ResourceConsumer, Level, ActiveHigh, Shared,) { BCM2836_SPI2_INTERRUPT }
-// })
-// Return (RBUF)
-// }
-// }
// PWM Driver
Device (PWM0)
@@ -393,5 +268,4 @@ Device (PWM0)
}
include ("Uart.asl")
-include ("Rhpx.asl")
include ("Sdhc.asl")
diff --git a/Platform/RaspberryPi/AcpiTables/SsdtGpio.asl b/Platform/RaspberryPi/AcpiTables/SsdtGpio.asl
new file mode 100644
index 0000000000..38e8a54a8f
--- /dev/null
+++ b/Platform/RaspberryPi/AcpiTables/SsdtGpio.asl
@@ -0,0 +1,159 @@
+/** @file
+ *
+ * Secondary System Description Table (SSDT) for the GPIO port
+ *
+ * Copyright (c) 2021, Arm Ltd. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-2-Clause-Patent
+ *
+ **/
+
+#include <IndustryStandard/Acpi.h>
+#include <IndustryStandard/Bcm2711.h>
+#include <IndustryStandard/Bcm2836.h>
+#include <IndustryStandard/Bcm2836Gpio.h>
+
+#include "AcpiTables.h"
+
+#define BCM_ALT0 0x4
+#define BCM_ALT1 0x5
+#define BCM_ALT2 0x6
+#define BCM_ALT3 0x7
+#define BCM_ALT4 0x3
+#define BCM_ALT5 0x2
+
+DefinitionBlock (__FILE__, "SSDT", 5, "RPIFDN", "RPI3GPIO", 2)
+{
+ External (\_SB_.GDV0, DeviceObj)
+ External (\_SB_.GDV0.RPIQ, DeviceObj)
+ Scope (\_SB_.GDV0)
+ {
+ include ("Rhpx.asl")
+
+ // Description: GPIO
+ Device (GPI0)
+ {
+ Name (_HID, "BCM2845")
+ Name (_CID, "BCM2845")
+ Name (_UID, 0x0)
+ Name (_CCA, 0x0)
+ Method (_STA)
+ {
+ Return(0xf)
+ }
+ Name (RBUF, ResourceTemplate ()
+ {
+ MEMORY32FIXED (ReadWrite, 0, GPIO_LENGTH, RMEM)
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared)
+ {
+ BCM2386_GPIO_INTERRUPT0, BCM2386_GPIO_INTERRUPT1,
+ BCM2386_GPIO_INTERRUPT2, BCM2386_GPIO_INTERRUPT3
+ }
+ })
+ Method (_CRS, 0x0, Serialized)
+ {
+ MEMORY32SETBASE (RBUF, RMEM, RBAS, GPIO_OFFSET)
+ Return (^RBUF)
+ }
+ }
+
+ // SPI
+ Device (SPI0)
+ {
+ Name (_HID, "BCM2838")
+ Name (_CID, "BCM2838")
+ Name (_UID, 0x0)
+ Name (_CCA, 0x0)
+ Method (_STA)
+ {
+ Return (0xf)
+ }
+ Name (RBUF, ResourceTemplate ()
+ {
+ MEMORY32FIXED (ReadWrite, 0, BCM2836_SPI0_LENGTH, RMEM)
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared) { BCM2836_SPI0_INTERRUPT }
+ PinFunction (Exclusive, PullDown, BCM_ALT0, "\\_SB.GDV0.GPI0", 0, ResourceConsumer, , ) { 9, 10, 11 } // MISO, MOSI, SCLK
+ PinFunction (Exclusive, PullUp, BCM_ALT0, "\\_SB.GDV0.GPI0", 0, ResourceConsumer, , ) { 8 } // CE0
+ PinFunction (Exclusive, PullUp, BCM_ALT0, "\\_SB.GDV0.GPI0", 0, ResourceConsumer, , ) { 7 } // CE1
+ })
+
+ Method (_CRS, 0x0, Serialized)
+ {
+ MEMORY32SETBASE (RBUF, RMEM, RBAS, BCM2836_SPI0_OFFSET)
+ Return (^RBUF)
+ }
+ }
+
+ Device (SPI1)
+ {
+ Name (_HID, "BCM2839")
+ Name (_CID, "BCM2839")
+ Name (_UID, 0x1)
+ Name (_CCA, 0x0)
+ Name (_DEP, Package() { \_SB.GDV0.RPIQ })
+ Method (_STA)
+ {
+ Return (0xf)
+ }
+ Name (RBUF, ResourceTemplate ()
+ {
+ MEMORY32FIXED (ReadWrite, 0, BCM2836_SPI1_LENGTH, RMEM)
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared,) { BCM2836_SPI1_INTERRUPT }
+ PinFunction (Exclusive, PullDown, BCM_ALT4, "\\_SB_.GDV0.GPI0", 0, ResourceConsumer, , ) { 19, 20, 21 } // MISO, MOSI, SCLK
+ PinFunction (Exclusive, PullDown, BCM_ALT4, "\\_SB_.GDV0.GPI0", 0, ResourceConsumer, , ) { 16 } // CE2
+ })
+
+ Method (_CRS, 0x0, Serialized)
+ {
+ MEMORY32SETBASE (RBUF, RMEM, RBAS, BCM2836_SPI1_OFFSET)
+ Return (^RBUF)
+ }
+ }
+
+ // SPI2 has no pins on GPIO header
+ // Device (SPI2)
+ // {
+ // Name (_HID, "BCM2839")
+ // Name (_CID, "BCM2839")
+ // Name (_UID, 0x2)
+ // Name (_CCA, 0x0)
+ // Name (_DEP, Package() { \_SB.GDV0.RPIQ })
+ // Method (_STA)
+ // {
+ // Return (0xf) // Disabled
+ // }
+ // Method (_CRS, 0x0, Serialized)
+ // {
+ // Name (RBUF, ResourceTemplate ()
+ // {
+ // MEMORY32FIXED (ReadWrite, BCM2836_SPI2_BASE_ADDRESS, BCM2836_SPI2_LENGTH, RMEM)
+ // Interrupt (ResourceConsumer, Level, ActiveHigh, Shared,) { BCM2836_SPI2_INTERRUPT }
+ // })
+ // Return (RBUF)
+ // }
+ // }
+
+ Device (I2C1)
+ {
+ Name (_HID, "BCM2841")
+ Name (_CID, "BCM2841")
+ Name (_UID, 0x1)
+ Name (_CCA, 0x0)
+ Method (_STA)
+ {
+ Return(0xf)
+ }
+ Name (RBUF, ResourceTemplate ()
+ {
+ MEMORY32FIXED (ReadWrite, 0, BCM2836_I2C1_LENGTH, RMEM)
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared) { BCM2836_I2C1_INTERRUPT }
+ PinFunction (Exclusive, PullUp, BCM_ALT0, "\\_SB_.GDV0.GPI0", 0, ResourceConsumer, , ) { 2, 3 }
+ })
+ Method (_CRS, 0x0, Serialized)
+ {
+ MEMORY32SETBASE (RBUF, RMEM, RBAS, BCM2836_I2C1_OFFSET)
+ Return (^RBUF)
+ }
+ }
+ }
+}
diff --git a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c b/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c
index bdabdec7a5..d22ecb3128 100644
--- a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c
+++ b/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c
@@ -838,6 +838,12 @@ STATIC CONST NAMESPACE_TABLES SdtTables[] = {
NULL
},
#endif
+ {
+ SIGNATURE_64 ('R', 'P', 'I', '3', 'G', 'P', 'I', 'O'),
+ 0,
+ 0,
+ NULL
+ },
{ // DSDT
SIGNATURE_64 ('R', 'P', 'I', 0, 0, 0, 0, 0),
0,
--
2.13.7
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH V2 04/10] Platform/RaspberryPi: Add menu item to enable/disable GPIO
2022-01-02 5:49 [PATCH V2 00/10] Platform/RaspberryPi: Utilize SPI flash for EFI variables Jeremy Linton
` (2 preceding siblings ...)
2022-01-02 5:49 ` [PATCH V2 03/10] Platform/RaspberryPi: Move GPIO/SPI/I2C to SSDT Jeremy Linton
@ 2022-01-02 5:49 ` Jeremy Linton
2022-01-02 5:49 ` [PATCH V2 05/10] Platform/RaspberryPi: Add constants for controlling SPI Jeremy Linton
` (7 subsequent siblings)
11 siblings, 0 replies; 13+ messages in thread
From: Jeremy Linton @ 2022-01-02 5:49 UTC (permalink / raw)
To: devel
Cc: pete, ardb+tianocore, leif, awarkentin, Sunny.Wang,
samer.el-haj-mahmoud, mariobalanica02, Jeremy Linton,
Ard Biesheuvel
Now that the GPIO devices are in their own SSDT lets add
a menu item for the rpi4 to enable/disable it. For the
rpi3 the SSDT is always exported.
Tested-by: Ard Biesheuvel <ardb@kernel.org>
Signed-off-by: Jeremy Linton <jeremy.linton@arm.com>
---
Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c | 17 ++++++++++++++++-
Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.inf | 1 +
Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxeHii.uni | 5 +++++
Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxeHii.vfr | 15 +++++++++++++++
Platform/RaspberryPi/Include/ConfigVars.h | 4 ++++
Platform/RaspberryPi/RPi3/RPi3.dsc | 6 ++++++
Platform/RaspberryPi/RPi4/RPi4.dsc | 7 +++++++
Platform/RaspberryPi/RaspberryPi.dec | 1 +
8 files changed, 55 insertions(+), 1 deletion(-)
diff --git a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c b/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c
index d22ecb3128..de7eb769ea 100644
--- a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c
+++ b/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c
@@ -308,12 +308,27 @@ SetupVariables (
}
}
+
+ Size = sizeof (UINT32);
+ Status = gRT->GetVariable (L"EnableGpio",
+ &gConfigDxeFormSetGuid,
+ NULL, &Size, &Var32);
+ if (EFI_ERROR (Status)) {
+ Status = PcdSet32S (PcdEnableGpio, PcdGet32 (PcdEnableGpio));
+ ASSERT_EFI_ERROR (Status);
+ }
+
} else {
/*
* Disable PCIe and XHCI
*/
Status = PcdSet32S (PcdXhciPci, 0);
ASSERT_EFI_ERROR (Status);
+ /*
+ * Enable GPIO
+ */
+ Status = PcdSet32S (PcdEnableGpio, 1);
+ ASSERT_EFI_ERROR (Status);
}
Size = sizeof (AssetTagVar);
@@ -840,7 +855,7 @@ STATIC CONST NAMESPACE_TABLES SdtTables[] = {
#endif
{
SIGNATURE_64 ('R', 'P', 'I', '3', 'G', 'P', 'I', 'O'),
- 0,
+ PcdToken (PcdEnableGpio),
0,
NULL
},
diff --git a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.inf b/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.inf
index ff182e831d..1cba4a2a22 100644
--- a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.inf
+++ b/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.inf
@@ -96,6 +96,7 @@
gRaspberryPiTokenSpaceGuid.PcdUartInUse
gRaspberryPiTokenSpaceGuid.PcdXhciPci
gRaspberryPiTokenSpaceGuid.PcdXhciReload
+ gRaspberryPiTokenSpaceGuid.PcdEnableGpio
[Depex]
gPcdProtocolGuid AND gRaspberryPiFirmwareProtocolGuid
diff --git a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxeHii.uni b/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxeHii.uni
index 8130638876..fb06d46a61 100644
--- a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxeHii.uni
+++ b/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxeHii.uni
@@ -67,6 +67,11 @@
#string STR_ADVANCED_XHCIRELOAD_DISABLE #language en-US "Disabled"
#string STR_ADVANCED_XHCIRELOAD_RELOAD #language en-US "Reload"
+#string STR_ADVANCED_ENABLEGPIO_PROMPT #language en-US "Export GPIO devices to OS"
+#string STR_ADVANCED_ENABLEGPIO_HELP #language en-US "OS can see the GPIO device and some low level SPI and I2C interfaces. Enabling this option will disable runtime variable support."
+#string STR_ADVANCED_ENABLEGPIO_DISABLE #language en-US "Disabled"
+#string STR_ADVANCED_ENABLEGPIO_ENABLE #language en-US "Enable"
+
#string STR_ADVANCED_ASSET_TAG_PROMPT #language en-US "Asset Tag"
#string STR_ADVANCED_ASSET_TAG_HELP #language en-US "Set the system Asset Tag"
diff --git a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxeHii.vfr b/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxeHii.vfr
index f13b70711d..04eb0a15a2 100644
--- a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxeHii.vfr
+++ b/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxeHii.vfr
@@ -66,6 +66,11 @@ formset
name = XhciReload,
guid = CONFIGDXE_FORM_SET_GUID;
+ efivarstore ADVANCED_ENABLEGPIO_VARSTORE_DATA,
+ attribute = EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS | EFI_VARIABLE_NON_VOLATILE,
+ name = EnableGpio,
+ guid = CONFIGDXE_FORM_SET_GUID;
+
efivarstore SYSTEM_TABLE_MODE_VARSTORE_DATA,
attribute = EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS | EFI_VARIABLE_NON_VOLATILE,
name = SystemTableMode,
@@ -244,6 +249,16 @@ formset
endoneof;
endif;
endif;
+
+ grayoutif ideqval SystemTableMode.Mode == SYSTEM_TABLE_MODE_DT;
+ oneof varid = EnableGpio.Value,
+ prompt = STRING_TOKEN(STR_ADVANCED_ENABLEGPIO_PROMPT),
+ help = STRING_TOKEN(STR_ADVANCED_ENABLEGPIO_HELP),
+ flags = NUMERIC_SIZE_4 | INTERACTIVE | RESET_REQUIRED,
+ option text = STRING_TOKEN(STR_ADVANCED_ENABLEGPIO_DISABLE), value = 0, flags = DEFAULT;
+ option text = STRING_TOKEN(STR_ADVANCED_ENABLEGPIO_ENABLE), value = 1, flags = 0;
+ endoneof;
+ endif;
#endif
string varid = AssetTag.AssetTag,
prompt = STRING_TOKEN(STR_ADVANCED_ASSET_TAG_PROMPT),
diff --git a/Platform/RaspberryPi/Include/ConfigVars.h b/Platform/RaspberryPi/Include/ConfigVars.h
index a5b32b5284..43a39891d4 100644
--- a/Platform/RaspberryPi/Include/ConfigVars.h
+++ b/Platform/RaspberryPi/Include/ConfigVars.h
@@ -81,6 +81,10 @@ typedef struct {
} ADVANCED_XHCIPCI_VARSTORE_DATA;
typedef struct {
+ UINT32 Value;
+} ADVANCED_ENABLEGPIO_VARSTORE_DATA;
+
+typedef struct {
#define SYSTEM_TABLE_MODE_ACPI 0
#define SYSTEM_TABLE_MODE_BOTH 1
#define SYSTEM_TABLE_MODE_DT 2
diff --git a/Platform/RaspberryPi/RPi3/RPi3.dsc b/Platform/RaspberryPi/RPi3/RPi3.dsc
index 9b00327002..9db4d93735 100644
--- a/Platform/RaspberryPi/RPi3/RPi3.dsc
+++ b/Platform/RaspberryPi/RPi3/RPi3.dsc
@@ -532,6 +532,12 @@
#
gRaspberryPiTokenSpaceGuid.PcdXhciReload|L"XhciReload"|gConfigDxeFormSetGuid|0x0|0
+ # Export GPIO block to OS
+ #
+ # 1 - Yes (for legacy reasons)
+ #
+ gRaspberryPiTokenSpaceGuid.PcdEnableGpio|L"EnableGpio"|gConfigDxeFormSetGuid|0x0|1
+
#
# Common UEFI ones.
#
diff --git a/Platform/RaspberryPi/RPi4/RPi4.dsc b/Platform/RaspberryPi/RPi4/RPi4.dsc
index 6de4407749..c918af6dab 100644
--- a/Platform/RaspberryPi/RPi4/RPi4.dsc
+++ b/Platform/RaspberryPi/RPi4/RPi4.dsc
@@ -551,6 +551,13 @@
#
gRaspberryPiTokenSpaceGuid.PcdXhciReload|L"XhciReload"|gConfigDxeFormSetGuid|0x0|0
+ # Export GPIO block to OS
+ #
+ # 0 - No
+ # 1 - Yes
+ #
+ gRaspberryPiTokenSpaceGuid.PcdEnableGpio|L"EnableGpio"|gConfigDxeFormSetGuid|0x0|0
+
#
# Common UEFI ones.
#
diff --git a/Platform/RaspberryPi/RaspberryPi.dec b/Platform/RaspberryPi/RaspberryPi.dec
index c50ebdcf77..97709f9b94 100644
--- a/Platform/RaspberryPi/RaspberryPi.dec
+++ b/Platform/RaspberryPi/RaspberryPi.dec
@@ -73,3 +73,4 @@
gRaspberryPiTokenSpaceGuid.PcdUartInUse|1|UINT32|0x00000021
gRaspberryPiTokenSpaceGuid.PcdXhciPci|0|UINT32|0x00000022
gRaspberryPiTokenSpaceGuid.PcdXhciReload|0|UINT32|0x00000023
+ gRaspberryPiTokenSpaceGuid.PcdEnableGpio|0|UINT32|0x00000024
--
2.13.7
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH V2 05/10] Platform/RaspberryPi: Add constants for controlling SPI
2022-01-02 5:49 [PATCH V2 00/10] Platform/RaspberryPi: Utilize SPI flash for EFI variables Jeremy Linton
` (3 preceding siblings ...)
2022-01-02 5:49 ` [PATCH V2 04/10] Platform/RaspberryPi: Add menu item to enable/disable GPIO Jeremy Linton
@ 2022-01-02 5:49 ` Jeremy Linton
2022-01-02 5:49 ` [PATCH V2 06/10] Platform/RaspberryPi: Add mailbox cmd to control audio amp Jeremy Linton
` (6 subsequent siblings)
11 siblings, 0 replies; 13+ messages in thread
From: Jeremy Linton @ 2022-01-02 5:49 UTC (permalink / raw)
To: devel
Cc: pete, ardb+tianocore, leif, awarkentin, Sunny.Wang,
samer.el-haj-mahmoud, mariobalanica02, Jeremy Linton,
Ard Biesheuvel
Add the #defines needed to access the SPI interface
documented in the BCM2711 Peripheral guide chapter 8.
Tested-by: Ard Biesheuvel <ardb@kernel.org>
Signed-off-by: Jeremy Linton <jeremy.linton@arm.com>
---
.../Bcm283x/Include/IndustryStandard/Bcm2836.h | 34 ++++++++++++++++++++++
1 file changed, 34 insertions(+)
diff --git a/Silicon/Broadcom/Bcm283x/Include/IndustryStandard/Bcm2836.h b/Silicon/Broadcom/Bcm283x/Include/IndustryStandard/Bcm2836.h
index a930c64af3..55a446a86c 100644
--- a/Silicon/Broadcom/Bcm283x/Include/IndustryStandard/Bcm2836.h
+++ b/Silicon/Broadcom/Bcm283x/Include/IndustryStandard/Bcm2836.h
@@ -109,6 +109,40 @@
#define BCM2836_SPI2_LENGTH 0x00000040
#define BCM2836_SPI2_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_SPI2_OFFSET)
+/* SPI register offsets */
+#define BCM2835_SPI_CS 0x00
+#define BCM2835_SPI_FIFO 0x04
+#define BCM2835_SPI_CLK 0x08
+#define BCM2835_SPI_DLEN 0x0c
+#define BCM2835_SPI_LTOH 0x10
+#define BCM2835_SPI_DC 0x14
+
+/* Bitfields in CS */
+#define BCM2835_SPI_CS_LEN_LONG 0x02000000
+#define BCM2835_SPI_CS_DMA_LEN 0x01000000
+#define BCM2835_SPI_CS_CSPOL2 0x00800000
+#define BCM2835_SPI_CS_CSPOL1 0x00400000
+#define BCM2835_SPI_CS_CSPOL0 0x00200000
+#define BCM2835_SPI_CS_RXF 0x00100000
+#define BCM2835_SPI_CS_RXR 0x00080000
+#define BCM2835_SPI_CS_TXD 0x00040000
+#define BCM2835_SPI_CS_RXD 0x00020000
+#define BCM2835_SPI_CS_DONE 0x00010000
+#define BCM2835_SPI_CS_LEN 0x00002000
+#define BCM2835_SPI_CS_REN 0x00001000
+#define BCM2835_SPI_CS_ADCS 0x00000800
+#define BCM2835_SPI_CS_INTR 0x00000400
+#define BCM2835_SPI_CS_INTD 0x00000200
+#define BCM2835_SPI_CS_DMAEN 0x00000100
+#define BCM2835_SPI_CS_TA 0x00000080
+#define BCM2835_SPI_CS_CSPOL 0x00000040
+#define BCM2835_SPI_CS_CLEAR_RX 0x00000020
+#define BCM2835_SPI_CS_CLEAR_TX 0x00000010
+#define BCM2835_SPI_CS_CPOL 0x00000008
+#define BCM2835_SPI_CS_CPHA 0x00000004
+#define BCM2835_SPI_CS_CS_10 0x00000002
+#define BCM2835_SPI_CS_CS_01 0x00000001
+
/* dma constants */
#define BCM2836_DMA0_OFFSET 0x00007000
#define BCM2836_DMA0_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_DMA0_OFFSET)
--
2.13.7
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH V2 06/10] Platform/RaspberryPi: Add mailbox cmd to control audio amp
2022-01-02 5:49 [PATCH V2 00/10] Platform/RaspberryPi: Utilize SPI flash for EFI variables Jeremy Linton
` (4 preceding siblings ...)
2022-01-02 5:49 ` [PATCH V2 05/10] Platform/RaspberryPi: Add constants for controlling SPI Jeremy Linton
@ 2022-01-02 5:49 ` Jeremy Linton
2022-01-02 5:49 ` [PATCH V2 07/10] Platform/RaspberryPi: Add SPI/GPIO to memory map Jeremy Linton
` (5 subsequent siblings)
11 siblings, 0 replies; 13+ messages in thread
From: Jeremy Linton @ 2022-01-02 5:49 UTC (permalink / raw)
To: devel
Cc: pete, ardb+tianocore, leif, awarkentin, Sunny.Wang,
samer.el-haj-mahmoud, mariobalanica02, Jeremy Linton,
Ard Biesheuvel
The lower level firmware can enable/disable a LDO audio
amp, which allows us to mute/unmute audio output while
the firmware is running.
Tested-by: Ard Biesheuvel <ardb@kernel.org>
Signed-off-by: Jeremy Linton <jeremy.linton@arm.com>
---
.../Drivers/RpiFirmwareDxe/RpiFirmwareDxe.c | 60 +++++++++++++++++++++-
.../RaspberryPi/Include/IndustryStandard/RpiMbox.h | 1 +
.../RaspberryPi/Include/Protocol/RpiFirmware.h | 7 +++
3 files changed, 67 insertions(+), 1 deletion(-)
diff --git a/Platform/RaspberryPi/Drivers/RpiFirmwareDxe/RpiFirmwareDxe.c b/Platform/RaspberryPi/Drivers/RpiFirmwareDxe/RpiFirmwareDxe.c
index 4edec0ad04..dca43d78a6 100644
--- a/Platform/RaspberryPi/Drivers/RpiFirmwareDxe/RpiFirmwareDxe.c
+++ b/Platform/RaspberryPi/Drivers/RpiFirmwareDxe/RpiFirmwareDxe.c
@@ -1532,6 +1532,63 @@ RpiFirmwareNotifyGpioSetCfg (
return Status;
}
+#pragma pack()
+typedef struct {
+ UINT32 State;
+} RPI_FW_SET_LDO_REG_TAG;
+
+typedef struct {
+ RPI_FW_BUFFER_HEAD BufferHead;
+ RPI_FW_TAG_HEAD TagHead;
+ RPI_FW_SET_LDO_REG_TAG TagBody;
+ UINT32 EndTag;
+} RPI_FW_SET_LDO_REG_CMD;
+#pragma pack()
+
+
+STATIC
+EFI_STATUS
+EFIAPI
+RpiFirmwareSetLdoRegState (
+ IN UINTN State
+ )
+{
+ RPI_FW_SET_LDO_REG_CMD *Cmd;
+ EFI_STATUS Status;
+ UINT32 Result;
+
+ if (!AcquireSpinLockOrFail (&mMailboxLock)) {
+ DEBUG ((DEBUG_ERROR, "%a: failed to acquire spinlock\n", __FUNCTION__));
+ return EFI_DEVICE_ERROR;
+ }
+
+ Cmd = mDmaBuffer;
+ ZeroMem (Cmd, sizeof (*Cmd));
+
+ Cmd->BufferHead.BufferSize = sizeof (*Cmd);
+ Cmd->BufferHead.Response = 0;
+ Cmd->TagHead.TagId = RPI_MBOX_SET_LDO_REGULATOR;
+ Cmd->TagHead.TagSize = sizeof (Cmd->TagBody);
+ Cmd->TagBody.State = State;
+
+ Cmd->TagHead.TagValueSize = 0;
+ Cmd->EndTag = 0;
+
+ Status = MailboxTransaction (Cmd->BufferHead.BufferSize, RPI_MBOX_VC_CHANNEL, &Result);
+
+ if (EFI_ERROR (Status) ||
+ Cmd->BufferHead.Response != RPI_MBOX_RESP_SUCCESS) {
+ DEBUG ((DEBUG_ERROR,
+ "%a: mailbox transaction error: Status == %r, Response == 0x%x\n",
+ __FUNCTION__, Status, Cmd->BufferHead.Response));
+ }
+
+ ReleaseSpinLock (&mMailboxLock);
+
+ return Status;
+}
+
+
STATIC RASPBERRY_PI_FIRMWARE_PROTOCOL mRpiFirmwareProtocol = {
RpiFirmwareSetPowerState,
RpiFirmwareGetMacAddress,
@@ -1557,7 +1614,8 @@ STATIC RASPBERRY_PI_FIRMWARE_PROTOCOL mRpiFirmwareProtocol = {
RpiFirmwareNotifyXhciReset,
RpiFirmwareGetCurrentClockState,
RpiFirmwareSetClockState,
- RpiFirmwareNotifyGpioSetCfg
+ RpiFirmwareNotifyGpioSetCfg,
+ RpiFirmwareSetLdoRegState
};
/**
diff --git a/Platform/RaspberryPi/Include/IndustryStandard/RpiMbox.h b/Platform/RaspberryPi/Include/IndustryStandard/RpiMbox.h
index 551c2b82e5..f36aaafaf8 100644
--- a/Platform/RaspberryPi/Include/IndustryStandard/RpiMbox.h
+++ b/Platform/RaspberryPi/Include/IndustryStandard/RpiMbox.h
@@ -92,6 +92,7 @@
#define RPI_MBOX_NOTIFY_REBOOT 0x00030048
#define RPI_MBOX_GET_POE_HAT_VAL 0x00030049
#define RPI_MBOX_SET_POE_HAT_VAL 0x00030050
+#define RPI_MBOX_SET_LDO_REGULATOR 0x00030056
#define RPI_MBOX_NOTIFY_XHCI_RESET 0x00030058
#define RPI_MBOX_SET_CLOCK_STATE 0x00038001
diff --git a/Platform/RaspberryPi/Include/Protocol/RpiFirmware.h b/Platform/RaspberryPi/Include/Protocol/RpiFirmware.h
index c48bb6e434..175894e37a 100644
--- a/Platform/RaspberryPi/Include/Protocol/RpiFirmware.h
+++ b/Platform/RaspberryPi/Include/Protocol/RpiFirmware.h
@@ -171,6 +171,12 @@ EFI_STATUS
UINTN State
);
+typedef
+EFI_STATUS
+(EFIAPI *SET_LDO_REGULATOR) (
+ UINTN State
+ );
+
typedef struct {
SET_POWER_STATE SetPowerState;
GET_MAC_ADDRESS GetMacAddress;
@@ -197,6 +203,7 @@ typedef struct {
GET_CLOCK_STATE GetClockState;
SET_CLOCK_STATE SetClockState;
GPIO_SET_CFG SetGpioConfig;
+ SET_LDO_REGULATOR SetLdoRegState;
} RASPBERRY_PI_FIRMWARE_PROTOCOL;
extern EFI_GUID gRaspberryPiFirmwareProtocolGuid;
--
2.13.7
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH V2 07/10] Platform/RaspberryPi: Add SPI/GPIO to memory map
2022-01-02 5:49 [PATCH V2 00/10] Platform/RaspberryPi: Utilize SPI flash for EFI variables Jeremy Linton
` (5 preceding siblings ...)
2022-01-02 5:49 ` [PATCH V2 06/10] Platform/RaspberryPi: Add mailbox cmd to control audio amp Jeremy Linton
@ 2022-01-02 5:49 ` Jeremy Linton
2022-01-02 5:49 ` [PATCH V2 08/10] Platform/RaspberryPi: Allow pin function selection at runtime Jeremy Linton
` (4 subsequent siblings)
11 siblings, 0 replies; 13+ messages in thread
From: Jeremy Linton @ 2022-01-02 5:49 UTC (permalink / raw)
To: devel
Cc: pete, ardb+tianocore, leif, awarkentin, Sunny.Wang,
samer.el-haj-mahmoud, mariobalanica02, Jeremy Linton,
Ard Biesheuvel
A large reason for using the SPI flash on this platform is that
it can be updated without OS interference at rutime. In order for
that to happen we need both the SPI, as well as the GPIO
which is used to change the pinmux from the PWM device to SPI added
to the UEFI memory map as being used by the runtime service.
Tested-by: Ard Biesheuvel <ardb@kernel.org>
Signed-off-by: Jeremy Linton <jeremy.linton@arm.com>
---
Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c b/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c
index de7eb769ea..b0db3312c5 100644
--- a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c
+++ b/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c
@@ -503,6 +503,22 @@ ApplyVariables (
DEBUG ((DEBUG_INFO, "Current CPU speed is %u MHz\n", Rate / FREQ_1_MHZ));
}
+ if (mModelFamily == 4) {
+ Status = gDS->AddMemorySpace (EfiGcdMemoryTypeMemoryMappedIo, BCM2836_SPI0_BASE_ADDRESS,
+ SIZE_4KB, EFI_MEMORY_UC | EFI_MEMORY_RUNTIME);
+ ASSERT_EFI_ERROR (Status);
+ Status = gDS->SetMemorySpaceAttributes (BCM2836_SPI0_BASE_ADDRESS,
+ SIZE_4KB, EFI_MEMORY_UC|EFI_MEMORY_RUNTIME);
+
+ Status = gDS->AddMemorySpace (EfiGcdMemoryTypeMemoryMappedIo, GPIO_BASE_ADDRESS,
+ SIZE_4KB, EFI_MEMORY_UC | EFI_MEMORY_RUNTIME);
+ ASSERT_EFI_ERROR (Status);
+ Status = gDS->SetMemorySpaceAttributes (GPIO_BASE_ADDRESS,
+ SIZE_4KB, EFI_MEMORY_UC|EFI_MEMORY_RUNTIME);
+
+ ASSERT_EFI_ERROR (Status);
+ }
+
if (mModelFamily >= 4 && PcdGet32 (PcdRamMoreThan3GB) != 0 &&
PcdGet32 (PcdRamLimitTo3GB) == 0) {
UINT64 SystemMemorySize;
--
2.13.7
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH V2 08/10] Platform/RaspberryPi: Allow pin function selection at runtime
2022-01-02 5:49 [PATCH V2 00/10] Platform/RaspberryPi: Utilize SPI flash for EFI variables Jeremy Linton
` (6 preceding siblings ...)
2022-01-02 5:49 ` [PATCH V2 07/10] Platform/RaspberryPi: Add SPI/GPIO to memory map Jeremy Linton
@ 2022-01-02 5:49 ` Jeremy Linton
2022-01-02 5:49 ` [PATCH V2 09/10] Platform/RaspberryPi: Add SPI flash variable store Jeremy Linton
` (3 subsequent siblings)
11 siblings, 0 replies; 13+ messages in thread
From: Jeremy Linton @ 2022-01-02 5:49 UTC (permalink / raw)
To: devel
Cc: pete, ardb+tianocore, leif, awarkentin, Sunny.Wang,
samer.el-haj-mahmoud, mariobalanica02, Jeremy Linton,
Ard Biesheuvel
Update GpioLib slightly so that we can change the GPIO pin
muxing at runtime. For the moment only the GpioPinFuncGet/Set()
routines are used at runtime, and only by the Variable service.
Tested-by: Ard Biesheuvel <ardb@kernel.org>
Signed-off-by: Jeremy Linton <jeremy.linton@arm.com>
---
Silicon/Broadcom/Bcm283x/Include/Library/GpioLib.h | 6 ++++++
Silicon/Broadcom/Bcm283x/Library/GpioLib/GpioLib.c | 16 ++++++++++++++--
2 files changed, 20 insertions(+), 2 deletions(-)
diff --git a/Silicon/Broadcom/Bcm283x/Include/Library/GpioLib.h b/Silicon/Broadcom/Bcm283x/Include/Library/GpioLib.h
index 1f7d2204e0..79765be4fb 100644
--- a/Silicon/Broadcom/Bcm283x/Include/Library/GpioLib.h
+++ b/Silicon/Broadcom/Bcm283x/Include/Library/GpioLib.h
@@ -45,4 +45,10 @@ GpioSetPull (
IN UINTN Pud
);
+VOID
+GpioSetupRuntime (
+ VOID
+);
+
+
#endif /* __GPIO_LIB__ */
diff --git a/Silicon/Broadcom/Bcm283x/Library/GpioLib/GpioLib.c b/Silicon/Broadcom/Bcm283x/Library/GpioLib/GpioLib.c
index eaf53e5369..fc1f928e6b 100644
--- a/Silicon/Broadcom/Bcm283x/Library/GpioLib/GpioLib.c
+++ b/Silicon/Broadcom/Bcm283x/Library/GpioLib/GpioLib.c
@@ -15,10 +15,22 @@
#include <Library/DebugLib.h>
#include <Library/IoLib.h>
#include <Library/GpioLib.h>
+#include <Library/UefiRuntimeLib.h>
#include <Library/TimerLib.h>
#include <IndustryStandard/Bcm2836.h>
#include <IndustryStandard/Bcm2836Gpio.h>
+
+STATIC EFI_PHYSICAL_ADDRESS GpioGfpSel0 = GPIO_GPFSEL0;
+
+VOID
+GpioSetupRuntime (
+ VOID
+ )
+{
+ EfiConvertPointer (0x0, (VOID**)&GpioGfpSel0);
+}
+
STATIC
VOID
GpioFSELModify (
@@ -30,7 +42,7 @@ GpioFSELModify (
UINT32 Val;
EFI_PHYSICAL_ADDRESS Reg;
- Reg = RegIndex * sizeof (UINT32) + GPIO_GPFSEL0;
+ Reg = RegIndex * sizeof (UINT32) + GpioGfpSel0;
ASSERT (Reg <= GPIO_GPFSEL5);
ASSERT ((~ModifyMask & FunctionMask) == 0);
@@ -77,7 +89,7 @@ GpioPinFuncGet (
RegIndex = Pin / 10;
SelIndex = Pin % 10;
- Reg = RegIndex * sizeof (UINT32) + GPIO_GPFSEL0;
+ Reg = RegIndex * sizeof (UINT32) + GpioGfpSel0;
Val = MmioRead32 (Reg);
Val >>= SelIndex * GPIO_FSEL_BITS_PER_PIN;
--
2.13.7
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH V2 09/10] Platform/RaspberryPi: Add SPI flash variable store.
2022-01-02 5:49 [PATCH V2 00/10] Platform/RaspberryPi: Utilize SPI flash for EFI variables Jeremy Linton
` (7 preceding siblings ...)
2022-01-02 5:49 ` [PATCH V2 08/10] Platform/RaspberryPi: Allow pin function selection at runtime Jeremy Linton
@ 2022-01-02 5:49 ` Jeremy Linton
2022-01-02 5:49 ` [PATCH V2 10/10] Platform/RaspberryPi: Update RPi4 Readme Jeremy Linton
` (2 subsequent siblings)
11 siblings, 0 replies; 13+ messages in thread
From: Jeremy Linton @ 2022-01-02 5:49 UTC (permalink / raw)
To: devel
Cc: pete, ardb+tianocore, leif, awarkentin, Sunny.Wang,
samer.el-haj-mahmoud, mariobalanica02, Jeremy Linton,
Ard Biesheuvel
The RPi4 has a 512KB SPI flash, which depending on RPi
and firmware revision has 300-180K free. We can use this
storage to persist variables when the OS is running or
over firmware upgrades. The problem is that the SPI is pin
mux'ed with the PWM audio, so we want to leave the PWM
configured for OS use. And of course there is the problem
of sharing the GPIO block with OS's that are aware of it.
Hence a previous patch set which moves the GPIO and some of
the low level i2c/etc devices into its own SSDT, and
disables them by default.
This patch, adds a few SPI access functions directly to
the variable store rather than creating another runtime
service since the early boot ordering is critical. These
functions are of the form ReadSpi(), WriteSpi(),
DisableSpiWp(), etc all with Spi in the name. On top of that
a few "Flash" routines are created which provide high level
functions for reading/writing and walking the portion of the
SPI flash we use to clone the variable store region.
Importantly WalkFlashVolume() walks the entire SPI flash
region, which has a simple header structure containing
filename+len for each region of the flash, to return how
much of the capacity is being utilized by the existing
bootloader/etc firmware.
So, if this is a RPi4, and there is sufficient space, and
that space doesn't have a valid varstore header we erase
it and flush the RPI's varstore region to the SPI. Then
we note its starting offset in mFvInstance->FlashOffset.
>From then on, writes to the EFI_FW_VOL_BLOCK_DEVICE are
written to both the RAM copy as well as the SPI flash. If
the empty region has a valid header we read the entire
region overtop of the one being passed as part of the RPi's
BL33, and continue as above.
At ready to boot we re-enable the LDO, and then during the
dump vars check, we check for DT or the GPIO being enabled
and disable the runtime SPI updates because we can't be sure
of what the OS might be doing with the GPIO. The dual ACPI
and DT mode, leaves it enabled (if GPIO is disabled) so
care should be taken.
Now, one of the problems here is that with the LDO enabled
any SPI accesses can be heard over the speakers as pops,
buzzes, or scratchy tones. This is happening even without
this patch because TFA and/or the rpi low level firmware
doesn't itself assure the LDO is disabled during resets, so
the early SoC startup is quite noisy. We add to this, but
alongside that a couple fairly trivial TFA patchs, to mute
it before reset, and again assure its off before releasing
to us solve a large part of this problem. That said, this
can now happen during runtime as well. Generally the OS's
aren't doing a lot of variable updates, but when they do
its generally barely noticable clicks since we aren't going
through the long process of muting/unmuting the LDO which
itself causes a pop.
So, this patch fixes a whole bunch of bugs on github that
exist because the variable store isn't persisted. It also
fixes a rather large bug in the existing variable store
code caused by the FaultTolerantWriteDxe erasing the entire
variable store region when it garbage collects during startup.
That latter bug is the result of FvbGetLbaAddress reading
recently erased data from the VolumeHeader before its been
recreated, and results in random UEFI crashes.
Tested-by: Ard Biesheuvel <ardb@kernel.org>
Signed-off-by: Jeremy Linton <jeremy.linton@arm.com>
---
.../Drivers/VarBlockServiceDxe/FvbInfo.c | 8 +-
.../Drivers/VarBlockServiceDxe/VarBlockService.c | 650 ++++++++++++++++++++-
.../Drivers/VarBlockServiceDxe/VarBlockService.h | 10 +
.../VarBlockServiceDxe/VarBlockServiceDxe.c | 38 +-
.../VarBlockServiceDxe/VarBlockServiceDxe.inf | 6 +
5 files changed, 690 insertions(+), 22 deletions(-)
diff --git a/Platform/RaspberryPi/Drivers/VarBlockServiceDxe/FvbInfo.c b/Platform/RaspberryPi/Drivers/VarBlockServiceDxe/FvbInfo.c
index 0e0c108dba..ee18f327e6 100644
--- a/Platform/RaspberryPi/Drivers/VarBlockServiceDxe/FvbInfo.c
+++ b/Platform/RaspberryPi/Drivers/VarBlockServiceDxe/FvbInfo.c
@@ -11,12 +11,7 @@
#include <Guid/SystemNvDataGuid.h>
#include <Library/BaseLib.h>
#include <Library/PcdLib.h>
-
-typedef struct {
- UINT64 FvLength;
- EFI_FIRMWARE_VOLUME_HEADER FvbInfo;
- EFI_FV_BLOCK_MAP_ENTRY End[1];
-} EFI_FVB_MEDIA_INFO;
+#include "VarBlockService.h"
EFI_FVB_MEDIA_INFO mPlatformFvbMediaInfo[] = {
//
@@ -38,6 +33,7 @@ EFI_FVB_MEDIA_INFO mPlatformFvbMediaInfo[] = {
FixedPcdGet32 (PcdNvStorageEventLogSize),
EFI_FVH_SIGNATURE,
EFI_FVB2_MEMORY_MAPPED |
+ EFI_FVB2_STICKY_WRITE |
EFI_FVB2_READ_ENABLED_CAP |
EFI_FVB2_READ_STATUS |
EFI_FVB2_WRITE_ENABLED_CAP |
diff --git a/Platform/RaspberryPi/Drivers/VarBlockServiceDxe/VarBlockService.c b/Platform/RaspberryPi/Drivers/VarBlockServiceDxe/VarBlockService.c
index 572309439a..0cf204738f 100644
--- a/Platform/RaspberryPi/Drivers/VarBlockServiceDxe/VarBlockService.c
+++ b/Platform/RaspberryPi/Drivers/VarBlockServiceDxe/VarBlockService.c
@@ -7,17 +7,28 @@
*
**/
+#include <Base.h>
+
+#include <IndustryStandard/Bcm2836.h>
+#include <IndustryStandard/Bcm2836Gpio.h>
+
#include <Protocol/DevicePath.h>
#include <Protocol/FirmwareVolumeBlock.h>
+#include <Protocol/RpiFirmware.h>
#include <Library/BaseLib.h>
#include <Library/BaseMemoryLib.h>
#include <Library/DebugLib.h>
#include <Library/DevicePathLib.h>
#include <Library/DxeServicesTableLib.h>
+#include <Library/GpioLib.h>
+#include <Library/IoLib.h>
#include <Library/MemoryAllocationLib.h>
+#include <Library/TimerLib.h>
#include <Library/UefiBootServicesTableLib.h>
+#include <Guid/VariableFormat.h>
+
#include "VarBlockService.h"
#define EFI_FVB2_STATUS \
@@ -85,6 +96,467 @@ EFI_FW_VOL_BLOCK_DEVICE mFvbDeviceTemplate = {
}
};
+/*
+ * This is a derived approximation for the number of BCM2835_SPI_CS
+ * register reads that can be accomplished in 1US on a bcm2711.
+ */
+#define SPI_CS_READS_PER_US 25
+
+STATIC
+VOID
+SpiDelay (
+ IN UINTN micro_sec
+ )
+/*++
+
+ Routine Description:
+ Delay loop based on how fast we can read SPI controller
+ state rather than a hardcoded delay since we are a runtime
+ service.
+
+ Arguments:
+ micro_sec - Approximate number of micro seconds to delay.
+
+ Returns:
+--*/
+{
+ UINT32 looping;
+ for (looping = 0; looping < micro_sec; looping++) {
+ UINT32 looping2;
+ //
+ // RPi4 does about 25 reg reads per micro second
+ //
+ for (looping2 = 0; looping2 < SPI_CS_READS_PER_US; looping2++) {
+ MmioRead32 (mFvInstance->SpiBase+BCM2835_SPI_CS);
+ }
+ }
+}
+
+STATIC
+INT32
+DoSpiCommand (
+ UINT8 *Buffer,
+ UINTN in_len,
+ UINTN out_len)
+/*++
+
+ Routine Description:
+ Read and/or Write data on the SPI bus. A buffer with
+ data to write/read is passed and this routine then writes
+ out_len data on the SPI bus, and reads in_len data back
+ into the buffer starting at the first location. Obviously
+ this means that the buffer must be greater than the largest
+ of in_len or out_len
+
+ Arguments:
+ in_len - bytes to read from the SPI to buffer
+ out_len - bytes to write on the SPI from buffer
+
+ Returns:
+ number of bytes read into buffer.
+--*/
+{
+ int cur_byte;
+ UINT32 ret = 0;
+
+ MmioWrite32 (mFvInstance->SpiBase + BCM2835_SPI_CS, BCM2835_SPI_CS_TA);
+
+ for (cur_byte = 0 ;cur_byte < in_len + out_len; cur_byte++)
+ {
+ int loop = 10000*SPI_CS_READS_PER_US;
+
+ while ((MmioRead32 (mFvInstance->SpiBase + BCM2835_SPI_CS) & BCM2835_SPI_CS_TXD) == 0) {
+ loop--;
+ if (loop == 0) {
+ DEBUG ((DEBUG_ERROR, "Write timeout %X\n", MmioRead32 (mFvInstance->SpiBase+BCM2835_SPI_CS)));
+ ret = -1;
+ break;
+ }
+ }
+
+ if (cur_byte < out_len) {
+ MmioWrite32 (mFvInstance->SpiBase + BCM2835_SPI_FIFO, Buffer[cur_byte]);
+ } else {
+ MmioWrite32 (mFvInstance->SpiBase + BCM2835_SPI_FIFO, 0);
+ }
+
+ loop = 10000 * SPI_CS_READS_PER_US;
+ while ((MmioRead32 (mFvInstance->SpiBase + BCM2835_SPI_CS) & BCM2835_SPI_CS_RXD) == 0) {
+ loop--;
+ if (loop == 0) {
+ DEBUG ((DEBUG_ERROR, "Read timeout %X\n", MmioRead32 (mFvInstance->SpiBase+BCM2835_SPI_CS)));
+ ret = -1;
+ break;
+ }
+ }
+
+ if (cur_byte < out_len) {
+ MmioRead32 (mFvInstance->SpiBase + BCM2835_SPI_FIFO);
+ } else {
+ ret++;
+ Buffer[cur_byte - out_len] = MmioRead32 (mFvInstance->SpiBase + BCM2835_SPI_FIFO);
+ }
+ }
+
+ MmioWrite32 (mFvInstance->SpiBase + BCM2835_SPI_CS, 0);
+
+ SpiDelay (1); //wait for /CS to settle
+
+ return ret;
+}
+
+#if (RPI_MODEL == 4)
+STATIC
+INT32
+ReadDeviceId (VOID)
+/*++
+
+ Routine Description:
+ Sends the SPI device identification command then checks to see
+ if its a winbond we recognize, and returns the expected capacity.
+
+ Arguments:
+
+ Returns:
+ Capacity of attached device
+--*/
+{
+ UINT8 Buffer[32];
+ Buffer[0] = 0x9F;
+
+ DoSpiCommand (Buffer, 3, 1); //EF 30 31 is the winbond W25X40CL on the base rpi4
+ if (Buffer[0] != 0xEF) {
+ DEBUG ((DEBUG_INFO, "ReadDeviceId %02X %02X %02X\n",
+ Buffer[0], Buffer[1], Buffer[2]));
+ }
+ // Lets assume we understand JEDEC type 0x30
+ if (Buffer[1] == 0x30) {
+ // it should be 512K
+ return 1 << Buffer[2]; //not really standard...
+ }
+
+ return 0;
+}
+
+STATIC
+INT32
+ReadSpi (
+ UINT32 Addr,
+ UINT8 *Buffer,
+ UINT32 Len)
+/*++
+
+ Routine Description:
+ Reads Len bytes of data at flash Addr into Buffer
+
+ Arguments:
+ Addr - Flash device address
+ Buffer - Buffer where data is returned, this
+ buffer must be at least 5 bytes long to
+ hold the command.
+ Len - Number of bytes to read into Buffer
+
+ Returns:
+ Number of bytes read
+--*/
+{
+ INT32 ret;
+ Buffer[0] = 0x0B; //send read data
+ Buffer[1] = (Addr >> 16) & 0xFF; // address MSB
+ Buffer[2] = (Addr >> 8) & 0xFF; //
+ Buffer[3] = Addr & 0xFF; // address LSB
+ Buffer[4] = 0;
+
+ ret = DoSpiCommand (Buffer, Len, 5);
+ return ret;
+}
+
+STATIC
+UINT32
+WalkFlashVolume (VOID)
+/*++
+
+ Routine Description:
+ Walk the RPi's SPI flash volume to determine if there is
+ free space we may consume as the backing store for a UEFI
+ variable store volume. This is fairly safe as the entire volume
+ can be recovered using the Raspberry Pi OS image tool to create
+ an EEPROM update disk. We aren't going to bother to
+ attempt to contain it in their volume format, rather hiding in
+ the free/unclaimed space. If this space is corrupted via an update
+ done outside of our control, we will fallback to the original
+ RPI_EFI.FD variables. AKA we should never really be worse off.
+
+ Arguments:
+ None
+
+ Returns:
+ A value that can be assigned to mFvInstance->FlashOffset
+ as the location we may right, otherwise 0.
+--*/
+{
+ UINT32 total_data;
+ UINT32 device_size;
+ UINT8 buffer[32];
+
+ device_size = ReadDeviceId ();
+ // newer write location 00051100
+
+ for (total_data = 0; total_data < device_size; ) {
+ UINT32 len;
+ if (ReadSpi (total_data, buffer, 24) == 24) {
+ len = 0;
+ len += (*(UINT8 *)&buffer[5]) << 16;
+ len += (*(UINT8 *)&buffer[6]) << 8;
+ len += (*(UINT8 *)&buffer[7]);
+
+ // round up to nearest 8 byte align
+ len += 7;
+ len &= 0xFFFFF8;
+
+ buffer[24]=0;
+ DEBUG ((DEBUG_INFO, "%X len=%d filename=%a \n", *(UINT32 *)buffer,
+ len, (char *)&buffer[8]));
+ if (*(UINT32 *)buffer == 0xFFFFFFFF) {
+ break;
+ }
+ total_data += 8 + len;
+ } else {
+ DEBUG ((DEBUG_ERROR, "Didn't get correct amount of data from SPI, abort its use\n"));
+ return 0;
+ }
+ }
+
+ DEBUG ((DEBUG_INFO, "First free sector at %X free space remaining %dK \n", total_data,(device_size-total_data)/1024));
+ if ((device_size - total_data) > SIZE_128KB) {
+ //start at the next 4k page
+ total_data = (total_data + SIZE_4KB) & 0xFFFFE000;
+ DEBUG ((DEBUG_INFO, "Start of Fv at %X\n", total_data));
+ } else {
+ total_data = 0;
+ }
+
+ return total_data;
+}
+
+
+STATIC
+INT32
+FlashRead (
+ UINT32 Addr,
+ UINT8 *Buffer,
+ UINT32 Len)
+/*++
+
+ Routine Description:
+ Reads Len data from variable storage area into Buffer
+
+ Arguments:
+ Addr - Offset into variable store region
+ Buffer - Buffer where data is returned, this
+ buffer must be at least 5 bytes long to
+ hold the command.
+ Len - Number of bytes to read into Buffer
+
+ Returns:
+ Number of bytes read
+--*/
+{
+ return ReadSpi (mFvInstance->FlashOffset + Addr, Buffer, Len);
+}
+#endif
+
+STATIC
+VOID
+DisableSpiWp (VOID)
+/*++
+
+ Routine Description:
+ Sends SPI flash command to disable write protection
+
+ Arguments:
+
+ Returns:
+
+--*/
+{
+ UINT8 Buffer[32];
+ Buffer[0] = 0x06;
+
+ DoSpiCommand (Buffer, 0, 1);
+}
+
+STATIC
+INT32
+ReadSpiStatus (VOID)
+/*++
+
+ Routine Description:
+ Sends SPI get status command
+ Arguments:
+
+ Returns:
+ Status of flash device
+--*/
+{
+ UINT8 Buffer[32];
+ Buffer[0] = 0x05;
+
+ DoSpiCommand (Buffer, 1, 1);
+
+ return Buffer[0];
+}
+
+
+STATIC
+VOID
+WriteSpi (
+ UINT32 Addr,
+ UINT8 *SrcBuffer,
+ UINT32 Len)
+/*++
+
+ Routine Description:
+ Writes Len bytes of SrcBuffer to SPI flash. The max write len is a single
+ 256 byte block, but this routine deals with the case where its misaligned
+ across two flash blocks.
+
+ Arguments:
+ Addr - Flash device address
+ SrcBuffer - Buffer from which data is written to the SPI flash
+ Len - Number of bytes to write
+
+ Returns:
+ Nothing
+--*/
+{
+ UINT8 Buffer[280];
+ UINTN loop;
+ int additional = 0;
+
+ if (Len > 256) Len = 256;
+
+ // check if request crosses boundary
+ if (((Addr + Len - 1) & 0xFFFFFF00) != (Addr & 0xFFFFFF00)) {
+ additional = (Addr + Len) & 0xFF;
+ Len -= additional;
+ }
+
+ do {
+
+ DisableSpiWp ();
+
+ while (ReadSpiStatus () != 2) {
+ DEBUG ((DEBUG_INFO, "Spi status %X \n", ReadSpiStatus ()));
+ }
+
+ Buffer[0] = 0x02; //write len
+ Buffer[1] = (Addr >> 16) & 0xFF;
+ Buffer[2] = (Addr >> 8) & 0xFF;
+ Buffer[3] = Addr & 0xFF;
+
+ CopyMem (&Buffer[4], SrcBuffer, Len);
+
+ DoSpiCommand (Buffer, 0, 4+Len);
+
+ loop = Len * 30000 * SPI_CS_READS_PER_US;
+ while (ReadSpiStatus () & 0x3) {
+ loop--;
+ if (loop == 0) {
+ DEBUG ((DEBUG_ERROR, "Write still busy, continue\n"));
+ break;
+ }
+ }
+
+ // deal with second block
+ if (additional) {
+ Addr += Len;
+ SrcBuffer += Len;
+ Len = additional;
+ additional = 0;
+ } else {
+ Len = 0;
+ }
+
+ } while (Len);
+}
+
+STATIC
+VOID
+Erase4kSpi (
+ UINT32 Addr)
+/*++
+
+ Routine Description:
+ Erases a complete SPI flash page, which in this
+ case is 4k at the given address.
+
+ Arguments:
+ Addr - Flash device address
+
+ Returns:
+ Nothing
+--*/
+{
+ UINT8 Buffer[32];
+ int loop = 300000 * SPI_CS_READS_PER_US;
+
+ DisableSpiWp ();
+
+ Buffer[0] = 0x20; //erase 4k
+ Buffer[1] = (Addr >> 16) & 0xFF;
+ Buffer[2] = (Addr >> 8) & 0xFF;
+ Buffer[3] = Addr & 0xFF;
+
+ DoSpiCommand (Buffer, 0, 4);
+
+ while (ReadSpiStatus () & 0x3) {
+ loop--;
+ if (loop == 0) {
+ DEBUG ((DEBUG_ERROR, "Erase still busy \n"));
+ break;
+ }
+ }
+}
+
+STATIC
+VOID
+FlashWrite (
+ IN UINTN Address,
+ IN UINT8 *Buffer,
+ IN UINTN NumBytes
+ )
+/*++
+
+ Routine Description:
+ Writes Len bytes of SrcBuffer to flash variable storage. This routine breaks
+ the writes into blocks <= 256 bytes, which is the max that can be written with
+ the SPI flash commands we are using.
+
+ Arguments:
+ Address - Variable store offset
+ Buffer - data buffer to write
+ NumBytes - bytes in buffer to write
+
+ Returns:
+
+--*/
+{
+ UINTN Off=Address;
+
+ while (NumBytes>0) {
+ int write_bytes = NumBytes;
+ if (write_bytes > 256) {
+ write_bytes = 256;
+ }
+ WriteSpi (mFvInstance->FlashOffset + Off, Buffer, write_bytes);
+
+ Off += write_bytes;
+ Buffer += write_bytes;
+ NumBytes -= write_bytes;
+ }
+}
+
EFI_STATUS
VarStoreWrite (
@@ -93,8 +565,47 @@ VarStoreWrite (
IN UINT8 *Buffer
)
{
+
+ if (Address<mFvInstance->FvBase) {
+ return EFI_INVALID_PARAMETER;
+ }
+
CopyMem ((VOID*)Address, Buffer, *NumBytes);
- mFvInstance->Dirty = TRUE;
+
+ if (mFvInstance->FlashOffset) {
+ GpioPinFuncSet (40, GPIO_FSEL_ALT4);
+ GpioPinFuncSet (41, GPIO_FSEL_ALT4);
+
+ FlashWrite (Address-mFvInstance->FvBase, Buffer, *NumBytes);
+
+ GpioPinFuncSet (40, GPIO_FSEL_ALT0);
+ GpioPinFuncSet (41, GPIO_FSEL_ALT0);
+ } else {
+ mFvInstance->Dirty = TRUE;
+ }
+
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+FlashErase (
+ IN UINTN Address,
+ IN UINTN LbaLength
+ )
+
+{
+ UINTN Off=Address;
+
+ while (LbaLength>0) {
+ int erase_bytes = LbaLength;
+ if (erase_bytes > 4096) {
+ erase_bytes = 4096;
+ }
+ Erase4kSpi (mFvInstance->FlashOffset + Off);
+
+ Off += erase_bytes;
+ LbaLength -= erase_bytes;
+ }
return EFI_SUCCESS;
}
@@ -106,8 +617,22 @@ VarStoreErase (
IN UINTN LbaLength
)
{
+ if (Address<mFvInstance->FvBase) {
+ return EFI_INVALID_PARAMETER;
+ }
SetMem ((VOID*)Address, LbaLength, 0xff);
- mFvInstance->Dirty = TRUE;
+
+ if (mFvInstance->FlashOffset) {
+ GpioPinFuncSet (40, GPIO_FSEL_ALT4);
+ GpioPinFuncSet (41, GPIO_FSEL_ALT4);
+
+ FlashErase (Address-mFvInstance->FvBase, LbaLength);
+
+ GpioPinFuncSet (40, GPIO_FSEL_ALT0);
+ GpioPinFuncSet (41, GPIO_FSEL_ALT0);
+ } else {
+ mFvInstance->Dirty = TRUE;
+ }
return EFI_SUCCESS;
}
@@ -166,8 +691,16 @@ FvbGetLbaAddress (
// Parse the blockmap of the FV to find which map entry the Lba belongs to.
//
while (TRUE) {
- NumBlocks = BlockMap->NumBlocks;
- BlockLength = BlockMap->Length;
+ if (BlockMap->NumBlocks==0xFFFFFFFF) {
+ NumBlocks = mFvInstance->NumOfBlocks;
+ } else {
+ NumBlocks = BlockMap->NumBlocks;
+ }
+ if (BlockMap->Length==0xFFFFFFFF) {
+ BlockLength = mFvInstance->BlockSize;
+ } else {
+ BlockLength = BlockMap->Length;
+ }
if (NumBlocks == 0 || BlockLength == 0) {
return EFI_INVALID_PARAMETER;
@@ -199,6 +732,7 @@ FvbGetLbaAddress (
Offset = Offset + NumBlocks * BlockLength;
BlockMap++;
}
+
}
@@ -371,6 +905,19 @@ FvbSetVolumeAttributes (
*AttribPtr = (*AttribPtr) | NewStatus;
*Attributes = *AttribPtr;
+ if (mFvInstance->FlashOffset) {
+ GpioPinFuncSet (40, GPIO_FSEL_ALT4);
+ GpioPinFuncSet (41, GPIO_FSEL_ALT4);
+
+ FlashErase (0, 0x1000);
+ FlashWrite (0, (UINT8*)mFvInstance->VolumeHeader, 0x1000);
+
+ GpioPinFuncSet (40, GPIO_FSEL_ALT0);
+ GpioPinFuncSet (41, GPIO_FSEL_ALT0);
+
+ }
+
+
return EFI_SUCCESS;
}
@@ -416,12 +963,16 @@ FvbProtocolGetBlockSize (
--*/
{
- return FvbGetLbaAddress (
- Lba,
- NULL,
- BlockSize,
- NumOfBlocks
- );
+ EFI_STATUS Status;
+
+ Status = FvbGetLbaAddress (
+ Lba,
+ NULL,
+ BlockSize,
+ NumOfBlocks
+ );
+
+ return Status;
}
@@ -602,7 +1153,7 @@ FvbProtocolWrite (
EFI_FVB_ATTRIBUTES_2 Attributes;
UINTN LbaAddress;
UINTN LbaLength;
- EFI_STATUS Status;
+ EFI_STATUS Status = EFI_SUCCESS;
EFI_STATUS ReturnStatus;
//
@@ -637,6 +1188,7 @@ FvbProtocolWrite (
return EFI_INVALID_PARAMETER;
}
+ // forces this write to split
if (LbaLength < (*NumBytes + Offset)) {
*NumBytes = (UINT32)(LbaLength - Offset);
Status = EFI_BAD_BUFFER_SIZE;
@@ -789,8 +1341,6 @@ ValidateFvHeader (
Expected =
(UINT16)(((UINTN)FwVolHeader->Checksum + 0x10000 - Checksum) & 0xffff);
- DEBUG ((DEBUG_INFO, "FV@%p Checksum is 0x%x, expected 0x%x\n",
- FwVolHeader, FwVolHeader->Checksum, Expected));
return EFI_NOT_FOUND;
}
@@ -825,6 +1375,7 @@ FvbInitialize (
UINTN NumOfBlocks;
RETURN_STATUS PcdStatus;
UINTN StartOffset;
+ EFI_FIRMWARE_VOLUME_HEADER SpiBuffer[2];
BaseAddress = PcdGet32 (PcdNvStorageVariableBase);
Length = (FixedPcdGet32 (PcdFlashNvStorageVariableSize) +
@@ -842,11 +1393,78 @@ FvbInitialize (
mFvInstance->FvBase = (UINTN)BaseAddress;
mFvInstance->FvLength = (UINTN)Length;
- mFvInstance->Offset = StartOffset;
+ mFvInstance->BlockSize = FixedPcdGet32 (PcdFirmwareBlockSize);
+ mFvInstance->Offset = StartOffset; // Start offset of RPI_EFI.FD file
/*
* Should I parse config.txt instead and find the real name?
*/
mFvInstance->MappedFile = L"RPI_EFI.FD";
+ /*
+ * SPI Control
+ */
+ mFvInstance->SpiBase = BCM2836_SPI0_BASE_ADDRESS;
+ mFvInstance->FlashOffset = 0;
+ mFvInstance->DisableRuntime = 0;
+
+ ZeroMem (SpiBuffer, sizeof (EFI_FIRMWARE_VOLUME_HEADER) * 2);
+#if (RPI_MODEL == 4)
+ /*
+ * On the RPI4 there is a 512KB flash chip
+ * used to store the low level bcm2711 bootstrap code
+ * and the XHCI firmware on newer devices. It has between
+ * ~330K and ~180K available depending on model/version
+ * Possibly less as its consumed for other purposes.
+ * It shares a GPIO pin with the 3.5mm audio port (pwm)
+ * so accessing it causes pops, shzzzz and bzzz
+ * noices that are sometimes audible even without us.
+ * During reboot for example. Newer TFA's will presumably
+ * help us out and disable the audio amp at shutdown
+ * and leave it disabled during startup. That means
+ * that this code can bzzzz if TFA hasn't assured the
+ * audio is off for us.
+ *
+ * Runtime audio pops are audible although barely noticable
+ * in Windows and DT based linux boots. Although the larger
+ * problem is configuring the GPIO pins. As such we disable
+ * runtime persistance if either DT boot mode, or ACPI GPIO
+ * is enabled.
+ */
+
+ GpioPinFuncSet (40, GPIO_FSEL_ALT4);
+ GpioPinFuncSet (41, GPIO_FSEL_ALT4);
+ GpioPinFuncSet (42, GPIO_FSEL_ALT4);
+ GpioPinFuncSet (43, GPIO_FSEL_ALT4);
+ GpioPinFuncSet (44, GPIO_FSEL_ALT4);
+ GpioPinFuncSet (45, GPIO_FSEL_ALT4);
+
+ GpioSetPull (43, GPIO_PULL_DOWN);
+ GpioSetPull (44, GPIO_PULL_DOWN);
+ GpioSetPull (45, GPIO_PULL_DOWN);
+
+ mFvInstance->FlashOffset = WalkFlashVolume ();
+
+ if (mFvInstance->FlashOffset) {
+ if (FlashRead (0, (UINT8*)SpiBuffer, sizeof (EFI_FIRMWARE_VOLUME_HEADER)*2)
+ != sizeof (EFI_FIRMWARE_VOLUME_HEADER) * 2) {
+ DEBUG ((DEBUG_ERROR, "Unable to read data from SPI\n"));
+ mFvInstance->FlashOffset = 0;
+ } else {
+ Status = ValidateFvHeader (SpiBuffer);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_INFO, "Invalid header on SPI, recreate volume\n"));
+ FlashErase (0, Length);
+ FlashWrite (0, (UINT8*)BaseAddress, Length);
+ }
+
+ // read the entire varstore...
+ if (FlashRead (0, (UINT8*)BaseAddress, Length) != Length) {
+ DEBUG ((DEBUG_ERROR, "Failed to read entire flash region\n"));
+ }
+ }
+ }
+ GpioPinFuncSet (40, GPIO_FSEL_ALT0);
+ GpioPinFuncSet (41, GPIO_FSEL_ALT0);
+#endif
Status = ValidateFvHeader (mFvInstance->VolumeHeader);
if (!EFI_ERROR (Status)) {
@@ -903,7 +1521,9 @@ FvbInitialize (
}
//
- // The total number of blocks in the FV.
+ // The total number of blocks in the FV. This should match:
+ // PcdFlashNvStorageVariableSize + PcdFlashNvStorageFtwWorkingSize +
+ // PcdFlashNvStorageFtwSpareSize + PcdNvStorageEventLogSize / PcdFirmwareBlockSize
//
mFvInstance->NumOfBlocks = NumOfBlocks;
diff --git a/Platform/RaspberryPi/Drivers/VarBlockServiceDxe/VarBlockService.h b/Platform/RaspberryPi/Drivers/VarBlockServiceDxe/VarBlockService.h
index b65c26453d..1b4f6bd877 100644
--- a/Platform/RaspberryPi/Drivers/VarBlockServiceDxe/VarBlockService.h
+++ b/Platform/RaspberryPi/Drivers/VarBlockServiceDxe/VarBlockService.h
@@ -30,9 +30,13 @@ typedef struct {
UINTN FvLength;
UINTN Offset;
UINTN NumOfBlocks;
+ UINTN BlockSize;
EFI_DEVICE_PATH_PROTOCOL *Device;
CHAR16 *MappedFile;
BOOLEAN Dirty;
+ UINTN SpiBase;
+ UINTN FlashOffset;
+ UINTN DisableRuntime;
} EFI_FW_VOL_INSTANCE;
extern EFI_FW_VOL_INSTANCE *mFvInstance;
@@ -208,4 +212,10 @@ FileClose (
IN EFI_FILE_PROTOCOL *File
);
+typedef struct {
+ UINT64 FvLength;
+ EFI_FIRMWARE_VOLUME_HEADER FvbInfo;
+ EFI_FV_BLOCK_MAP_ENTRY End[1];
+} EFI_FVB_MEDIA_INFO;
+
#endif
diff --git a/Platform/RaspberryPi/Drivers/VarBlockServiceDxe/VarBlockServiceDxe.c b/Platform/RaspberryPi/Drivers/VarBlockServiceDxe/VarBlockServiceDxe.c
index 4071a3fca4..99ae78f158 100644
--- a/Platform/RaspberryPi/Drivers/VarBlockServiceDxe/VarBlockServiceDxe.c
+++ b/Platform/RaspberryPi/Drivers/VarBlockServiceDxe/VarBlockServiceDxe.c
@@ -8,8 +8,10 @@
*
**/
+#include <Library/GpioLib.h>
+#include <Protocol/RpiFirmware.h>
#include "VarBlockService.h"
-
+#include "ConfigVars.h"
//
// Minimum delay to enact before reset, when variables are dirty (in μs).
// Needed to ensure that SSD-based USB 3.0 devices have time to flush their
@@ -104,9 +106,14 @@ FvbVirtualAddressChangeEvent (
--*/
{
+ if (mFvInstance->DisableRuntime) {
+ mFvInstance->FlashOffset = 0; //disable flash writes
+ }
+ EfiConvertPointer (0x0, (VOID**)&mFvInstance->SpiBase);
EfiConvertPointer (0x0, (VOID**)&mFvInstance->FvBase);
EfiConvertPointer (0x0, (VOID**)&mFvInstance->VolumeHeader);
EfiConvertPointer (0x0, (VOID**)&mFvInstance);
+ GpioSetupRuntime ();
}
@@ -175,6 +182,15 @@ DumpVars (
if (!mFvInstance->Dirty) {
DEBUG ((DEBUG_INFO, "Variables not dirty, not dumping!\n"));
+ // if there is a valid SPI flash volume in use, don't delay the reset
+ if (mFvInstance->FlashOffset) {
+ PcdSet32S (PcdPlatformResetDelay, 0);
+ }
+ if ((PcdGet32 (PcdSystemTableMode) == SYSTEM_TABLE_MODE_DT) ||
+ PcdGet32 (PcdEnableGpio)) {
+ mFvInstance->DisableRuntime = TRUE;
+ }
+
return;
}
@@ -200,6 +216,24 @@ DumpVars (
mFvInstance->Dirty = FALSE;
}
+STATIC
+VOID
+EnableAudioLdo (VOID)
+{
+ EFI_STATUS Status;
+ RASPBERRY_PI_FIRMWARE_PROTOCOL *mFwProtocol;
+
+ Status = gBS->LocateProtocol (&gRaspberryPiFirmwareProtocolGuid,
+ NULL, (VOID**)&mFwProtocol);
+ ASSERT_EFI_ERROR (Status);
+ if (EFI_ERROR (Status)) {
+ return;
+ }
+
+ mFwProtocol->SetLdoRegState (1);
+ ASSERT_EFI_ERROR (Status);
+}
+
VOID
ReadyToBootHandler (
@@ -230,6 +264,8 @@ ReadyToBootHandler (
DumpVars (NULL, NULL);
Status = gBS->CloseEvent (Event);
ASSERT_EFI_ERROR (Status);
+
+ EnableAudioLdo ();
}
diff --git a/Platform/RaspberryPi/Drivers/VarBlockServiceDxe/VarBlockServiceDxe.inf b/Platform/RaspberryPi/Drivers/VarBlockServiceDxe/VarBlockServiceDxe.inf
index c2edb25bd4..6fe5a22dd3 100644
--- a/Platform/RaspberryPi/Drivers/VarBlockServiceDxe/VarBlockServiceDxe.inf
+++ b/Platform/RaspberryPi/Drivers/VarBlockServiceDxe/VarBlockServiceDxe.inf
@@ -37,6 +37,7 @@
MdePkg/MdePkg.dec
MdeModulePkg/MdeModulePkg.dec
Platform/RaspberryPi/RaspberryPi.dec
+ Silicon/Broadcom/Bcm283x/Bcm283x.dec
[LibraryClasses]
BaseLib
@@ -44,6 +45,7 @@
DebugLib
DevicePathLib
DxeServicesTableLib
+ GpioLib
MemoryAllocationLib
PcdLib
UefiBootServicesTableLib
@@ -61,6 +63,7 @@
gEfiBlockIoProtocolGuid
gEfiFirmwareVolumeBlockProtocolGuid # PROTOCOL SOMETIMES_PRODUCED
gEfiDevicePathProtocolGuid # PROTOCOL SOMETIMES_PRODUCED
+ gRaspberryPiFirmwareProtocolGuid ## CONSUMES
[FixedPcd]
gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
@@ -75,12 +78,15 @@
gArmTokenSpaceGuid.PcdFdSize
[Pcd]
+ gBcm283xTokenSpaceGuid.PcdBcm283xRegistersAddress
gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase
gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase
gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase
gRaspberryPiTokenSpaceGuid.PcdNvStorageEventLogBase
gRaspberryPiTokenSpaceGuid.PcdPlatformResetDelay
gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64
+ gRaspberryPiTokenSpaceGuid.PcdSystemTableMode
+ gRaspberryPiTokenSpaceGuid.PcdEnableGpio
[FeaturePcd]
--
2.13.7
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH V2 10/10] Platform/RaspberryPi: Update RPi4 Readme
2022-01-02 5:49 [PATCH V2 00/10] Platform/RaspberryPi: Utilize SPI flash for EFI variables Jeremy Linton
` (8 preceding siblings ...)
2022-01-02 5:49 ` [PATCH V2 09/10] Platform/RaspberryPi: Add SPI flash variable store Jeremy Linton
@ 2022-01-02 5:49 ` Jeremy Linton
2022-02-01 18:03 ` [edk2-devel] [PATCH V2 00/10] Platform/RaspberryPi: Utilize SPI flash for EFI variables 0n0w1c
2022-02-10 16:38 ` Jeff Booher-Kaeding
11 siblings, 0 replies; 13+ messages in thread
From: Jeremy Linton @ 2022-01-02 5:49 UTC (permalink / raw)
To: devel
Cc: pete, ardb+tianocore, leif, awarkentin, Sunny.Wang,
samer.el-haj-mahmoud, mariobalanica02, Jeremy Linton
Replace the paragraph about NVRAM/UEFI variables, with
something that explains the situation a bit better.
Update the UEFI settings table.
Tweak the DT overlay list, and note support for
CM4 and RPi400.
Update the missing block to describe some higher level
goals and point users at the github issues page.
Signed-off-by: Jeremy Linton <jeremy.linton@arm.com>
---
Platform/RaspberryPi/RPi4/Readme.md | 63 +++++++++++++++++++++++++++++++------
1 file changed, 53 insertions(+), 10 deletions(-)
diff --git a/Platform/RaspberryPi/RPi4/Readme.md b/Platform/RaspberryPi/RPi4/Readme.md
index 80899f4ca4..38ae0372fb 100644
--- a/Platform/RaspberryPi/RPi4/Readme.md
+++ b/Platform/RaspberryPi/RPi4/Readme.md
@@ -16,6 +16,8 @@ Raspberry Pi is a trademark of the [Raspberry Pi Foundation](https://www.raspber
The RPi4 target supports Pi revisions based on the BCM2711 SoC:
- Raspberry Pi 4B
+- Raspberry Compute Module 4
+- Raspberry Pi 400
Please see the RPi3 target for the BCM2837-based variants, such as the Raspberry
Pi 3B.
@@ -44,10 +46,11 @@ Build instructions from the top level edk2-platforms Readme.md apply.
1. Format a uSD card as FAT16 or FAT32
2. Copy the generated `RPI_EFI.fd` firmware onto the partition
3. Download and copy the following files from https://github.com/raspberrypi/firmware/tree/master/boot
- - `bcm2711-rpi-4-b.dtb`
+ - `bcm2711-rpi-4-b.dtb`, `bcm2711-rpi-cm4.dtb`, or `bcm2711-rpi-400.dtb`
- `fixup4.dat`
- `start4.elf`
- `overlays/miniuart-bt.dbto` or `overlays/disable-bt.dtbo` (Optional)
+ - `overlays/upstream-pi4.dtbo` (Optional)
4. Create a `config.txt` with the following content:
```
arm_64bit=1
@@ -62,7 +65,12 @@ Build instructions from the top level edk2-platforms Readme.md apply.
```
dtoverlay=miniuart-bt
```
- Note: doing so requires `miniuart-bt.dbto` to have been copied into an `overlays/`
+ Additionally, if you want to use linux in DT mode
+ ```
+ dtoverlay=upstream-pi4
+ ```
+
+ Note: doing so requires `miniuart-bt.dbto` or `upstream-pi4.dtbo` to have been copied into an `overlays/`
directory on the uSD card. Alternatively, you may use `disable-bt` instead of
`miniuart-bt` if you don't require Bluetooth.
5. Insert the uSD card and power up the Pi.
@@ -84,6 +92,8 @@ By default, UEFI will use the device tree loaded by the VideoCore firmware. This
depends on the model/variant, and relies on the presence on specific files on your boot media.
E.g.:
- `bcm2711-rpi-4-b.dtb` (for Pi 4B)
+ - `bcm2711-rpi-cm4.dtb` (for CM4)
+ - `bcm2711-rpi-400.dtb` (for Pi 400)
You can override the DTB and provide a custom one. Copy the relevant `.dtb` into the root of
the SD or USB, and then edit your `config.txt` so that it looks like:
@@ -110,11 +120,36 @@ Note, that the ultimate contents of `/chosen/bootargs` are a combination of seve
## NVRAM
-The Raspberry Pi has no NVRAM.
-
-NVRAM is emulated, with the non-volatile store backed by the UEFI image itself. This
-means that any changes made in UEFI proper are persisted, but changes made from within
-an Operating System aren't.
+The Raspberry Pi doesn't have NVRAM dedicated for UEFI.
+
+While UEFI variables and associated functions will appear to work correctly,
+changes made while the OS is active won't persist over reboot except when
+three conditions are true. Those conditions are:
+- The OS must be running in ACPI mode.
+- The GPIO controller is not exported to the OS.
+- There must be sufficient free space on the SPI flash.
+
+In explanation, there are two different methods used to persist firmware
+configurations. The firmware first attempts to find 128K of free space on the
+SPI flash utilized by the SoC for early boot. If that fails, updates are
+written directly to the RPI_EFI.fd image, but only when two conditions are
+true. Those conditions are:
+- The OS is not yet booted.
+- The RPI_EFI.fd image is stored on media that the firmware can rewrite.
+
+The SPI is generally a better choice, but it only works if the firmware
+controls the GPIO pin muxing (since it shares pins with the PWM Audio) and the
+associated SPI controller while the OS is running. That is where the DT and
+GPIO restrictions come in.
+
+Finally, since the variables store utilizes free space on an SPI flash device
+reserved for early boot/low-level firmware functions, future versions of the
+RPi foundation firmware may consume more of the available free space. The SPI
+flash may be upgraded/downgraded using the official
+[RPi imager](https://github.com/raspberrypi/rpi-imager) update flash tool. That
+tool writes an SD disk image that, when placed in the RPi, will erase and
+reprogram the entire SPI flash, thereby wiping out the UEFI variable store in
+the process.
## RTC
@@ -141,9 +176,12 @@ all functionality may be available.
## Missing Functionality
-- Network booting via onboard NIC.
-- SPCR hardcodes type to PL011, and thus will not expose correct
- (miniUART) UART if DT overlays to switch UART are used on Pi 4B.
+- Capsule update
+- CPPC (in progress)
+- External RTC support and CM4 IO Board RTC
+- Support more HATs in ACPI mode
+- Various OS drivers for onboard devices (GPU in linux, etc)
+- Other stuff, check https://github.com/pftf/RPi4/issues
# Configuration Settings
The Raspberry Pi UEFI configuration settings can be viewed and changed using both the UI configuration menu (under `Device Manager` -> `Raspberry Pi Configuration`), as well as the UEFI Shell. To configure using the UEFI Shell, use `setvar` command to read/write the UEFI variables with GUID = `CD7CC258-31DB-22E6-9F22-63B0B8EED6B5`.
@@ -179,6 +217,11 @@ Screenshot support | `DisplayEnableSShot` | Control-Alt-F12 = `0x00000
**Advanced Configuration** |
Limit RAM to 3 GB | `RamLimitTo3GB` | Disable = `0x00000000` <br> Enabled= `0x00000001` (default)
System Table Selection | `SystemTableMode`| ACPI = `0x00000000` (default)<br> ACPI + Devicetree = `0x00000001` <br> Devicetree = `0x00000002`
+ACPI fan control | `FanOnGpio` | Disable = `0x00000000` <br> Otherwise numeric GPIO pin
+ACPI fan temperature | `FanTemp` | Hex numeric value degrees C
+ACPI XHCI/PCIe | `XhciPci` | Xhci = `0x00000000` <br> PCIe = `0x00000001` <br> always PCIe `0x00000002`
+DT Reload XHCI firmware | `XhciReload` | Disable = `0x00000000` <br> Enabled= `0x00000001`
+Export GPIO devices to OS | `EnableGpio` | Disable = `0x00000000` <br> Enabled= `0x00000001`
Asset Tag | `AssetTag` | String, 32 characters or less (e.g. `L"ABCD123"`)<br> (default `L""`)
**SD/MMC Configuration** |
uSD/eMMC Routing | `SdIsArasan` | Arasan SDHC = `0x00000001` <br> eMMC2 SDHCI = `0x00000000` (default)
--
2.13.7
^ permalink raw reply related [flat|nested] 13+ messages in thread* Re: [edk2-devel] [PATCH V2 00/10] Platform/RaspberryPi: Utilize SPI flash for EFI variables
2022-01-02 5:49 [PATCH V2 00/10] Platform/RaspberryPi: Utilize SPI flash for EFI variables Jeremy Linton
` (9 preceding siblings ...)
2022-01-02 5:49 ` [PATCH V2 10/10] Platform/RaspberryPi: Update RPi4 Readme Jeremy Linton
@ 2022-02-01 18:03 ` 0n0w1c
2022-02-10 16:38 ` Jeff Booher-Kaeding
11 siblings, 0 replies; 13+ messages in thread
From: 0n0w1c @ 2022-02-01 18:03 UTC (permalink / raw)
To: Jeremy Linton, devel
[-- Attachment #1: Type: text/plain, Size: 41 bytes --]
Tested-by: 0n0w1c <fr332hack@gmail.com>
[-- Attachment #2: Type: text/html, Size: 47 bytes --]
^ permalink raw reply [flat|nested] 13+ messages in thread* Re: [edk2-devel] [PATCH V2 00/10] Platform/RaspberryPi: Utilize SPI flash for EFI variables
2022-01-02 5:49 [PATCH V2 00/10] Platform/RaspberryPi: Utilize SPI flash for EFI variables Jeremy Linton
` (10 preceding siblings ...)
2022-02-01 18:03 ` [edk2-devel] [PATCH V2 00/10] Platform/RaspberryPi: Utilize SPI flash for EFI variables 0n0w1c
@ 2022-02-10 16:38 ` Jeff Booher-Kaeding
11 siblings, 0 replies; 13+ messages in thread
From: Jeff Booher-Kaeding @ 2022-02-10 16:38 UTC (permalink / raw)
To: Jeremy Linton, devel
[-- Attachment #1: Type: text/plain, Size: 4361 bytes --]
Patches applied cleanly & built with no issues. No issues spotted in functional testing & passes the SCT tests required by SBBR.
-Jeff
On Sat, Jan 1, 2022 at 09:49 PM, Jeremy Linton wrote:
>
> The RPi4 has a SPI flash with unused capacity. This set detects if
> that capacity is sufficient for a UEFI variable store and utilizes
> it as such. This fixes a long list of problems, and along the way likely
> also fixes a random boot failure caused by the FaultTolerantWriteDxe
> garbage collecting, and erasing the flash volume header which is being
> used to return information about the underlying variable storage capacity=
>
> .
>
> This set was dependent on an earlier, mostly ignored set of changes to
> move the GPIO/etc devices into their own SSDT and disable them. Because
> of that, the two sets have been merged.
>
> Why is that? Because the SPI flash is mux'ed with the PWM used to play
> audio out the 3.5mm audio jack on this device. This causes a long list
> of problems we must try and avoid, starting with the fact that the pins
> need to be controlled by the uefi runtime service. The other problem is
> obviously that any time a variable is updated, if the user is utilizing
> the 3.5mm audio they will hear clicks and pops. Turns out that behavior
> isn't unique to this patch set because the low level boot/etc exhibits th=
>
> is
> when running in a TFA+uboot/edk2 environment. A fairly small tweak to TFA
> fixes the majority of this, and the remaining runtime problems caused
> by this patch actually are very slight and generally not noticeable unles=
>
> s
> one goes looking for them. OTOH, we revert to the earlier non persisted
> variable store if the firmware is running in a DT only mode, or the
> user enables the ACPI GPIO block.
>
> V1->V2:
> Move Rhpx.asl into GPIO SSDT, this fixes a windows problem if the
> GPIO description is removed.
> Add longer explanation to Readme.md as well as update it to note
> CM4/RPi400, newer menu item variables, etc.
> Various code cleanups caught by updated PatchCheck
> More agressive ifdef'ing out RPi4 only code for RPi3
>
> Jeremy Linton (10):
> Platform/RaspberryPi: Cleanup menu visibility
> Platform/RaspberryPi: Give the user control over the XHCI mailbox
> Platform/RaspberryPi: Move GPIO/SPI/I2C to SSDT
> Platform/RaspberryPi: Add menu item to enable/disable GPIO
> Platform/RaspberryPi: Add constants for controlling SPI
> Platform/RaspberryPi: Add mailbox cmd to control audio amp
> Platform/RaspberryPi: Add SPI/GPIO to memory map
> Platform/RaspberryPi: Allow pin function selection at runtime
> Platform/RaspberryPi: Add SPI flash variable store.
> Platform/RaspberryPi: Update RPi4 Readme
>
> Platform/RaspberryPi/AcpiTables/AcpiTables.inf | 1 +
> Platform/RaspberryPi/AcpiTables/Dsdt.asl | 7 -
> Platform/RaspberryPi/AcpiTables/GpuDevs.asl | 126 ----
> Platform/RaspberryPi/AcpiTables/SsdtGpio.asl | 159 +++++
> Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c | 47 ++
> .../RaspberryPi/Drivers/ConfigDxe/ConfigDxe.inf | 2 +
> .../RaspberryPi/Drivers/ConfigDxe/ConfigDxeHii.uni | 10 +
> .../RaspberryPi/Drivers/ConfigDxe/ConfigDxeHii.vfr | 36 +-
> Platform/RaspberryPi/Drivers/FdtDxe/FdtDxe.c | 4 +
> Platform/RaspberryPi/Drivers/FdtDxe/FdtDxe.inf | 1 +
> .../Drivers/RpiFirmwareDxe/RpiFirmwareDxe.c | 60 +-
> .../Drivers/VarBlockServiceDxe/FvbInfo.c | 8 +-
> .../Drivers/VarBlockServiceDxe/VarBlockService.c | 657 +++++++++++++++=
> +++++-
> .../Drivers/VarBlockServiceDxe/VarBlockService.h | 10 +
> .../VarBlockServiceDxe/VarBlockServiceDxe.c | 38 +-
> .../VarBlockServiceDxe/VarBlockServiceDxe.inf | 6 +
> Platform/RaspberryPi/Include/ConfigVars.h | 4 +
> .../RaspberryPi/Include/IndustryStandard/RpiMbox.h | 1 +
> .../RaspberryPi/Include/Protocol/RpiFirmware.h | 7 +
> Platform/RaspberryPi/RPi3/RPi3.dsc | 12 +
> Platform/RaspberryPi/RPi4/RPi4.dsc | 14 +
> Platform/RaspberryPi/RPi4/Readme.md | 63 +-
> Platform/RaspberryPi/RaspberryPi.dec | 2 +
> .../Bcm283x/Include/IndustryStandard/Bcm2836.h | 34 ++
> Silicon/Broadcom/Bcm283x/Include/Library/GpioLib.h | 6 +
> Silicon/Broadcom/Bcm283x/Library/GpioLib/GpioLib.c | 16 +-
> 26 files changed, 1160 insertions(+), 171 deletions(-)
> create mode 100644 Platform/RaspberryPi/AcpiTables/SsdtGpio.asl
>
> --=20
> 2.13.7
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