From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mx0b-002e3701.pphosted.com (mx0b-002e3701.pphosted.com [148.163.143.35]) by mx.groups.io with SMTP id smtpd.web09.2656.1641618744269146435 for ; Fri, 07 Jan 2022 21:12:24 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@hpe.com header.s=pps0720 header.b=VZh4KAMR; spf=permerror, err=parse error for token &{10 18 %{ir}.%{v}.%{d}.spf.has.pphosted.com}: invalid domain name (domain: hpe.com, ip: 148.163.143.35, mailfrom: prvs=000704d8ca=abner.chang@hpe.com) Received: from pps.filterd (m0148664.ppops.net [127.0.0.1]) by mx0b-002e3701.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 2082Whin026172 for ; Sat, 8 Jan 2022 05:12:23 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=hpe.com; h=from : to : cc : subject : date : message-id : mime-version : content-transfer-encoding; s=pps0720; bh=VU1yWu1CIXwehk+/gPRllT8XD+QCaWw1pBs3wnvuyxE=; b=VZh4KAMRV3OKs4UcQ1bhf0a3nHeW3UigCFunVf2H/15RzMz9lmMm3BNRu2AUtjtmUDFh JUc2NzMKwAWa+sRL5KW/d89A9yH14zk55Cdg/rF7g03+T2HdhzAJClb+B9bw/pINcm25 rJVVtuftjwg4Ie7WZMD9hqH/v74xEx5EBMGDPToKHybIGtVO9CZ7+NOpzAT/xWq5c7M6 WPQN7sF5tKpWn/hTvb4KwC5amXfqVsRGGNtzC4GiKsa5rx4dnRTA/oBLaLlzskcjmojk XN1CYoebGF8IAJTxxSsfYrnXIbupesmDbLKMuYcioTl86dlhq99w+psqZwGBvc+8tkVa Ew== Received: from g2t2352.austin.hpe.com (g2t2352.austin.hpe.com [15.233.44.25]) by mx0b-002e3701.pphosted.com (PPS) with ESMTPS id 3df1qw8kx7-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Sat, 08 Jan 2022 05:12:22 +0000 Received: from g2t2360.austin.hpecorp.net (g2t2360.austin.hpecorp.net [16.196.225.135]) by g2t2352.austin.hpe.com (Postfix) with ESMTP id 26D9F62 for ; Sat, 8 Jan 2022 05:12:22 +0000 (UTC) Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.229]) by g2t2360.austin.hpecorp.net (Postfix) with ESMTP id 6EAFE3D; Sat, 8 Jan 2022 05:12:21 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com Subject: [PATCH 02/79] ProcessorPkg/Library: RISC-V CPU library Date: Sat, 8 Jan 2022 12:10:22 +0800 Message-Id: <20220108041121.16005-1-abner.chang@hpe.com> X-Mailer: git-send-email 2.31.1 MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: PS4c93gPHFWj74h9KCMWqh7AvzCRGwig X-Proofpoint-GUID: PS4c93gPHFWj74h9KCMWqh7AvzCRGwig X-HPE-SCL: -1 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.790,Hydra:6.0.425,FMLib:17.11.62.513 definitions=2022-01-08_01,2022-01-07_01,2021-12-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 adultscore=0 priorityscore=1501 lowpriorityscore=0 mlxscore=0 phishscore=0 malwarescore=0 clxscore=1015 suspectscore=0 impostorscore=0 mlxlogscore=768 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2110150000 definitions=main-2201080036 Content-Transfer-Encoding: quoted-printable (This is migrated from edk2-platforms:Silicon/RISC-V) This library provides CSR assembly functions to read/write RISC-V specific Control and Status registers. Signed-off-by: Abner Chang Co-authored-by: Gilbert Chen Reviewed-by: Leif Lindholm Cc: Leif Lindholm Cc: Gilbert Chen --- .../Library/RiscVCpuLib/RiscVCpuLib.inf | 34 ++++++ .../Include/Library/RiscVCpuLib.h | 71 +++++++++++ .../ProcessorPkg/Library/RiscVCpuLib/Cpu.S | 111 ++++++++++++++++++ 3 files changed, 216 insertions(+) create mode 100644 Silicon/RISC-V/ProcessorPkg/Library/RiscVCpuLib/RiscVCp= uLib.inf create mode 100644 Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVCpuLib= .h create mode 100644 Silicon/RISC-V/ProcessorPkg/Library/RiscVCpuLib/Cpu.S diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVCpuLib/RiscVCpuLib.in= f b/Silicon/RISC-V/ProcessorPkg/Library/RiscVCpuLib/RiscVCpuLib.inf new file mode 100644 index 0000000000..7928dd5536 --- /dev/null +++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVCpuLib/RiscVCpuLib.inf @@ -0,0 +1,34 @@ +## @file=0D +# RISC-V RV64 CPU library=0D +#=0D +# Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. Al= l rights reserved.
=0D +#=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +##=0D +=0D +[Defines]=0D + INF_VERSION =3D 0x0001001b=0D + BASE_NAME =3D RiscVCpuLib=0D + FILE_GUID =3D 8C6CFB0D-A0EE-40D5-90DA-2E51EAE0583F= =0D + MODULE_TYPE =3D BASE=0D + VERSION_STRING =3D 1.0=0D + LIBRARY_CLASS =3D RiscVCpuLib=0D +=0D +#=0D +# The following information is for reference only and not required by the = build tools.=0D +#=0D +# VALID_ARCHITECTURES =3D RISCV64=0D +#=0D +=0D +[Sources]=0D +=0D +[Sources.RISCV64]=0D + Cpu.S=0D +=0D +[Packages]=0D + MdeModulePkg/MdeModulePkg.dec=0D + MdePkg/MdePkg.dec=0D + Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec=0D +=0D +=0D diff --git a/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVCpuLib.h b/Si= licon/RISC-V/ProcessorPkg/Include/Library/RiscVCpuLib.h new file mode 100644 index 0000000000..f37d4c20d0 --- /dev/null +++ b/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVCpuLib.h @@ -0,0 +1,71 @@ +/** @file=0D + RISC-V CPU library definitions.=0D +=0D + Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. Al= l rights reserved.
=0D +=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +=0D +#ifndef RISCV_CPU_LIB_H_=0D +#define RISCV_CPU_LIB_H_=0D +=0D +#include "RiscVImpl.h"=0D +=0D +/**=0D + RISCV_TRAP_HANDLER=0D +**/=0D +typedef=0D +VOID=0D +(EFIAPI *RISCV_TRAP_HANDLER)(=0D + VOID=0D + );=0D +=0D +VOID=0D +RiscVSetMachineScratch (RISCV_MACHINE_MODE_CONTEXT *RiscvContext);=0D +=0D +UINT32=0D +RiscVGetMachineScratch (VOID);=0D +=0D +UINT32=0D +RiscVGetMachineTrapCause (VOID);=0D +=0D +UINT64=0D +RiscVReadMachineTimer (VOID);=0D +=0D +VOID=0D +RiscVSetMachineTimerCmp (UINT64);=0D +=0D +UINT64=0D +RiscVReadMachineTimerCmp(VOID);=0D +=0D +UINT64=0D +RiscVReadMachineInterruptEnable(VOID);=0D +=0D +UINT64=0D +RiscVReadMachineInterruptPending(VOID);=0D +=0D +UINT64=0D +RiscVReadMachineStatus(VOID);=0D +=0D +VOID=0D +RiscVWriteMachineStatus(UINT64);=0D +=0D +UINT64=0D +RiscVReadMachineTrapVector(VOID);=0D +=0D +UINT64=0D +RiscVReadMachineIsa (VOID);=0D +=0D +UINT64=0D +RiscVReadMachineVendorId (VOID);=0D +=0D +UINT64=0D +RiscVReadMachineArchitectureId (VOID);=0D +=0D +UINT64=0D +RiscVReadMachineImplementId (VOID);=0D +=0D +VOID=0D +RiscVSetSupervisorAddressTranslationRegister(UINT64);=0D +=0D +#endif=0D diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVCpuLib/Cpu.S b/Silico= n/RISC-V/ProcessorPkg/Library/RiscVCpuLib/Cpu.S new file mode 100644 index 0000000000..06ba80cb5f --- /dev/null +++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVCpuLib/Cpu.S @@ -0,0 +1,111 @@ +//------------------------------------------------------------------------= ------=0D +//=0D +// RISC-V CPU functions.=0D +//=0D +// Copyright (c) 2016 - 2020, Hewlett Packard Enterprise Development LP. A= ll rights reserved.
=0D +//=0D +// SPDX-License-Identifier: BSD-2-Clause-Patent=0D +//=0D +//------------------------------------------------------------------------= ------=0D +#include =0D +#include =0D +=0D +.data=0D +=0D +.text=0D +.align 3=0D +=0D +//=0D +// Set machine mode scratch.=0D +// @param a0 : Pointer to RISCV_MACHINE_MODE_CONTEXT.=0D +//=0D +ASM_FUNC (RiscVSetMachineScratch)=0D + csrrw a1, RISCV_CSR_MACHINE_MSCRATCH, a0=0D + ret=0D +=0D +//=0D +// Get machine mode scratch.=0D +// @retval a0 : Pointer to RISCV_MACHINE_MODE_CONTEXT.=0D +//=0D +ASM_FUNC (RiscVGetMachineScratch)=0D + csrrs a0, RISCV_CSR_MACHINE_MSCRATCH, 0=0D + ret=0D +=0D +//=0D +// Get machine trap cause CSR.=0D +//=0D +ASM_FUNC (RiscVGetMachineTrapCause)=0D + csrrs a0, RISCV_CSR_MACHINE_MCAUSE, 0=0D + ret=0D +=0D +//=0D +// Get machine interrupt enable=0D +//=0D +ASM_FUNC (RiscVReadMachineInterruptEnable)=0D + csrr a0, RISCV_CSR_MACHINE_MIE=0D + ret=0D +=0D +//=0D +// Get machine interrupt pending=0D +//=0D +ASM_FUNC (RiscVReadMachineInterruptPending)=0D + csrr a0, RISCV_CSR_MACHINE_MIP=0D + ret=0D +=0D +//=0D +// Get machine status=0D +//=0D +ASM_FUNC (RiscVReadMachineStatus)=0D + csrr a0, RISCV_CSR_MACHINE_MSTATUS=0D + ret=0D +=0D +//=0D +// Set machine status=0D +//=0D +ASM_FUNC (RiscVWriteMachineStatus)=0D + csrw RISCV_CSR_MACHINE_MSTATUS, a0=0D + ret=0D +=0D +//=0D +// Get machine trap vector=0D +//=0D +ASM_FUNC (RiscVReadMachineTrapVector)=0D + csrr a0, RISCV_CSR_MACHINE_MTVEC=0D + ret=0D +=0D +//=0D +// Read machine ISA=0D +//=0D +ASM_FUNC (RiscVReadMachineIsa)=0D + csrr a0, RISCV_CSR_MACHINE_MISA=0D + ret=0D +=0D +//=0D +// Read machine vendor ID=0D +//=0D +ASM_FUNC (RiscVReadMachineVendorId)=0D + csrr a0, RISCV_CSR_MACHINE_MVENDORID=0D + ret=0D +=0D +//=0D +// Read machine architecture ID=0D +//=0D +ASM_FUNC (RiscVReadMachineArchitectureId)=0D + csrr a0, RISCV_CSR_MACHINE_MARCHID=0D + ret=0D +=0D +//=0D +// Read machine implementation ID=0D +//=0D +ASM_FUNC (RiscVReadMachineImplementId)=0D + csrr a0, RISCV_CSR_MACHINE_MIMPID=0D + ret=0D +=0D +//=0D +// Set Supervisor Address Translation and=0D +// Protection Register.=0D +//=0D +ASM_FUNC (RiscVSetSupervisorAddressTranslationRegister)=0D + csrw RISCV_CSR_SUPERVISOR_SATP, a0=0D + ret=0D +=0D --=20 2.31.1