From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mx0a-002e3701.pphosted.com (mx0a-002e3701.pphosted.com [148.163.147.86]) by mx.groups.io with SMTP id smtpd.web12.2693.1641618756147169752 for ; Fri, 07 Jan 2022 21:12:36 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@hpe.com header.s=pps0720 header.b=DKtL1Udd; spf=permerror, err=parse error for token &{10 18 %{ir}.%{v}.%{d}.spf.has.pphosted.com}: invalid domain name (domain: hpe.com, ip: 148.163.147.86, mailfrom: prvs=000704d8ca=abner.chang@hpe.com) Received: from pps.filterd (m0134422.ppops.net [127.0.0.1]) by mx0b-002e3701.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 2084sjHX026974 for ; Sat, 8 Jan 2022 05:12:36 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=hpe.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding; s=pps0720; bh=k1L5H+1pPgYd9JOVDfLCdjtaot/Ms7VlcMQI86J07Mw=; b=DKtL1Udd9KVgaCkmipxIQFSP2OLBOLc0XEyHsS4SyuWIGqcQIvrWC99vrG6CVe80LyLo yjm5ulczxT243PjP0DRhWb4iD35UiPniSFPweAdwfN1TZ1Pe2GWitYnWbvOvxga393TK X88Xswzs4EbMOo6n9zFOngtfn4h25y00atCVBQT5NVDtvU9fw/Ir1pbFg+WExQVKiAMR laIYQ9jkFmp3IHqp9WYYbhF4wcbksA7zIwDah8FwzY1MXbvjyqdmCkLHYvdRbaLrL9b8 kNjpwfui90V25aMhb+2r3QMaeIghydVL1OpDiS8ui+jsknmf3P7GWbjTKDBY7EPgpLsd VQ== Received: from g2t2354.austin.hpe.com (g2t2354.austin.hpe.com [15.233.44.27]) by mx0b-002e3701.pphosted.com (PPS) with ESMTPS id 3df40k82yd-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Sat, 08 Jan 2022 05:12:35 +0000 Received: from g2t2360.austin.hpecorp.net (g2t2360.austin.hpecorp.net [16.196.225.135]) by g2t2354.austin.hpe.com (Postfix) with ESMTP id DD55481 for ; Sat, 8 Jan 2022 05:12:34 +0000 (UTC) Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.229]) by g2t2360.austin.hpecorp.net (Postfix) with ESMTP id 3205A36; Sat, 8 Jan 2022 05:12:34 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com Subject: [PATCH 14/79] PlatformPkg/Library: Add FirmwareContextProcessorSpecificLib module Date: Sat, 8 Jan 2022 12:10:34 +0800 Message-Id: <20220108041121.16005-13-abner.chang@hpe.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20220108041121.16005-1-abner.chang@hpe.com> References: <20220108041121.16005-1-abner.chang@hpe.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: evKuQkJZpEjsnW4BsOT8y_ciLLBUgWQz X-Proofpoint-GUID: evKuQkJZpEjsnW4BsOT8y_ciLLBUgWQz X-HPE-SCL: -1 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.790,Hydra:6.0.425,FMLib:17.11.62.513 definitions=2022-01-08_01,2022-01-07_01,2021-12-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 adultscore=0 priorityscore=1501 malwarescore=0 spamscore=0 clxscore=1015 phishscore=0 impostorscore=0 mlxscore=0 mlxlogscore=999 bulkscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2110150000 definitions=main-2201080036 Content-Transfer-Encoding: quoted-printable (This is migrated from edk2-platforms:Platform/RISC-V) Add OpenSBI firmware context processor specific library which provides interface to create processor specific firmware context hob data. Signed-off-by: Abner Chang Co-authored-by: Gilbert Chen Reviewed-by: Leif Lindholm Cc: Leif Lindholm Cc: Gilbert Chen --- .../FirmwareContextProcessorSpecificLib.inf | 31 +++++ .../FirmwareContextProcessorSpecificLib.h | 53 ++++++++ .../FirmwareContextProcessorSpecificLib.c | 119 ++++++++++++++++++ 3 files changed, 203 insertions(+) create mode 100644 Platform/RISC-V/PlatformPkg/Library/FirmwareContextProc= essorSpecificLib/FirmwareContextProcessorSpecificLib.inf create mode 100644 Platform/RISC-V/PlatformPkg/Include/Library/FirmwareCon= textProcessorSpecificLib.h create mode 100644 Platform/RISC-V/PlatformPkg/Library/FirmwareContextProc= essorSpecificLib/FirmwareContextProcessorSpecificLib.c diff --git a/Platform/RISC-V/PlatformPkg/Library/FirmwareContextProcessorSp= ecificLib/FirmwareContextProcessorSpecificLib.inf b/Platform/RISC-V/Platfor= mPkg/Library/FirmwareContextProcessorSpecificLib/FirmwareContextProcessorSp= ecificLib.inf new file mode 100644 index 0000000000..69568511ce --- /dev/null +++ b/Platform/RISC-V/PlatformPkg/Library/FirmwareContextProcessorSpecificL= ib/FirmwareContextProcessorSpecificLib.inf @@ -0,0 +1,31 @@ +#/** @file=0D +#=0D +# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
=0D +#=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +#**/=0D +=0D +[Defines]=0D + INF_VERSION =3D 0x0001001b=0D + BASE_NAME =3D FirmwareContextProcessorSpecificLib=0D + FILE_GUID =3D 8BEC9FD7-C554-403A-94F1-0EBBFD81A242= =0D + MODULE_TYPE =3D PEIM=0D + VERSION_STRING =3D 1.0=0D + LIBRARY_CLASS =3D FirmwareContextProcessorSpecificLib=0D +=0D +[Sources.common]=0D + FirmwareContextProcessorSpecificLib.c=0D +=0D +[Packages]=0D + MdeModulePkg/MdeModulePkg.dec=0D + MdePkg/MdePkg.dec=0D + Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec=0D +=0D +[LibraryClasses]=0D + BaseLib=0D + PcdLib=0D + MemoryAllocationLib=0D + PrintLib=0D +=0D +=0D diff --git a/Platform/RISC-V/PlatformPkg/Include/Library/FirmwareContextPro= cessorSpecificLib.h b/Platform/RISC-V/PlatformPkg/Include/Library/FirmwareC= ontextProcessorSpecificLib.h new file mode 100644 index 0000000000..f3b096c257 --- /dev/null +++ b/Platform/RISC-V/PlatformPkg/Include/Library/FirmwareContextProcessorS= pecificLib.h @@ -0,0 +1,53 @@ +/** @file=0D + Firmware Context Processor-specific common library=0D +=0D + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All right= s reserved.
=0D +=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +#ifndef FIRMWARE_CONTEXT_PROCESSOR_SPECIFIC_LIB_H=0D +#define FIRMWARE_CONTEXT_PROCESSOR_SPECIFIC_LIB_H=0D +=0D +#include =0D +#include =0D +#include =0D +=0D +/**=0D + Build up common firmware context processor-specific information=0D +=0D + @param FirmwareContextHartSpecific Pointer to EFI_RISCV_FIRMWARE_CONTE= XT_HART_SPECIFIC=0D + @param ParentProcessorGuid Pointer to GUID of Processor which = contains this core=0D + @param ParentProcessorUid Unique ID of pysical processor whic= h owns this core.=0D + @param CoreGuid Pointer to GUID of core=0D + @param HartId Hart ID of this core.=0D + @param IsBootHart This is boot hart or not=0D + @param ProcessorSpecDataHob Pointer to RISC_V_PROCESSOR_SPECIFI= C_DATA_HOB=0D +=0D + @return EFI_STATUS=0D +=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +CommonFirmwareContextHartSpecificInfo (=0D + EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC *FirmwareContextHartSpecific,=0D + EFI_GUID *ParentProcessorGuid,=0D + UINTN ParentProcessorUid,=0D + EFI_GUID *CoreGuid,=0D + UINTN HartId,=0D + BOOLEAN IsBootHart,=0D + RISC_V_PROCESSOR_SPECIFIC_HOB_DATA *ProcessorSpecDataHob=0D + );=0D +=0D +/**=0D + Print debug information of the processor specific data for a hart=0D +=0D + @param ProcessorSpecificDataHob Pointer to RISC_V_PROCESSOR_SPECIFI= C_DATA_HOB=0D +**/=0D +VOID=0D +EFIAPI=0D +DebugPrintHartSpecificInfo (=0D + RISC_V_PROCESSOR_SPECIFIC_HOB_DATA *ProcessorSpecificDataHob=0D + );=0D +=0D +#endif=0D diff --git a/Platform/RISC-V/PlatformPkg/Library/FirmwareContextProcessorSp= ecificLib/FirmwareContextProcessorSpecificLib.c b/Platform/RISC-V/PlatformP= kg/Library/FirmwareContextProcessorSpecificLib/FirmwareContextProcessorSpec= ificLib.c new file mode 100644 index 0000000000..c62f77bc49 --- /dev/null +++ b/Platform/RISC-V/PlatformPkg/Library/FirmwareContextProcessorSpecificL= ib/FirmwareContextProcessorSpecificLib.c @@ -0,0 +1,119 @@ +/**@file=0D + Common library to build upfirmware context processor-specific informatio= n=0D +=0D + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All right= s reserved.
=0D +=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +=0D +//=0D +// The package level header files this module uses=0D +//=0D +#include =0D +=0D +//=0D +// The Library classes this module consumes=0D +//=0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +=0D +/**=0D + Build up common firmware context processor-specific information=0D +=0D + @param FirmwareContextHartSpecific Pointer to EFI_RISCV_FIRMWARE_CONTE= XT_HART_SPECIFIC=0D + @param ParentProcessorGuid Pointer to GUID of Processor which = contains this core=0D + @param ParentProcessorUid Unique ID of pysical processor whic= h owns this core.=0D + @param CoreGuid Pointer to GUID of core=0D + @param HartId Hart ID of this core.=0D + @param IsBootHart This is boot hart or not=0D + @param ProcessorSpecificDataHob Pointer to RISC_V_PROCESSOR_SPECIFI= C_DATA_HOB=0D +=0D + @return EFI_STATUS=0D +=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +CommonFirmwareContextHartSpecificInfo (=0D + EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC *FirmwareContextHartSpecific,=0D + EFI_GUID *ParentProcessorGuid,=0D + UINTN ParentProcessorUid,=0D + EFI_GUID *CoreGuid,=0D + UINTN HartId,=0D + BOOLEAN IsBootHart,=0D + RISC_V_PROCESSOR_SPECIFIC_HOB_DATA *ProcessorSpecificDataHob=0D + )=0D +{=0D + //=0D + // Build up RISC_V_PROCESSOR_SPECIFIC_DATA_HOB.=0D + //=0D + CopyGuid (&ProcessorSpecificDataHob->ParentPrcessorGuid, ParentProcessor= Guid);=0D + ProcessorSpecificDataHob->ParentProcessorUid =3D ParentProcessorUid;=0D + CopyGuid (&ProcessorSpecificDataHob->CoreGuid, CoreGuid);=0D + ProcessorSpecificDataHob->Context =3D NULL;=0D + ProcessorSpecificDataHob->ProcessorSpecificData.Revision =3D=0D + SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA_REVISION;=0D + ProcessorSpecificDataHob->ProcessorSpecificData.Length =3D=0D + sizeof (SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA);=0D + ProcessorSpecificDataHob->ProcessorSpecificData.HartId.Value64_L =3D (UI= NT64)HartId;=0D + ProcessorSpecificDataHob->ProcessorSpecificData.HartId.Value64_H =3D 0;= =0D + ProcessorSpecificDataHob->ProcessorSpecificData.BootHartId =3D (UINT8)Is= BootHart;=0D + ProcessorSpecificDataHob->ProcessorSpecificData.InstSetSupported =3D=0D + FirmwareContextHartSpecific->IsaExtensionSupported;=0D + ProcessorSpecificDataHob->ProcessorSpecificData.PrivilegeModeSupported = =3D=0D + SMBIOS_RISC_V_PSD_MACHINE_MODE_SUPPORTED;=0D + if ((ProcessorSpecificDataHob->ProcessorSpecificData.InstSetSupported &= =0D + RISC_V_ISA_SUPERVISOR_MODE_IMPLEMENTED) !=3D 0) {=0D + ProcessorSpecificDataHob->ProcessorSpecificData.PrivilegeModeSupported= |=3D=0D + SMBIOS_RISC_V_PSD_SUPERVISOR_MODE_SUPPORTED;=0D + }=0D + if ((ProcessorSpecificDataHob->ProcessorSpecificData.InstSetSupported &= =0D + RISC_V_ISA_USER_MODE_IMPLEMENTED) !=3D 0) {=0D + ProcessorSpecificDataHob->ProcessorSpecificData.PrivilegeModeSupported= |=3D=0D + SMBIOS_RISC_V_PSD_USER_MODE_SUPPORTED;=0D + }=0D + ProcessorSpecificDataHob->ProcessorSpecificData.MachineVendorId.Value64_= L =3D=0D + FirmwareContextHartSpecific->MachineVendorId.Value64_L;=0D + ProcessorSpecificDataHob->ProcessorSpecificData.MachineVendorId.Value64_= H =3D=0D + FirmwareContextHartSpecific->MachineVendorId.Value64_H;=0D + ProcessorSpecificDataHob->ProcessorSpecificData.MachineArchId.Value64_L = =3D=0D + FirmwareContextHartSpecific->MachineArchId.Value64_L;=0D + ProcessorSpecificDataHob->ProcessorSpecificData.MachineArchId.Value64_H = =3D=0D + FirmwareContextHartSpecific->MachineArchId.Value64_H;=0D + ProcessorSpecificDataHob->ProcessorSpecificData.MachineImplId.Value64_L = =3D=0D + FirmwareContextHartSpecific->MachineImplId.Value64_L;=0D + ProcessorSpecificDataHob->ProcessorSpecificData.MachineImplId.Value64_H = =3D=0D + FirmwareContextHartSpecific->MachineImplId.Value64_H;=0D + return EFI_SUCCESS;=0D +}=0D +=0D +/**=0D + Print debug information of the processor specific data for a hart=0D +=0D + @param ProcessorSpecificDataHob Pointer to RISC_V_PROCESSOR_SPECIFI= C_DATA_HOB=0D +**/=0D +VOID=0D +EFIAPI=0D +DebugPrintHartSpecificInfo (=0D + RISC_V_PROCESSOR_SPECIFIC_HOB_DATA *ProcessorSpecificDataHob=0D + )=0D +{=0D + DEBUG ((DEBUG_INFO, " *HartId =3D 0x%x\n", ProcessorSpecificDataH= ob->ProcessorSpecificData.HartId.Value64_L));=0D + DEBUG ((DEBUG_INFO, " *Is Boot Hart? =3D 0x%x\n", ProcessorSpecif= icDataHob->ProcessorSpecificData.BootHartId));=0D + DEBUG ((DEBUG_INFO, " *PrivilegeModeSupported =3D 0x%x\n", Proces= sorSpecificDataHob->ProcessorSpecificData.PrivilegeModeSupported));=0D + DEBUG ((DEBUG_INFO, " *MModeExcepDelegation =3D 0x%x\n", Processo= rSpecificDataHob->ProcessorSpecificData.MModeExcepDelegation.Value64_L));=0D + DEBUG ((DEBUG_INFO, " *MModeInterruptDelegation =3D 0x%x\n", Proc= essorSpecificDataHob->ProcessorSpecificData.MModeInterruptDelegation.Value6= 4_L));=0D + DEBUG ((DEBUG_INFO, " *HartXlen =3D 0x%x\n", ProcessorSpecificDat= aHob->ProcessorSpecificData.HartXlen ));=0D + DEBUG ((DEBUG_INFO, " *MachineModeXlen =3D 0x%x\n", ProcessorSpec= ificDataHob->ProcessorSpecificData.MachineModeXlen));=0D + DEBUG ((DEBUG_INFO, " *SupervisorModeXlen =3D 0x%x\n", ProcessorS= pecificDataHob->ProcessorSpecificData.SupervisorModeXlen));=0D + DEBUG ((DEBUG_INFO, " *UserModeXlen =3D 0x%x\n", ProcessorSpecifi= cDataHob->ProcessorSpecificData.UserModeXlen));=0D + DEBUG ((DEBUG_INFO, " *InstSetSupported =3D 0x%x\n", ProcessorSpe= cificDataHob->ProcessorSpecificData.InstSetSupported));=0D + DEBUG ((DEBUG_INFO, " *MachineVendorId =3D 0x%x\n", ProcessorSpec= ificDataHob->ProcessorSpecificData.MachineVendorId.Value64_L));=0D + DEBUG ((DEBUG_INFO, " *MachineArchId =3D 0x%x\n", ProcessorSpecif= icDataHob->ProcessorSpecificData.MachineArchId.Value64_L));=0D + DEBUG ((DEBUG_INFO, " *MachineImplId =3D 0x%x\n", ProcessorSpecif= icDataHob->ProcessorSpecificData.MachineImplId.Value64_L));=0D +}=0D --=20 2.31.1