From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mx0b-002e3701.pphosted.com (mx0b-002e3701.pphosted.com [148.163.143.35]) by mx.groups.io with SMTP id smtpd.web09.2657.1641618744853147990 for ; Fri, 07 Jan 2022 21:12:25 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@hpe.com header.s=pps0720 header.b=BwBJE7ZN; spf=permerror, err=parse error for token &{10 18 %{ir}.%{v}.%{d}.spf.has.pphosted.com}: invalid domain name (domain: hpe.com, ip: 148.163.143.35, mailfrom: prvs=000704d8ca=abner.chang@hpe.com) Received: from pps.filterd (m0150245.ppops.net [127.0.0.1]) by mx0b-002e3701.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 2084fiZ6020987 for ; Sat, 8 Jan 2022 05:12:24 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=hpe.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding; s=pps0720; bh=hQUmznxJ7qhR806n45QiEJkiq87ZgJf4w2/x00Hhzj8=; b=BwBJE7ZN4++v5KmuPVYFV+s5FnXFNbNQiZrkynPNSpXVIpxDNKU9FO+dZMrtAQYrZrHp gH2rJMSDa0ckw91KEKAJNqIwY8+wc/LVXvZWpFGPqR3wH0T7j+p3/TJVCt/pWQ6/yMAq +IGWm7ric0OVEuyBSEU1KEUyJzkU4gk+tv3lWEKaPqcidEfUCP5E+nCU3iCZ8LJFKLyx 7WOcB7uymhGWrzm7OMKq6g3Wzy1XM6pGirf2Nf4f5O3dc/dASNDS6hkb8ZiBf6E6ziQS N1K+f4URPK1TOlKizMJ8mOjAcARUY7U0sAeW4rXYPOBRFy+6taBw5WxLVsMmCh1UIj3A gQ== Received: from g2t2352.austin.hpe.com (g2t2352.austin.hpe.com [15.233.44.25]) by mx0b-002e3701.pphosted.com (PPS) with ESMTPS id 3df3tfg4a7-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Sat, 08 Jan 2022 05:12:23 +0000 Received: from g2t2360.austin.hpecorp.net (g2t2360.austin.hpecorp.net [16.196.225.135]) by g2t2352.austin.hpe.com (Postfix) with ESMTP id 31F7963 for ; Sat, 8 Jan 2022 05:12:23 +0000 (UTC) Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.229]) by g2t2360.austin.hpecorp.net (Postfix) with ESMTP id 790603D; Sat, 8 Jan 2022 05:12:22 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com Subject: [PATCH 03/79] ProcessorPkg/Library: Add RISC-V exception library Date: Sat, 8 Jan 2022 12:10:23 +0800 Message-Id: <20220108041121.16005-2-abner.chang@hpe.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20220108041121.16005-1-abner.chang@hpe.com> References: <20220108041121.16005-1-abner.chang@hpe.com> MIME-Version: 1.0 X-Proofpoint-GUID: zmNPIGTNCJOp9CSB_Ta8pxQLZNseylcT X-Proofpoint-ORIG-GUID: zmNPIGTNCJOp9CSB_Ta8pxQLZNseylcT X-HPE-SCL: -1 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.790,Hydra:6.0.425,FMLib:17.11.62.513 definitions=2022-01-08_01,2022-01-07_01,2021-12-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 malwarescore=0 phishscore=0 spamscore=0 mlxscore=0 lowpriorityscore=0 impostorscore=0 mlxlogscore=999 adultscore=0 clxscore=1015 priorityscore=1501 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2110150000 definitions=main-2201080036 Content-Transfer-Encoding: quoted-printable (This is migrated from edk2-platforms:Silicon/RISC-V) Initial RISC-V Supervisor Mode trap handler. Signed-off-by: Abner Chang Co-authored-by: Gilbert Chen Reviewed-by: Leif Lindholm Cc: Leif Lindholm Cc: Gilbert Chen --- .../CpuExceptionHandlerDxeLib.inf | 43 ++++ .../CpuExceptionHandlerLib.h | 107 ++++++++++ .../CpuExceptionHandlerLib.c | 194 ++++++++++++++++++ .../CpuExceptionHandlerLib.uni | 13 ++ .../RiscVExceptionLib/SupervisorTrapHandler.S | 112 ++++++++++ 5 files changed, 469 insertions(+) create mode 100644 Silicon/RISC-V/ProcessorPkg/Library/RiscVExceptionLib/C= puExceptionHandlerDxeLib.inf create mode 100644 Silicon/RISC-V/ProcessorPkg/Library/RiscVExceptionLib/C= puExceptionHandlerLib.h create mode 100644 Silicon/RISC-V/ProcessorPkg/Library/RiscVExceptionLib/C= puExceptionHandlerLib.c create mode 100644 Silicon/RISC-V/ProcessorPkg/Library/RiscVExceptionLib/C= puExceptionHandlerLib.uni create mode 100644 Silicon/RISC-V/ProcessorPkg/Library/RiscVExceptionLib/S= upervisorTrapHandler.S diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVExceptionLib/CpuExcep= tionHandlerDxeLib.inf b/Silicon/RISC-V/ProcessorPkg/Library/RiscVExceptionL= ib/CpuExceptionHandlerDxeLib.inf new file mode 100644 index 0000000000..fc200d3cca --- /dev/null +++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVExceptionLib/CpuExceptionHan= dlerDxeLib.inf @@ -0,0 +1,43 @@ +## @file=0D +# RISC-V CPU Exception Handler Library=0D +#=0D +# Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. A= ll rights reserved.
=0D +#=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +#=0D +=0D +[Defines]=0D + INF_VERSION =3D 0x0001001b=0D + BASE_NAME =3D CpuExceptionHandlerLib=0D + MODULE_UNI_FILE =3D CpuExceptionHandlerLib.uni=0D + FILE_GUID =3D 16309FCF-E900-459C-B071-052118394D11= =0D + MODULE_TYPE =3D DXE_DRIVER=0D + VERSION_STRING =3D 1.0=0D + LIBRARY_CLASS =3D CpuExceptionHandlerLib=0D + CONSTRUCTOR =3D CpuExceptionHandlerLibConstructor=0D +=0D +#=0D +# The following information is for reference only and not required by the = build tools.=0D +#=0D +# VALID_ARCHITECTURES =3D RISCV64=0D +#=0D +=0D +[Sources.RISCV64]=0D + SupervisorTrapHandler.S=0D +=0D +[Sources.common]=0D + CpuExceptionHandlerLib.c=0D + CpuExceptionHandlerLib.h=0D +=0D +[LibraryClasses]=0D + BaseLib=0D + DebugLib=0D + RiscVCpuLib=0D + UefiBootServicesTableLib=0D +=0D +[Packages]=0D + MdePkg/MdePkg.dec=0D + MdeModulePkg/MdeModulePkg.dec=0D + Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec=0D +=0D diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVExceptionLib/CpuExcep= tionHandlerLib.h b/Silicon/RISC-V/ProcessorPkg/Library/RiscVExceptionLib/Cp= uExceptionHandlerLib.h new file mode 100644 index 0000000000..3e480e9b09 --- /dev/null +++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVExceptionLib/CpuExceptionHan= dlerLib.h @@ -0,0 +1,107 @@ +/**@file=0D +=0D + RISC-V Exception Handler library definition file.=0D +=0D + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All right= s reserved.
=0D +=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +=0D +#ifndef RISCV_CPU_EXECPTION_HANDLER_LIB_H_=0D +#define RISCV_CPU_EXECPTION_HANDLER_LIB_H_=0D +=0D +extern void SupervisorModeTrap(void);=0D +=0D +//=0D +// Index of SMode trap register=0D +//=0D +#define SMODE_TRAP_REGS_zero 0=0D +#define SMODE_TRAP_REGS_ra 1=0D +#define SMODE_TRAP_REGS_sp 2=0D +#define SMODE_TRAP_REGS_gp 3=0D +#define SMODE_TRAP_REGS_tp 4=0D +#define SMODE_TRAP_REGS_t0 5=0D +#define SMODE_TRAP_REGS_t1 6=0D +#define SMODE_TRAP_REGS_t2 7=0D +#define SMODE_TRAP_REGS_s0 8=0D +#define SMODE_TRAP_REGS_s1 9=0D +#define SMODE_TRAP_REGS_a0 10=0D +#define SMODE_TRAP_REGS_a1 11=0D +#define SMODE_TRAP_REGS_a2 12=0D +#define SMODE_TRAP_REGS_a3 13=0D +#define SMODE_TRAP_REGS_a4 14=0D +#define SMODE_TRAP_REGS_a5 15=0D +#define SMODE_TRAP_REGS_a6 16=0D +#define SMODE_TRAP_REGS_a7 17=0D +#define SMODE_TRAP_REGS_s2 18=0D +#define SMODE_TRAP_REGS_s3 19=0D +#define SMODE_TRAP_REGS_s4 20=0D +#define SMODE_TRAP_REGS_s5 21=0D +#define SMODE_TRAP_REGS_s6 22=0D +#define SMODE_TRAP_REGS_s7 23=0D +#define SMODE_TRAP_REGS_s8 24=0D +#define SMODE_TRAP_REGS_s9 25=0D +#define SMODE_TRAP_REGS_s10 26=0D +#define SMODE_TRAP_REGS_s11 27=0D +#define SMODE_TRAP_REGS_t3 28=0D +#define SMODE_TRAP_REGS_t4 29=0D +#define SMODE_TRAP_REGS_t5 30=0D +#define SMODE_TRAP_REGS_t6 31=0D +#define SMODE_TRAP_REGS_sepc 32=0D +#define SMODE_TRAP_REGS_sstatus 33=0D +#define SMODE_TRAP_REGS_sie 34=0D +#define SMODE_TRAP_REGS_last 35=0D +=0D +#define SMODE_TRAP_REGS_OFFSET(x) ((SMODE_TRAP_REGS_##x) * __SIZEOF_POINTE= R__)=0D +#define SMODE_TRAP_REGS_SIZE SMODE_TRAP_REGS_OFFSET(last)=0D +=0D +#pragma pack(1)=0D +typedef struct {=0D +//=0D +// Below are follow the format of EFI_SYSTEM_CONTEXT=0D +//=0D + RISC_V_REGS_PROTOTYPE zero;=0D + RISC_V_REGS_PROTOTYPE ra;=0D + RISC_V_REGS_PROTOTYPE sp;=0D + RISC_V_REGS_PROTOTYPE gp;=0D + RISC_V_REGS_PROTOTYPE tp;=0D + RISC_V_REGS_PROTOTYPE t0;=0D + RISC_V_REGS_PROTOTYPE t1;=0D + RISC_V_REGS_PROTOTYPE t2;=0D + RISC_V_REGS_PROTOTYPE s0;=0D + RISC_V_REGS_PROTOTYPE s1;=0D + RISC_V_REGS_PROTOTYPE a0;=0D + RISC_V_REGS_PROTOTYPE a1;=0D + RISC_V_REGS_PROTOTYPE a2;=0D + RISC_V_REGS_PROTOTYPE a3;=0D + RISC_V_REGS_PROTOTYPE a4;=0D + RISC_V_REGS_PROTOTYPE a5;=0D + RISC_V_REGS_PROTOTYPE a6;=0D + RISC_V_REGS_PROTOTYPE a7;=0D + RISC_V_REGS_PROTOTYPE s2;=0D + RISC_V_REGS_PROTOTYPE s3;=0D + RISC_V_REGS_PROTOTYPE s4;=0D + RISC_V_REGS_PROTOTYPE s5;=0D + RISC_V_REGS_PROTOTYPE s6;=0D + RISC_V_REGS_PROTOTYPE s7;=0D + RISC_V_REGS_PROTOTYPE s8;=0D + RISC_V_REGS_PROTOTYPE s9;=0D + RISC_V_REGS_PROTOTYPE s10;=0D + RISC_V_REGS_PROTOTYPE s11;=0D + RISC_V_REGS_PROTOTYPE t3;=0D + RISC_V_REGS_PROTOTYPE t4;=0D + RISC_V_REGS_PROTOTYPE t5;=0D + RISC_V_REGS_PROTOTYPE t6;=0D +//=0D +// Below are the additional information to=0D +// EFI_SYSTEM_CONTEXT, private to supervisor mode trap=0D +// and not public to EFI environment.=0D +//=0D + RISC_V_REGS_PROTOTYPE sepc;=0D + RISC_V_REGS_PROTOTYPE sstatus;=0D + RISC_V_REGS_PROTOTYPE sie;=0D +} SMODE_TRAP_REGISTERS;=0D +#pragma pack()=0D +=0D +#endif=0D diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVExceptionLib/CpuExcep= tionHandlerLib.c b/Silicon/RISC-V/ProcessorPkg/Library/RiscVExceptionLib/Cp= uExceptionHandlerLib.c new file mode 100644 index 0000000000..a9316ae758 --- /dev/null +++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVExceptionLib/CpuExceptionHan= dlerLib.c @@ -0,0 +1,194 @@ +/** @file=0D + RISC-V Exception Handler library implementition.=0D +=0D + Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. Al= l rights reserved.
=0D +=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +=0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +=0D +#include "CpuExceptionHandlerLib.h"=0D +=0D +STATIC EFI_CPU_INTERRUPT_HANDLER mInterruptHandlers[2];=0D +=0D +/**=0D + Initializes all CPU exceptions entries and provides the default exceptio= n handlers.=0D +=0D + Caller should try to get an array of interrupt and/or exception vectors = that are in use and need to=0D + persist by EFI_VECTOR_HANDOFF_INFO defined in PI 1.3 specification.=0D + If caller cannot get reserved vector list or it does not exists, set Vec= torInfo to NULL.=0D + If VectorInfo is not NULL, the exception vectors will be initialized per= vector attribute accordingly.=0D +=0D + @param[in] VectorInfo Pointer to reserved vector list.=0D +=0D + @retval EFI_SUCCESS CPU Exception Entries have been successful= ly initialized=0D + with default exception handlers.=0D + @retval EFI_INVALID_PARAMETER VectorInfo includes the invalid content if= VectorInfo is not NULL.=0D + @retval EFI_UNSUPPORTED This function is not supported.=0D +=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +InitializeCpuExceptionHandlers (=0D + IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL=0D + )=0D +{=0D + return EFI_SUCCESS;=0D +}=0D +=0D +/**=0D + Initializes all CPU interrupt/exceptions entries and provides the defaul= t interrupt/exception handlers.=0D +=0D + Caller should try to get an array of interrupt and/or exception vectors = that are in use and need to=0D + persist by EFI_VECTOR_HANDOFF_INFO defined in PI 1.3 specification.=0D + If caller cannot get reserved vector list or it does not exists, set Vec= torInfo to NULL.=0D + If VectorInfo is not NULL, the exception vectors will be initialized per= vector attribute accordingly.=0D +=0D + @param[in] VectorInfo Pointer to reserved vector list.=0D +=0D + @retval EFI_SUCCESS All CPU interrupt/exception entries have b= een successfully initialized=0D + with default interrupt/exception handlers.= =0D + @retval EFI_INVALID_PARAMETER VectorInfo includes the invalid content if= VectorInfo is not NULL.=0D + @retval EFI_UNSUPPORTED This function is not supported.=0D +=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +InitializeCpuInterruptHandlers (=0D + IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL=0D + )=0D +{=0D + return EFI_SUCCESS;=0D +}=0D +=0D +/**=0D + Registers a function to be called from the processor interrupt handler.= =0D +=0D + This function registers and enables the handler specified by InterruptHa= ndler for a processor=0D + interrupt or exception type specified by InterruptType. If InterruptHand= ler is NULL, then the=0D + handler for the processor interrupt or exception type specified by Inter= ruptType is uninstalled.=0D + The installed handler is called once for each processor interrupt or exc= eption.=0D + NOTE: This function should be invoked after InitializeCpuExceptionHandle= rs() or=0D + InitializeCpuInterruptHandlers() invoked, otherwise EFI_UNSUPPORTED retu= rned.=0D +=0D + @param[in] InterruptType Defines which interrupt or exception to ho= ok.=0D + @param[in] InterruptHandler A pointer to a function of type EFI_CPU_IN= TERRUPT_HANDLER that is called=0D + when a processor interrupt occurs. If this= parameter is NULL, then the handler=0D + will be uninstalled.=0D +=0D + @retval EFI_SUCCESS The handler for the processor interrupt wa= s successfully installed or uninstalled.=0D + @retval EFI_ALREADY_STARTED InterruptHandler is not NULL, and a handle= r for InterruptType was=0D + previously installed.=0D + @retval EFI_INVALID_PARAMETER InterruptHandler is NULL, and a handler fo= r InterruptType was not=0D + previously installed.=0D + @retval EFI_UNSUPPORTED The interrupt specified by InterruptType i= s not supported,=0D + or this function is not supported.=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +RegisterCpuInterruptHandler (=0D + IN EFI_EXCEPTION_TYPE InterruptType,=0D + IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler=0D + )=0D +{=0D +=0D + DEBUG ((DEBUG_INFO, "%a: Type:%x Handler: %x\n", __FUNCTION__, Interrupt= Type, InterruptHandler));=0D + mInterruptHandlers[InterruptType] =3D InterruptHandler;=0D + return EFI_SUCCESS;=0D +}=0D +/**=0D + Machine mode trap handler.=0D +=0D + @param[in] SmodeTrapReg Registers before trap occurred.=0D +=0D +**/=0D +VOID=0D +RiscVSupervisorModeTrapHandler (=0D + SMODE_TRAP_REGISTERS *SmodeTrapReg=0D + )=0D +{=0D + UINTN SCause;=0D + EFI_SYSTEM_CONTEXT RiscVSystemContext;=0D +=0D + RiscVSystemContext.SystemContextRiscV64 =3D (EFI_SYSTEM_CONTEXT_RISCV64 = *)SmodeTrapReg;=0D + //=0D + // Check scasue register.=0D + //=0D + SCause =3D (UINTN)csr_read(RISCV_CSR_SUPERVISOR_SCAUSE);=0D + if ((SCause & (1UL << (sizeof (UINTN) * 8- 1))) !=3D 0) {=0D + //=0D + // This is interrupt event.=0D + //=0D + SCause &=3D ~(1UL << (sizeof (UINTN) * 8- 1));=0D + if((SCause =3D=3D SCAUSE_SUPERVISOR_TIMER_INT) && (mInterruptHandlers[= EXCEPT_RISCV_TIMER_INT] !=3D NULL)) {=0D + mInterruptHandlers[EXCEPT_RISCV_TIMER_INT](EXCEPT_RISCV_TIMER_INT, R= iscVSystemContext);=0D + }=0D + }=0D +}=0D +=0D +/**=0D + Initializes all CPU exceptions entries with optional extra initializatio= ns.=0D +=0D + By default, this method should include all functionalities implemented b= y=0D + InitializeCpuExceptionHandlers(), plus extra initialization works, if an= y.=0D + This could be done by calling InitializeCpuExceptionHandlers() directly= =0D + in this method besides the extra works.=0D +=0D + InitData is optional and its use and content are processor arch dependen= t.=0D + The typical usage of it is to convey resources which have to be reserved= =0D + elsewhere and are necessary for the extra initializations of exception.= =0D +=0D + @param[in] VectorInfo Pointer to reserved vector list.=0D + @param[in] InitData Pointer to data optional for extra initializat= ions=0D + of exception.=0D +=0D + @retval EFI_SUCCESS The exceptions have been successfully=0D + initialized.=0D + @retval EFI_INVALID_PARAMETER VectorInfo or InitData contains invalid= =0D + content.=0D + @retval EFI_UNSUPPORTED This function is not supported.=0D +=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +InitializeCpuExceptionHandlersEx (=0D + IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL,=0D + IN CPU_EXCEPTION_INIT_DATA *InitData OPTIONAL=0D + )=0D +{=0D + return InitializeCpuExceptionHandlers (VectorInfo);=0D +}=0D +=0D +/**=0D + The constructor function to initial interrupt handlers in=0D + RISCV_MACHINE_MODE_CONTEXT.=0D +=0D + @param ImageHandle The firmware allocated handle for the EFI image.=0D + @param SystemTable A pointer to the EFI System Table.=0D +=0D + @retval EFI_SUCCESS The destructor completed successfully.=0D + @retval Other value The destructor did not complete successfully.=0D +=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +CpuExceptionHandlerLibConstructor (=0D + IN EFI_HANDLE ImageHandle,=0D + IN EFI_SYSTEM_TABLE *SystemTable=0D + )=0D +{=0D + //=0D + // Set Superviosr mode trap handler.=0D + //=0D + csr_write(CSR_STVEC, SupervisorModeTrap);=0D +=0D + return EFI_SUCCESS;=0D +}=0D diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVExceptionLib/CpuExcep= tionHandlerLib.uni b/Silicon/RISC-V/ProcessorPkg/Library/RiscVExceptionLib/= CpuExceptionHandlerLib.uni new file mode 100644 index 0000000000..00cca22130 --- /dev/null +++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVExceptionLib/CpuExceptionHan= dlerLib.uni @@ -0,0 +1,13 @@ +// /** @file=0D +//=0D +// Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. A= ll rights reserved.
=0D +//=0D +// SPDX-License-Identifier: BSD-2-Clause-Patent=0D +//=0D +// **/=0D +=0D +=0D +#string STR_MODULE_ABSTRACT #language en-US "RISC-V CPU Except= ion Handler Librarys."=0D +=0D +#string STR_MODULE_DESCRIPTION #language en-US "RISC-V CPU Except= ion Handler Librarys."=0D +=0D diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVExceptionLib/Supervis= orTrapHandler.S b/Silicon/RISC-V/ProcessorPkg/Library/RiscVExceptionLib/Sup= ervisorTrapHandler.S new file mode 100644 index 0000000000..f6699bb19b --- /dev/null +++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVExceptionLib/SupervisorTrapH= andler.S @@ -0,0 +1,112 @@ +/** @file=0D + RISC-V Processor supervisor mode trap handler=0D +=0D + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All right= s reserved.
=0D +=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +=0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +=0D +#include "CpuExceptionHandlerLib.h"=0D +=0D + .align 3=0D + .section .entry, "ax", %progbits=0D + .globl SupervisorModeTrap=0D +SupervisorModeTrap:=0D + addi sp, sp, -SMODE_TRAP_REGS_SIZE=0D +=0D + /* Save all general regisers except SP */=0D + sd t0, SMODE_TRAP_REGS_OFFSET(t0)(sp)=0D +=0D + csrr t0, RISCV_CSR_SUPERVISOR_SSTATUS=0D + and t0, t0, (1 << SSTATUS_SIE_BIT_POSITION) | (1 << SSTATUS_SPP_BIT_PO= SITION)=0D + sd t0, SMODE_TRAP_REGS_OFFSET(sstatus)(sp)=0D + csrr t0, RISCV_CSR_SUPERVISOR_SEPC=0D + sd t0, SMODE_TRAP_REGS_OFFSET(sepc)(sp)=0D + csrr t0, RISCV_CSR_SUPERVISOR_SIE=0D + sd t0, SMODE_TRAP_REGS_OFFSET(sie)(sp)=0D + ld t0, SMODE_TRAP_REGS_OFFSET(t0)(sp)=0D +=0D + sd ra, SMODE_TRAP_REGS_OFFSET(ra)(sp)=0D + sd gp, SMODE_TRAP_REGS_OFFSET(gp)(sp)=0D + sd tp, SMODE_TRAP_REGS_OFFSET(tp)(sp)=0D + sd t1, SMODE_TRAP_REGS_OFFSET(t1)(sp)=0D + sd t2, SMODE_TRAP_REGS_OFFSET(t2)(sp)=0D + sd s0, SMODE_TRAP_REGS_OFFSET(s0)(sp)=0D + sd s1, SMODE_TRAP_REGS_OFFSET(s1)(sp)=0D + sd a0, SMODE_TRAP_REGS_OFFSET(a0)(sp)=0D + sd a1, SMODE_TRAP_REGS_OFFSET(a1)(sp)=0D + sd a2, SMODE_TRAP_REGS_OFFSET(a2)(sp)=0D + sd a3, SMODE_TRAP_REGS_OFFSET(a3)(sp)=0D + sd a4, SMODE_TRAP_REGS_OFFSET(a4)(sp)=0D + sd a5, SMODE_TRAP_REGS_OFFSET(a5)(sp)=0D + sd a6, SMODE_TRAP_REGS_OFFSET(a6)(sp)=0D + sd a7, SMODE_TRAP_REGS_OFFSET(a7)(sp)=0D + sd s2, SMODE_TRAP_REGS_OFFSET(s2)(sp)=0D + sd s3, SMODE_TRAP_REGS_OFFSET(s3)(sp)=0D + sd s4, SMODE_TRAP_REGS_OFFSET(s4)(sp)=0D + sd s5, SMODE_TRAP_REGS_OFFSET(s5)(sp)=0D + sd s6, SMODE_TRAP_REGS_OFFSET(s6)(sp)=0D + sd s7, SMODE_TRAP_REGS_OFFSET(s7)(sp)=0D + sd s8, SMODE_TRAP_REGS_OFFSET(s8)(sp)=0D + sd s9, SMODE_TRAP_REGS_OFFSET(s9)(sp)=0D + sd s10, SMODE_TRAP_REGS_OFFSET(s10)(sp)=0D + sd s11, SMODE_TRAP_REGS_OFFSET(s11)(sp)=0D + sd t3, SMODE_TRAP_REGS_OFFSET(t3)(sp)=0D + sd t4, SMODE_TRAP_REGS_OFFSET(t4)(sp)=0D + sd t5, SMODE_TRAP_REGS_OFFSET(t5)(sp)=0D + sd t6, SMODE_TRAP_REGS_OFFSET(t6)(sp)=0D +=0D + /* Call to Supervisor mode trap handler in CpuExceptionHandlerLib.c */=0D + call RiscVSupervisorModeTrapHandler=0D +=0D + /* Restore all general regisers except SP */=0D + ld ra, SMODE_TRAP_REGS_OFFSET(ra)(sp)=0D + ld gp, SMODE_TRAP_REGS_OFFSET(gp)(sp)=0D + ld tp, SMODE_TRAP_REGS_OFFSET(tp)(sp)=0D + ld t2, SMODE_TRAP_REGS_OFFSET(t2)(sp)=0D + ld s0, SMODE_TRAP_REGS_OFFSET(s0)(sp)=0D + ld s1, SMODE_TRAP_REGS_OFFSET(s1)(sp)=0D + ld a0, SMODE_TRAP_REGS_OFFSET(a0)(sp)=0D + ld a1, SMODE_TRAP_REGS_OFFSET(a1)(sp)=0D + ld a2, SMODE_TRAP_REGS_OFFSET(a2)(sp)=0D + ld a3, SMODE_TRAP_REGS_OFFSET(a3)(sp)=0D + ld a4, SMODE_TRAP_REGS_OFFSET(a4)(sp)=0D + ld a5, SMODE_TRAP_REGS_OFFSET(a5)(sp)=0D + ld a6, SMODE_TRAP_REGS_OFFSET(a6)(sp)=0D + ld a7, SMODE_TRAP_REGS_OFFSET(a7)(sp)=0D + ld s2, SMODE_TRAP_REGS_OFFSET(s2)(sp)=0D + ld s3, SMODE_TRAP_REGS_OFFSET(s3)(sp)=0D + ld s4, SMODE_TRAP_REGS_OFFSET(s4)(sp)=0D + ld s5, SMODE_TRAP_REGS_OFFSET(s5)(sp)=0D + ld s6, SMODE_TRAP_REGS_OFFSET(s6)(sp)=0D + ld s7, SMODE_TRAP_REGS_OFFSET(s7)(sp)=0D + ld s8, SMODE_TRAP_REGS_OFFSET(s8)(sp)=0D + ld s9, SMODE_TRAP_REGS_OFFSET(s9)(sp)=0D + ld s10, SMODE_TRAP_REGS_OFFSET(s10)(sp)=0D + ld s11, SMODE_TRAP_REGS_OFFSET(s11)(sp)=0D + ld t3, SMODE_TRAP_REGS_OFFSET(t3)(sp)=0D + ld t4, SMODE_TRAP_REGS_OFFSET(t4)(sp)=0D + ld t5, SMODE_TRAP_REGS_OFFSET(t5)(sp)=0D + ld t6, SMODE_TRAP_REGS_OFFSET(t6)(sp)=0D +=0D + ld t0, SMODE_TRAP_REGS_OFFSET(sepc)(sp)=0D + csrw RISCV_CSR_SUPERVISOR_SEPC, t0=0D + ld t0, SMODE_TRAP_REGS_OFFSET(sie)(sp)=0D + csrw RISCV_CSR_SUPERVISOR_SIE, t0=0D + csrr t0, RISCV_CSR_SUPERVISOR_SSTATUS=0D + ld t1, SMODE_TRAP_REGS_OFFSET(sstatus)(sp)=0D + or t0, t0, t1=0D + csrw RISCV_CSR_SUPERVISOR_SSTATUS, t0=0D + ld t1, SMODE_TRAP_REGS_OFFSET(t1)(sp)=0D + ld t0, SMODE_TRAP_REGS_OFFSET(t0)(sp)=0D + addi sp, sp, SMODE_TRAP_REGS_SIZE=0D + sret=0D --=20 2.31.1