From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mx0b-002e3701.pphosted.com (mx0b-002e3701.pphosted.com [148.163.143.35]) by mx.groups.io with SMTP id smtpd.web09.2661.1641618763744722293 for ; Fri, 07 Jan 2022 21:12:44 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@hpe.com header.s=pps0720 header.b=nUTGCzJ3; spf=permerror, err=parse error for token &{10 18 %{ir}.%{v}.%{d}.spf.has.pphosted.com}: invalid domain name (domain: hpe.com, ip: 148.163.143.35, mailfrom: prvs=000704d8ca=abner.chang@hpe.com) Received: from pps.filterd (m0134425.ppops.net [127.0.0.1]) by mx0b-002e3701.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 2084negg022121 for ; Sat, 8 Jan 2022 05:12:43 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=hpe.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : content-transfer-encoding : mime-version; s=pps0720; bh=moWKDgiJuztrKgIcT0G9Bbx3aoCdrHWhHhxi5ENtYac=; b=nUTGCzJ3mFk4dzmAPQZorwPyL5VQVUKbuslhMtAczRV5gre3rEZ3EYLgEocy5KCz///3 xWShF0dtruU17nMFrwBMRulAOhzPOQXPCnXjnPmC+V74TGOmO/B5+wH/+mRsZ3yB2c6+ Ai0YFAUNtduqpRi9whhFAcAvGPL/kkBiRIjBInJ7ne+oyW8ohkhbTHa31tADV5AHdUig kDZ+bKn5wCMvyD5BlI6nwISSOjxoL9HeYEe+00ty7UXdClkUWgoODY4DNY5d0xoIcmOg AtuWqrJpzqoPgmRiL4lNWhAsNwsP+Okzyh+Lvb7ttBWs/Qg/OwQjVq1YLTQdG2R/n36j Wg== Received: from g2t2354.austin.hpe.com (g2t2354.austin.hpe.com [15.233.44.27]) by mx0b-002e3701.pphosted.com (PPS) with ESMTPS id 3df3wtg3be-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Sat, 08 Jan 2022 05:12:42 +0000 Received: from g2t2360.austin.hpecorp.net (g2t2360.austin.hpecorp.net [16.196.225.135]) by g2t2354.austin.hpe.com (Postfix) with ESMTP id 32BC59D for ; Sat, 8 Jan 2022 05:12:42 +0000 (UTC) Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.229]) by g2t2360.austin.hpecorp.net (Postfix) with ESMTP id 7B3C637; Sat, 8 Jan 2022 05:12:41 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com Subject: [PATCH 21/79] RISC-V/PlatformPkg: Revise Readme.md Date: Sat, 8 Jan 2022 12:10:41 +0800 Message-Id: <20220108041121.16005-20-abner.chang@hpe.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20220108041121.16005-1-abner.chang@hpe.com> References: <20220108041121.16005-1-abner.chang@hpe.com> X-Proofpoint-GUID: wk8so8w9210cydNNyKqRPyg1ME8OspkW X-Proofpoint-ORIG-GUID: wk8so8w9210cydNNyKqRPyg1ME8OspkW X-Proofpoint-UnRewURL: 0 URL was un-rewritten MIME-Version: 1.0 X-HPE-SCL: -1 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.790,Hydra:6.0.425,FMLib:17.11.62.513 definitions=2022-01-08_01,2022-01-07_01,2021-12-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 phishscore=0 bulkscore=0 priorityscore=1501 suspectscore=0 lowpriorityscore=0 spamscore=0 impostorscore=0 mlxscore=0 malwarescore=0 clxscore=1015 mlxlogscore=999 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2110150000 definitions=main-2201080036 Content-Transfer-Encoding: quoted-printable (This is migrated from edk2-platforms:Platform) Update RISC-V PlatformPkg Readme.md to align with the latest implementation. Signed-off-by: Abner Chang Co-authored-by: Daniel Schaefer Reviewed-by: Daniel Schaefer Cc: Leif Lindholm Cc: Michael D Kinney Cc: Daniel Schaefer --- Platform/RISC-V/PlatformPkg/Readme.md | 88 ++++++++++++++++----------- 1 file changed, 52 insertions(+), 36 deletions(-) diff --git a/Platform/RISC-V/PlatformPkg/Readme.md b/Platform/RISC-V/Platfo= rmPkg/Readme.md index 2632ebeb28..4b933a2e0f 100644 --- a/Platform/RISC-V/PlatformPkg/Readme.md +++ b/Platform/RISC-V/PlatformPkg/Readme.md @@ -1,49 +1,62 @@ # Introduction=0D =0D -## EDK2 RISC-V Platform Packages=0D -RISC-V platform package provides the generic and common modules for RISC-V= =0D -platforms. RISC-V platform package could include RiscPlatformPkg.dec to=0D -use the common drivers, libraries, definitions, PCDs and etc. for the=0D -platform development.=0D +## EDK2 RISC-V Platform Project=0D =0D -There are two packages to support RISC-V:=0D -- `edk2-platforms/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec`=0D -- `edk2-platforms/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec`=0D +### EDK2 Build Architecture for RISC-V=0D +The edk2 build architecture which is supported and verified on edk2 code b= ase for=0D +RISC-V platforms is `RISCV64`.=0D =0D -`RiscVPlatformPkg` provides SEC phase and NULL libs.=0D -`RiscVProcessorPkg` provides many libraries, PEIMs and DXE drivers.=0D +### Toolchain for RISC-V=0D +The toolchain is on RISC-V GitHub (https://github.com/riscv/riscv-gnu-tool= chain)=0D +for building edk2 RISC-V binary. The corresponding edk2 Toolchain tag for = building=0D +RISC-V platform is "GCC5" declared in `tools_def.txt`.=0D =0D -### Download the sources ###=0D +### Packages=0D +There are two packages to support RISC-V edk2 platforms:=0D +- `Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec`=0D +- `Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec`=0D +=0D +`RiscVPlatformPkg` currently provides the generic SEC driver for all RISC-= V platforms,=0D +and some platform level libraries.=0D +`RiscVProcessorPkg` currently provides RISC-V processor related libraries,= PEI modules,=0D +DXE drivers and industrial standard header files.=0D +=0D +## EDK2 RISC-V Platform Package=0D +RISC-V platform package provides the common modules for RISC-V platforms. = RISC-V=0D +platform vendors could include RiscPlatformPkg.dec to use the common drive= rs, libraries,=0D +definitions, PCDs and etc. for the RISC-V platforms development.=0D +=0D +### Download the Source Code ###=0D ```=0D git clone https://github.com/tianocore/edk2.git=0D +git clone https://github.com/tianocore/edk2-platforms.git=0D =0D -git clone https://github.com/changab/edk2-platforms.git=0D -# Check out branch: riscv-smode-lib=0D ```=0D =0D -To build it, you have to follow the regular steps for EDK2 and additionall= y set=0D -an environmen variable to point to your RISC-V toolchain installation,=0D -including the binary prefixes:=0D -=0D +You have to follow the build steps for=0D +EDK2 (https://github.com/tianocore/tianocore.github.io/wiki/Getting-Starte= d-with-EDK-II)=0D +and additionally set an environment variable to point to your RISC-V toolc= hain binaries=0D +for building RISC-V platforms,=0D ```=0D +# e.g. If the toolchain binaries are under /riscv-gnu-toolchain-binaries/b= in=0D export GCC5_RISCV64_PREFIX=3D/riscv-gnu-toolchain-binaries/bin/riscv64-unk= nown-elf-=0D ```=0D =0D -Then you can build the image for the SiFive HifiveUnleashed platform:=0D +Then you can build the edk2 firmware image for RISC-V platforms.=0D =0D ```=0D +# e.g. For building SiFive Hifive Unleashed platform:=0D build -a RISCV64 -t GCC5 -p Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveU= nleashedBoard/U540.dsc=0D ```=0D =0D -### EDK2 project=0D -All changes in edk2 are upstream, however, most of the RISC-V code is in=0D -edk2-platforms. Therefore you have to check out the branch `riscv-smode-li= b` on=0D -`github.com/changab/edk2-platforms`.=0D -=0D -The build architecture which is supported and verified so far is `RISCV64`= .=0D -The latest master of the RISC-V toolchain https://github.com/riscv/riscv-g= nu-toolchain=0D -should work but the latest verified commit is `b468107e701433e1caca3dbc8ae= f8d40`.=0D -Toolchain tag is "GCC5" declared in `tools_def.txt`=0D +## RISC-V OpenSBI Library=0D +RISC-V [OpenSBI](https://github.com/riscv/opensbi) is the implementation o= f=0D +[RISC-V SBI (Supervisor Binary Interface) specification](https://github.co= m/riscv/riscv-sbi-doc).=0D +For EDK2 UEFI firmware solution, RISC-V OpenSBI is integrated as a library= =0D +[(submoudule)](Silicon/RISC-V/ProcessorPkg/Library/RiscVOpensbiLib/opensbi= ) in EDK2=0D +RISC-V Processor Package. The RISC-V OpenSBI library is built in SEC drive= r without=0D +any modifications and provides the interfaces for supervisor mode executio= n environment=0D +to execute privileged operations.=0D =0D ## RISC-V Platform PCD settings=0D ### EDK2 Firmware Volume Settings=0D @@ -54,9 +67,9 @@ EDK2 Firmware volume related PCDs which declared in platf= orm FDF file. |PcdRiscVSecFvBase| The base address of SEC Firmware Volume|=0D |PcdRiscVSecFvSize| The size of SEC Firmware Volume|=0D |PcdRiscVPeiFvBase| The base address of PEI Firmware Volume|=0D -|PcdRiscVPeiFvSize| The size of SEC Firmware Volume|=0D +|PcdRiscVPeiFvSize| The size of PEI Firmware Volume|=0D |PcdRiscVDxeFvBase| The base address of DXE Firmware Volume|=0D -|PcdRiscVDxeFvSize| The size of SEC Firmware Volume|=0D +|PcdRiscVDxeFvSize| The size of DXE Firmware Volume|=0D =0D ### EDK2 EFI Variable Region Settings=0D The PCD settings regard to EFI Variable=0D @@ -84,21 +97,24 @@ Below PCDs could be set in platform FDF file. |--------------|---------|=0D |PcdHartCount| Number of RISC-V HARTs, the value is processor-implementati= on specific|=0D |PcdBootHartId| The ID of RISC-V HART to execute main fimrware code and bo= ot system to OS|=0D +|PcdBootableHartNumber|The bootable HART number, which is incorporate with= RISC-V OpenSBI platform hart_index2id value|=0D =0D ### RISC-V OpenSBI Settings=0D =0D | **PCD name** |**Usage**|=0D |--------------|---------|=0D -|PcdScratchRamBase| The base address of OpenSBI scratch buffer for all RIS= C-V HARTs|=0D -|PcdScratchRamSize| The total size of OpenSBI scratch buffer for all RISC-= V HARTs|=0D -|PcdOpenSbiStackSize| The size of initial stack of each RISC-V HART for bo= oting system use OpenSBI|=0D +|PcdScratchRamBase| The base address of RISC-V OpenSBI scratch buffer for = all RISC-V HARTs|=0D +|PcdScratchRamSize| The total size of RISC-V OpenSBI scratch buffer for al= l RISC-V HARTs|=0D +|PcdOpenSbiStackSize| The size of initial stack of each RISC-V HART for bo= oting system use RISC-V OpenSBI|=0D |PcdTemporaryRamBase| The base address of temporary memory for PEI phase|= =0D |PcdTemporaryRamSize| The temporary memory size for PEI phase|=0D +|PcdPeiCorePrivilegeMode|The target RISC-V privilege mode for edk2 PEI pha= se|=0D =0D ## Supported Operating Systems=0D -Only support to boot to EFI Shell so far.=0D -=0D -Porting GRUB2 and Linux EFISTUB is in progress.=0D +Currently support boot to EFI Shell and Linux kernel.=0D +Refer to below link for more information,=0D +https://github.com/riscv/riscv-uefi-edk2-docs=0D =0D ## Known Issues and Limitations=0D -Only RISC-V RV64 is verified.=0D +Only RISC-V RV64 is verified on edk2.=0D +=0D --=20 2.31.1