From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mx0b-002e3701.pphosted.com (mx0b-002e3701.pphosted.com [148.163.143.35]) by mx.groups.io with SMTP id smtpd.web08.2748.1641618771100470081 for ; Fri, 07 Jan 2022 21:12:51 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@hpe.com header.s=pps0720 header.b=lGBCTpVA; spf=permerror, err=parse error for token &{10 18 %{ir}.%{v}.%{d}.spf.has.pphosted.com}: invalid domain name (domain: hpe.com, ip: 148.163.143.35, mailfrom: prvs=000704d8ca=abner.chang@hpe.com) Received: from pps.filterd (m0150244.ppops.net [127.0.0.1]) by mx0b-002e3701.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 20844kWl006770 for ; Sat, 8 Jan 2022 05:12:50 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=hpe.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding; s=pps0720; bh=F1HoJB3/dm3cVd+dez8/32r2MSePRa9oCrYXuXXs/CA=; b=lGBCTpVAvIsy1YjedYelE7dZ/jsBlcAJoRHcjnKU6ONer/IgLoaYSD4U6fM20+R360+y t8TPy6BBABRBjENz+dSY/4rvoLUmzcf65qx1J5tUISJuMLyim7r4rTPCTPempU1hOnZe rYhj2/+NuDzoZfXgoPs2MZEUJAiGz98JNKt33I2YgvJanXq3g79wwfo0KiOyPmsczVv9 DX0FtLyM9vFQc0L0PwoNMDcTdrwQrbCbQcHT5HcAeTzJSJwtkx7E5ZY/PkJdIjlzvLyy WDUAda/wQ0XDE2LRe+QVvM2LLgaTEXnQ/5EBX9XvS0Fr9erG/GP3+35qB8YAs6kHlHSR Sw== Received: from g2t2353.austin.hpe.com (g2t2353.austin.hpe.com [15.233.44.26]) by mx0b-002e3701.pphosted.com (PPS) with ESMTPS id 3df395r7s4-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Sat, 08 Jan 2022 05:12:50 +0000 Received: from g2t2360.austin.hpecorp.net (g2t2360.austin.hpecorp.net [16.196.225.135]) by g2t2353.austin.hpe.com (Postfix) with ESMTP id 7AAE46D for ; Sat, 8 Jan 2022 05:12:49 +0000 (UTC) Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.229]) by g2t2360.austin.hpecorp.net (Postfix) with ESMTP id C2C2E37; Sat, 8 Jan 2022 05:12:48 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com Subject: [PATCH 28/79] U5SeriesPkg: Deduplicate PlatformPei Date: Sat, 8 Jan 2022 12:10:48 +0800 Message-Id: <20220108041121.16005-27-abner.chang@hpe.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20220108041121.16005-1-abner.chang@hpe.com> References: <20220108041121.16005-1-abner.chang@hpe.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: h0Lc9U0rpwZBSXX-tndHzWFTMrNTntxI X-Proofpoint-GUID: h0Lc9U0rpwZBSXX-tndHzWFTMrNTntxI X-HPE-SCL: -1 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.790,Hydra:6.0.425,FMLib:17.11.62.513 definitions=2022-01-08_01,2022-01-07_01,2021-12-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 phishscore=0 mlxlogscore=999 adultscore=0 lowpriorityscore=0 suspectscore=0 mlxscore=0 bulkscore=0 priorityscore=1501 clxscore=1015 impostorscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2110150000 definitions=main-2201080036 Content-Transfer-Encoding: quoted-printable (This is migrated from edk2-platforms) The current (and future) RISC-V platforms share a lot of PlatformPei code that does not need to be duplicated. If we see that they need to have different behavior in the future, we can add platform specific libraires for that specific code. The upcoming RiscvVirt is only 1205 lines with this patch. Still way too much. Hopefully MinPlatform will help. 26 ./RiscvVirt.dec 13 ./RiscvVirt.uni 12 ./RiscvVirtPkgExtra.uni 78 ./VarStore.fdf.inc 66 ./RiscvVirt.fdf.inc 654 ./RiscvVirt.dsc 356 ./RiscvVirt.fdf 1205 total Cc: Abner Chang Cc: Sunil V L Reviewed-by: Abner Chang Signed-off-by: Daniel Schaefer --- .../Universal/Pei/PlatformPei/PlatformPei.inf | 74 +++++ .../Universal/Pei/PlatformPei/Platform.h | 86 +++++ .../Universal/Pei/PlatformPei/Fv.c | 51 +++ .../Universal/Pei/PlatformPei/MemDetect.c | 81 +++++ .../Universal/Pei/PlatformPei/Platform.c | 314 ++++++++++++++++++ 5 files changed, 606 insertions(+) create mode 100644 Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei/P= latformPei.inf create mode 100644 Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei/P= latform.h create mode 100644 Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei/F= v.c create mode 100644 Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei/M= emDetect.c create mode 100644 Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei/P= latform.c diff --git a/Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei/Platform= Pei.inf b/Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei/PlatformPei= .inf new file mode 100644 index 0000000000..e7f5eef630 --- /dev/null +++ b/Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei/PlatformPei.inf @@ -0,0 +1,74 @@ +## @file=0D +# Platform PEI driver=0D +#=0D +# This module provides platform specific function to detect boot mode.=0D +#=0D +# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
=0D +#=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +##=0D +=0D +[Defines]=0D + INF_VERSION =3D 0x0001001b=0D + BASE_NAME =3D PlatformPei=0D + FILE_GUID =3D 5592FC16-8FEF-4DE3-A6CF-6C59081E4EB7= =0D + MODULE_TYPE =3D PEIM=0D + VERSION_STRING =3D 1.0=0D + ENTRY_POINT =3D InitializePlatform=0D +=0D +#=0D +# The following information is for reference only and not required by the = build tools.=0D +#=0D +# VALID_ARCHITECTURES =3D RISCV64=0D +#=0D +=0D +[Sources]=0D + Fv.c=0D + MemDetect.c=0D + Platform.c=0D +=0D +[Packages]=0D + MdeModulePkg/MdeModulePkg.dec=0D + MdePkg/MdePkg.dec=0D + Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec=0D + Platform/SiFive/U5SeriesPkg/U5SeriesPkg.dec=0D + Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec=0D + Silicon/SiFive/SiFive.dec=0D + UefiCpuPkg/UefiCpuPkg.dec=0D +=0D +[Guids]=0D + gEfiMemoryTypeInformationGuid=0D + gSiFiveU5SeriesPlatformsPkgTokenSpaceGuid=0D +=0D +[LibraryClasses]=0D + DebugLib=0D + HobLib=0D + IoLib=0D + PciLib=0D + PeiResourcePublicationLib=0D + PeiServicesLib=0D + PeiServicesTablePointerLib=0D + PeimEntryPoint=0D + PcdLib=0D + SiliconSiFiveU5MCCoreplexInfoLib=0D +=0D +[Pcd]=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdEmuVariableNvStoreReserved=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdPciDisableBusEnumeration=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdVariableStoreSize=0D + gEfiMdePkgTokenSpaceGuid.PcdGuidedExtractHandlerTableAddress=0D + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVDxeFvBase=0D + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVDxeFvSize=0D + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdTemporaryRamBase=0D + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdTemporaryRamSize=0D + gSiFiveU5SeriesPlatformsPkgTokenSpaceGuid.PcdNumberofU5Cores=0D + gSiFiveU5SeriesPlatformsPkgTokenSpaceGuid.PcdE5MCSupported=0D +=0D +[Ppis]=0D + gEfiPeiMasterBootModePpiGuid=0D +=0D +[Depex]=0D + TRUE=0D diff --git a/Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei/Platform= .h b/Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei/Platform.h new file mode 100644 index 0000000000..c2cdd6d75b --- /dev/null +++ b/Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei/Platform.h @@ -0,0 +1,86 @@ +/** @file=0D + Platform PEI module include file.=0D +=0D + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All right= s reserved.
=0D + Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.
=0D +=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +=0D +#ifndef PLATFORM_PEI_H_INCLUDED_=0D +#define PLATFORM_PEI_H_INCLUDED_=0D +=0D +VOID=0D +AddIoMemoryBaseSizeHob (=0D + EFI_PHYSICAL_ADDRESS MemoryBase,=0D + UINT64 MemorySize=0D + );=0D +=0D +VOID=0D +AddIoMemoryRangeHob (=0D + EFI_PHYSICAL_ADDRESS MemoryBase,=0D + EFI_PHYSICAL_ADDRESS MemoryLimit=0D + );=0D +=0D +VOID=0D +AddMemoryBaseSizeHob (=0D + EFI_PHYSICAL_ADDRESS MemoryBase,=0D + UINT64 MemorySize=0D + );=0D +=0D +VOID=0D +AddMemoryRangeHob (=0D + EFI_PHYSICAL_ADDRESS MemoryBase,=0D + EFI_PHYSICAL_ADDRESS MemoryLimit=0D + );=0D +=0D +VOID=0D +AddUntestedMemoryBaseSizeHob (=0D + EFI_PHYSICAL_ADDRESS MemoryBase,=0D + UINT64 MemorySize=0D + );=0D +=0D +VOID=0D +AddReservedMemoryBaseSizeHob (=0D + EFI_PHYSICAL_ADDRESS MemoryBase,=0D + UINT64 MemorySize=0D + );=0D +=0D +VOID=0D +AddUntestedMemoryRangeHob (=0D + EFI_PHYSICAL_ADDRESS MemoryBase,=0D + EFI_PHYSICAL_ADDRESS MemoryLimit=0D + );=0D +=0D +VOID=0D +AddressWidthInitialization (=0D + VOID=0D + );=0D +=0D +EFI_STATUS=0D +PublishPeiMemory (=0D + VOID=0D + );=0D +=0D +UINT32=0D +GetSystemMemorySizeBelow4gb (=0D + VOID=0D + );=0D +=0D +VOID=0D +InitializeRamRegions (=0D + VOID=0D + );=0D +=0D +EFI_STATUS=0D +PeiFvInitialization (=0D + VOID=0D + );=0D +=0D +EFI_STATUS=0D +InitializeXen (=0D + VOID=0D + );=0D +=0D +#endif // _PLATFORM_PEI_H_INCLUDED_=0D diff --git a/Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei/Fv.c b/P= latform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei/Fv.c new file mode 100644 index 0000000000..060d66238d --- /dev/null +++ b/Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei/Fv.c @@ -0,0 +1,51 @@ +/** @file=0D + Build FV related hobs for platform.=0D +=0D + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All right= s reserved.
=0D + Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.
=0D +=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +=0D +#include "PiPei.h"=0D +#include "Platform.h"=0D +#include =0D +#include =0D +#include =0D +#include =0D +=0D +/**=0D + Publish PEI & DXE (Decompressed) Memory based FVs to let PEI=0D + and DXE know about them.=0D +=0D + @retval EFI_SUCCESS Platform PEI FVs were initialized successfully.=0D +=0D +**/=0D +EFI_STATUS=0D +PeiFvInitialization (=0D + VOID=0D + )=0D +{=0D + DEBUG ((DEBUG_INFO, "Platform PEI Firmware Volume Initialization\n"));=0D + //=0D + // Let DXE know about the DXE FV=0D + //=0D + BuildFvHob (PcdGet32 (PcdRiscVDxeFvBase), PcdGet32 (PcdRiscVDxeFvSize));= =0D + DEBUG ((DEBUG_INFO, "Platform builds DXE FV at %x, size %x.\n",=0D + PcdGet32 (PcdRiscVDxeFvBase),=0D + PcdGet32 (PcdRiscVDxeFvSize)));=0D +=0D + //=0D + // Let PEI know about the DXE FV so it can find the DXE Core=0D + //=0D + PeiServicesInstallFvInfoPpi (=0D + NULL,=0D + (VOID *)(UINTN) PcdGet32 (PcdRiscVDxeFvBase),=0D + PcdGet32 (PcdRiscVDxeFvSize),=0D + NULL,=0D + NULL=0D + );=0D +=0D + return EFI_SUCCESS;=0D +}=0D diff --git a/Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei/MemDetec= t.c b/Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei/MemDetect.c new file mode 100644 index 0000000000..c15d6bb5d4 --- /dev/null +++ b/Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei/MemDetect.c @@ -0,0 +1,81 @@ +/**@file=0D + Memory Detection for Virtual Machines.=0D +=0D + Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All right= s reserved.
=0D + Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.
=0D +=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +Module Name:=0D +=0D + MemDetect.c=0D +=0D +**/=0D +=0D +//=0D +// The package level header files this module uses=0D +//=0D +#include =0D +=0D +//=0D +// The Library classes this module consumes=0D +//=0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +=0D +#include "Platform.h"=0D +=0D +=0D +/**=0D + Publish PEI core memory=0D +=0D + @return EFI_SUCCESS The PEIM initialized successfully.=0D +=0D +**/=0D +EFI_STATUS=0D +PublishPeiMemory (=0D + VOID=0D + )=0D +{=0D + EFI_STATUS Status;=0D + EFI_PHYSICAL_ADDRESS MemoryBase;=0D + UINT64 MemorySize;=0D +=0D + //=0D + // TODO: This value should come from platform=0D + // configuration or the memory sizing code.=0D + //=0D + MemoryBase =3D 0x80000000UL + 0x1000000UL;=0D + MemorySize =3D 0x40000000UL - 0x1000000UL; //1GB - 16MB=0D +=0D + DEBUG((DEBUG_INFO, "%a: MemoryBase:0x%x MemorySize:%x\n", __FUNCTION__, = MemoryBase, MemorySize));=0D +=0D + //=0D + // Publish this memory to the PEI Core=0D + //=0D + Status =3D PublishSystemMemory(MemoryBase, MemorySize);=0D + ASSERT_EFI_ERROR (Status);=0D +=0D + return Status;=0D +}=0D +=0D +/**=0D + Publish system RAM and reserve memory regions=0D +=0D +**/=0D +VOID=0D +InitializeRamRegions (=0D + VOID=0D + )=0D +{=0D + //=0D + // TODO: This value should come from platform=0D + // configuration or the memory sizing code.=0D + //=0D + AddMemoryRangeHob(0x81000000UL, 0x81000000UL + 0x3F000000UL);=0D +}=0D diff --git a/Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei/Platform= .c b/Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei/Platform.c new file mode 100644 index 0000000000..24192c692b --- /dev/null +++ b/Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei/Platform.c @@ -0,0 +1,314 @@ +/**@file=0D + Platform PEI driver=0D +=0D + Copyright (c) 2019-2021, Hewlett Packard Enterprise Development LP. All = rights reserved.
=0D + Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.
=0D + Copyright (c) 2011, Andrei Warkentin =0D +=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +=0D +//=0D +// The package level header files this module uses=0D +//=0D +#include =0D +=0D +//=0D +// The Library classes this module consumes=0D +//=0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +=0D +#include =0D +=0D +#include "Platform.h"=0D +=0D +EFI_MEMORY_TYPE_INFORMATION mDefaultMemoryTypeInformation[] =3D {=0D + { EfiACPIMemoryNVS, 0x004 },=0D + { EfiACPIReclaimMemory, 0x008 },=0D + { EfiReservedMemoryType, 0x004 },=0D + { EfiRuntimeServicesData, 0x024 },=0D + { EfiRuntimeServicesCode, 0x030 },=0D + { EfiBootServicesCode, 0x180 },=0D + { EfiBootServicesData, 0xF00 },=0D + { EfiMaxMemoryType, 0x000 }=0D +};=0D +=0D +=0D +EFI_PEI_PPI_DESCRIPTOR mPpiBootMode[] =3D {=0D + {=0D + EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,=0D + &gEfiPeiMasterBootModePpiGuid,=0D + NULL=0D + }=0D +};=0D +=0D +STATIC EFI_BOOT_MODE mBootMode =3D BOOT_WITH_FULL_CONFIGURATION;=0D +=0D +VOID=0D +AddIoMemoryBaseSizeHob (=0D + EFI_PHYSICAL_ADDRESS MemoryBase,=0D + UINT64 MemorySize=0D + )=0D +{=0D + BuildResourceDescriptorHob (=0D + EFI_RESOURCE_MEMORY_MAPPED_IO,=0D + EFI_RESOURCE_ATTRIBUTE_PRESENT |=0D + EFI_RESOURCE_ATTRIBUTE_INITIALIZED |=0D + EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |=0D + EFI_RESOURCE_ATTRIBUTE_TESTED,=0D + MemoryBase,=0D + MemorySize=0D + );=0D +}=0D +=0D +VOID=0D +AddReservedMemoryBaseSizeHob (=0D + EFI_PHYSICAL_ADDRESS MemoryBase,=0D + UINT64 MemorySize=0D + )=0D +{=0D + BuildResourceDescriptorHob (=0D + EFI_RESOURCE_MEMORY_RESERVED,=0D + EFI_RESOURCE_ATTRIBUTE_PRESENT |=0D + EFI_RESOURCE_ATTRIBUTE_INITIALIZED |=0D + EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |=0D + EFI_RESOURCE_ATTRIBUTE_TESTED,=0D + MemoryBase,=0D + MemorySize=0D + );=0D +}=0D +=0D +VOID=0D +AddIoMemoryRangeHob (=0D + EFI_PHYSICAL_ADDRESS MemoryBase,=0D + EFI_PHYSICAL_ADDRESS MemoryLimit=0D + )=0D +{=0D + AddIoMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));= =0D +}=0D +=0D +=0D +VOID=0D +AddMemoryBaseSizeHob (=0D + EFI_PHYSICAL_ADDRESS MemoryBase,=0D + UINT64 MemorySize=0D + )=0D +{=0D + BuildResourceDescriptorHob (=0D + EFI_RESOURCE_SYSTEM_MEMORY,=0D + EFI_RESOURCE_ATTRIBUTE_PRESENT |=0D + EFI_RESOURCE_ATTRIBUTE_INITIALIZED |=0D + EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |=0D + EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |=0D + EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |=0D + EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |=0D + EFI_RESOURCE_ATTRIBUTE_TESTED,=0D + MemoryBase,=0D + MemorySize=0D + );=0D +}=0D +=0D +=0D +VOID=0D +AddMemoryRangeHob (=0D + EFI_PHYSICAL_ADDRESS MemoryBase,=0D + EFI_PHYSICAL_ADDRESS MemoryLimit=0D + )=0D +{=0D + AddMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));=0D +}=0D +=0D +=0D +VOID=0D +AddUntestedMemoryBaseSizeHob (=0D + EFI_PHYSICAL_ADDRESS MemoryBase,=0D + UINT64 MemorySize=0D + )=0D +{=0D + BuildResourceDescriptorHob (=0D + EFI_RESOURCE_SYSTEM_MEMORY,=0D + EFI_RESOURCE_ATTRIBUTE_PRESENT |=0D + EFI_RESOURCE_ATTRIBUTE_INITIALIZED |=0D + EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |=0D + EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |=0D + EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |=0D + EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE,=0D + MemoryBase,=0D + MemorySize=0D + );=0D +}=0D +=0D +VOID=0D +AddUntestedMemoryRangeHob (=0D + EFI_PHYSICAL_ADDRESS MemoryBase,=0D + EFI_PHYSICAL_ADDRESS MemoryLimit=0D + )=0D +{=0D + AddUntestedMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryB= ase));=0D +}=0D +=0D +VOID=0D +AddPciResource (=0D + VOID=0D + )=0D +{=0D + //=0D + // Platform-specific=0D + //=0D +}=0D +=0D +VOID=0D +MemMapInitialization (=0D + VOID=0D + )=0D +{=0D + //=0D + // Create Memory Type Information HOB=0D + //=0D + BuildGuidDataHob (=0D + &gEfiMemoryTypeInformationGuid,=0D + mDefaultMemoryTypeInformation,=0D + sizeof(mDefaultMemoryTypeInformation)=0D + );=0D +=0D + //=0D + // Add PCI IO Port space available for PCI resource allocations.=0D + //=0D + AddPciResource ();=0D +}=0D +=0D +VOID=0D +MiscInitialization (=0D + VOID=0D + )=0D +{=0D + //=0D + // Build the CPU HOB with guest RAM size dependent address width and 16-= bits=0D + // of IO space. (Side note: unlike other HOBs, the CPU HOB is needed dur= ing=0D + // S3 resume as well, so we build it unconditionally.)=0D + //=0D + // TODO: Determine this dynamically from the platform=0D + // setting or the HART configuration.=0D + //=0D + BuildCpuHob (48, 32);=0D +}=0D +=0D +/**=0D + Check if system returns from S3.=0D +=0D + @return BOOLEAN TRUE, system returned from S3=0D + FALSE, system is not returned from S3=0D +=0D +**/=0D +BOOLEAN=0D +CheckResumeFromS3 (=0D + VOID=0D + )=0D +{=0D + //=0D + //Platform implementation-specific=0D + //=0D + return FALSE;=0D +}=0D +=0D +=0D +VOID=0D +BootModeInitialization (=0D + VOID=0D + )=0D +{=0D + EFI_STATUS Status;=0D +=0D + if (CheckResumeFromS3 () =3D=3D TRUE) {=0D + DEBUG ((DEBUG_INFO, "This is wake from S3\n"));=0D + } else {=0D + DEBUG ((DEBUG_INFO, "This is normal boot\n"));=0D + }=0D + Status =3D PeiServicesSetBootMode (mBootMode);=0D + ASSERT_EFI_ERROR (Status);=0D +=0D + Status =3D PeiServicesInstallPpi (mPpiBootMode);=0D + ASSERT_EFI_ERROR (Status);=0D +}=0D +=0D +/**=0D + Build processor information for U54 Coreplex processor.=0D +=0D + @return EFI_SUCCESS Status.=0D +=0D +**/=0D +EFI_STATUS=0D +BuildCoreInformationHob (=0D + VOID=0D +)=0D +{=0D + EFI_STATUS Status;=0D + RISC_V_PROCESSOR_SMBIOS_HOB_DATA *SmbiosHobPtr;=0D +=0D + // TODO: Create SMBIOS libs for non-U540 platforms=0D + Status =3D CreateU5MCCoreplexProcessorSpecificDataHob (0);=0D + if (EFI_ERROR (Status)) {=0D + ASSERT(FALSE);=0D + }=0D + Status =3D CreateU5MCProcessorSmbiosDataHob (0, &SmbiosHobPtr);=0D + if (EFI_ERROR (Status)) {=0D + ASSERT(FALSE);=0D + }=0D +=0D + DEBUG ((DEBUG_INFO, "U5 MC Coreplex SMBIOS DATA HOB at address 0x%x\n", = SmbiosHobPtr));=0D +=0D + return EFI_SUCCESS;=0D +}=0D +=0D +/**=0D + Perform Platform PEI initialization.=0D +=0D + @param FileHandle Handle of the file being invoked.=0D + @param PeiServices Describes the list of possible PEI Services.=0D +=0D + @return EFI_SUCCESS The PEIM initialized successfully.=0D +=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +InitializePlatform (=0D + IN EFI_PEI_FILE_HANDLE FileHandle,=0D + IN CONST EFI_PEI_SERVICES **PeiServices=0D + )=0D +{=0D + EFI_STATUS Status;=0D +=0D + DEBUG ((DEBUG_INFO, "Platform PEIM Loaded\n"));=0D +=0D + BootModeInitialization ();=0D + DEBUG ((DEBUG_INFO, "Platform BOOT mode initiated.\n"));=0D + PublishPeiMemory ();=0D + DEBUG ((DEBUG_INFO, "PEI memory published.\n"));=0D + InitializeRamRegions ();=0D + DEBUG ((DEBUG_INFO, "Platform RAM regions initiated.\n"));=0D +=0D + if (mBootMode !=3D BOOT_ON_S3_RESUME) {=0D + PeiFvInitialization ();=0D + MemMapInitialization ();=0D + }=0D +=0D + MiscInitialization ();=0D + Status =3D BuildCoreInformationHob ();=0D + if (EFI_ERROR (Status)) {=0D + DEBUG ((DEBUG_ERROR, "Fail to build processor informstion HOB.\n"));=0D + ASSERT(FALSE);=0D + }=0D + return EFI_SUCCESS;=0D +}=0D --=20 2.31.1