From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mx0b-002e3701.pphosted.com (mx0b-002e3701.pphosted.com [148.163.143.35]) by mx.groups.io with SMTP id smtpd.web09.2658.1641618745698650679 for ; Fri, 07 Jan 2022 21:12:26 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@hpe.com header.s=pps0720 header.b=ZCf4HPSx; spf=permerror, err=parse error for token &{10 18 %{ir}.%{v}.%{d}.spf.has.pphosted.com}: invalid domain name (domain: hpe.com, ip: 148.163.143.35, mailfrom: prvs=000704d8ca=abner.chang@hpe.com) Received: from pps.filterd (m0148664.ppops.net [127.0.0.1]) by mx0b-002e3701.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 2083bH6w000643 for ; Sat, 8 Jan 2022 05:12:25 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=hpe.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding; s=pps0720; bh=gtjS0cUcld7TE1WDua/yBH+s2w+qESTv5hSZ+fy98z0=; b=ZCf4HPSxr/6hergKRSuiTmw6WnDrbRw+dGn+kqXx2ZBs8IcriSSwAF41Ye2sXwHVpUiC ptUKAKaiJLv3nyrW18F0BIrRACSZEKjOI8v9iOIYJ6TgY6ioDdELQty3S9hhb3V8xADl 00sG9cKYqsR2SbjRUIma5d42A9J75nENXFryJRJWnHL3yDj3my5v9j7j/eJQY9Facf5t gf9B1qY92TXaZz/AkDNXzIk3/Vd30tgh4KhE6bQ+YmStcLVPdDgp93hIwGg/VDQmj3CU mJKQaPyVAlqLqO24f5q6kL7usH2/4Hfi/WTEHLZ2R2sU5j5J5iu0TAGQyxJ8kevdRK4Q Ig== Received: from g2t2353.austin.hpe.com (g2t2353.austin.hpe.com [15.233.44.26]) by mx0b-002e3701.pphosted.com (PPS) with ESMTPS id 3df1qw8kxd-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Sat, 08 Jan 2022 05:12:24 +0000 Received: from g2t2360.austin.hpecorp.net (g2t2360.austin.hpecorp.net [16.196.225.135]) by g2t2353.austin.hpe.com (Postfix) with ESMTP id 4F28F65 for ; Sat, 8 Jan 2022 05:12:24 +0000 (UTC) Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.229]) by g2t2360.austin.hpecorp.net (Postfix) with ESMTP id 83DF736; Sat, 8 Jan 2022 05:12:23 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com Subject: [PATCH 04/79] ProcessorPkg/Library: Add RISC-V timer library Date: Sat, 8 Jan 2022 12:10:24 +0800 Message-Id: <20220108041121.16005-3-abner.chang@hpe.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20220108041121.16005-1-abner.chang@hpe.com> References: <20220108041121.16005-1-abner.chang@hpe.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: nyJOujsyGL_Pk9kqyaDuftI0hKTt5VOu X-Proofpoint-GUID: nyJOujsyGL_Pk9kqyaDuftI0hKTt5VOu X-HPE-SCL: -1 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.790,Hydra:6.0.425,FMLib:17.11.62.513 definitions=2022-01-08_01,2022-01-07_01,2021-12-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 adultscore=0 priorityscore=1501 lowpriorityscore=0 mlxscore=0 phishscore=0 malwarescore=0 clxscore=1015 suspectscore=0 impostorscore=0 mlxlogscore=999 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2110150000 definitions=main-2201080036 Content-Transfer-Encoding: quoted-printable (This is migrated from edk2-platforms:Silicon/RISC-V) Timer library for RISC-V. Signed-off-by: Abner Chang Co-authored-by: Gilbert Chen Reviewed-by: Leif Lindholm Cc: Leif Lindholm Cc: Gilbert Chen --- .../RiscVTimerLib/BaseRiscVTimerLib.inf | 34 +++ .../Library/RiscVTimerLib/RiscVTimerLib.c | 199 ++++++++++++++++++ 2 files changed, 233 insertions(+) create mode 100644 Silicon/RISC-V/ProcessorPkg/Library/RiscVTimerLib/BaseR= iscVTimerLib.inf create mode 100644 Silicon/RISC-V/ProcessorPkg/Library/RiscVTimerLib/RiscV= TimerLib.c diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVTimerLib/BaseRiscVTim= erLib.inf b/Silicon/RISC-V/ProcessorPkg/Library/RiscVTimerLib/BaseRiscVTime= rLib.inf new file mode 100644 index 0000000000..c914d3b4b6 --- /dev/null +++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVTimerLib/BaseRiscVTimerLib.i= nf @@ -0,0 +1,34 @@ +## @file=0D +# RISC-V Timer Library Instance.=0D +#=0D +# Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. A= ll rights reserved.
=0D +#=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +##=0D +=0D +[Defines]=0D + INF_VERSION =3D 0x0001001b=0D + BASE_NAME =3D BaseRiscVTimerLib=0D + FILE_GUID =3D F0450728-3221-488E-8C63-BD3A8DF500E2=0D + MODULE_TYPE =3D BASE=0D + VERSION_STRING =3D 1.0=0D + LIBRARY_CLASS =3D TimerLib=0D +=0D +[Sources]=0D + RiscVTimerLib.c=0D +=0D +[Packages]=0D + MdePkg/MdePkg.dec=0D + Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec=0D +=0D +[Pcd]=0D + gUefiRiscVPkgTokenSpaceGuid.PcdRiscVMachineTimerTickInNanoSecond=0D + gUefiRiscVPkgTokenSpaceGuid.PcdRiscVMachineTimerFrequencyInHerz=0D +=0D +[LibraryClasses]=0D + BaseLib=0D + PcdLib=0D + RiscVCpuLib=0D + RiscVPlatformTimerLib=0D +=0D diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVTimerLib/RiscVTimerLi= b.c b/Silicon/RISC-V/ProcessorPkg/Library/RiscVTimerLib/RiscVTimerLib.c new file mode 100644 index 0000000000..97fe2aef4b --- /dev/null +++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVTimerLib/RiscVTimerLib.c @@ -0,0 +1,199 @@ +/** @file=0D + RISC-V instance of Timer Library.=0D +=0D + Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. Al= l rights reserved.
=0D +=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +=0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +=0D +/**=0D + Stalls the CPU for at least the given number of ticks.=0D +=0D + Stalls the CPU for at least the given number of ticks. It's invoked by=0D + MicroSecondDelay() and NanoSecondDelay().=0D +=0D + @param Delay A period of time to delay in ticks.=0D +=0D +**/=0D +VOID=0D +InternalRiscVTimerDelay (=0D + IN UINT32 Delay=0D + )=0D +{=0D + UINT32 Ticks;=0D + UINT32 Times;=0D +=0D + Times =3D Delay >> (RISCV_TIMER_COMPARE_BITS - 2);=0D + Delay &=3D (( 1 << (RISCV_TIMER_COMPARE_BITS - 2)) - 1);=0D + do {=0D + //=0D + // The target timer count is calculated here=0D + //=0D + Ticks =3D RiscVReadMachineTimer () + Delay;=0D + Delay =3D 1 << (RISCV_TIMER_COMPARE_BITS - 2);=0D + while (((Ticks - RiscVReadMachineTimer ()) & ( 1 << (RISCV_TIMER_COMPA= RE_BITS - 1))) =3D=3D 0) {=0D + CpuPause ();=0D + }=0D + } while (Times-- > 0);=0D +}=0D +=0D +/**=0D + Stalls the CPU for at least the given number of microseconds.=0D +=0D + Stalls the CPU for the number of microseconds specified by MicroSeconds.= =0D +=0D + @param MicroSeconds The minimum number of microseconds to delay.=0D +=0D + @return MicroSeconds=0D +=0D +**/=0D +UINTN=0D +EFIAPI=0D +MicroSecondDelay (=0D + IN UINTN MicroSeconds=0D + )=0D +{=0D + InternalRiscVTimerDelay (=0D + (UINT32)DivU64x32 (=0D + MultU64x32 (=0D + MicroSeconds,=0D + PcdGet64 (PcdRiscVMachineTimerFrequencyInHerz)=0D + ),=0D + 1000000u=0D + )=0D + );=0D + return MicroSeconds;=0D +}=0D +=0D +/**=0D + Stalls the CPU for at least the given number of nanoseconds.=0D +=0D + Stalls the CPU for the number of nanoseconds specified by NanoSeconds.=0D +=0D + @param NanoSeconds The minimum number of nanoseconds to delay.=0D +=0D + @return NanoSeconds=0D +=0D +**/=0D +UINTN=0D +EFIAPI=0D +NanoSecondDelay (=0D + IN UINTN NanoSeconds=0D + )=0D +{=0D + InternalRiscVTimerDelay (=0D + (UINT32)DivU64x32 (=0D + MultU64x32 (=0D + NanoSeconds,=0D + PcdGet64 (PcdRiscVMachineTimerFrequencyInHerz)=0D + ),=0D + 1000000000u=0D + )=0D + );=0D + return NanoSeconds;=0D +}=0D +=0D +/**=0D + Retrieves the current value of a 64-bit free running performance counter= .=0D +=0D + Retrieves the current value of a 64-bit free running performance counter= . The=0D + counter can either count up by 1 or count down by 1. If the physical=0D + performance counter counts by a larger increment, then the counter value= s=0D + must be translated. The properties of the counter can be retrieved from= =0D + GetPerformanceCounterProperties().=0D +=0D + @return The current value of the free running performance counter.=0D +=0D +**/=0D +UINT64=0D +EFIAPI=0D +GetPerformanceCounter (=0D + VOID=0D + )=0D +{=0D + return (UINT64)RiscVReadMachineTimer ();=0D +}=0D +=0D +/**return=0D + Retrieves the 64-bit frequency in Hz and the range of performance counte= r=0D + values.=0D +=0D + If StartValue is not NULL, then the value that the performance counter s= tarts=0D + with immediately after is it rolls over is returned in StartValue. If=0D + EndValue is not NULL, then the value that the performance counter end wi= th=0D + immediately before it rolls over is returned in EndValue. The 64-bit=0D + frequency of the performance counter in Hz is always returned. If StartV= alue=0D + is less than EndValue, then the performance counter counts up. If StartV= alue=0D + is greater than EndValue, then the performance counter counts down. For= =0D + example, a 64-bit free running counter that counts up would have a Start= Value=0D + of 0 and an EndValue of 0xFFFFFFFFFFFFFFFF. A 24-bit free running counte= r=0D + that counts down would have a StartValue of 0xFFFFFF and an EndValue of = 0.=0D +=0D + @param StartValue The value the performance counter starts with when i= t=0D + rolls over.=0D + @param EndValue The value that the performance counter ends with bef= ore=0D + it rolls over.=0D +=0D + @return The frequency in Hz.=0D +=0D +**/=0D +UINT64=0D +EFIAPI=0D +GetPerformanceCounterProperties (=0D + OUT UINT64 *StartValue, OPTIONAL=0D + OUT UINT64 *EndValue OPTIONAL=0D + )=0D +{=0D + if (StartValue !=3D NULL) {=0D + *StartValue =3D 0;=0D + }=0D +=0D + if (EndValue !=3D NULL) {=0D + *EndValue =3D 32 - 1;=0D + }=0D +=0D + return PcdGet64 (PcdRiscVMachineTimerFrequencyInHerz);=0D +}=0D +=0D +/**=0D + Converts elapsed ticks of performance counter to time in nanoseconds.=0D +=0D + This function converts the elapsed ticks of running performance counter = to=0D + time value in unit of nanoseconds.=0D +=0D + @param Ticks The number of elapsed ticks of running performance cou= nter.=0D +=0D + @return The elapsed time in nanoseconds.=0D +=0D +**/=0D +UINT64=0D +EFIAPI=0D +GetTimeInNanoSecond (=0D + IN UINT64 Ticks=0D + )=0D +{=0D + UINT64 NanoSeconds;=0D + UINT32 Remainder;=0D +=0D + //=0D + // Ticks=0D + // Time =3D --------- x 1,000,000,000=0D + // Frequency=0D + //=0D + NanoSeconds =3D MultU64x32 (DivU64x32Remainder (Ticks, PcdGet64 (PcdRisc= VMachineTimerFrequencyInHerz), &Remainder), 1000000000u);=0D +=0D + //=0D + // Frequency < 0x100000000, so Remainder < 0x100000000, then (Remainder = * 1,000,000,000)=0D + // will not overflow 64-bit.=0D + //=0D + NanoSeconds +=3D DivU64x32 (MultU64x32 ((UINT64) Remainder, 1000000000u)= , PcdGet64 (PcdRiscVMachineTimerFrequencyInHerz));=0D +=0D + return NanoSeconds;=0D +}=0D --=20 2.31.1