From: "Abner Chang" <abner.chang@hpe.com>
To: devel@edk2.groups.io
Cc: abner.chang@hpe.com
Subject: [PATCH 31/79] Silicon/RISC-V: Introduce FirmwareContext library
Date: Sat, 8 Jan 2022 12:10:51 +0800 [thread overview]
Message-ID: <20220108041121.16005-30-abner.chang@hpe.com> (raw)
In-Reply-To: <20220108041121.16005-1-abner.chang@hpe.com>
(This is migrated from edk2-platforms:Silicon)
Add RISC-V FirmwareContext library for different FirmwareContext
implementations. This instance uses SBI firmware extension to
get the pointer to FirmwareContext.
Cc: Sunil V L <sunilvl@ventanamicro.com>
Cc: Daniel Schaefer <daniel.schaefer@hpe.com>
Reviewed-by: Abner Chang <abner.chang@hpe.com>
Reviewed-by: Daniel Schaefer <daniel.schaefer@hpe.com>
Signed-off-by: Abner Chang <abner.chang@hpe.com>
---
.../RISC-V/ProcessorPkg/RiscVProcessorPkg.dec | 1 +
.../RISC-V/ProcessorPkg/RiscVProcessorPkg.dsc | 4 +-
.../RiscVFirmwareContextSbiLib.inf | 34 ++++++++++++
.../RiscVFirmwareContextSscratchLib.inf | 33 ++++++++++++
.../RiscVFirmwareContextStvecLib.inf | 34 ++++++++++++
.../Include/IndustryStandard/RiscV.h | 3 +-
.../Include/Library/RiscVCpuLib.h | 14 ++++-
.../Include/Library/RiscVFirmwareContextLib.h | 43 +++++++++++++++
.../RiscVFirmwareContextSbiLib.c | 52 +++++++++++++++++++
.../RiscVFirmwareContextSscratchLib.c | 48 +++++++++++++++++
.../RiscVFirmwareContextStvecLib.c | 48 +++++++++++++++++
.../ProcessorPkg/Library/RiscVCpuLib/Cpu.S | 34 +++++++++++-
12 files changed, 344 insertions(+), 4 deletions(-)
create mode 100644 Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSbiLib/RiscVFirmwareContextSbiLib.inf
create mode 100644 Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSscratchLib/RiscVFirmwareContextSscratchLib.inf
create mode 100644 Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextStvecLib/RiscVFirmwareContextStvecLib.inf
create mode 100644 Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVFirmwareContextLib.h
create mode 100644 Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSbiLib/RiscVFirmwareContextSbiLib.c
create mode 100644 Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSscratchLib/RiscVFirmwareContextSscratchLib.c
create mode 100644 Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextStvecLib/RiscVFirmwareContextStvecLib.c
diff --git a/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec b/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec
index 0b64b33f0f..08279a97b1 100644
--- a/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec
+++ b/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec
@@ -24,6 +24,7 @@
RiscVPlatformDxeIplLib|Include/Library/RiscVPlatformDxeIpl.h
RiscVCpuLib|Include/Library/RiscVCpuLib.h
RiscVEdk2SbiLib|Include/Library/RiscVEdk2SbiLib.h
+ RiscVFirmwareContextLib|Include/Library/RiscVFirmwareContextLib.h
[Guids]
gUefiRiscVPkgTokenSpaceGuid = { 0x4261e9c8, 0x52c0, 0x4b34, { 0x85, 0x3d, 0x48, 0x46, 0xea, 0xd3, 0xb7, 0x2c}}
diff --git a/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dsc b/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dsc
index 5c5cfcb525..1292ba1bea 100644
--- a/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dsc
+++ b/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dsc
@@ -65,13 +65,14 @@
UefiLib|MdePkg/Library/UefiLib/UefiLib.inf
DevicePathLib|MdePkg/Library/UefiDevicePathLibDevicePathProtocol/UefiDevicePathLibDevicePathProtocol.inf
RiscVPlatformTimerLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVPlatformTimerLibNull/RiscVPlatformTimerLib.inf
- PeiServicesTablePointerLib|Silicon/RISC-V/ProcessorPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerLibOpenSbi.inf
[LibraryClasses.common.PEI_CORE]
PeiServicesTablePointerLib|Silicon/RISC-V/ProcessorPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerLibOpenSbi.inf
+ RiscVFirmwareContextLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSbiLib/RiscVFirmwareContextSbiLib.inf
[LibraryClasses.common.PEIM]
PeiServicesTablePointerLib|Silicon/RISC-V/ProcessorPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerLibOpenSbi.inf
+ RiscVFirmwareContextLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSbiLib/RiscVFirmwareContextSbiLib.inf
HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf
PeimEntryPoint|MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf
@@ -92,6 +93,7 @@
[Components]
Silicon/RISC-V/ProcessorPkg/Library/RiscVTimerLib/BaseRiscVTimerLib.inf
Silicon/RISC-V/ProcessorPkg/Library/RiscVExceptionLib/CpuExceptionHandlerDxeLib.inf
+ Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSbiLib/RiscVFirmwareContextSbiLib.inf
Silicon/RISC-V/ProcessorPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerLibOpenSbi.inf
Silicon/RISC-V/ProcessorPkg/Library/RiscVOpensbiLib/RiscVOpensbiLib.inf
Silicon/RISC-V/ProcessorPkg/Library/RiscVPlatformTimerLibNull/RiscVPlatformTimerLib.inf
diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSbiLib/RiscVFirmwareContextSbiLib.inf b/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSbiLib/RiscVFirmwareContextSbiLib.inf
new file mode 100644
index 0000000000..168b705453
--- /dev/null
+++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSbiLib/RiscVFirmwareContextSbiLib.inf
@@ -0,0 +1,34 @@
+## @file
+# Instance of OpebSBI Firmware Conext Library
+#
+# This iinstance uses RISC-V OpenSBI Firmware Extension SBI.
+#
+# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001b
+ BASE_NAME = RiscVFirmwareContextSbiLib
+ FILE_GUID = 3709E048-6794-427A-B728-BFE3FFD6D461
+ MODULE_TYPE = PEIM
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = RiscVFirmwareContextLib|PEIM PEI_CORE
+
+#
+# VALID_ARCHITECTURES = RISCV64
+#
+[Sources]
+ RiscVFirmwareContextSbiLib.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec
+
+[LibraryClasses]
+ DebugLib
+ RiscVCpuLib
+ RiscVEdk2SbiLib
+
diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSscratchLib/RiscVFirmwareContextSscratchLib.inf b/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSscratchLib/RiscVFirmwareContextSscratchLib.inf
new file mode 100644
index 0000000000..750c1cf51f
--- /dev/null
+++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSscratchLib/RiscVFirmwareContextSscratchLib.inf
@@ -0,0 +1,33 @@
+## @file
+# Instance of OpebSBI Firmware Conext Library
+#
+# This instance uses RISC-V Supervisor mode SCRATCH CSR
+#
+# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001b
+ BASE_NAME = RiscVFirmwareContextSscratchLib
+ FILE_GUID = 3709E048-6794-427A-B728-BFE3FFD6D461
+ MODULE_TYPE = PEIM
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = RiscVFirmwareContextLib|PEIM PEI_CORE
+
+#
+# VALID_ARCHITECTURES = RISCV64
+#
+[Sources]
+ RiscVFirmwareContextSscratchLib.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec
+
+[LibraryClasses]
+ DebugLib
+ RiscVCpuLib
+
diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextStvecLib/RiscVFirmwareContextStvecLib.inf b/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextStvecLib/RiscVFirmwareContextStvecLib.inf
new file mode 100644
index 0000000000..fa894cda91
--- /dev/null
+++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextStvecLib/RiscVFirmwareContextStvecLib.inf
@@ -0,0 +1,34 @@
+## @file
+# Instance of OpebSBI Firmware Conext Library
+#
+# This iinstance Supervisor mode STVEC CSR
+#
+# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001b
+ BASE_NAME = RiscVFirmwareContextStvecLib
+ FILE_GUID = 42DCFFAC-1DBD-4264-80A3-85CC7167AC82
+ MODULE_TYPE = PEIM
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = RiscVFirmwareContextLib|PEIM PEI_CORE
+
+#
+# VALID_ARCHITECTURES = RISCV64
+#
+[Sources]
+ RiscVFirmwareContextStvecLib.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec
+
+[LibraryClasses]
+ DebugLib
+ RiscVCpuLib
+
+
diff --git a/Silicon/RISC-V/ProcessorPkg/Include/IndustryStandard/RiscV.h b/Silicon/RISC-V/ProcessorPkg/Include/IndustryStandard/RiscV.h
index 2a992394ed..f6726bda24 100644
--- a/Silicon/RISC-V/ProcessorPkg/Include/IndustryStandard/RiscV.h
+++ b/Silicon/RISC-V/ProcessorPkg/Include/IndustryStandard/RiscV.h
@@ -1,7 +1,7 @@
/** @file
RISC-V package definitions.
- Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+ Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -96,6 +96,7 @@
#define SSTATUS_SIE_BIT_POSITION 1
#define SSTATUS_SPP_BIT_POSITION 8
#define RISCV_CSR_SUPERVISOR_SIE 0x104
+#define RISCV_CSR_SUPERVISOR_STVEC 0x105
#define RISCV_CSR_SUPERVISOR_SSCRATCH 0x140
#define RISCV_CSR_SUPERVISOR_SEPC 0x141
#define RISCV_CSR_SUPERVISOR_SCAUSE 0x142
diff --git a/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVCpuLib.h b/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVCpuLib.h
index f37d4c20d0..f70723567e 100644
--- a/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVCpuLib.h
+++ b/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVCpuLib.h
@@ -1,7 +1,7 @@
/** @file
RISC-V CPU library definitions.
- Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+ Copyright (c) 2016 - 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@@ -68,4 +68,16 @@ RiscVReadMachineImplementId (VOID);
VOID
RiscVSetSupervisorAddressTranslationRegister(UINT64);
+VOID
+RiscVSetSupervisorScratch (UINT64);
+
+UINT64
+RiscVGetSupervisorScratch (VOID);
+
+VOID
+RiscVSetSupervisorStvec (UINT64);
+
+UINT64
+RiscVGetSupervisorStvec (VOID);
+
#endif
diff --git a/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVFirmwareContextLib.h b/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVFirmwareContextLib.h
new file mode 100644
index 0000000000..f35c4e0c51
--- /dev/null
+++ b/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVFirmwareContextLib.h
@@ -0,0 +1,43 @@
+/** @file
+ Library to get/set Firmware Context.
+
+ Copyright (c) 2021, Hewlett Packard Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef RISCV_FIRMWARE_CONTEXT_LIB_H_
+#define RISCV_FIRMWARE_CONTEXT_LIB_H_
+
+#include <Uefi.h>
+#include <IndustryStandard/RiscVOpensbi.h>
+
+/**
+ Get pointer to OpenSBI Firmware Context
+
+ Get the pointer of firmware context.
+
+ @param FirmwareContextPtr Pointer to retrieve pointer to the
+ Firmware Context.
+**/
+VOID
+EFIAPI
+GetFirmwareContextPointer (
+ IN OUT EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT **FirmwareContextPtr
+ );
+
+/**
+ Set pointer to OpenSBI Firmware Context
+
+ Set the pointer of firmware context.
+
+ @param FirmwareContextPtr Pointer to Firmware Context.
+**/
+VOID
+EFIAPI
+SetFirmwareContextPointer (
+ IN EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *FirmwareContextPtr
+ );
+
+#endif
diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSbiLib/RiscVFirmwareContextSbiLib.c b/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSbiLib/RiscVFirmwareContextSbiLib.c
new file mode 100644
index 0000000000..6125618eaf
--- /dev/null
+++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSbiLib/RiscVFirmwareContextSbiLib.c
@@ -0,0 +1,52 @@
+/** @file
+ This iinstance uses RISC-V OpenSBI Firmware Extension SBI to
+ get the pointer of firmware context.
+
+ Copyright (c) 2021 Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <PiPei.h>
+#include <Library/DebugLib.h>
+#include <Library/RiscVCpuLib.h>
+#include <Library/RiscVEdk2SbiLib.h>
+#include <sbi/sbi_scratch.h>
+#include <sbi/sbi_platform.h>
+
+/**
+ Get pointer to OpenSBI Firmware Context
+
+ Get the pointer of firmware context through OpenSBI FW Extension SBI.
+
+ @param FirmwareContextPtr Pointer to retrieve pointer to the
+ Firmware Context.
+**/
+VOID
+EFIAPI
+GetFirmwareContextPointer (
+ IN OUT EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT **FirmwareContextPtr
+ )
+{
+ SbiGetFirmwareContext (FirmwareContextPtr);
+}
+
+/**
+ Set the pointer to OpenSBI Firmware Context
+
+ Set the pointer of firmware context through OpenSBI FW Extension SBI.
+
+ @param FirmwareContextPtr Pointer to Firmware Context.
+**/
+VOID
+EFIAPI
+SetFirmwareContextPointer (
+ IN EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *FirmwareContextPtr
+ )
+{
+ //
+ // We don't have to set firmware context pointer using
+ // OpenSBI FW Extension SBI.
+ //
+}
+
diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSscratchLib/RiscVFirmwareContextSscratchLib.c b/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSscratchLib/RiscVFirmwareContextSscratchLib.c
new file mode 100644
index 0000000000..2504e17132
--- /dev/null
+++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSscratchLib/RiscVFirmwareContextSscratchLib.c
@@ -0,0 +1,48 @@
+/** @file
+ This instance uses Supervisor mode SCRATCH CSR to get/set the
+ pointer of firmware context.
+
+ Copyright (c) 2021 Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <PiPei.h>
+
+#include <IndustryStandard/RiscVOpensbi.h>
+
+#include <Library/DebugLib.h>
+#include <Library/RiscVCpuLib.h>
+
+/**
+ Get pointer to OpenSBI Firmware Context
+
+ Get the pointer of firmware context through Supervisor mode SCRATCH CSR.
+
+ @param FirmwareContextPtr Pointer to retrieve pointer to the
+ Firmware Context.
+**/
+VOID
+EFIAPI
+GetFirmwareContextPointer (
+ IN OUT EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT **FirmwareContextPtr
+ )
+{
+ *FirmwareContextPtr = (EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *)RiscVGetSupervisorScratch ();
+}
+
+/**
+ Set the pointer to OpenSBI Firmware Context
+
+ Set the pointer of firmware context through Supervisor mode SCRATCH CSR.
+
+ @param FirmwareContextPtr Pointer to Firmware Context.
+**/
+VOID
+EFIAPI
+SetFirmwareContextPointer (
+ IN EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *FirmwareContextPtr
+ )
+{
+ RiscVSetSupervisorScratch ((UINT64)FirmwareContextPtr);
+}
diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextStvecLib/RiscVFirmwareContextStvecLib.c b/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextStvecLib/RiscVFirmwareContextStvecLib.c
new file mode 100644
index 0000000000..7d1675355a
--- /dev/null
+++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextStvecLib/RiscVFirmwareContextStvecLib.c
@@ -0,0 +1,48 @@
+/** @file
+ This instance uses This iinstance Supervisor mode STVEC CSR to
+ get/set the pointer of firmware context.
+
+ Copyright (c) 2021 Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <PiPei.h>
+
+#include <IndustryStandard/RiscVOpensbi.h>
+
+#include <Library/DebugLib.h>
+#include <Library/RiscVCpuLib.h>
+
+/**
+ Get pointer to OpenSBI Firmware Context
+
+ Get the pointer of firmware context through Supervisor mode STVEC CSR.
+
+ @param FirmwareContextPtr Pointer to retrieve pointer to the
+ Firmware Context.
+**/
+VOID
+EFIAPI
+GetFirmwareContextPointer (
+ IN OUT EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT **FirmwareContextPtr
+ )
+{
+ *FirmwareContextPtr = (EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *)RiscVGetSupervisorStvec ();
+}
+
+/**
+ Set pointer to OpenSBI Firmware Context
+
+ Set the pointer of firmware context through Supervisor mode STVEC CSR
+
+ @param FirmwareContextPtr Pointer to Firmware Context.
+**/
+VOID
+EFIAPI
+SetFirmwareContextPointer (
+ IN EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *FirmwareContextPtr
+ )
+{
+ RiscVSetSupervisorStvec ((UINT64)FirmwareContextPtr);
+}
diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVCpuLib/Cpu.S b/Silicon/RISC-V/ProcessorPkg/Library/RiscVCpuLib/Cpu.S
index 06ba80cb5f..e242c9b866 100644
--- a/Silicon/RISC-V/ProcessorPkg/Library/RiscVCpuLib/Cpu.S
+++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVCpuLib/Cpu.S
@@ -2,7 +2,7 @@
//
// RISC-V CPU functions.
//
-// Copyright (c) 2016 - 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+// Copyright (c) 2016 - 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
//
// SPDX-License-Identifier: BSD-2-Clause-Patent
//
@@ -101,6 +101,38 @@ ASM_FUNC (RiscVReadMachineImplementId)
csrr a0, RISCV_CSR_MACHINE_MIMPID
ret
+//
+// Set Supervisor mode scratch.
+// @param a0 : Value set to Supervisor mode scratch
+//
+ASM_FUNC (RiscVSetSupervisorScratch)
+ csrrw a1, RISCV_CSR_SUPERVISOR_SSCRATCH, a0
+ ret
+
+//
+// Get Supervisor mode scratch.
+// @retval a0 : Value in Supervisor mode scratch
+//
+ASM_FUNC (RiscVGetSupervisorScratch)
+ csrr a0, RISCV_CSR_SUPERVISOR_SSCRATCH
+ ret
+
+//
+// Set Supervisor mode trap vector.
+// @param a0 : Value set to Supervisor mode trap vector
+//
+ASM_FUNC (RiscVSetSupervisorStvec)
+ csrrw a1, RISCV_CSR_SUPERVISOR_STVEC, a0
+ ret
+
+//
+// Get Supervisor mode scratch.
+// @retval a0 : Value in Supervisor mode trap vector
+//
+ASM_FUNC (RiscVGetSupervisorStvec)
+ csrr a0, RISCV_CSR_SUPERVISOR_STVEC
+ ret
+
//
// Set Supervisor Address Translation and
// Protection Register.
--
2.31.1
next prev parent reply other threads:[~2022-01-08 5:12 UTC|newest]
Thread overview: 39+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-01-08 4:10 [PATCH 02/79] ProcessorPkg/Library: RISC-V CPU library Abner Chang
2022-01-08 4:10 ` [PATCH 03/79] ProcessorPkg/Library: Add RISC-V exception library Abner Chang
2022-01-08 4:10 ` [PATCH 04/79] ProcessorPkg/Library: Add RISC-V timer library Abner Chang
2022-01-08 4:10 ` [PATCH 05/79] ProcessorPkg/RiscVOpensbLib: Add opensbi submodule Abner Chang
2022-01-08 4:10 ` [PATCH 06/79] ProcessorPkg/Library: Add RiscVOpensbiLib Abner Chang
2022-01-08 4:10 ` [PATCH 07/79] ProcessorPkg/Library: Add RiscVEdk2SbiLib Abner Chang
2022-01-08 4:10 ` [PATCH 08/79] ProcessorPkg/Library: RISC-V PEI Service Table Pointer library Abner Chang
2022-01-08 4:10 ` [PATCH 09/79] ProcessorPkg/CpuDxe: Add RISC-V CPU DXE driver Abner Chang
2022-01-08 4:10 ` [PATCH 10/79] ProcessorPkg/SmbiosDxe: Generic SMBIOS DXE driver for RISC-V platforms Abner Chang
2022-01-08 4:10 ` [PATCH 11/79] ProcesorPkg/Library: NULL instance of RISC-V platform timer library Abner Chang
2022-01-08 4:10 ` [PATCH 12/79] RISC-V/ProcessorPkg: RISC-V package Abner Chang
2022-01-08 4:10 ` [PATCH 13/79] PlatformPkg/Library: RISC-V Platform Temporary Memory library Abner Chang
2022-01-08 4:10 ` [PATCH 14/79] PlatformPkg/Library: Add FirmwareContextProcessorSpecificLib module Abner Chang
2022-01-08 4:10 ` [PATCH 15/79] PlatformPkg/Library: NULL instance of RiscVOpensbiPlatformLib Abner Chang
2022-01-08 4:10 ` [PATCH 16/79] PlatformPkg/Library: NULL instance of PlatformMemoryTestLib Abner Chang
2022-01-08 4:10 ` [PATCH 17/79] PlatformPkg/Library: NULL instance of PlatformUpdateProgressLib Abner Chang
2022-01-08 4:10 ` [PATCH 18/79] PlatformPkg/Library: Platform Boot Manager library Abner Chang
2022-01-08 4:10 ` [PATCH 19/79] PlatformPkg/SecMain: RISC-V SecMain module Abner Chang
2022-01-08 4:10 ` [PATCH 20/79] PlatformPkg: Add RiscVPlatformPkg Abner Chang
2022-01-08 4:10 ` [PATCH 21/79] RISC-V/PlatformPkg: Revise Readme.md Abner Chang
2022-01-08 4:10 ` [PATCH 22/79] Silicon/SiFive: Handle case of NULL FirmwareContext Abner Chang
2022-01-08 4:10 ` [PATCH 23/79] Silicon/RISC-V: Update old SMBIOS struct filed name Abner Chang
2022-01-08 4:10 ` [PATCH 24/79] Platform/RISC-V: Consume MdeLibs.dsc.inc for RegisterFilterLib Abner Chang
2022-01-08 4:10 ` [PATCH 25/79] Silicon/RISC_V: " Abner Chang
2022-01-08 4:10 ` [PATCH 26/79] RISC-V/CpuDxe: Ignore set memory attributes failure Abner Chang
2022-01-08 4:10 ` [PATCH 27/79] Signal EndOfDxe in boot manager Abner Chang
2022-01-08 4:10 ` [PATCH 28/79] U5SeriesPkg: Deduplicate PlatformPei Abner Chang
2022-01-08 4:10 ` [PATCH 29/79] RISC-V: Split SMBIOS out of PlatformPei Abner Chang
2022-01-08 4:10 ` [PATCH 30/79] RISC-V: Use U5 SMBIOS library only for those platforms Abner Chang
2022-01-08 4:10 ` Abner Chang [this message]
2022-01-08 4:10 ` [PATCH 32/79] Silicon/RISC-V: PeiServiceTableLib uses RiscVFirmwareContextLib Abner Chang
2022-01-08 4:10 ` [PATCH 33/79] RISC-V/PlatformPkg: Build DeviceTree and use that in SEC Abner Chang
2022-01-08 4:10 ` [PATCH 34/79] RISC-V/PlatformPkg: Add FdtPeim to pass DTB from PEI to DXE via HOB Abner Chang
2022-01-08 4:10 ` [PATCH 35/79] RISC-V/PlatformPkg: Fixup FDT from HOB and install into config table Abner Chang
2022-01-08 4:10 ` [PATCH 36/79] RISC-V: Switch to latest OpenSBI Abner Chang
2022-01-08 4:10 ` [PATCH 37/79] RISC-V: Implement ResetSystem RT call Abner Chang
2022-01-08 4:10 ` [PATCH 38/79] Move OpenSbiPlatformLib to RISC-V/PlatformPkg Abner Chang
2022-01-08 4:10 ` [PATCH 39/79] RISC-V/PlatformPkg: Update document Abner Chang
2022-01-08 4:11 ` [PATCH 40/79] RISC-V: Add RISC-V PeiCoreEntryPoint library Abner Chang
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