* [PATCH 02/79] ProcessorPkg/Library: RISC-V CPU library
@ 2022-01-08 4:10 Abner Chang
2022-01-08 4:10 ` [PATCH 03/79] ProcessorPkg/Library: Add RISC-V exception library Abner Chang
` (37 more replies)
0 siblings, 38 replies; 39+ messages in thread
From: Abner Chang @ 2022-01-08 4:10 UTC (permalink / raw)
To: devel; +Cc: abner.chang
(This is migrated from edk2-platforms:Silicon/RISC-V)
This library provides CSR assembly functions to read/write RISC-V
specific Control and Status registers.
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Co-authored-by: Gilbert Chen <gilbert.chen@hpe.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>
---
.../Library/RiscVCpuLib/RiscVCpuLib.inf | 34 ++++++
.../Include/Library/RiscVCpuLib.h | 71 +++++++++++
.../ProcessorPkg/Library/RiscVCpuLib/Cpu.S | 111 ++++++++++++++++++
3 files changed, 216 insertions(+)
create mode 100644 Silicon/RISC-V/ProcessorPkg/Library/RiscVCpuLib/RiscVCpuLib.inf
create mode 100644 Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVCpuLib.h
create mode 100644 Silicon/RISC-V/ProcessorPkg/Library/RiscVCpuLib/Cpu.S
diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVCpuLib/RiscVCpuLib.inf b/Silicon/RISC-V/ProcessorPkg/Library/RiscVCpuLib/RiscVCpuLib.inf
new file mode 100644
index 0000000000..7928dd5536
--- /dev/null
+++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVCpuLib/RiscVCpuLib.inf
@@ -0,0 +1,34 @@
+## @file
+# RISC-V RV64 CPU library
+#
+# Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001b
+ BASE_NAME = RiscVCpuLib
+ FILE_GUID = 8C6CFB0D-A0EE-40D5-90DA-2E51EAE0583F
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = RiscVCpuLib
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = RISCV64
+#
+
+[Sources]
+
+[Sources.RISCV64]
+ Cpu.S
+
+[Packages]
+ MdeModulePkg/MdeModulePkg.dec
+ MdePkg/MdePkg.dec
+ Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec
+
+
diff --git a/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVCpuLib.h b/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVCpuLib.h
new file mode 100644
index 0000000000..f37d4c20d0
--- /dev/null
+++ b/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVCpuLib.h
@@ -0,0 +1,71 @@
+/** @file
+ RISC-V CPU library definitions.
+
+ Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef RISCV_CPU_LIB_H_
+#define RISCV_CPU_LIB_H_
+
+#include "RiscVImpl.h"
+
+/**
+ RISCV_TRAP_HANDLER
+**/
+typedef
+VOID
+(EFIAPI *RISCV_TRAP_HANDLER)(
+ VOID
+ );
+
+VOID
+RiscVSetMachineScratch (RISCV_MACHINE_MODE_CONTEXT *RiscvContext);
+
+UINT32
+RiscVGetMachineScratch (VOID);
+
+UINT32
+RiscVGetMachineTrapCause (VOID);
+
+UINT64
+RiscVReadMachineTimer (VOID);
+
+VOID
+RiscVSetMachineTimerCmp (UINT64);
+
+UINT64
+RiscVReadMachineTimerCmp(VOID);
+
+UINT64
+RiscVReadMachineInterruptEnable(VOID);
+
+UINT64
+RiscVReadMachineInterruptPending(VOID);
+
+UINT64
+RiscVReadMachineStatus(VOID);
+
+VOID
+RiscVWriteMachineStatus(UINT64);
+
+UINT64
+RiscVReadMachineTrapVector(VOID);
+
+UINT64
+RiscVReadMachineIsa (VOID);
+
+UINT64
+RiscVReadMachineVendorId (VOID);
+
+UINT64
+RiscVReadMachineArchitectureId (VOID);
+
+UINT64
+RiscVReadMachineImplementId (VOID);
+
+VOID
+RiscVSetSupervisorAddressTranslationRegister(UINT64);
+
+#endif
diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVCpuLib/Cpu.S b/Silicon/RISC-V/ProcessorPkg/Library/RiscVCpuLib/Cpu.S
new file mode 100644
index 0000000000..06ba80cb5f
--- /dev/null
+++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVCpuLib/Cpu.S
@@ -0,0 +1,111 @@
+//------------------------------------------------------------------------------
+//
+// RISC-V CPU functions.
+//
+// Copyright (c) 2016 - 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+//
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+//------------------------------------------------------------------------------
+#include <Base.h>
+#include <RiscVImpl.h>
+
+.data
+
+.text
+.align 3
+
+//
+// Set machine mode scratch.
+// @param a0 : Pointer to RISCV_MACHINE_MODE_CONTEXT.
+//
+ASM_FUNC (RiscVSetMachineScratch)
+ csrrw a1, RISCV_CSR_MACHINE_MSCRATCH, a0
+ ret
+
+//
+// Get machine mode scratch.
+// @retval a0 : Pointer to RISCV_MACHINE_MODE_CONTEXT.
+//
+ASM_FUNC (RiscVGetMachineScratch)
+ csrrs a0, RISCV_CSR_MACHINE_MSCRATCH, 0
+ ret
+
+//
+// Get machine trap cause CSR.
+//
+ASM_FUNC (RiscVGetMachineTrapCause)
+ csrrs a0, RISCV_CSR_MACHINE_MCAUSE, 0
+ ret
+
+//
+// Get machine interrupt enable
+//
+ASM_FUNC (RiscVReadMachineInterruptEnable)
+ csrr a0, RISCV_CSR_MACHINE_MIE
+ ret
+
+//
+// Get machine interrupt pending
+//
+ASM_FUNC (RiscVReadMachineInterruptPending)
+ csrr a0, RISCV_CSR_MACHINE_MIP
+ ret
+
+//
+// Get machine status
+//
+ASM_FUNC (RiscVReadMachineStatus)
+ csrr a0, RISCV_CSR_MACHINE_MSTATUS
+ ret
+
+//
+// Set machine status
+//
+ASM_FUNC (RiscVWriteMachineStatus)
+ csrw RISCV_CSR_MACHINE_MSTATUS, a0
+ ret
+
+//
+// Get machine trap vector
+//
+ASM_FUNC (RiscVReadMachineTrapVector)
+ csrr a0, RISCV_CSR_MACHINE_MTVEC
+ ret
+
+//
+// Read machine ISA
+//
+ASM_FUNC (RiscVReadMachineIsa)
+ csrr a0, RISCV_CSR_MACHINE_MISA
+ ret
+
+//
+// Read machine vendor ID
+//
+ASM_FUNC (RiscVReadMachineVendorId)
+ csrr a0, RISCV_CSR_MACHINE_MVENDORID
+ ret
+
+//
+// Read machine architecture ID
+//
+ASM_FUNC (RiscVReadMachineArchitectureId)
+ csrr a0, RISCV_CSR_MACHINE_MARCHID
+ ret
+
+//
+// Read machine implementation ID
+//
+ASM_FUNC (RiscVReadMachineImplementId)
+ csrr a0, RISCV_CSR_MACHINE_MIMPID
+ ret
+
+//
+// Set Supervisor Address Translation and
+// Protection Register.
+//
+ASM_FUNC (RiscVSetSupervisorAddressTranslationRegister)
+ csrw RISCV_CSR_SUPERVISOR_SATP, a0
+ ret
+
--
2.31.1
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH 03/79] ProcessorPkg/Library: Add RISC-V exception library
2022-01-08 4:10 [PATCH 02/79] ProcessorPkg/Library: RISC-V CPU library Abner Chang
@ 2022-01-08 4:10 ` Abner Chang
2022-01-08 4:10 ` [PATCH 04/79] ProcessorPkg/Library: Add RISC-V timer library Abner Chang
` (36 subsequent siblings)
37 siblings, 0 replies; 39+ messages in thread
From: Abner Chang @ 2022-01-08 4:10 UTC (permalink / raw)
To: devel; +Cc: abner.chang
(This is migrated from edk2-platforms:Silicon/RISC-V)
Initial RISC-V Supervisor Mode trap handler.
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Co-authored-by: Gilbert Chen <gilbert.chen@hpe.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>
---
.../CpuExceptionHandlerDxeLib.inf | 43 ++++
.../CpuExceptionHandlerLib.h | 107 ++++++++++
.../CpuExceptionHandlerLib.c | 194 ++++++++++++++++++
.../CpuExceptionHandlerLib.uni | 13 ++
.../RiscVExceptionLib/SupervisorTrapHandler.S | 112 ++++++++++
5 files changed, 469 insertions(+)
create mode 100644 Silicon/RISC-V/ProcessorPkg/Library/RiscVExceptionLib/CpuExceptionHandlerDxeLib.inf
create mode 100644 Silicon/RISC-V/ProcessorPkg/Library/RiscVExceptionLib/CpuExceptionHandlerLib.h
create mode 100644 Silicon/RISC-V/ProcessorPkg/Library/RiscVExceptionLib/CpuExceptionHandlerLib.c
create mode 100644 Silicon/RISC-V/ProcessorPkg/Library/RiscVExceptionLib/CpuExceptionHandlerLib.uni
create mode 100644 Silicon/RISC-V/ProcessorPkg/Library/RiscVExceptionLib/SupervisorTrapHandler.S
diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVExceptionLib/CpuExceptionHandlerDxeLib.inf b/Silicon/RISC-V/ProcessorPkg/Library/RiscVExceptionLib/CpuExceptionHandlerDxeLib.inf
new file mode 100644
index 0000000000..fc200d3cca
--- /dev/null
+++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVExceptionLib/CpuExceptionHandlerDxeLib.inf
@@ -0,0 +1,43 @@
+## @file
+# RISC-V CPU Exception Handler Library
+#
+# Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+
+[Defines]
+ INF_VERSION = 0x0001001b
+ BASE_NAME = CpuExceptionHandlerLib
+ MODULE_UNI_FILE = CpuExceptionHandlerLib.uni
+ FILE_GUID = 16309FCF-E900-459C-B071-052118394D11
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = CpuExceptionHandlerLib
+ CONSTRUCTOR = CpuExceptionHandlerLibConstructor
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = RISCV64
+#
+
+[Sources.RISCV64]
+ SupervisorTrapHandler.S
+
+[Sources.common]
+ CpuExceptionHandlerLib.c
+ CpuExceptionHandlerLib.h
+
+[LibraryClasses]
+ BaseLib
+ DebugLib
+ RiscVCpuLib
+ UefiBootServicesTableLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec
+
diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVExceptionLib/CpuExceptionHandlerLib.h b/Silicon/RISC-V/ProcessorPkg/Library/RiscVExceptionLib/CpuExceptionHandlerLib.h
new file mode 100644
index 0000000000..3e480e9b09
--- /dev/null
+++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVExceptionLib/CpuExceptionHandlerLib.h
@@ -0,0 +1,107 @@
+/**@file
+
+ RISC-V Exception Handler library definition file.
+
+ Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef RISCV_CPU_EXECPTION_HANDLER_LIB_H_
+#define RISCV_CPU_EXECPTION_HANDLER_LIB_H_
+
+extern void SupervisorModeTrap(void);
+
+//
+// Index of SMode trap register
+//
+#define SMODE_TRAP_REGS_zero 0
+#define SMODE_TRAP_REGS_ra 1
+#define SMODE_TRAP_REGS_sp 2
+#define SMODE_TRAP_REGS_gp 3
+#define SMODE_TRAP_REGS_tp 4
+#define SMODE_TRAP_REGS_t0 5
+#define SMODE_TRAP_REGS_t1 6
+#define SMODE_TRAP_REGS_t2 7
+#define SMODE_TRAP_REGS_s0 8
+#define SMODE_TRAP_REGS_s1 9
+#define SMODE_TRAP_REGS_a0 10
+#define SMODE_TRAP_REGS_a1 11
+#define SMODE_TRAP_REGS_a2 12
+#define SMODE_TRAP_REGS_a3 13
+#define SMODE_TRAP_REGS_a4 14
+#define SMODE_TRAP_REGS_a5 15
+#define SMODE_TRAP_REGS_a6 16
+#define SMODE_TRAP_REGS_a7 17
+#define SMODE_TRAP_REGS_s2 18
+#define SMODE_TRAP_REGS_s3 19
+#define SMODE_TRAP_REGS_s4 20
+#define SMODE_TRAP_REGS_s5 21
+#define SMODE_TRAP_REGS_s6 22
+#define SMODE_TRAP_REGS_s7 23
+#define SMODE_TRAP_REGS_s8 24
+#define SMODE_TRAP_REGS_s9 25
+#define SMODE_TRAP_REGS_s10 26
+#define SMODE_TRAP_REGS_s11 27
+#define SMODE_TRAP_REGS_t3 28
+#define SMODE_TRAP_REGS_t4 29
+#define SMODE_TRAP_REGS_t5 30
+#define SMODE_TRAP_REGS_t6 31
+#define SMODE_TRAP_REGS_sepc 32
+#define SMODE_TRAP_REGS_sstatus 33
+#define SMODE_TRAP_REGS_sie 34
+#define SMODE_TRAP_REGS_last 35
+
+#define SMODE_TRAP_REGS_OFFSET(x) ((SMODE_TRAP_REGS_##x) * __SIZEOF_POINTER__)
+#define SMODE_TRAP_REGS_SIZE SMODE_TRAP_REGS_OFFSET(last)
+
+#pragma pack(1)
+typedef struct {
+//
+// Below are follow the format of EFI_SYSTEM_CONTEXT
+//
+ RISC_V_REGS_PROTOTYPE zero;
+ RISC_V_REGS_PROTOTYPE ra;
+ RISC_V_REGS_PROTOTYPE sp;
+ RISC_V_REGS_PROTOTYPE gp;
+ RISC_V_REGS_PROTOTYPE tp;
+ RISC_V_REGS_PROTOTYPE t0;
+ RISC_V_REGS_PROTOTYPE t1;
+ RISC_V_REGS_PROTOTYPE t2;
+ RISC_V_REGS_PROTOTYPE s0;
+ RISC_V_REGS_PROTOTYPE s1;
+ RISC_V_REGS_PROTOTYPE a0;
+ RISC_V_REGS_PROTOTYPE a1;
+ RISC_V_REGS_PROTOTYPE a2;
+ RISC_V_REGS_PROTOTYPE a3;
+ RISC_V_REGS_PROTOTYPE a4;
+ RISC_V_REGS_PROTOTYPE a5;
+ RISC_V_REGS_PROTOTYPE a6;
+ RISC_V_REGS_PROTOTYPE a7;
+ RISC_V_REGS_PROTOTYPE s2;
+ RISC_V_REGS_PROTOTYPE s3;
+ RISC_V_REGS_PROTOTYPE s4;
+ RISC_V_REGS_PROTOTYPE s5;
+ RISC_V_REGS_PROTOTYPE s6;
+ RISC_V_REGS_PROTOTYPE s7;
+ RISC_V_REGS_PROTOTYPE s8;
+ RISC_V_REGS_PROTOTYPE s9;
+ RISC_V_REGS_PROTOTYPE s10;
+ RISC_V_REGS_PROTOTYPE s11;
+ RISC_V_REGS_PROTOTYPE t3;
+ RISC_V_REGS_PROTOTYPE t4;
+ RISC_V_REGS_PROTOTYPE t5;
+ RISC_V_REGS_PROTOTYPE t6;
+//
+// Below are the additional information to
+// EFI_SYSTEM_CONTEXT, private to supervisor mode trap
+// and not public to EFI environment.
+//
+ RISC_V_REGS_PROTOTYPE sepc;
+ RISC_V_REGS_PROTOTYPE sstatus;
+ RISC_V_REGS_PROTOTYPE sie;
+} SMODE_TRAP_REGISTERS;
+#pragma pack()
+
+#endif
diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVExceptionLib/CpuExceptionHandlerLib.c b/Silicon/RISC-V/ProcessorPkg/Library/RiscVExceptionLib/CpuExceptionHandlerLib.c
new file mode 100644
index 0000000000..a9316ae758
--- /dev/null
+++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVExceptionLib/CpuExceptionHandlerLib.c
@@ -0,0 +1,194 @@
+/** @file
+ RISC-V Exception Handler library implementition.
+
+ Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <PiPei.h>
+#include <Library/CpuExceptionHandlerLib.h>
+#include <Library/DebugLib.h>
+#include <Library/RiscVCpuLib.h>
+#include <sbi/riscv_asm.h>
+#include <sbi/riscv_encoding.h>
+#include <sbi/sbi_types.h>
+
+#include "CpuExceptionHandlerLib.h"
+
+STATIC EFI_CPU_INTERRUPT_HANDLER mInterruptHandlers[2];
+
+/**
+ Initializes all CPU exceptions entries and provides the default exception handlers.
+
+ Caller should try to get an array of interrupt and/or exception vectors that are in use and need to
+ persist by EFI_VECTOR_HANDOFF_INFO defined in PI 1.3 specification.
+ If caller cannot get reserved vector list or it does not exists, set VectorInfo to NULL.
+ If VectorInfo is not NULL, the exception vectors will be initialized per vector attribute accordingly.
+
+ @param[in] VectorInfo Pointer to reserved vector list.
+
+ @retval EFI_SUCCESS CPU Exception Entries have been successfully initialized
+ with default exception handlers.
+ @retval EFI_INVALID_PARAMETER VectorInfo includes the invalid content if VectorInfo is not NULL.
+ @retval EFI_UNSUPPORTED This function is not supported.
+
+**/
+EFI_STATUS
+EFIAPI
+InitializeCpuExceptionHandlers (
+ IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL
+ )
+{
+ return EFI_SUCCESS;
+}
+
+/**
+ Initializes all CPU interrupt/exceptions entries and provides the default interrupt/exception handlers.
+
+ Caller should try to get an array of interrupt and/or exception vectors that are in use and need to
+ persist by EFI_VECTOR_HANDOFF_INFO defined in PI 1.3 specification.
+ If caller cannot get reserved vector list or it does not exists, set VectorInfo to NULL.
+ If VectorInfo is not NULL, the exception vectors will be initialized per vector attribute accordingly.
+
+ @param[in] VectorInfo Pointer to reserved vector list.
+
+ @retval EFI_SUCCESS All CPU interrupt/exception entries have been successfully initialized
+ with default interrupt/exception handlers.
+ @retval EFI_INVALID_PARAMETER VectorInfo includes the invalid content if VectorInfo is not NULL.
+ @retval EFI_UNSUPPORTED This function is not supported.
+
+**/
+EFI_STATUS
+EFIAPI
+InitializeCpuInterruptHandlers (
+ IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL
+ )
+{
+ return EFI_SUCCESS;
+}
+
+/**
+ Registers a function to be called from the processor interrupt handler.
+
+ This function registers and enables the handler specified by InterruptHandler for a processor
+ interrupt or exception type specified by InterruptType. If InterruptHandler is NULL, then the
+ handler for the processor interrupt or exception type specified by InterruptType is uninstalled.
+ The installed handler is called once for each processor interrupt or exception.
+ NOTE: This function should be invoked after InitializeCpuExceptionHandlers() or
+ InitializeCpuInterruptHandlers() invoked, otherwise EFI_UNSUPPORTED returned.
+
+ @param[in] InterruptType Defines which interrupt or exception to hook.
+ @param[in] InterruptHandler A pointer to a function of type EFI_CPU_INTERRUPT_HANDLER that is called
+ when a processor interrupt occurs. If this parameter is NULL, then the handler
+ will be uninstalled.
+
+ @retval EFI_SUCCESS The handler for the processor interrupt was successfully installed or uninstalled.
+ @retval EFI_ALREADY_STARTED InterruptHandler is not NULL, and a handler for InterruptType was
+ previously installed.
+ @retval EFI_INVALID_PARAMETER InterruptHandler is NULL, and a handler for InterruptType was not
+ previously installed.
+ @retval EFI_UNSUPPORTED The interrupt specified by InterruptType is not supported,
+ or this function is not supported.
+**/
+EFI_STATUS
+EFIAPI
+RegisterCpuInterruptHandler (
+ IN EFI_EXCEPTION_TYPE InterruptType,
+ IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler
+ )
+{
+
+ DEBUG ((DEBUG_INFO, "%a: Type:%x Handler: %x\n", __FUNCTION__, InterruptType, InterruptHandler));
+ mInterruptHandlers[InterruptType] = InterruptHandler;
+ return EFI_SUCCESS;
+}
+/**
+ Machine mode trap handler.
+
+ @param[in] SmodeTrapReg Registers before trap occurred.
+
+**/
+VOID
+RiscVSupervisorModeTrapHandler (
+ SMODE_TRAP_REGISTERS *SmodeTrapReg
+ )
+{
+ UINTN SCause;
+ EFI_SYSTEM_CONTEXT RiscVSystemContext;
+
+ RiscVSystemContext.SystemContextRiscV64 = (EFI_SYSTEM_CONTEXT_RISCV64 *)SmodeTrapReg;
+ //
+ // Check scasue register.
+ //
+ SCause = (UINTN)csr_read(RISCV_CSR_SUPERVISOR_SCAUSE);
+ if ((SCause & (1UL << (sizeof (UINTN) * 8- 1))) != 0) {
+ //
+ // This is interrupt event.
+ //
+ SCause &= ~(1UL << (sizeof (UINTN) * 8- 1));
+ if((SCause == SCAUSE_SUPERVISOR_TIMER_INT) && (mInterruptHandlers[EXCEPT_RISCV_TIMER_INT] != NULL)) {
+ mInterruptHandlers[EXCEPT_RISCV_TIMER_INT](EXCEPT_RISCV_TIMER_INT, RiscVSystemContext);
+ }
+ }
+}
+
+/**
+ Initializes all CPU exceptions entries with optional extra initializations.
+
+ By default, this method should include all functionalities implemented by
+ InitializeCpuExceptionHandlers(), plus extra initialization works, if any.
+ This could be done by calling InitializeCpuExceptionHandlers() directly
+ in this method besides the extra works.
+
+ InitData is optional and its use and content are processor arch dependent.
+ The typical usage of it is to convey resources which have to be reserved
+ elsewhere and are necessary for the extra initializations of exception.
+
+ @param[in] VectorInfo Pointer to reserved vector list.
+ @param[in] InitData Pointer to data optional for extra initializations
+ of exception.
+
+ @retval EFI_SUCCESS The exceptions have been successfully
+ initialized.
+ @retval EFI_INVALID_PARAMETER VectorInfo or InitData contains invalid
+ content.
+ @retval EFI_UNSUPPORTED This function is not supported.
+
+**/
+EFI_STATUS
+EFIAPI
+InitializeCpuExceptionHandlersEx (
+ IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL,
+ IN CPU_EXCEPTION_INIT_DATA *InitData OPTIONAL
+ )
+{
+ return InitializeCpuExceptionHandlers (VectorInfo);
+}
+
+/**
+ The constructor function to initial interrupt handlers in
+ RISCV_MACHINE_MODE_CONTEXT.
+
+ @param ImageHandle The firmware allocated handle for the EFI image.
+ @param SystemTable A pointer to the EFI System Table.
+
+ @retval EFI_SUCCESS The destructor completed successfully.
+ @retval Other value The destructor did not complete successfully.
+
+**/
+EFI_STATUS
+EFIAPI
+CpuExceptionHandlerLibConstructor (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ //
+ // Set Superviosr mode trap handler.
+ //
+ csr_write(CSR_STVEC, SupervisorModeTrap);
+
+ return EFI_SUCCESS;
+}
diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVExceptionLib/CpuExceptionHandlerLib.uni b/Silicon/RISC-V/ProcessorPkg/Library/RiscVExceptionLib/CpuExceptionHandlerLib.uni
new file mode 100644
index 0000000000..00cca22130
--- /dev/null
+++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVExceptionLib/CpuExceptionHandlerLib.uni
@@ -0,0 +1,13 @@
+// /** @file
+//
+// Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+//
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+// **/
+
+
+#string STR_MODULE_ABSTRACT #language en-US "RISC-V CPU Exception Handler Librarys."
+
+#string STR_MODULE_DESCRIPTION #language en-US "RISC-V CPU Exception Handler Librarys."
+
diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVExceptionLib/SupervisorTrapHandler.S b/Silicon/RISC-V/ProcessorPkg/Library/RiscVExceptionLib/SupervisorTrapHandler.S
new file mode 100644
index 0000000000..f6699bb19b
--- /dev/null
+++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVExceptionLib/SupervisorTrapHandler.S
@@ -0,0 +1,112 @@
+/** @file
+ RISC-V Processor supervisor mode trap handler
+
+ Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Base.h>
+#include <RiscVImpl.h>
+#include <sbi/riscv_asm.h>
+#include <sbi/riscv_encoding.h>
+#include <sbi/sbi_platform.h>
+#include <sbi/sbi_scratch.h>
+#include <sbi/sbi_trap.h>
+
+#include "CpuExceptionHandlerLib.h"
+
+ .align 3
+ .section .entry, "ax", %progbits
+ .globl SupervisorModeTrap
+SupervisorModeTrap:
+ addi sp, sp, -SMODE_TRAP_REGS_SIZE
+
+ /* Save all general regisers except SP */
+ sd t0, SMODE_TRAP_REGS_OFFSET(t0)(sp)
+
+ csrr t0, RISCV_CSR_SUPERVISOR_SSTATUS
+ and t0, t0, (1 << SSTATUS_SIE_BIT_POSITION) | (1 << SSTATUS_SPP_BIT_POSITION)
+ sd t0, SMODE_TRAP_REGS_OFFSET(sstatus)(sp)
+ csrr t0, RISCV_CSR_SUPERVISOR_SEPC
+ sd t0, SMODE_TRAP_REGS_OFFSET(sepc)(sp)
+ csrr t0, RISCV_CSR_SUPERVISOR_SIE
+ sd t0, SMODE_TRAP_REGS_OFFSET(sie)(sp)
+ ld t0, SMODE_TRAP_REGS_OFFSET(t0)(sp)
+
+ sd ra, SMODE_TRAP_REGS_OFFSET(ra)(sp)
+ sd gp, SMODE_TRAP_REGS_OFFSET(gp)(sp)
+ sd tp, SMODE_TRAP_REGS_OFFSET(tp)(sp)
+ sd t1, SMODE_TRAP_REGS_OFFSET(t1)(sp)
+ sd t2, SMODE_TRAP_REGS_OFFSET(t2)(sp)
+ sd s0, SMODE_TRAP_REGS_OFFSET(s0)(sp)
+ sd s1, SMODE_TRAP_REGS_OFFSET(s1)(sp)
+ sd a0, SMODE_TRAP_REGS_OFFSET(a0)(sp)
+ sd a1, SMODE_TRAP_REGS_OFFSET(a1)(sp)
+ sd a2, SMODE_TRAP_REGS_OFFSET(a2)(sp)
+ sd a3, SMODE_TRAP_REGS_OFFSET(a3)(sp)
+ sd a4, SMODE_TRAP_REGS_OFFSET(a4)(sp)
+ sd a5, SMODE_TRAP_REGS_OFFSET(a5)(sp)
+ sd a6, SMODE_TRAP_REGS_OFFSET(a6)(sp)
+ sd a7, SMODE_TRAP_REGS_OFFSET(a7)(sp)
+ sd s2, SMODE_TRAP_REGS_OFFSET(s2)(sp)
+ sd s3, SMODE_TRAP_REGS_OFFSET(s3)(sp)
+ sd s4, SMODE_TRAP_REGS_OFFSET(s4)(sp)
+ sd s5, SMODE_TRAP_REGS_OFFSET(s5)(sp)
+ sd s6, SMODE_TRAP_REGS_OFFSET(s6)(sp)
+ sd s7, SMODE_TRAP_REGS_OFFSET(s7)(sp)
+ sd s8, SMODE_TRAP_REGS_OFFSET(s8)(sp)
+ sd s9, SMODE_TRAP_REGS_OFFSET(s9)(sp)
+ sd s10, SMODE_TRAP_REGS_OFFSET(s10)(sp)
+ sd s11, SMODE_TRAP_REGS_OFFSET(s11)(sp)
+ sd t3, SMODE_TRAP_REGS_OFFSET(t3)(sp)
+ sd t4, SMODE_TRAP_REGS_OFFSET(t4)(sp)
+ sd t5, SMODE_TRAP_REGS_OFFSET(t5)(sp)
+ sd t6, SMODE_TRAP_REGS_OFFSET(t6)(sp)
+
+ /* Call to Supervisor mode trap handler in CpuExceptionHandlerLib.c */
+ call RiscVSupervisorModeTrapHandler
+
+ /* Restore all general regisers except SP */
+ ld ra, SMODE_TRAP_REGS_OFFSET(ra)(sp)
+ ld gp, SMODE_TRAP_REGS_OFFSET(gp)(sp)
+ ld tp, SMODE_TRAP_REGS_OFFSET(tp)(sp)
+ ld t2, SMODE_TRAP_REGS_OFFSET(t2)(sp)
+ ld s0, SMODE_TRAP_REGS_OFFSET(s0)(sp)
+ ld s1, SMODE_TRAP_REGS_OFFSET(s1)(sp)
+ ld a0, SMODE_TRAP_REGS_OFFSET(a0)(sp)
+ ld a1, SMODE_TRAP_REGS_OFFSET(a1)(sp)
+ ld a2, SMODE_TRAP_REGS_OFFSET(a2)(sp)
+ ld a3, SMODE_TRAP_REGS_OFFSET(a3)(sp)
+ ld a4, SMODE_TRAP_REGS_OFFSET(a4)(sp)
+ ld a5, SMODE_TRAP_REGS_OFFSET(a5)(sp)
+ ld a6, SMODE_TRAP_REGS_OFFSET(a6)(sp)
+ ld a7, SMODE_TRAP_REGS_OFFSET(a7)(sp)
+ ld s2, SMODE_TRAP_REGS_OFFSET(s2)(sp)
+ ld s3, SMODE_TRAP_REGS_OFFSET(s3)(sp)
+ ld s4, SMODE_TRAP_REGS_OFFSET(s4)(sp)
+ ld s5, SMODE_TRAP_REGS_OFFSET(s5)(sp)
+ ld s6, SMODE_TRAP_REGS_OFFSET(s6)(sp)
+ ld s7, SMODE_TRAP_REGS_OFFSET(s7)(sp)
+ ld s8, SMODE_TRAP_REGS_OFFSET(s8)(sp)
+ ld s9, SMODE_TRAP_REGS_OFFSET(s9)(sp)
+ ld s10, SMODE_TRAP_REGS_OFFSET(s10)(sp)
+ ld s11, SMODE_TRAP_REGS_OFFSET(s11)(sp)
+ ld t3, SMODE_TRAP_REGS_OFFSET(t3)(sp)
+ ld t4, SMODE_TRAP_REGS_OFFSET(t4)(sp)
+ ld t5, SMODE_TRAP_REGS_OFFSET(t5)(sp)
+ ld t6, SMODE_TRAP_REGS_OFFSET(t6)(sp)
+
+ ld t0, SMODE_TRAP_REGS_OFFSET(sepc)(sp)
+ csrw RISCV_CSR_SUPERVISOR_SEPC, t0
+ ld t0, SMODE_TRAP_REGS_OFFSET(sie)(sp)
+ csrw RISCV_CSR_SUPERVISOR_SIE, t0
+ csrr t0, RISCV_CSR_SUPERVISOR_SSTATUS
+ ld t1, SMODE_TRAP_REGS_OFFSET(sstatus)(sp)
+ or t0, t0, t1
+ csrw RISCV_CSR_SUPERVISOR_SSTATUS, t0
+ ld t1, SMODE_TRAP_REGS_OFFSET(t1)(sp)
+ ld t0, SMODE_TRAP_REGS_OFFSET(t0)(sp)
+ addi sp, sp, SMODE_TRAP_REGS_SIZE
+ sret
--
2.31.1
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH 04/79] ProcessorPkg/Library: Add RISC-V timer library
2022-01-08 4:10 [PATCH 02/79] ProcessorPkg/Library: RISC-V CPU library Abner Chang
2022-01-08 4:10 ` [PATCH 03/79] ProcessorPkg/Library: Add RISC-V exception library Abner Chang
@ 2022-01-08 4:10 ` Abner Chang
2022-01-08 4:10 ` [PATCH 05/79] ProcessorPkg/RiscVOpensbLib: Add opensbi submodule Abner Chang
` (35 subsequent siblings)
37 siblings, 0 replies; 39+ messages in thread
From: Abner Chang @ 2022-01-08 4:10 UTC (permalink / raw)
To: devel; +Cc: abner.chang
(This is migrated from edk2-platforms:Silicon/RISC-V)
Timer library for RISC-V.
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Co-authored-by: Gilbert Chen <gilbert.chen@hpe.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>
---
.../RiscVTimerLib/BaseRiscVTimerLib.inf | 34 +++
.../Library/RiscVTimerLib/RiscVTimerLib.c | 199 ++++++++++++++++++
2 files changed, 233 insertions(+)
create mode 100644 Silicon/RISC-V/ProcessorPkg/Library/RiscVTimerLib/BaseRiscVTimerLib.inf
create mode 100644 Silicon/RISC-V/ProcessorPkg/Library/RiscVTimerLib/RiscVTimerLib.c
diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVTimerLib/BaseRiscVTimerLib.inf b/Silicon/RISC-V/ProcessorPkg/Library/RiscVTimerLib/BaseRiscVTimerLib.inf
new file mode 100644
index 0000000000..c914d3b4b6
--- /dev/null
+++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVTimerLib/BaseRiscVTimerLib.inf
@@ -0,0 +1,34 @@
+## @file
+# RISC-V Timer Library Instance.
+#
+# Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001b
+ BASE_NAME = BaseRiscVTimerLib
+ FILE_GUID = F0450728-3221-488E-8C63-BD3A8DF500E2
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = TimerLib
+
+[Sources]
+ RiscVTimerLib.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec
+
+[Pcd]
+ gUefiRiscVPkgTokenSpaceGuid.PcdRiscVMachineTimerTickInNanoSecond
+ gUefiRiscVPkgTokenSpaceGuid.PcdRiscVMachineTimerFrequencyInHerz
+
+[LibraryClasses]
+ BaseLib
+ PcdLib
+ RiscVCpuLib
+ RiscVPlatformTimerLib
+
diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVTimerLib/RiscVTimerLib.c b/Silicon/RISC-V/ProcessorPkg/Library/RiscVTimerLib/RiscVTimerLib.c
new file mode 100644
index 0000000000..97fe2aef4b
--- /dev/null
+++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVTimerLib/RiscVTimerLib.c
@@ -0,0 +1,199 @@
+/** @file
+ RISC-V instance of Timer Library.
+
+ Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Uefi.h>
+#include <Library/BaseLib.h>
+#include <Library/DebugLib.h>
+#include <Library/PcdLib.h>
+#include <Library/RiscVCpuLib.h>
+
+/**
+ Stalls the CPU for at least the given number of ticks.
+
+ Stalls the CPU for at least the given number of ticks. It's invoked by
+ MicroSecondDelay() and NanoSecondDelay().
+
+ @param Delay A period of time to delay in ticks.
+
+**/
+VOID
+InternalRiscVTimerDelay (
+ IN UINT32 Delay
+ )
+{
+ UINT32 Ticks;
+ UINT32 Times;
+
+ Times = Delay >> (RISCV_TIMER_COMPARE_BITS - 2);
+ Delay &= (( 1 << (RISCV_TIMER_COMPARE_BITS - 2)) - 1);
+ do {
+ //
+ // The target timer count is calculated here
+ //
+ Ticks = RiscVReadMachineTimer () + Delay;
+ Delay = 1 << (RISCV_TIMER_COMPARE_BITS - 2);
+ while (((Ticks - RiscVReadMachineTimer ()) & ( 1 << (RISCV_TIMER_COMPARE_BITS - 1))) == 0) {
+ CpuPause ();
+ }
+ } while (Times-- > 0);
+}
+
+/**
+ Stalls the CPU for at least the given number of microseconds.
+
+ Stalls the CPU for the number of microseconds specified by MicroSeconds.
+
+ @param MicroSeconds The minimum number of microseconds to delay.
+
+ @return MicroSeconds
+
+**/
+UINTN
+EFIAPI
+MicroSecondDelay (
+ IN UINTN MicroSeconds
+ )
+{
+ InternalRiscVTimerDelay (
+ (UINT32)DivU64x32 (
+ MultU64x32 (
+ MicroSeconds,
+ PcdGet64 (PcdRiscVMachineTimerFrequencyInHerz)
+ ),
+ 1000000u
+ )
+ );
+ return MicroSeconds;
+}
+
+/**
+ Stalls the CPU for at least the given number of nanoseconds.
+
+ Stalls the CPU for the number of nanoseconds specified by NanoSeconds.
+
+ @param NanoSeconds The minimum number of nanoseconds to delay.
+
+ @return NanoSeconds
+
+**/
+UINTN
+EFIAPI
+NanoSecondDelay (
+ IN UINTN NanoSeconds
+ )
+{
+ InternalRiscVTimerDelay (
+ (UINT32)DivU64x32 (
+ MultU64x32 (
+ NanoSeconds,
+ PcdGet64 (PcdRiscVMachineTimerFrequencyInHerz)
+ ),
+ 1000000000u
+ )
+ );
+ return NanoSeconds;
+}
+
+/**
+ Retrieves the current value of a 64-bit free running performance counter.
+
+ Retrieves the current value of a 64-bit free running performance counter. The
+ counter can either count up by 1 or count down by 1. If the physical
+ performance counter counts by a larger increment, then the counter values
+ must be translated. The properties of the counter can be retrieved from
+ GetPerformanceCounterProperties().
+
+ @return The current value of the free running performance counter.
+
+**/
+UINT64
+EFIAPI
+GetPerformanceCounter (
+ VOID
+ )
+{
+ return (UINT64)RiscVReadMachineTimer ();
+}
+
+/**return
+ Retrieves the 64-bit frequency in Hz and the range of performance counter
+ values.
+
+ If StartValue is not NULL, then the value that the performance counter starts
+ with immediately after is it rolls over is returned in StartValue. If
+ EndValue is not NULL, then the value that the performance counter end with
+ immediately before it rolls over is returned in EndValue. The 64-bit
+ frequency of the performance counter in Hz is always returned. If StartValue
+ is less than EndValue, then the performance counter counts up. If StartValue
+ is greater than EndValue, then the performance counter counts down. For
+ example, a 64-bit free running counter that counts up would have a StartValue
+ of 0 and an EndValue of 0xFFFFFFFFFFFFFFFF. A 24-bit free running counter
+ that counts down would have a StartValue of 0xFFFFFF and an EndValue of 0.
+
+ @param StartValue The value the performance counter starts with when it
+ rolls over.
+ @param EndValue The value that the performance counter ends with before
+ it rolls over.
+
+ @return The frequency in Hz.
+
+**/
+UINT64
+EFIAPI
+GetPerformanceCounterProperties (
+ OUT UINT64 *StartValue, OPTIONAL
+ OUT UINT64 *EndValue OPTIONAL
+ )
+{
+ if (StartValue != NULL) {
+ *StartValue = 0;
+ }
+
+ if (EndValue != NULL) {
+ *EndValue = 32 - 1;
+ }
+
+ return PcdGet64 (PcdRiscVMachineTimerFrequencyInHerz);
+}
+
+/**
+ Converts elapsed ticks of performance counter to time in nanoseconds.
+
+ This function converts the elapsed ticks of running performance counter to
+ time value in unit of nanoseconds.
+
+ @param Ticks The number of elapsed ticks of running performance counter.
+
+ @return The elapsed time in nanoseconds.
+
+**/
+UINT64
+EFIAPI
+GetTimeInNanoSecond (
+ IN UINT64 Ticks
+ )
+{
+ UINT64 NanoSeconds;
+ UINT32 Remainder;
+
+ //
+ // Ticks
+ // Time = --------- x 1,000,000,000
+ // Frequency
+ //
+ NanoSeconds = MultU64x32 (DivU64x32Remainder (Ticks, PcdGet64 (PcdRiscVMachineTimerFrequencyInHerz), &Remainder), 1000000000u);
+
+ //
+ // Frequency < 0x100000000, so Remainder < 0x100000000, then (Remainder * 1,000,000,000)
+ // will not overflow 64-bit.
+ //
+ NanoSeconds += DivU64x32 (MultU64x32 ((UINT64) Remainder, 1000000000u), PcdGet64 (PcdRiscVMachineTimerFrequencyInHerz));
+
+ return NanoSeconds;
+}
--
2.31.1
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH 05/79] ProcessorPkg/RiscVOpensbLib: Add opensbi submodule
2022-01-08 4:10 [PATCH 02/79] ProcessorPkg/Library: RISC-V CPU library Abner Chang
2022-01-08 4:10 ` [PATCH 03/79] ProcessorPkg/Library: Add RISC-V exception library Abner Chang
2022-01-08 4:10 ` [PATCH 04/79] ProcessorPkg/Library: Add RISC-V timer library Abner Chang
@ 2022-01-08 4:10 ` Abner Chang
2022-01-08 4:10 ` [PATCH 06/79] ProcessorPkg/Library: Add RiscVOpensbiLib Abner Chang
` (34 subsequent siblings)
37 siblings, 0 replies; 39+ messages in thread
From: Abner Chang @ 2022-01-08 4:10 UTC (permalink / raw)
To: devel; +Cc: abner.chang
(This is migrated from edk2-platforms:Silicon/RISC-V)
Add submodule opensbi under
Silicon/RISC-V/ProcessorPkg/Library/RiscVOpensbLlib.
The current supported opensbi version for RISC-V edk2 port is tags/v0.6.
Signed-off-by: Daniel Schaefer <daniel.schaefer@hpe.com>
Reviewed-by: Leif Lindholm <leif@nuviainc.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Abner Chang <abner.chang@hpe.com>
Cc: Gilbert Chen <gilbert.chen@hpe.com>
---
Silicon/RISC-V/ProcessorPkg/Library/RiscVOpensbiLib/opensbi | 1 +
1 file changed, 1 insertion(+)
create mode 160000 Silicon/RISC-V/ProcessorPkg/Library/RiscVOpensbiLib/opensbi
diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVOpensbiLib/opensbi b/Silicon/RISC-V/ProcessorPkg/Library/RiscVOpensbiLib/opensbi
new file mode 160000
index 0000000000..ac5e821d50
--- /dev/null
+++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVOpensbiLib/opensbi
@@ -0,0 +1 @@
+Subproject commit ac5e821d50be631f26274765a59bc1b444ffd862
--
2.31.1
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH 06/79] ProcessorPkg/Library: Add RiscVOpensbiLib
2022-01-08 4:10 [PATCH 02/79] ProcessorPkg/Library: RISC-V CPU library Abner Chang
` (2 preceding siblings ...)
2022-01-08 4:10 ` [PATCH 05/79] ProcessorPkg/RiscVOpensbLib: Add opensbi submodule Abner Chang
@ 2022-01-08 4:10 ` Abner Chang
2022-01-08 4:10 ` [PATCH 07/79] ProcessorPkg/Library: Add RiscVEdk2SbiLib Abner Chang
` (33 subsequent siblings)
37 siblings, 0 replies; 39+ messages in thread
From: Abner Chang @ 2022-01-08 4:10 UTC (permalink / raw)
To: devel; +Cc: abner.chang
(This is migrated from edk2-platforms:Silicon/RISC-V)
EDK2 RISC-V OpenSBI library which pull in external source files under
RISC-V/ProcessorPkg/Library/RiscVOpensbiLib/opensbi to the build process.
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Co-authored-by: Daniel Schaefer <daniel.schaefer@hpe.com>
Co-authored-by: Gilbert Chen <gilbert.chen@hpe.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Gilbert Chen <gilbert.chen@hpe.com>
Cc: Daniel Schaefer <daniel.schaefer@hpe.com>
---
.../RiscVOpensbiLib/RiscVOpensbiLib.inf | 82 +++++++++++++++++++
.../Include/IndustryStandard/RiscVOpensbi.h | 59 +++++++++++++
.../ProcessorPkg/Include/OpensbiTypes.h | 80 ++++++++++++++++++
3 files changed, 221 insertions(+)
create mode 100644 Silicon/RISC-V/ProcessorPkg/Library/RiscVOpensbiLib/RiscVOpensbiLib.inf
create mode 100644 Silicon/RISC-V/ProcessorPkg/Include/IndustryStandard/RiscVOpensbi.h
create mode 100644 Silicon/RISC-V/ProcessorPkg/Include/OpensbiTypes.h
diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVOpensbiLib/RiscVOpensbiLib.inf b/Silicon/RISC-V/ProcessorPkg/Library/RiscVOpensbiLib/RiscVOpensbiLib.inf
new file mode 100644
index 0000000000..71cc76444e
--- /dev/null
+++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVOpensbiLib/RiscVOpensbiLib.inf
@@ -0,0 +1,82 @@
+## @file
+# RISC-V Opensbi Library Instance.
+#
+# Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001b
+ BASE_NAME = RiscVOpensbiLib
+ FILE_GUID = 6EF0C812-66F6-11E9-93CE-3F5D5F0DF0A7
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = RiscVOpensbiLib
+
+[Sources]
+ opensbi/lib/sbi/riscv_asm.c
+ opensbi/lib/sbi/riscv_atomic.c
+ opensbi/lib/sbi/riscv_hardfp.S
+ opensbi/lib/sbi/riscv_locks.c
+ opensbi/lib/sbi/sbi_bitmap.c
+ opensbi/lib/sbi/sbi_bitops.c
+ opensbi/lib/sbi/sbi_console.c
+ opensbi/lib/sbi/sbi_ecall.c
+ opensbi/lib/sbi/sbi_ecall_base.c
+ opensbi/lib/sbi/sbi_ecall_hsm.c
+ opensbi/lib/sbi/sbi_ecall_legacy.c
+ opensbi/lib/sbi/sbi_ecall_replace.c
+ opensbi/lib/sbi/sbi_ecall_vendor.c
+ opensbi/lib/sbi/sbi_emulate_csr.c
+ opensbi/lib/sbi/sbi_fifo.c
+ opensbi/lib/sbi/sbi_hart.c
+ opensbi/lib/sbi/sbi_math.c
+ opensbi/lib/sbi/sbi_hfence.S
+ opensbi/lib/sbi/sbi_hsm.c
+ opensbi/lib/sbi/sbi_illegal_insn.c
+ opensbi/lib/sbi/sbi_init.c
+ opensbi/lib/sbi/sbi_ipi.c
+ opensbi/lib/sbi/sbi_misaligned_ldst.c
+ opensbi/lib/sbi/sbi_platform.c
+ opensbi/lib/sbi/sbi_scratch.c
+ opensbi/lib/sbi/sbi_string.c
+ opensbi/lib/sbi/sbi_system.c
+ opensbi/lib/sbi/sbi_timer.c
+ opensbi/lib/sbi/sbi_tlb.c
+ opensbi/lib/sbi/sbi_trap.c
+ opensbi/lib/sbi/sbi_unpriv.c
+ opensbi/lib/sbi/sbi_expected_trap.S
+
+ opensbi/lib/utils/fdt/fdt_helper.c
+ opensbi/lib/utils/fdt/fdt_fixup.c
+ opensbi/lib/utils/ipi/fdt_ipi.c
+ opensbi/lib/utils/ipi/fdt_ipi_clint.c
+ opensbi/lib/utils/irqchip/fdt_irqchip.c
+ opensbi/lib/utils/irqchip/fdt_irqchip_plic.c
+ opensbi/lib/utils/irqchip/plic.c
+ opensbi/lib/utils/reset/fdt_reset.c
+ opensbi/lib/utils/reset/fdt_reset_htif.c
+ opensbi/lib/utils/reset/fdt_reset_sifive.c
+ opensbi/lib/utils/serial/fdt_serial.c
+ opensbi/lib/utils/serial/fdt_serial_htif.c
+ opensbi/lib/utils/serial/fdt_serial_shakti.c
+ opensbi/lib/utils/serial/fdt_serial_sifive.c
+ opensbi/lib/utils/serial/fdt_serial_uart8250.c
+ opensbi/lib/utils/serial/shakti-uart.c
+ opensbi/lib/utils/serial/sifive-uart.c
+ opensbi/lib/utils/serial/uart8250.c
+ opensbi/lib/utils/sys/clint.c
+ opensbi/lib/utils/sys/htif.c
+ opensbi/lib/utils/sys/sifive_test.c
+ opensbi/lib/utils/timer/fdt_timer.c
+ opensbi/lib/utils/timer/fdt_timer_clint.c
+
+[Packages]
+ EmbeddedPkg/EmbeddedPkg.dec # For libfdt.
+ MdePkg/MdePkg.dec
+ Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec
+
+[BuildOptions]
+ GCC:*_*_*_PP_FLAGS = -D__ASSEMBLY__
diff --git a/Silicon/RISC-V/ProcessorPkg/Include/IndustryStandard/RiscVOpensbi.h b/Silicon/RISC-V/ProcessorPkg/Include/IndustryStandard/RiscVOpensbi.h
new file mode 100644
index 0000000000..2dab696af8
--- /dev/null
+++ b/Silicon/RISC-V/ProcessorPkg/Include/IndustryStandard/RiscVOpensbi.h
@@ -0,0 +1,59 @@
+/** @file
+ SBI inline function calls.
+
+ Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef EDK2_SBI_H_
+#define EDK2_SBI_H_
+
+#include <RiscVImpl.h>
+#include <sbi/riscv_asm.h>
+#include <sbi/riscv_atomic.h>
+#include <sbi/sbi_ecall_interface.h>
+#include <sbi/sbi_error.h>
+#include <sbi/sbi_platform.h>
+#include <sbi/sbi_scratch.h>
+#include <sbi/sbi_types.h>
+#include <sbi/sbi_hartmask.h>
+
+#define RISC_V_MAX_HART_SUPPORTED SBI_HARTMASK_MAX_BITS
+
+typedef
+VOID
+(EFIAPI *RISCV_HART_SWITCH_MODE)(
+ IN UINTN FuncArg0,
+ IN UINTN FuncArg1,
+ IN UINTN NextAddr,
+ IN UINTN NextMode,
+ IN BOOLEAN NextVirt
+ );
+
+//
+// Keep the structure member in 64-bit alignment.
+//
+typedef struct {
+ UINT64 IsaExtensionSupported; // The ISA extension this core supported.
+ RISCV_UINT128 MachineVendorId; // Machine vendor ID
+ RISCV_UINT128 MachineArchId; // Machine Architecture ID
+ RISCV_UINT128 MachineImplId; // Machine Implementation ID
+ RISCV_HART_SWITCH_MODE HartSwitchMode; // OpenSBI's function to switch the mode of a hart
+} EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC;
+#define FIRMWARE_CONTEXT_HART_SPECIFIC_SIZE (64 * 8) // This is the size of EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC
+ // structure. Referred by both C code and assembly code.
+
+typedef struct {
+ VOID *PeiServiceTable; // PEI Service table
+ EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC *HartSpecific[RISC_V_MAX_HART_SUPPORTED];
+} EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT;
+
+//
+// Typedefs of OpenSBI type to make them conform to EDK2 coding guidelines
+//
+typedef struct sbi_scratch SBI_SCRATCH;
+typedef struct sbi_platform SBI_PLATFORM;
+
+#endif
diff --git a/Silicon/RISC-V/ProcessorPkg/Include/OpensbiTypes.h b/Silicon/RISC-V/ProcessorPkg/Include/OpensbiTypes.h
new file mode 100644
index 0000000000..37e407908a
--- /dev/null
+++ b/Silicon/RISC-V/ProcessorPkg/Include/OpensbiTypes.h
@@ -0,0 +1,80 @@
+/** @file
+ RISC-V OpesbSBI header file reference.
+
+ Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+#ifndef EDK2_SBI_TYPES_H_
+#define EDK2_SBI_TYPES_H_
+
+#include <Base.h>
+
+typedef INT8 s8;
+typedef UINT8 u8;
+typedef UINT8 uint8_t;
+
+typedef INT16 s16;
+typedef UINT16 u16;
+typedef INT16 int16_t;
+typedef UINT16 uint16_t;
+
+typedef INT32 s32;
+typedef UINT32 u32;
+typedef INT32 int32_t;
+typedef UINT32 uint32_t;
+
+typedef INT64 s64;
+typedef UINT64 u64;
+typedef INT64 int64_t;
+typedef UINT64 uint64_t;
+
+// PRILX is not used in EDK2 but we need to define it here because when
+// defining our own types, this constant is not defined but used by OpenSBI.
+#define PRILX "016lx"
+
+typedef BOOLEAN bool;
+typedef unsigned long ulong;
+typedef UINT64 uintptr_t;
+typedef UINT64 size_t;
+typedef INT64 ssize_t;
+typedef UINT64 virtual_addr_t;
+typedef UINT64 virtual_size_t;
+typedef UINT64 physical_addr_t;
+typedef UINT64 physical_size_t;
+
+#define true TRUE
+#define false FALSE
+
+#define __packed __attribute__((packed))
+#define __noreturn __attribute__((noreturn))
+
+#if defined(__GNUC__) || defined(__clang__)
+ #define likely(x) __builtin_expect((x), 1)
+ #define unlikely(x) __builtin_expect((x), 0)
+#else
+ #define likely(x) (x)
+ #define unlikely(x) (x)
+#endif
+
+#undef offsetof
+#ifdef __compiler_offsetof
+#define offsetof(TYPE, MEMBER) __compiler_offsetof(TYPE,MEMBER)
+#else
+#define offsetof(TYPE, MEMBER) ((size_t) &((TYPE *)0)->MEMBER)
+#endif
+
+#define container_of(ptr, type, member) ({ \
+ const typeof(((type *)0)->member) * __mptr = (ptr); \
+ (type *)((char *)__mptr - offsetof(type, member)); })
+
+#define array_size(x) (sizeof(x) / sizeof((x)[0]))
+
+#define CLAMP(a, lo, hi) MIN(MAX(a, lo), hi)
+#define ROUNDUP(a, b) ((((a)-1) / (b) + 1) * (b))
+#define ROUNDDOWN(a, b) ((a) / (b) * (b))
+
+/* clang-format on */
+
+#endif
--
2.31.1
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH 07/79] ProcessorPkg/Library: Add RiscVEdk2SbiLib
2022-01-08 4:10 [PATCH 02/79] ProcessorPkg/Library: RISC-V CPU library Abner Chang
` (3 preceding siblings ...)
2022-01-08 4:10 ` [PATCH 06/79] ProcessorPkg/Library: Add RiscVOpensbiLib Abner Chang
@ 2022-01-08 4:10 ` Abner Chang
2022-01-08 4:10 ` [PATCH 08/79] ProcessorPkg/Library: RISC-V PEI Service Table Pointer library Abner Chang
` (32 subsequent siblings)
37 siblings, 0 replies; 39+ messages in thread
From: Abner Chang @ 2022-01-08 4:10 UTC (permalink / raw)
To: devel; +Cc: abner.chang
From: Daniel Schaefer <daniel.schaefer@hpe.com>
(This is migrated from edk2-platforms:Silicon/RISC-V)
Library provides interfaces to invoke SBI ecalls.
Signed-off-by: Daniel Schaefer <daniel.schaefer@hpe.com>
Reviewed-by: Leif Lindholm <leif@nuviainc.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Gilbert Chen <gilbert.chen@hpe.com>
Cc: Abner Chang <abner.chang@hpe.com>
---
.../RiscVEdk2SbiLib/RiscVEdk2SbiLib.inf | 28 +
.../Include/Library/RiscVEdk2SbiLib.h | 563 +++++++++++
.../Library/RiscVEdk2SbiLib/RiscVEdk2SbiLib.c | 897 ++++++++++++++++++
3 files changed, 1488 insertions(+)
create mode 100644 Silicon/RISC-V/ProcessorPkg/Library/RiscVEdk2SbiLib/RiscVEdk2SbiLib.inf
create mode 100644 Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVEdk2SbiLib.h
create mode 100644 Silicon/RISC-V/ProcessorPkg/Library/RiscVEdk2SbiLib/RiscVEdk2SbiLib.c
diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVEdk2SbiLib/RiscVEdk2SbiLib.inf b/Silicon/RISC-V/ProcessorPkg/Library/RiscVEdk2SbiLib/RiscVEdk2SbiLib.inf
new file mode 100644
index 0000000000..18d6ebc2ac
--- /dev/null
+++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVEdk2SbiLib/RiscVEdk2SbiLib.inf
@@ -0,0 +1,28 @@
+## @file
+# RISC-V Library to call SBI ecalls
+#
+# Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001b
+ BASE_NAME = RiscVEdk2SbiLib
+ FILE_GUID = 0DF1BBBD-F7E5-4E8A-BCF1-9D63D2DD9FDD
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = RiscVEdk2SbiLib
+
+[Sources]
+ RiscVEdk2SbiLib.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec
+ Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec
+
+[LibraryClasses]
+ BaseLib
+
diff --git a/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVEdk2SbiLib.h b/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVEdk2SbiLib.h
new file mode 100644
index 0000000000..558841a970
--- /dev/null
+++ b/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVEdk2SbiLib.h
@@ -0,0 +1,563 @@
+/** @file
+ Library to call the RISC-V SBI ecalls
+
+ Copyright (c) 2020, Hewlett Packard Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Glossary:
+ - Hart - Hardware Thread, similar to a CPU core
+**/
+
+#ifndef RISCV_SBI_LIB_H_
+#define RISCV_SBI_LIB_H_
+
+#include <Uefi.h>
+#include <IndustryStandard/RiscVOpensbi.h>
+#include <sbi/sbi_scratch.h>
+#include <sbi/sbi_platform.h>
+
+//
+// EDK2 OpenSBI Firmware extension.
+//
+#define SBI_EDK2_FW_EXT (SBI_EXT_FIRMWARE_START | SBI_OPENSBI_IMPID)
+//
+// EDK2 OpenSBI Firmware extension functions.
+//
+#define SBI_EXT_FW_MSCRATCH_FUNC 0
+#define SBI_EXT_FW_MSCRATCH_HARTID_FUNC 1
+
+//
+// EDK2 OpenSBI firmware extension return status.
+//
+typedef struct {
+ UINTN Error; ///< SBI status code
+ UINTN Value; ///< Value returned
+} SbiRet;
+
+/**
+ Get the implemented SBI specification version
+
+ The minor number of the SBI specification is encoded in the low 24 bits,
+ with the major number encoded in the next 7 bits. Bit 32 must be 0 and is
+ reserved for future expansion.
+
+ @param[out] SpecVersion The Version of the SBI specification.
+**/
+VOID
+EFIAPI
+SbiGetSpecVersion (
+ OUT UINTN *SpecVersion
+ );
+
+/**
+ Get the SBI implementation ID
+
+ This ID is used to idenetify a specific SBI implementation in order to work
+ around any quirks it might have.
+
+ @param[out] ImplId The ID of the SBI implementation.
+**/
+VOID
+EFIAPI
+SbiGetImplId (
+ OUT UINTN *ImplId
+ );
+
+/**
+ Get the SBI implementation version
+
+ The version of this SBI implementation.
+ The encoding of this number is determined by the specific SBI implementation.
+
+ @param[out] ImplVersion The version of the SBI implementation.
+**/
+VOID
+EFIAPI
+SbiGetImplVersion (
+ OUT UINTN *ImplVersion
+ );
+
+/**
+ Probe whether an SBI extension is available
+
+ ProbeResult is set to 0 if the extension is not available or to an extension
+ specified value if it is available.
+
+ @param[in] ExtensionId The extension ID.
+ @param[out] ProbeResult The return value of the probe.
+**/
+VOID
+EFIAPI
+SbiProbeExtension (
+ IN INTN ExtensionId,
+ OUT INTN *ProbeResult
+ );
+
+/**
+ Get the CPU's vendor ID
+
+ Reads the mvendorid CSR.
+
+ @param[out] MachineVendorId The CPU's vendor ID.
+**/
+VOID
+EFIAPI
+SbiGetMachineVendorId (
+ OUT UINTN *MachineVendorId
+ );
+
+/**
+ Get the CPU's architecture ID
+
+ Reads the marchid CSR.
+
+ @param[out] MachineArchId The CPU's architecture ID.
+**/
+VOID
+EFIAPI
+SbiGetMachineArchId (
+ OUT UINTN *MachineArchId
+ );
+
+/**
+ Get the CPU's implementation ID
+
+ Reads the mimpid CSR.
+
+ @param[out] MachineImplId The CPU's implementation ID.
+**/
+VOID
+EFIAPI
+SbiGetMachineImplId (
+ OUT UINTN *MachineImplId
+ );
+
+/**
+ Politely ask the SBI to start a given hart.
+
+ This call may return before the hart has actually started executing, if the
+ SBI implementation can guarantee that the hart is actually going to start.
+
+ Before the hart jumps to StartAddr, the hart MUST configure PMP if present
+ and switch to S-mode.
+
+ @param[in] HartId The id of the hart to start.
+ @param[in] StartAddr The physical address, where the hart starts
+ executing from.
+ @param[in] Priv An XLEN-bit value, which will be in register
+ a1 when the hart starts.
+ @retval EFI_SUCCESS Hart was stopped and will start executing from StartAddr.
+ @retval EFI_LOAD_ERROR StartAddr is not valid, possibly due to following reasons:
+ - It is not a valid physical address.
+ - The address is prohibited by PMP to run in
+ supervisor mode.
+ @retval EFI_INVALID_PARAMETER HartId is not a valid hart id
+ @retval EFI_ALREADY_STARTED The hart is already running.
+ @retval other The start request failed for unknown reasons.
+**/
+EFI_STATUS
+EFIAPI
+SbiHartStart (
+ IN UINTN HartId,
+ IN UINTN StartAddr,
+ IN UINTN Priv
+ );
+
+/**
+ Return execution of the calling hart to SBI.
+
+ MUST be called in S-Mode with user interrupts disabled.
+ This call is not expected to return, unless a failure occurs.
+
+ @retval EFI_SUCCESS Never occurs. When successful, the call does not return.
+ @retval other Failed to stop hard for an unknown reason.
+**/
+EFI_STATUS
+EFIAPI
+SbiHartStop (
+ );
+
+/**
+ Get the current status of a hart.
+
+ Since harts can transition between states at any time, the status retrieved
+ by this function may already be out of date, once it returns.
+
+ Possible values for HartStatus are:
+ 0: STARTED
+ 1: STOPPED
+ 2: START_REQUEST_PENDING
+ 3: STOP_REQUEST_PENDING
+
+ @param[out] HartStatus The pointer in which the hart's status is
+ stored.
+ @retval EFI_SUCCESS The operation succeeds.
+ @retval EFI_INVALID_PARAMETER A parameter is invalid.
+**/
+EFI_STATUS
+EFIAPI
+SbiHartGetStatus (
+ IN UINTN HartId,
+ OUT UINTN *HartStatus
+ );
+
+///
+/// Timer extension
+///
+
+/**
+ Clear pending timer interrupt bit and set timer for next event after Time.
+
+ To clear the timer without scheduling a timer event, set Time to a
+ practically infinite value or mask the timer interrupt by clearing sie.STIE.
+
+ @param[in] Time The time offset to the next scheduled timer interrupt.
+**/
+VOID
+EFIAPI
+SbiSetTimer (
+ IN UINT64 Time
+ );
+
+///
+/// IPI extension
+///
+
+/**
+ Send IPI to all harts specified in the mask.
+
+ The interrupts are registered as supervisor software interrupts at the
+ receiving hart.
+
+ @param[in] HartMask Scalar bit-vector containing hart ids
+ @param[in] HartMaskBase The starting hartid from which the bit-vector
+ must be computed. If set to -1, HartMask is
+ ignored and all harts are considered.
+ @retval EFI_SUCCESS IPI was sent to all the targeted harts.
+ @retval EFI_INVALID_PARAMETER Either hart_mask_base or any of the hartid
+ from hart_mask is not valid i.e. either the
+ hartid is not enabled by the platform or is
+ not available to the supervisor.
+**/
+EFI_STATUS
+EFIAPI
+SbiSendIpi (
+ IN UINTN *HartMask,
+ IN UINTN HartMaskBase
+ );
+
+///
+/// Remote fence extension
+///
+
+/**
+ Instructs remote harts to execute a FENCE.I instruction.
+
+ @param[in] HartMask Scalar bit-vector containing hart ids
+ @param[in] HartMaskBase The starting hartid from which the bit-vector
+ must be computed. If set to -1, HartMask is
+ ignored and all harts are considered.
+ @retval EFI_SUCCESS IPI was sent to all the targeted harts.
+ @retval EFI_INVALID_PARAMETER Either hart_mask_base or any of the hartid
+ from hart_mask is not valid i.e. either the
+ hartid is not enabled by the platform or is
+ not available to the supervisor.
+**/
+EFI_STATUS
+EFIAPI
+SbiRemoteFenceI (
+ IN UINTN *HartMask,
+ IN UINTN HartMaskBase
+ );
+
+/**
+ Instructs the remote harts to execute one or more SFENCE.VMA instructions.
+
+ The SFENCE.VMA covers the range of virtual addresses between StartAaddr and Size.
+
+ The remote fence function acts as a full tlb flush if * StartAddr and size
+ are both 0 * size is equal to 2^XLEN-1
+
+ @param[in] HartMask Scalar bit-vector containing hart ids
+ @param[in] HartMaskBase The starting hartid from which the bit-vector
+ must be computed. If set to -1, HartMask is
+ ignored and all harts are considered.
+ @param[in] StartAddr The first address of the affected range.
+ @param[in] Size How many addresses are affected.
+ @retval EFI_SUCCESS IPI was sent to all the targeted harts.
+ @retval EFI_LOAD_ERROR StartAddr or Size is not valid.
+ @retval EFI_INVALID_PARAMETER Either hart_mask_base or any of the hartid
+ from hart_mask is not valid i.e. either the
+ hartid is not enabled by the platform or is
+ not available to the supervisor.
+**/
+EFI_STATUS
+EFIAPI
+SbiRemoteSfenceVma (
+ IN UINTN *HartMask,
+ IN UINTN HartMaskBase,
+ IN UINTN StartAddr,
+ IN UINTN Size
+ );
+
+/**
+ Instructs the remote harts to execute one or more SFENCE.VMA instructions.
+
+ The SFENCE.VMA covers the range of virtual addresses between StartAaddr and Size.
+ Covers only the given ASID.
+
+ The remote fence function acts as a full tlb flush if * StartAddr and size
+ are both 0 * size is equal to 2^XLEN-1
+
+ @param[in] HartMask Scalar bit-vector containing hart ids
+ @param[in] HartMaskBase The starting hartid from which the bit-vector
+ must be computed. If set to -1, HartMask is
+ ignored and all harts are considered.
+ @param[in] StartAddr The first address of the affected range.
+ @param[in] Size How many addresses are affected.
+ @retval EFI_SUCCESS IPI was sent to all the targeted harts.
+ @retval EFI_LOAD_ERROR StartAddr or Size is not valid.
+ @retval EFI_INVALID_PARAMETER Either hart_mask_base or any of the hartid
+ from hart_mask is not valid i.e. either the
+ hartid is not enabled by the platform or is
+ not available to the supervisor.
+**/
+EFI_STATUS
+EFIAPI
+SbiRemoteSfenceVmaAsid (
+ IN UINTN *HartMask,
+ IN UINTN HartMaskBase,
+ IN UINTN StartAddr,
+ IN UINTN Size,
+ IN UINTN Asid
+ );
+
+/**
+ Instructs the remote harts to execute one or more SFENCE.GVMA instructions.
+
+ The SFENCE.GVMA covers the range of virtual addresses between StartAaddr and Size.
+ Covers only the given VMID.
+ This function call is only valid for harts implementing the hypervisor extension.
+
+ The remote fence function acts as a full tlb flush if * StartAddr and size
+ are both 0 * size is equal to 2^XLEN-1
+
+ @param[in] HartMask Scalar bit-vector containing hart ids
+ @param[in] HartMaskBase The starting hartid from which the bit-vector
+ must be computed. If set to -1, HartMask is
+ ignored and all harts are considered.
+ @param[in] StartAddr The first address of the affected range.
+ @param[in] Size How many addresses are affected.
+ @retval EFI_SUCCESS IPI was sent to all the targeted harts.
+ @retval EFI_LOAD_ERROR StartAddr or Size is not valid.
+ @retval EFI_UNSUPPORTED SBI does not implement this function or one
+ of the target harts does not support the
+ hypervisor extension.
+ @retval EFI_INVALID_PARAMETER Either hart_mask_base or any of the hartid
+ from hart_mask is not valid i.e. either the
+ hartid is not enabled by the platform or is
+ not available to the supervisor.
+**/
+EFI_STATUS
+EFIAPI
+SbiRemoteHfenceGvmaVmid (
+ IN UINTN *HartMask,
+ IN UINTN HartMaskBase,
+ IN UINTN StartAddr,
+ IN UINTN Size,
+ IN UINTN Vmid
+ );
+
+/**
+ Instructs the remote harts to execute one or more SFENCE.GVMA instructions.
+
+ The SFENCE.GVMA covers the range of virtual addresses between StartAaddr and Size.
+ This function call is only valid for harts implementing the hypervisor extension.
+
+ The remote fence function acts as a full tlb flush if * StartAddr and size
+ are both 0 * size is equal to 2^XLEN-1
+
+ @param[in] HartMask Scalar bit-vector containing hart ids
+ @param[in] HartMaskBase The starting hartid from which the bit-vector
+ must be computed. If set to -1, HartMask is
+ ignored and all harts are considered.
+ @param[in] StartAddr The first address of the affected range.
+ @param[in] Size How many addresses are affected.
+ @retval EFI_SUCCESS IPI was sent to all the targeted harts.
+ @retval EFI_LOAD_ERROR StartAddr or Size is not valid.
+ @retval EFI_UNSUPPORTED SBI does not implement this function or one
+ of the target harts does not support the
+ hypervisor extension.
+ @retval EFI_INVALID_PARAMETER Either hart_mask_base or any of the hartid
+ from hart_mask is not valid i.e. either the
+ hartid is not enabled by the platform or is
+ not available to the supervisor.
+**/
+EFI_STATUS
+EFIAPI
+SbiRemoteHfenceGvma (
+ IN UINTN *HartMask,
+ IN UINTN HartMaskBase,
+ IN UINTN StartAddr,
+ IN UINTN Size
+ );
+
+/**
+ Instructs the remote harts to execute one or more SFENCE.VVMA instructions.
+
+ The SFENCE.GVMA covers the range of virtual addresses between StartAaddr and Size.
+ Covers only the given ASID.
+ This function call is only valid for harts implementing the hypervisor extension.
+
+ The remote fence function acts as a full tlb flush if * StartAddr and size
+ are both 0 * size is equal to 2^XLEN-1
+
+ @param[in] HartMask Scalar bit-vector containing hart ids
+ @param[in] HartMaskBase The starting hartid from which the bit-vector
+ must be computed. If set to -1, HartMask is
+ ignored and all harts are considered.
+ @param[in] StartAddr The first address of the affected range.
+ @param[in] Size How many addresses are affected.
+ @retval EFI_SUCCESS IPI was sent to all the targeted harts.
+ @retval EFI_LOAD_ERROR StartAddr or Size is not valid.
+ @retval EFI_UNSUPPORTED SBI does not implement this function or one
+ of the target harts does not support the
+ hypervisor extension.
+ @retval EFI_INVALID_PARAMETER Either hart_mask_base or any of the hartid
+ from hart_mask is not valid i.e. either the
+ hartid is not enabled by the platform or is
+ not available to the supervisor.
+**/
+EFI_STATUS
+EFIAPI
+SbiRemoteHfenceVvmaAsid (
+ IN UINTN *HartMask,
+ IN UINTN HartMaskBase,
+ IN UINTN StartAddr,
+ IN UINTN Size,
+ IN UINTN Asid
+ );
+
+/**
+ Instructs the remote harts to execute one or more SFENCE.VVMA instructions.
+
+ The SFENCE.GVMA covers the range of virtual addresses between StartAaddr and Size.
+ This function call is only valid for harts implementing the hypervisor extension.
+
+ The remote fence function acts as a full tlb flush if * StartAddr and size
+ are both 0 * size is equal to 2^XLEN-1
+
+ @param[in] HartMask Scalar bit-vector containing hart ids
+ @param[in] HartMaskBase The starting hartid from which the bit-vector
+ must be computed. If set to -1, HartMask is
+ ignored and all harts are considered.
+ @param[in] StartAddr The first address of the affected range.
+ @param[in] Size How many addresses are affected.
+ @retval EFI_SUCCESS IPI was sent to all the targeted harts.
+ @retval EFI_LOAD_ERROR StartAddr or Size is not valid.
+ @retval EFI_UNSUPPORTED SBI does not implement this function or one
+ of the target harts does not support the
+ hypervisor extension.
+ @retval EFI_INVALID_PARAMETER Either hart_mask_base or any of the hartid
+ from hart_mask is not valid i.e. either the
+ hartid is not enabled by the platform or is
+ not available to the supervisor.
+**/
+EFI_STATUS
+EFIAPI
+SbiRemoteHfenceVvma (
+ IN UINTN *HartMask,
+ IN UINTN HartMaskBase,
+ IN UINTN StartAddr,
+ IN UINTN Size
+ );
+
+///
+/// Vendor Specific extension space: Extension Ids 0x09000000 through 0x09FFFFFF
+///
+
+/**
+ Call a function in a vendor defined SBI extension
+
+ ASSERT() if the ExtensionId is not in the designated SBI Vendor Extension
+ Space.
+
+ @param[in] ExtensionId The SBI vendor extension ID.
+ @param[in] FunctionId The function ID to call in this extension.
+ @param[in] NumArgs How many arguments are passed.
+ @param[in] ... Actual Arguments to the function.
+ @retval EFI_SUCCESS if the SBI function was called and it was successful
+ @retval EFI_INVALID_PARAMETER if NumArgs exceeds 6
+ @retval others if the called SBI function returns an error
+**/
+EFI_STATUS
+EFIAPI
+SbiVendorCall (
+ IN UINTN ExtensionId,
+ IN UINTN FunctionId,
+ IN UINTN NumArgs,
+ ...
+ );
+
+///
+/// Firmware SBI Extension
+///
+/// This SBI Extension is defined and used by EDK2 only in order to be able to
+/// run PI and DXE phase in S-Mode.
+///
+
+/**
+ Get scratch space of the current hart.
+
+ Please consider using the wrapper SbiGetFirmwareContext if you only need to
+ access the firmware context.
+
+ @param[out] ScratchSpace The scratch space pointer.
+ @retval EFI_SUCCESS The operation succeeds.
+**/
+EFI_STATUS
+EFIAPI
+SbiGetMscratch (
+ OUT SBI_SCRATCH **ScratchSpace
+ );
+
+/**
+ Get scratch space of the given hart id.
+
+ @param[in] HartId The hart id.
+ @param[out] ScratchSpace The scratch space pointer.
+ @retval EFI_SUCCESS The operation succeeds.
+**/
+EFI_STATUS
+EFIAPI
+SbiGetMscratchHartid (
+ IN UINTN HartId,
+ OUT SBI_SCRATCH **ScratchSpace
+ );
+
+/**
+ Get firmware context of the calling hart.
+
+ @param[out] FirmwareContext The firmware context pointer.
+ @retval EFI_SUCCESS The operation succeeds.
+**/
+EFI_STATUS
+EFIAPI
+SbiGetFirmwareContext (
+ OUT EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT **FirmwareContext
+ );
+
+/**
+ Set firmware context of the calling hart.
+
+ @param[in] FirmwareContext The firmware context pointer.
+ @retval EFI_SUCCESS The operation succeeds.
+**/
+EFI_STATUS
+EFIAPI
+SbiSetFirmwareContext (
+ IN EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *FirmwareContext
+ );
+
+#endif
diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVEdk2SbiLib/RiscVEdk2SbiLib.c b/Silicon/RISC-V/ProcessorPkg/Library/RiscVEdk2SbiLib/RiscVEdk2SbiLib.c
new file mode 100644
index 0000000000..0df505d267
--- /dev/null
+++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVEdk2SbiLib/RiscVEdk2SbiLib.c
@@ -0,0 +1,897 @@
+/** @file
+ Instance of the SBI ecall library.
+
+ It allows calling an SBI function via an ecall from S-Mode.
+
+ The legacy extensions are not included because they are not necessary.
+ They would be:
+ - SbiLegacySetTimer -> Use SbiSetTimer
+ - SbiLegacyConsolePutChar -> No replacement - Use regular UEFI functions
+ - SbiLegacyConsoleGetChar -> No replacement - Use regular UEFI functions
+ - SbiLegacyClearIpi -> Write 0 to SSIP
+ - SbiLegacySendIpi -> Use SbiSendIpi
+ - SbiLegacyRemoteFenceI -> Use SbiRemoteFenceI
+ - SbiLegacyRemoteSfenceVma -> Use SbiRemoteSfenceVma
+ - SbiLegacyRemoteSfenceVmaAsid -> Use SbiRemoteSfenceVmaAsid
+ - SbiLegacyShutdown -> Wait for new System Reset extension
+
+ Copyright (c) 2020, Hewlett Packard Development LP. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Revision Reference:
+ - OpenSBI Version 0.6
+**/
+
+#include <IndustryStandard/RiscVOpensbi.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/RiscVEdk2SbiLib.h>
+#include <sbi/riscv_asm.h>
+#include <sbi/sbi_hart.h>
+#include <sbi/sbi_types.h>
+#include <sbi/sbi_init.h>
+
+
+//
+// Maximum arguments for SBI ecall
+// It's possible to pass more but no SBI call uses more as of SBI 0.2.
+// The additional arguments would have to be passed on the stack instead of as
+// registers, like it's done now.
+//
+#define SBI_CALL_MAX_ARGS 6
+
+/**
+ Call SBI call using ecall instruction.
+
+ Asserts when NumArgs exceeds SBI_CALL_MAX_ARGS.
+
+ @param[in] ExtId SBI extension ID.
+ @param[in] FuncId SBI function ID.
+ @param[in] NumArgs Number of arguments to pass to the ecall.
+ @param[in] ... Argument list for the ecall.
+
+ @retval Returns SbiRet structure with value and error code.
+
+**/
+STATIC
+SbiRet
+EFIAPI
+SbiCall(
+ IN UINTN ExtId,
+ IN UINTN FuncId,
+ IN UINTN NumArgs,
+ ...
+ )
+{
+ UINTN I;
+ SbiRet Ret;
+ UINTN Args[SBI_CALL_MAX_ARGS];
+ VA_LIST ArgList;
+ VA_START (ArgList, NumArgs);
+
+ ASSERT (NumArgs <= SBI_CALL_MAX_ARGS);
+
+ for (I = 0; I < SBI_CALL_MAX_ARGS; I++) {
+ if (I < NumArgs) {
+ Args[I] = VA_ARG (ArgList, UINTN);
+ } else {
+ // Default to 0 for all arguments that are not given
+ Args[I] = 0;
+ }
+ }
+
+ VA_END(ArgList);
+
+ register UINTN a0 asm ("a0") = Args[0];
+ register UINTN a1 asm ("a1") = Args[1];
+ register UINTN a2 asm ("a2") = Args[2];
+ register UINTN a3 asm ("a3") = Args[3];
+ register UINTN a4 asm ("a4") = Args[4];
+ register UINTN a5 asm ("a5") = Args[5];
+ register UINTN a6 asm ("a6") = (UINTN)(FuncId);
+ register UINTN a7 asm ("a7") = (UINTN)(ExtId);
+ asm volatile ("ecall" \
+ : "+r" (a0), "+r" (a1) \
+ : "r" (a2), "r" (a3), "r" (a4), "r" (a5), "r" (a6), "r" (a7) \
+ : "memory"); \
+ Ret.Error = a0;
+ Ret.Value = a1;
+ return Ret;
+}
+
+/**
+ Translate SBI error code to EFI status.
+
+ @param[in] SbiError SBI error code
+ @retval EFI_STATUS
+**/
+
+STATIC
+EFI_STATUS
+EFIAPI
+TranslateError(
+ IN UINTN SbiError
+ )
+{
+ switch (SbiError) {
+ case SBI_SUCCESS:
+ return EFI_SUCCESS;
+ case SBI_ERR_FAILED:
+ return EFI_DEVICE_ERROR;
+ break;
+ case SBI_ERR_NOT_SUPPORTED:
+ return EFI_UNSUPPORTED;
+ break;
+ case SBI_ERR_INVALID_PARAM:
+ return EFI_INVALID_PARAMETER;
+ break;
+ case SBI_ERR_DENIED:
+ return EFI_ACCESS_DENIED;
+ break;
+ case SBI_ERR_INVALID_ADDRESS:
+ return EFI_LOAD_ERROR;
+ break;
+ case SBI_ERR_ALREADY_AVAILABLE:
+ return EFI_ALREADY_STARTED;
+ break;
+ default:
+ //
+ // Reaches here only if SBI has defined a new error type
+ //
+ ASSERT (FALSE);
+ return EFI_UNSUPPORTED;
+ break;
+ }
+}
+
+//
+// OpenSBI library interface function for the base extension
+//
+
+/**
+ Get the implemented SBI specification version
+
+ The minor number of the SBI specification is encoded in the low 24 bits,
+ with the major number encoded in the next 7 bits. Bit 32 must be 0 and is
+ reserved for future expansion.
+
+ @param[out] SpecVersion The Version of the SBI specification.
+**/
+VOID
+EFIAPI
+SbiGetSpecVersion (
+ OUT UINTN *SpecVersion
+ )
+{
+ SbiRet Ret = SbiCall (SBI_EXT_BASE, SBI_EXT_BASE_GET_SPEC_VERSION, 0);
+
+ if (!Ret.Error) {
+ *SpecVersion = (UINTN)Ret.Value;
+ }
+}
+
+/**
+ Get the SBI implementation ID
+
+ This ID is used to idenetify a specific SBI implementation in order to work
+ around any quirks it might have.
+
+ @param[out] ImplId The ID of the SBI implementation.
+**/
+VOID
+EFIAPI
+SbiGetImplId (
+ OUT UINTN *ImplId
+ )
+{
+ SbiRet Ret = SbiCall (SBI_EXT_BASE, SBI_EXT_BASE_GET_IMP_ID, 0);
+ *ImplId = (UINTN)Ret.Value;
+}
+
+/**
+ Get the SBI implementation version
+
+ The version of this SBI implementation.
+ The encoding of this number is determined by the specific SBI implementation.
+
+ @param[out] ImplVersion The version of the SBI implementation.
+**/
+VOID
+EFIAPI
+SbiGetImplVersion (
+ OUT UINTN *ImplVersion
+ )
+{
+ SbiRet Ret = SbiCall (SBI_EXT_BASE, SBI_EXT_BASE_GET_IMP_VERSION, 0);
+ *ImplVersion = (UINTN)Ret.Value;
+}
+
+/**
+ Probe whether an SBI extension is available
+
+ ProbeResult is set to 0 if the extension is not available or to an extension
+ specified value if it is available.
+
+ @param[in] ExtensionId The extension ID.
+ @param[out] ProbeResult The return value of the probe.
+**/
+VOID
+EFIAPI
+SbiProbeExtension (
+ IN INTN ExtensionId,
+ OUT INTN *ProbeResult
+ )
+{
+ SbiRet Ret = SbiCall (SBI_EXT_BASE, SBI_EXT_BASE_PROBE_EXT, 0);
+ *ProbeResult = (UINTN)Ret.Value;
+}
+
+/**
+ Get the CPU's vendor ID
+
+ Reads the mvendorid CSR.
+
+ @param[out] MachineVendorId The CPU's vendor ID.
+**/
+VOID
+EFIAPI
+SbiGetMachineVendorId (
+ OUT UINTN *MachineVendorId
+ )
+{
+ SbiRet Ret = SbiCall (SBI_EXT_BASE, SBI_EXT_BASE_GET_MVENDORID, 0);
+ *MachineVendorId = (UINTN)Ret.Value;
+}
+
+/**
+ Get the CPU's architecture ID
+
+ Reads the marchid CSR.
+
+ @param[out] MachineArchId The CPU's architecture ID.
+**/
+VOID
+EFIAPI
+SbiGetMachineArchId (
+ OUT UINTN *MachineArchId
+ )
+{
+ SbiRet Ret = SbiCall (SBI_EXT_BASE, SBI_EXT_BASE_GET_MARCHID, 0);
+ *MachineArchId = (UINTN)Ret.Value;
+}
+
+/**
+ Get the CPU's architecture ID
+
+ Reads the marchid CSR.
+
+ @param[out] MachineImplId The CPU's implementation ID.
+**/
+VOID
+EFIAPI
+SbiGetMachineImplId (
+ OUT UINTN *MachineImplId
+ )
+{
+ SbiRet Ret = SbiCall (SBI_EXT_BASE, SBI_EXT_BASE_GET_MIMPID, 0);
+ *MachineImplId = (UINTN)Ret.Value;
+}
+
+//
+// SBI interface function for the hart state management extension
+//
+
+/**
+ Politely ask the SBI to start a given hart.
+
+ This call may return before the hart has actually started executing, if the
+ SBI implementation can guarantee that the hart is actually going to start.
+
+ Before the hart jumps to StartAddr, the hart MUST configure PMP if present
+ and switch to S-mode.
+
+ @param[in] HartId The id of the hart to start.
+ @param[in] StartAddr The physical address, where the hart starts
+ executing from.
+ @param[in] Priv An XLEN-bit value, which will be in register
+ a1 when the hart starts.
+ @retval EFI_SUCCESS Hart was stopped and will start executing from StartAddr.
+ @retval EFI_LOAD_ERROR StartAddr is not valid, possibly due to following reasons:
+ - It is not a valid physical address.
+ - The address is prohibited by PMP to run in
+ supervisor mode.
+ @retval EFI_INVALID_PARAMETER HartId is not a valid hart id
+ @retval EFI_ALREADY_STARTED The hart is already running.
+ @retval other The start request failed for unknown reasons.
+**/
+EFI_STATUS
+EFIAPI
+SbiHartStart (
+ IN UINTN HartId,
+ IN UINTN StartAddr,
+ IN UINTN Priv
+ )
+{
+ SbiRet Ret = SbiCall (
+ SBI_EXT_HSM,
+ SBI_EXT_HSM_HART_START,
+ 3,
+ HartId,
+ StartAddr,
+ Priv
+ );
+ return TranslateError (Ret.Error);
+}
+
+/**
+ Return execution of the calling hart to SBI.
+
+ MUST be called in S-Mode with user interrupts disabled.
+ This call is not expected to return, unless a failure occurs.
+
+ @retval EFI_SUCCESS Never occurs. When successful, the call does not return.
+ @retval other Failed to stop hard for an unknown reason.
+**/
+EFI_STATUS
+EFIAPI
+SbiHartStop (
+ )
+{
+ SbiRet Ret = SbiCall (SBI_EXT_HSM, SBI_EXT_HSM_HART_STOP, 0);
+ return TranslateError (Ret.Error);
+}
+
+/**
+ Get the current status of a hart.
+
+ Since harts can transition between states at any time, the status retrieved
+ by this function may already be out of date, once it returns.
+
+ Possible values for HartStatus are:
+ 0: STARTED
+ 1: STOPPED
+ 2: START_REQUEST_PENDING
+ 3: STOP_REQUEST_PENDING
+
+ @param[out] HartStatus The pointer in which the hart's status is
+ stored.
+ @retval EFI_SUCCESS The operation succeeds.
+ @retval EFI_INVALID_PARAMETER A parameter is invalid.
+**/
+EFI_STATUS
+EFIAPI
+SbiHartGetStatus (
+ IN UINTN HartId,
+ OUT UINTN *HartStatus
+ )
+{
+ SbiRet Ret = SbiCall (SBI_EXT_HSM, SBI_EXT_HSM_HART_GET_STATUS, 1, HartId);
+
+ if (!Ret.Error) {
+ *HartStatus = (UINTN)Ret.Value;
+ }
+
+ return TranslateError (Ret.Error);
+}
+
+/**
+ Clear pending timer interrupt bit and set timer for next event after Time.
+
+ To clear the timer without scheduling a timer event, set Time to a
+ practically infinite value or mask the timer interrupt by clearing sie.STIE.
+
+ @param[in] Time The time offset to the next scheduled timer interrupt.
+**/
+VOID
+EFIAPI
+SbiSetTimer (
+ IN UINT64 Time
+ )
+{
+ SbiCall (SBI_EXT_TIME, SBI_EXT_TIME_SET_TIMER, 1, Time);
+}
+
+EFI_STATUS
+EFIAPI
+SbiSendIpi (
+ IN UINTN *HartMask,
+ IN UINTN HartMaskBase
+ )
+{
+ SbiRet Ret = SbiCall (
+ SBI_EXT_IPI,
+ SBI_EXT_IPI_SEND_IPI,
+ 2,
+ (UINTN)HartMask,
+ HartMaskBase
+ );
+ return TranslateError (Ret.Error);
+}
+
+/**
+ Instructs remote harts to execute a FENCE.I instruction.
+
+ @param[in] HartMask Scalar bit-vector containing hart ids
+ @param[in] HartMaskBase The starting hartid from which the bit-vector
+ must be computed. If set to -1, HartMask is
+ ignored and all harts are considered.
+ @retval EFI_SUCCESS IPI was sent to all the targeted harts.
+ @retval EFI_INVALID_PARAMETER Either hart_mask_base or any of the hartid
+ from hart_mask is not valid i.e. either the
+ hartid is not enabled by the platform or is
+ not available to the supervisor.
+**/
+EFI_STATUS
+EFIAPI
+SbiRemoteFenceI (
+ IN UINTN *HartMask,
+ IN UINTN HartMaskBase
+ )
+{
+ SbiRet Ret = SbiCall (
+ SBI_EXT_RFENCE,
+ SBI_EXT_RFENCE_REMOTE_FENCE_I,
+ 2,
+ (UINTN)HartMask,
+ HartMaskBase
+ );
+ return TranslateError (Ret.Error);
+}
+
+/**
+ Instructs the remote harts to execute one or more SFENCE.VMA instructions.
+
+ The SFENCE.VMA covers the range of virtual addresses between StartAaddr and Size.
+
+ The remote fence function acts as a full tlb flush if * StartAddr and size
+ are both 0 * size is equal to 2^XLEN-1
+
+ @param[in] HartMask Scalar bit-vector containing hart ids
+ @param[in] HartMaskBase The starting hartid from which the bit-vector
+ must be computed. If set to -1, HartMask is
+ ignored and all harts are considered.
+ @param[in] StartAddr The first address of the affected range.
+ @param[in] Size How many addresses are affected.
+ @retval EFI_SUCCESS IPI was sent to all the targeted harts.
+ @retval EFI_LOAD_ERROR StartAddr or Size is not valid.
+ @retval EFI_INVALID_PARAMETER Either hart_mask_base or any of the hartid
+ from hart_mask is not valid i.e. either the
+ hartid is not enabled by the platform or is
+ not available to the supervisor.
+**/
+EFI_STATUS
+EFIAPI
+SbiRemoteSfenceVma (
+ IN UINTN *HartMask,
+ IN UINTN HartMaskBase,
+ IN UINTN StartAddr,
+ IN UINTN Size
+ )
+{
+ SbiRet Ret = SbiCall (
+ SBI_EXT_RFENCE,
+ SBI_EXT_RFENCE_REMOTE_SFENCE_VMA,
+ 4,
+ (UINTN)HartMask,
+ HartMaskBase,
+ StartAddr,
+ Size
+ );
+ return TranslateError (Ret.Error);
+}
+
+/**
+ Instructs the remote harts to execute one or more SFENCE.VMA instructions.
+
+ The SFENCE.VMA covers the range of virtual addresses between StartAaddr and Size.
+ Covers only the given ASID.
+
+ The remote fence function acts as a full tlb flush if * StartAddr and size
+ are both 0 * size is equal to 2^XLEN-1
+
+ @param[in] HartMask Scalar bit-vector containing hart ids
+ @param[in] HartMaskBase The starting hartid from which the bit-vector
+ must be computed. If set to -1, HartMask is
+ ignored and all harts are considered.
+ @param[in] StartAddr The first address of the affected range.
+ @param[in] Size How many addresses are affected.
+ @retval EFI_SUCCESS IPI was sent to all the targeted harts.
+ @retval EFI_LOAD_ERROR StartAddr or Size is not valid.
+ @retval EFI_INVALID_PARAMETER Either hart_mask_base or any of the hartid
+ from hart_mask is not valid i.e. either the
+ hartid is not enabled by the platform or is
+ not available to the supervisor.
+**/
+EFI_STATUS
+EFIAPI
+SbiRemoteSfenceVmaAsid (
+ IN UINTN *HartMask,
+ IN UINTN HartMaskBase,
+ IN UINTN StartAddr,
+ IN UINTN Size,
+ IN UINTN Asid
+ )
+{
+ SbiRet Ret = SbiCall (
+ SBI_EXT_RFENCE,
+ SBI_EXT_RFENCE_REMOTE_SFENCE_VMA_ASID,
+ 5,
+ (UINTN)HartMask,
+ HartMaskBase,
+ StartAddr,
+ Size,
+ Asid
+ );
+ return TranslateError (Ret.Error);
+}
+
+/**
+ Instructs the remote harts to execute one or more SFENCE.GVMA instructions.
+
+ The SFENCE.GVMA covers the range of virtual addresses between StartAaddr and Size.
+ Covers only the given VMID.
+ This function call is only valid for harts implementing the hypervisor extension.
+
+ The remote fence function acts as a full tlb flush if * StartAddr and size
+ are both 0 * size is equal to 2^XLEN-1
+
+ @param[in] HartMask Scalar bit-vector containing hart ids
+ @param[in] HartMaskBase The starting hartid from which the bit-vector
+ must be computed. If set to -1, HartMask is
+ ignored and all harts are considered.
+ @param[in] StartAddr The first address of the affected range.
+ @param[in] Size How many addresses are affected.
+ @retval EFI_SUCCESS IPI was sent to all the targeted harts.
+ @retval EFI_LOAD_ERROR StartAddr or Size is not valid.
+ @retval EFI_UNSUPPORTED SBI does not implement this function or one
+ of the target harts does not support the
+ hypervisor extension.
+ @retval EFI_INVALID_PARAMETER Either hart_mask_base or any of the hartid
+ from hart_mask is not valid i.e. either the
+ hartid is not enabled by the platform or is
+ not available to the supervisor.
+**/
+EFI_STATUS
+EFIAPI
+SbiRemoteHFenceGvmaVmid (
+ IN UINTN *HartMask,
+ IN UINTN HartMaskBase,
+ IN UINTN StartAddr,
+ IN UINTN Size,
+ IN UINTN Vmid
+ )
+{
+ SbiRet Ret = SbiCall (
+ SBI_EXT_RFENCE,
+ SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA,
+ 5,
+ (UINTN)HartMask,
+ HartMaskBase,
+ StartAddr,
+ Size,
+ Vmid
+ );
+ return TranslateError (Ret.Error);
+}
+
+/**
+ Instructs the remote harts to execute one or more SFENCE.GVMA instructions.
+
+ The SFENCE.GVMA covers the range of virtual addresses between StartAaddr and Size.
+ This function call is only valid for harts implementing the hypervisor extension.
+
+ The remote fence function acts as a full tlb flush if * StartAddr and size
+ are both 0 * size is equal to 2^XLEN-1
+
+ @param[in] HartMask Scalar bit-vector containing hart ids
+ @param[in] HartMaskBase The starting hartid from which the bit-vector
+ must be computed. If set to -1, HartMask is
+ ignored and all harts are considered.
+ @param[in] StartAddr The first address of the affected range.
+ @param[in] Size How many addresses are affected.
+ @retval EFI_SUCCESS IPI was sent to all the targeted harts.
+ @retval EFI_LOAD_ERROR StartAddr or Size is not valid.
+ @retval EFI_UNSUPPORTED SBI does not implement this function or one
+ of the target harts does not support the
+ hypervisor extension.
+ @retval EFI_INVALID_PARAMETER Either hart_mask_base or any of the hartid
+ from hart_mask is not valid i.e. either the
+ hartid is not enabled by the platform or is
+ not available to the supervisor.
+**/
+EFI_STATUS
+EFIAPI
+SbiRemoteHFenceGvma (
+ IN UINTN *HartMask,
+ IN UINTN HartMaskBase,
+ IN UINTN StartAddr,
+ IN UINTN Size
+ )
+{
+ SbiRet Ret = SbiCall (
+ SBI_EXT_RFENCE,
+ SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA_VMID,
+ 4,
+ (UINTN)HartMask,
+ HartMaskBase,
+ StartAddr,
+ Size
+ );
+ return TranslateError (Ret.Error);
+}
+
+/**
+ Instructs the remote harts to execute one or more SFENCE.VVMA instructions.
+
+ The SFENCE.GVMA covers the range of virtual addresses between StartAaddr and Size.
+ Covers only the given ASID.
+ This function call is only valid for harts implementing the hypervisor extension.
+
+ The remote fence function acts as a full tlb flush if * StartAddr and size
+ are both 0 * size is equal to 2^XLEN-1
+
+ @param[in] HartMask Scalar bit-vector containing hart ids
+ @param[in] HartMaskBase The starting hartid from which the bit-vector
+ must be computed. If set to -1, HartMask is
+ ignored and all harts are considered.
+ @param[in] StartAddr The first address of the affected range.
+ @param[in] Size How many addresses are affected.
+ @retval EFI_SUCCESS IPI was sent to all the targeted harts.
+ @retval EFI_LOAD_ERROR StartAddr or Size is not valid.
+ @retval EFI_UNSUPPORTED SBI does not implement this function or one
+ of the target harts does not support the
+ hypervisor extension.
+ @retval EFI_INVALID_PARAMETER Either hart_mask_base or any of the hartid
+ from hart_mask is not valid i.e. either the
+ hartid is not enabled by the platform or is
+ not available to the supervisor.
+**/
+EFI_STATUS
+EFIAPI
+SbiRemoteHFenceVvmaAsid (
+ IN UINTN *HartMask,
+ IN UINTN HartMaskBase,
+ IN UINTN StartAddr,
+ IN UINTN Size,
+ IN UINTN Asid
+ )
+{
+ SbiRet Ret = SbiCall (
+ SBI_EXT_RFENCE,
+ SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA,
+ 5,
+ (UINTN)HartMask,
+ HartMaskBase,
+ StartAddr,
+ Size,
+ Asid
+ );
+ return TranslateError (Ret.Error);
+}
+
+/**
+ Instructs the remote harts to execute one or more SFENCE.VVMA instructions.
+
+ The SFENCE.GVMA covers the range of virtual addresses between StartAaddr and Size.
+ This function call is only valid for harts implementing the hypervisor extension.
+
+ The remote fence function acts as a full tlb flush if * StartAddr and size
+ are both 0 * size is equal to 2^XLEN-1
+
+ @param[in] HartMask Scalar bit-vector containing hart ids
+ @param[in] HartMaskBase The starting hartid from which the bit-vector
+ must be computed. If set to -1, HartMask is
+ ignored and all harts are considered.
+ @param[in] StartAddr The first address of the affected range.
+ @param[in] Size How many addresses are affected.
+ @retval EFI_SUCCESS IPI was sent to all the targeted harts.
+ @retval EFI_LOAD_ERROR StartAddr or Size is not valid.
+ @retval EFI_UNSUPPORTED SBI does not implement this function or one
+ of the target harts does not support the
+ hypervisor extension.
+ @retval EFI_INVALID_PARAMETER Either hart_mask_base or any of the hartid
+ from hart_mask is not valid i.e. either the
+ hartid is not enabled by the platform or is
+ not available to the supervisor.
+**/
+EFI_STATUS
+EFIAPI
+SbiRemoteHFenceVvma (
+ IN UINTN *HartMask,
+ IN UINTN HartMaskBase,
+ IN UINTN StartAddr,
+ IN UINTN Size
+ )
+{
+ SbiRet Ret = SbiCall (
+ SBI_EXT_RFENCE,
+ SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA_ASID,
+ 4,
+ (UINTN)HartMask,
+ HartMaskBase,
+ StartAddr,
+ Size
+ );
+ return TranslateError (Ret.Error);
+}
+
+//
+// SBI interface function for the vendor extension
+//
+
+/**
+ Call a function in a vendor defined SBI extension
+
+ ASSERT() if the ExtensionId is not in the designated SBI Vendor Extension
+ Space or NumArgs exceeds SBI_CALL_MAX_ARGS.
+
+ @param[in] ExtensionId The SBI vendor extension ID.
+ @param[in] FunctionId The function ID to call in this extension.
+ @param[in] NumArgs How many arguments are passed.
+ @param[in] ... Actual Arguments to the function.
+ @retval EFI_SUCCESS if the SBI function was called and it was successful
+ @retval others if the called SBI function returns an error
+**/
+EFI_STATUS
+EFIAPI
+SbiVendorCall (
+ IN UINTN ExtensionId,
+ IN UINTN FunctionId,
+ IN UINTN NumArgs,
+ ...
+ )
+{
+ SbiRet Ret;
+ VA_LIST Args;
+ VA_START (Args, NumArgs);
+
+ ASSERT (ExtensionId >= SBI_EXT_VENDOR_START && ExtensionId <= SBI_EXT_VENDOR_END);
+ ASSERT (NumArgs <= SBI_CALL_MAX_ARGS);
+
+ switch (NumArgs) {
+ case 0:
+ Ret = SbiCall (ExtensionId, FunctionId, NumArgs);
+ break;
+ case 1:
+ Ret = SbiCall (ExtensionId, FunctionId, NumArgs, VA_ARG (Args, UINTN));
+ break;
+ case 2:
+ Ret = SbiCall (ExtensionId, FunctionId, NumArgs, VA_ARG (Args, UINTN),
+ VA_ARG (Args, UINTN));
+ break;
+ case 3:
+ Ret = SbiCall (ExtensionId, FunctionId, NumArgs, VA_ARG (Args, UINTN),
+ VA_ARG (Args, UINTN), VA_ARG (Args, UINTN));
+ break;
+ case 4:
+ Ret = SbiCall (ExtensionId, FunctionId, NumArgs, VA_ARG (Args, UINTN),
+ VA_ARG (Args, UINTN), VA_ARG (Args, UINTN),
+ VA_ARG (Args, UINTN));
+ break;
+ case 5:
+ Ret = SbiCall (ExtensionId, FunctionId, NumArgs, VA_ARG (Args, UINTN),
+ VA_ARG (Args, UINTN), VA_ARG (Args, UINTN),
+ VA_ARG (Args, UINTN), VA_ARG (Args, UINTN));
+ break;
+ case 6:
+ Ret = SbiCall (ExtensionId, FunctionId, NumArgs, VA_ARG (Args, UINTN),
+ VA_ARG (Args, UINTN), VA_ARG (Args, UINTN),
+ VA_ARG (Args, UINTN), VA_ARG (Args, UINTN),
+ VA_ARG (Args, UINTN));
+ break;
+ default:
+ // Too many args. In theory SBI can handle more arguments when they are
+ // passed on the stack but no SBI extension uses this, therefore it's
+ // not yet implemented here.
+ return EFI_INVALID_PARAMETER;
+ }
+
+ VA_END(Args);
+ return TranslateError (Ret.Error);
+}
+
+//
+// SBI Firmware extension
+//
+
+/**
+ Get scratch space of the current hart.
+
+ Please consider using the wrapper SbiGetFirmwareContext if you only need to
+ access the firmware context.
+
+ @param[out] ScratchSpace The scratch space pointer.
+ @retval EFI_SUCCESS The operation succeeds.
+**/
+EFI_STATUS
+EFIAPI
+SbiGetMscratch (
+ OUT SBI_SCRATCH **ScratchSpace
+ )
+{
+ SbiRet Ret = SbiCall (SBI_EDK2_FW_EXT, SBI_EXT_FW_MSCRATCH_FUNC, 0);
+
+ if (!Ret.Error) {
+ *ScratchSpace = (SBI_SCRATCH *)Ret.Value;
+ }
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Get scratch space of the given hart id.
+
+ @param[in] HartId The hart id.
+ @param[out] ScratchSpace The scratch space pointer.
+ @retval EFI_SUCCESS The operation succeeds.
+**/
+EFI_STATUS
+EFIAPI
+SbiGetMscratchHartid (
+ IN UINTN HartId,
+ OUT SBI_SCRATCH **ScratchSpace
+ )
+{
+ SbiRet Ret = SbiCall (
+ SBI_EDK2_FW_EXT,
+ SBI_EXT_FW_MSCRATCH_HARTID_FUNC,
+ 1,
+ HartId
+ );
+
+ if (!Ret.Error) {
+ *ScratchSpace = (SBI_SCRATCH *)Ret.Value;
+ }
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Get firmware context of the calling hart.
+
+ @param[out] FirmwareContext The firmware context pointer.
+ @retval EFI_SUCCESS The operation succeeds.
+**/
+EFI_STATUS
+EFIAPI
+SbiGetFirmwareContext (
+ OUT EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT **FirmwareContext
+ )
+{
+ SBI_SCRATCH *ScratchSpace;
+ SBI_PLATFORM *SbiPlatform;
+ SbiRet Ret = SbiCall (SBI_EDK2_FW_EXT, SBI_EXT_FW_MSCRATCH_FUNC, 0);
+
+ if (!Ret.Error) {
+ ScratchSpace = (SBI_SCRATCH *)Ret.Value;
+ SbiPlatform = (SBI_PLATFORM *)sbi_platform_ptr(ScratchSpace);
+ *FirmwareContext = (EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *)SbiPlatform->firmware_context;
+ }
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Set firmware context of the calling hart.
+
+ @param[in] FirmwareContext The firmware context pointer.
+ @retval EFI_SUCCESS The operation succeeds.
+**/
+EFI_STATUS
+EFIAPI
+SbiSetFirmwareContext (
+ IN EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *FirmwareContext
+ )
+{
+ SBI_SCRATCH *ScratchSpace;
+ SBI_PLATFORM *SbiPlatform;
+ SbiRet Ret = SbiCall (SBI_EDK2_FW_EXT, SBI_EXT_FW_MSCRATCH_FUNC, 0);
+
+ if (!Ret.Error) {
+ ScratchSpace = (SBI_SCRATCH *)Ret.Value;
+ SbiPlatform = (SBI_PLATFORM *)sbi_platform_ptr (ScratchSpace);
+ SbiPlatform->firmware_context = (UINTN)FirmwareContext;
+ }
+
+ return EFI_SUCCESS;
+}
--
2.31.1
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH 08/79] ProcessorPkg/Library: RISC-V PEI Service Table Pointer library
2022-01-08 4:10 [PATCH 02/79] ProcessorPkg/Library: RISC-V CPU library Abner Chang
` (4 preceding siblings ...)
2022-01-08 4:10 ` [PATCH 07/79] ProcessorPkg/Library: Add RiscVEdk2SbiLib Abner Chang
@ 2022-01-08 4:10 ` Abner Chang
2022-01-08 4:10 ` [PATCH 09/79] ProcessorPkg/CpuDxe: Add RISC-V CPU DXE driver Abner Chang
` (31 subsequent siblings)
37 siblings, 0 replies; 39+ messages in thread
From: Abner Chang @ 2022-01-08 4:10 UTC (permalink / raw)
To: devel; +Cc: abner.chang
(This is migrated from edk2-platforms:Silicon/RISC-V)
Implementation of RISC-V PEI Service Table Pointer library using
RISC-V OpenSbi.
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Co-authored-by: Daniel Schaefer <daniel.schaefer@hpe.com>
Co-authored-by: Gilbert Chen <gilbert.chen@hpe.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>
---
.../PeiServicesTablePointerLibOpenSbi.inf | 39 ++++++
.../PeiServicesTablePointerOpenSbi.c | 117 ++++++++++++++++++
.../PeiServicesTablePointerLibOpenSbi.uni | 23 ++++
3 files changed, 179 insertions(+)
create mode 100644 Silicon/RISC-V/ProcessorPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerLibOpenSbi.inf
create mode 100644 Silicon/RISC-V/ProcessorPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerOpenSbi.c
create mode 100644 Silicon/RISC-V/ProcessorPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerLibOpenSbi.uni
diff --git a/Silicon/RISC-V/ProcessorPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerLibOpenSbi.inf b/Silicon/RISC-V/ProcessorPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerLibOpenSbi.inf
new file mode 100644
index 0000000000..f23272016b
--- /dev/null
+++ b/Silicon/RISC-V/ProcessorPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerLibOpenSbi.inf
@@ -0,0 +1,39 @@
+## @file
+# Instance of PEI Services Table Pointer Library using RISC-V OpenSBI FirmwareContext.
+#
+# PEI Services Table Pointer Library implementation that retrieves a pointer to the
+# PEI Services Table from a RISC-V OpenSBI sbi_platform firmware context structure.
+#
+# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001b
+ BASE_NAME = PeiServicesTablePointerLibOpenSbi
+ MODULE_UNI_FILE = PeiServicesTablePointerLibOpenSbi.uni
+ FILE_GUID = B4054E46-FE75-4290-B442-4836B1265D8F
+ MODULE_TYPE = PEIM
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = PeiServicesTablePointerLib|PEIM PEI_CORE
+
+ CONSTRUCTOR = PeiServicesTablePointerLibOpenSbiConstructor
+
+#
+# VALID_ARCHITECTURES = RISCV64
+#
+
+[Sources]
+ PeiServicesTablePointerOpenSbi.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec
+
+[LibraryClasses]
+ DebugLib
+ RiscVCpuLib
+ RiscVEdk2SbiLib
+
diff --git a/Silicon/RISC-V/ProcessorPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerOpenSbi.c b/Silicon/RISC-V/ProcessorPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerOpenSbi.c
new file mode 100644
index 0000000000..0c1473e932
--- /dev/null
+++ b/Silicon/RISC-V/ProcessorPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerOpenSbi.c
@@ -0,0 +1,117 @@
+/** @file
+ PEI Services Table Pointer Library.
+
+ Copyright (c) 2019 - 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <PiPei.h>
+#include <Library/DebugLib.h>
+#include <Library/RiscVCpuLib.h>
+#include <Library/RiscVEdk2SbiLib.h>
+#include <Library/PeiServicesTablePointerLib.h>
+#include <sbi/sbi_scratch.h>
+#include <sbi/sbi_platform.h>
+
+/**
+ Caches a pointer PEI Services Table.
+
+ Caches the pointer to the PEI Services Table specified by PeiServicesTablePointer
+ in a CPU specific manner as specified in the CPU binding section of the Platform Initialization
+ Pre-EFI Initialization Core Interface Specification.
+
+ If PeiServicesTablePointer is NULL, then ASSERT().
+
+ @param PeiServicesTablePointer The address of PeiServices pointer.
+**/
+VOID
+EFIAPI
+SetPeiServicesTablePointer (
+ IN CONST EFI_PEI_SERVICES ** PeiServicesTablePointer
+ )
+{
+ EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *FirmwareContext;
+ SbiGetFirmwareContext (&FirmwareContext);
+
+ FirmwareContext->PeiServiceTable = (VOID *)(UINTN)PeiServicesTablePointer;
+
+ DEBUG ((DEBUG_INFO, "Set PEI Service 0x%x at OpenSBI Firmware Context at 0x%x\n",
+ PeiServicesTablePointer,
+ FirmwareContext
+ ));
+}
+
+/**
+ Retrieves the cached value of the PEI Services Table pointer.
+
+ Returns the cached value of the PEI Services Table pointer in a CPU specific manner
+ as specified in the CPU binding section of the Platform Initialization Pre-EFI
+ Initialization Core Interface Specification.
+
+ If the cached PEI Services Table pointer is NULL, then ASSERT().
+
+ @return The pointer to PeiServices.
+
+**/
+CONST EFI_PEI_SERVICES **
+EFIAPI
+GetPeiServicesTablePointer (
+ VOID
+ )
+{
+ EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *FirmwareContext;
+ SbiGetFirmwareContext (&FirmwareContext);
+
+ return (CONST EFI_PEI_SERVICES **)FirmwareContext->PeiServiceTable;
+}
+
+/**
+ The constructor function caches the pointer to PEI services.
+
+ The constructor function caches the pointer to PEI services.
+ It will always return EFI_SUCCESS.
+
+ @param FileHandle The handle of FFS header the loaded driver.
+ @param PeiServices The pointer to the PEI services.
+
+ @retval EFI_SUCCESS The constructor always returns EFI_SUCCESS.
+
+**/
+EFI_STATUS
+EFIAPI
+PeiServicesTablePointerLibOpenSbiConstructor (
+ IN EFI_PEI_FILE_HANDLE FileHandle,
+ IN CONST EFI_PEI_SERVICES **PeiServices
+ )
+{
+ SetPeiServicesTablePointer (PeiServices);
+ return EFI_SUCCESS;
+}
+
+/**
+ Perform CPU specific actions required to migrate the PEI Services Table
+ pointer from temporary RAM to permanent RAM.
+
+ For IA32 CPUs, the PEI Services Table pointer is stored in the 4 bytes
+ immediately preceding the Interrupt Descriptor Table (IDT) in memory.
+ For X64 CPUs, the PEI Services Table pointer is stored in the 8 bytes
+ immediately preceding the Interrupt Descriptor Table (IDT) in memory.
+ For Itanium, ARM or RISC-V CPUs, a the PEI Services Table Pointer is stored in
+ a dedicated CPU register. This means that there is no memory storage
+ associated with storing the PEI Services Table pointer, so no additional
+ migration actions are required for Itanium, ARM or RISC-V CPUs.
+
+**/
+VOID
+EFIAPI
+MigratePeiServicesTablePointer (
+ VOID
+ )
+{
+ //
+ // PEI Services Table pointer is cached in the global variable. No additional
+ // migration actions are required.
+ //
+ return;
+}
diff --git a/Silicon/RISC-V/ProcessorPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerLibOpenSbi.uni b/Silicon/RISC-V/ProcessorPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerLibOpenSbi.uni
new file mode 100644
index 0000000000..f6fad8bcb5
--- /dev/null
+++ b/Silicon/RISC-V/ProcessorPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerLibOpenSbi.uni
@@ -0,0 +1,23 @@
+// /** @file
+//
+// Instance of PEI Services Table Pointer Library using RISC-V OpenSBI FirmwareContext.
+//
+// PEI Services Table Pointer Library implementation that retrieves a pointer to the
+// PEI Services Table from a RISC-V OpenSBI sbi_platform firmware context structure.
+//
+// Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+//
+// This program and the accompanying materials
+// are licensed and made available under the terms and conditions of the BSD License
+// which accompanies this distribution. The full text of the license may be found at
+// http://opensource.org/licenses/bsd-license.php.
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+// **/
+
+
+#string STR_MODULE_ABSTRACT #language en-US "Instance of PEI Services Table Pointer Library using global variable for the table pointer"
+
+#string STR_MODULE_DESCRIPTION #language en-US "The PEI Services Table Pointer Library implementation that retrieves a pointer to the PEI Services Table from a global variable. Not available to modules that execute from read-only memory."
+
--
2.31.1
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH 09/79] ProcessorPkg/CpuDxe: Add RISC-V CPU DXE driver.
2022-01-08 4:10 [PATCH 02/79] ProcessorPkg/Library: RISC-V CPU library Abner Chang
` (5 preceding siblings ...)
2022-01-08 4:10 ` [PATCH 08/79] ProcessorPkg/Library: RISC-V PEI Service Table Pointer library Abner Chang
@ 2022-01-08 4:10 ` Abner Chang
2022-01-08 4:10 ` [PATCH 10/79] ProcessorPkg/SmbiosDxe: Generic SMBIOS DXE driver for RISC-V platforms Abner Chang
` (30 subsequent siblings)
37 siblings, 0 replies; 39+ messages in thread
From: Abner Chang @ 2022-01-08 4:10 UTC (permalink / raw)
To: devel; +Cc: abner.chang
(This is migrated from edk2-platforms:Silicon/RISC-V)
The driver produces RISC-V EFI_CPU_ARCH_PROTOCOL and use RISC-V
platform level timer library.
Due to RISC-V timer Control Status Register (CSR) is platform
implementation specific, RISC-V CPU DXE driver invokes platform level
timer library to access to timer CSRs.
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Co-authored-by: Gilbert Chen <gilbert.chen@hpe.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>
---
.../ProcessorPkg/Universal/CpuDxe/CpuDxe.inf | 48 +++
.../ProcessorPkg/Universal/CpuDxe/CpuDxe.h | 199 +++++++++++
.../ProcessorPkg/Universal/CpuDxe/CpuDxe.c | 316 ++++++++++++++++++
.../ProcessorPkg/Universal/CpuDxe/CpuDxe.uni | 13 +
| 14 +
5 files changed, 590 insertions(+)
create mode 100644 Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxe.inf
create mode 100644 Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxe.h
create mode 100644 Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxe.c
create mode 100644 Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxe.uni
create mode 100644 Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxeExtra.uni
diff --git a/Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxe.inf b/Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxe.inf
new file mode 100644
index 0000000000..29cc4413bd
--- /dev/null
+++ b/Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxe.inf
@@ -0,0 +1,48 @@
+## @file
+# RISC-V CPU DXE module.
+#
+# Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001b
+ BASE_NAME = CpuDxe
+ MODULE_UNI_FILE = CpuDxe.uni
+ FILE_GUID = 2AEB1f3E-5B6B-441B-92C1-4A9E6FC85E92
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+
+ ENTRY_POINT = InitializeCpu
+
+[Packages]
+ MdeModulePkg/MdeModulePkg.dec
+ MdePkg/MdePkg.dec
+ Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec
+
+[LibraryClasses]
+ BaseLib
+ CpuLib
+ CpuExceptionHandlerLib
+ DebugLib
+ RiscVCpuLib
+ TimerLib
+ UefiBootServicesTableLib
+ UefiDriverEntryPoint
+
+[Sources]
+ CpuDxe.c
+ CpuDxe.h
+
+[Protocols]
+ gEfiCpuArchProtocolGuid ## PRODUCES
+
+[Pcd]
+ gUefiRiscVPkgTokenSpaceGuid.PcdRiscVMachineTimerFrequencyInHerz
+
+[Depex]
+ TRUE
+
+[UserExtensions.TianoCore."ExtraFiles"]
+ CpuDxeExtra.uni
diff --git a/Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxe.h b/Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxe.h
new file mode 100644
index 0000000000..c2c2739434
--- /dev/null
+++ b/Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxe.h
@@ -0,0 +1,199 @@
+/** @file
+ RISC-V CPU DXE module header file.
+
+ Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef CPU_DXE_H_
+#define CPU_DXE_H_
+
+#include <PiDxe.h>
+
+#include <Protocol/Cpu.h>
+#include <Library/BaseLib.h>
+#include <Library/CpuExceptionHandlerLib.h>
+#include <Library/DebugLib.h>
+#include <Library/RiscVCpuLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiDriverEntryPoint.h>
+
+/**
+ Flush CPU data cache. If the instruction cache is fully coherent
+ with all DMA operations then function can just return EFI_SUCCESS.
+
+ @param This Protocol instance structure
+ @param Start Physical address to start flushing from.
+ @param Length Number of bytes to flush. Round up to chipset
+ granularity.
+ @param FlushType Specifies the type of flush operation to perform.
+
+ @retval EFI_SUCCESS If cache was flushed
+ @retval EFI_UNSUPPORTED If flush type is not supported.
+ @retval EFI_DEVICE_ERROR If requested range could not be flushed.
+
+**/
+EFI_STATUS
+EFIAPI
+CpuFlushCpuDataCache (
+ IN EFI_CPU_ARCH_PROTOCOL *This,
+ IN EFI_PHYSICAL_ADDRESS Start,
+ IN UINT64 Length,
+ IN EFI_CPU_FLUSH_TYPE FlushType
+ );
+
+/**
+ Enables CPU interrupts.
+
+ @param This Protocol instance structure
+
+ @retval EFI_SUCCESS If interrupts were enabled in the CPU
+ @retval EFI_DEVICE_ERROR If interrupts could not be enabled on the CPU.
+
+**/
+EFI_STATUS
+EFIAPI
+CpuEnableInterrupt (
+ IN EFI_CPU_ARCH_PROTOCOL *This
+ );
+
+/**
+ Disables CPU interrupts.
+
+ @param This Protocol instance structure
+
+ @retval EFI_SUCCESS If interrupts were disabled in the CPU.
+ @retval EFI_DEVICE_ERROR If interrupts could not be disabled on the CPU.
+
+**/
+EFI_STATUS
+EFIAPI
+CpuDisableInterrupt (
+ IN EFI_CPU_ARCH_PROTOCOL *This
+ );
+
+/**
+ Return the state of interrupts.
+
+ @param This Protocol instance structure
+ @param State Pointer to the CPU's current interrupt state
+
+ @retval EFI_SUCCESS If interrupts were disabled in the CPU.
+ @retval EFI_INVALID_PARAMETER State is NULL.
+
+**/
+EFI_STATUS
+EFIAPI
+CpuGetInterruptState (
+ IN EFI_CPU_ARCH_PROTOCOL *This,
+ OUT BOOLEAN *State
+ );
+
+/**
+ Generates an INIT to the CPU.
+
+ @param This Protocol instance structure
+ @param InitType Type of CPU INIT to perform
+
+ @retval EFI_SUCCESS If CPU INIT occurred. This value should never be
+ seen.
+ @retval EFI_DEVICE_ERROR If CPU INIT failed.
+ @retval EFI_UNSUPPORTED Requested type of CPU INIT not supported.
+
+**/
+EFI_STATUS
+EFIAPI
+CpuInit (
+ IN EFI_CPU_ARCH_PROTOCOL *This,
+ IN EFI_CPU_INIT_TYPE InitType
+ );
+
+/**
+ Registers a function to be called from the CPU interrupt handler.
+
+ @param This Protocol instance structure
+ @param InterruptType Defines which interrupt to hook. IA-32
+ valid range is 0x00 through 0xFF
+ @param InterruptHandler A pointer to a function of type
+ EFI_CPU_INTERRUPT_HANDLER that is called
+ when a processor interrupt occurs. A null
+ pointer is an error condition.
+
+ @retval EFI_SUCCESS If handler installed or uninstalled.
+ @retval EFI_ALREADY_STARTED InterruptHandler is not NULL, and a handler
+ for InterruptType was previously installed.
+ @retval EFI_INVALID_PARAMETER InterruptHandler is NULL, and a handler for
+ InterruptType was not previously installed.
+ @retval EFI_UNSUPPORTED The interrupt specified by InterruptType
+ is not supported.
+
+**/
+EFI_STATUS
+EFIAPI
+CpuRegisterInterruptHandler (
+ IN EFI_CPU_ARCH_PROTOCOL *This,
+ IN EFI_EXCEPTION_TYPE InterruptType,
+ IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler
+ );
+
+/**
+ Returns a timer value from one of the CPU's internal timers. There is no
+ inherent time interval between ticks but is a function of the CPU frequency.
+
+ @param This - Protocol instance structure.
+ @param TimerIndex - Specifies which CPU timer is requested.
+ @param TimerValue - Pointer to the returned timer value.
+ @param TimerPeriod - A pointer to the amount of time that passes
+ in femtoseconds (10-15) for each increment
+ of TimerValue. If TimerValue does not
+ increment at a predictable rate, then 0 is
+ returned. The amount of time that has
+ passed between two calls to GetTimerValue()
+ can be calculated with the formula
+ (TimerValue2 - TimerValue1) * TimerPeriod.
+ This parameter is optional and may be NULL.
+
+ @retval EFI_SUCCESS - If the CPU timer count was returned.
+ @retval EFI_UNSUPPORTED - If the CPU does not have any readable timers.
+ @retval EFI_DEVICE_ERROR - If an error occurred while reading the timer.
+ @retval EFI_INVALID_PARAMETER - TimerIndex is not valid or TimerValue is NULL.
+
+**/
+EFI_STATUS
+EFIAPI
+CpuGetTimerValue (
+ IN EFI_CPU_ARCH_PROTOCOL *This,
+ IN UINT32 TimerIndex,
+ OUT UINT64 *TimerValue,
+ OUT UINT64 *TimerPeriod OPTIONAL
+ );
+
+/**
+ Set memory cacheability attributes for given range of memeory.
+
+ @param This Protocol instance structure
+ @param BaseAddress Specifies the start address of the
+ memory range
+ @param Length Specifies the length of the memory range
+ @param Attributes The memory cacheability for the memory range
+
+ @retval EFI_SUCCESS If the cacheability of that memory range is
+ set successfully
+ @retval EFI_UNSUPPORTED If the desired operation cannot be done
+ @retval EFI_INVALID_PARAMETER The input parameter is not correct,
+ such as Length = 0
+
+**/
+EFI_STATUS
+EFIAPI
+CpuSetMemoryAttributes (
+ IN EFI_CPU_ARCH_PROTOCOL *This,
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ IN UINT64 Length,
+ IN UINT64 Attributes
+ );
+
+#endif
+
diff --git a/Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxe.c b/Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxe.c
new file mode 100644
index 0000000000..27a07b1561
--- /dev/null
+++ b/Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxe.c
@@ -0,0 +1,316 @@
+/** @file
+ RISC-V CPU DXE driver.
+
+ Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "CpuDxe.h"
+
+//
+// Global Variables
+//
+STATIC BOOLEAN mInterruptState = FALSE;
+STATIC EFI_HANDLE mCpuHandle = NULL;
+
+EFI_CPU_ARCH_PROTOCOL gCpu = {
+ CpuFlushCpuDataCache,
+ CpuEnableInterrupt,
+ CpuDisableInterrupt,
+ CpuGetInterruptState,
+ CpuInit,
+ CpuRegisterInterruptHandler,
+ CpuGetTimerValue,
+ CpuSetMemoryAttributes,
+ 1, // NumberOfTimers
+ 4 // DmaBufferAlignment
+};
+
+//
+// CPU Arch Protocol Functions
+//
+
+/**
+ Flush CPU data cache. If the instruction cache is fully coherent
+ with all DMA operations then function can just return EFI_SUCCESS.
+
+ @param This Protocol instance structure
+ @param Start Physical address to start flushing from.
+ @param Length Number of bytes to flush. Round up to chipset
+ granularity.
+ @param FlushType Specifies the type of flush operation to perform.
+
+ @retval EFI_SUCCESS If cache was flushed
+ @retval EFI_UNSUPPORTED If flush type is not supported.
+ @retval EFI_DEVICE_ERROR If requested range could not be flushed.
+
+**/
+EFI_STATUS
+EFIAPI
+CpuFlushCpuDataCache (
+ IN EFI_CPU_ARCH_PROTOCOL *This,
+ IN EFI_PHYSICAL_ADDRESS Start,
+ IN UINT64 Length,
+ IN EFI_CPU_FLUSH_TYPE FlushType
+ )
+{
+ return EFI_SUCCESS;
+}
+
+
+/**
+ Enables CPU interrupts.
+
+ @param This Protocol instance structure
+
+ @retval EFI_SUCCESS If interrupts were enabled in the CPU
+ @retval EFI_DEVICE_ERROR If interrupts could not be enabled on the CPU.
+
+**/
+EFI_STATUS
+EFIAPI
+CpuEnableInterrupt (
+ IN EFI_CPU_ARCH_PROTOCOL *This
+ )
+{
+ EnableInterrupts ();
+ mInterruptState = TRUE;
+ return EFI_SUCCESS;
+}
+
+
+/**
+ Disables CPU interrupts.
+
+ @param This Protocol instance structure
+
+ @retval EFI_SUCCESS If interrupts were disabled in the CPU.
+ @retval EFI_DEVICE_ERROR If interrupts could not be disabled on the CPU.
+
+**/
+EFI_STATUS
+EFIAPI
+CpuDisableInterrupt (
+ IN EFI_CPU_ARCH_PROTOCOL *This
+ )
+{
+ DisableInterrupts ();
+ mInterruptState = FALSE;
+ return EFI_SUCCESS;
+}
+
+
+/**
+ Return the state of interrupts.
+
+ @param This Protocol instance structure
+ @param State Pointer to the CPU's current interrupt state
+
+ @retval EFI_SUCCESS If interrupts were disabled in the CPU.
+ @retval EFI_INVALID_PARAMETER State is NULL.
+
+**/
+EFI_STATUS
+EFIAPI
+CpuGetInterruptState (
+ IN EFI_CPU_ARCH_PROTOCOL *This,
+ OUT BOOLEAN *State
+ )
+{
+ if (State == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ *State = mInterruptState;
+ return EFI_SUCCESS;
+}
+
+
+/**
+ Generates an INIT to the CPU.
+
+ @param This Protocol instance structure
+ @param InitType Type of CPU INIT to perform
+
+ @retval EFI_SUCCESS If CPU INIT occurred. This value should never be
+ seen.
+ @retval EFI_DEVICE_ERROR If CPU INIT failed.
+ @retval EFI_UNSUPPORTED Requested type of CPU INIT not supported.
+
+**/
+EFI_STATUS
+EFIAPI
+CpuInit (
+ IN EFI_CPU_ARCH_PROTOCOL *This,
+ IN EFI_CPU_INIT_TYPE InitType
+ )
+{
+ return EFI_UNSUPPORTED;
+}
+
+
+/**
+ Registers a function to be called from the CPU interrupt handler.
+
+ @param This Protocol instance structure
+ @param InterruptType Defines which interrupt to hook. IA-32
+ valid range is 0x00 through 0xFF
+ @param InterruptHandler A pointer to a function of type
+ EFI_CPU_INTERRUPT_HANDLER that is called
+ when a processor interrupt occurs. A null
+ pointer is an error condition.
+
+ @retval EFI_SUCCESS If handler installed or uninstalled.
+ @retval EFI_ALREADY_STARTED InterruptHandler is not NULL, and a handler
+ for InterruptType was previously installed.
+ @retval EFI_INVALID_PARAMETER InterruptHandler is NULL, and a handler for
+ InterruptType was not previously installed.
+ @retval EFI_UNSUPPORTED The interrupt specified by InterruptType
+ is not supported.
+
+**/
+EFI_STATUS
+EFIAPI
+CpuRegisterInterruptHandler (
+ IN EFI_CPU_ARCH_PROTOCOL *This,
+ IN EFI_EXCEPTION_TYPE InterruptType,
+ IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler
+ )
+{
+ return RegisterCpuInterruptHandler (InterruptType, InterruptHandler);
+}
+
+
+/**
+ Returns a timer value from one of the CPU's internal timers. There is no
+ inherent time interval between ticks but is a function of the CPU frequency.
+
+ @param This - Protocol instance structure.
+ @param TimerIndex - Specifies which CPU timer is requested.
+ @param TimerValue - Pointer to the returned timer value.
+ @param TimerPeriod - A pointer to the amount of time that passes
+ in femtoseconds (10-15) for each increment
+ of TimerValue. If TimerValue does not
+ increment at a predictable rate, then 0 is
+ returned. The amount of time that has
+ passed between two calls to GetTimerValue()
+ can be calculated with the formula
+ (TimerValue2 - TimerValue1) * TimerPeriod.
+ This parameter is optional and may be NULL.
+
+ @retval EFI_SUCCESS - If the CPU timer count was returned.
+ @retval EFI_UNSUPPORTED - If the CPU does not have any readable timers.
+ @retval EFI_DEVICE_ERROR - If an error occurred while reading the timer.
+ @retval EFI_INVALID_PARAMETER - TimerIndex is not valid or TimerValue is NULL.
+
+**/
+EFI_STATUS
+EFIAPI
+CpuGetTimerValue (
+ IN EFI_CPU_ARCH_PROTOCOL *This,
+ IN UINT32 TimerIndex,
+ OUT UINT64 *TimerValue,
+ OUT UINT64 *TimerPeriod OPTIONAL
+ )
+{
+ if (TimerValue == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ if (TimerIndex != 0) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ *TimerValue = (UINT64)RiscVReadMachineTimer ();
+ if (TimerPeriod != NULL) {
+ *TimerPeriod = DivU64x32 (
+ 1000000000000000u,
+ PcdGet64 (PcdRiscVMachineTimerFrequencyInHerz)
+ );
+ }
+ return EFI_SUCCESS;
+}
+
+
+/**
+ Implementation of SetMemoryAttributes() service of CPU Architecture Protocol.
+
+ This function modifies the attributes for the memory region specified by BaseAddress and
+ Length from their current attributes to the attributes specified by Attributes.
+
+ @param This The EFI_CPU_ARCH_PROTOCOL instance.
+ @param BaseAddress The physical address that is the start address of a memory region.
+ @param Length The size in bytes of the memory region.
+ @param Attributes The bit mask of attributes to set for the memory region.
+
+ @retval EFI_SUCCESS The attributes were set for the memory region.
+ @retval EFI_ACCESS_DENIED The attributes for the memory resource range specified by
+ BaseAddress and Length cannot be modified.
+ @retval EFI_INVALID_PARAMETER Length is zero.
+ Attributes specified an illegal combination of attributes that
+ cannot be set together.
+ @retval EFI_OUT_OF_RESOURCES There are not enough system resources to modify the attributes of
+ the memory resource range.
+ @retval EFI_UNSUPPORTED The processor does not support one or more bytes of the memory
+ resource range specified by BaseAddress and Length.
+ The bit mask of attributes is not support for the memory resource
+ range specified by BaseAddress and Length.
+
+**/
+EFI_STATUS
+EFIAPI
+CpuSetMemoryAttributes (
+ IN EFI_CPU_ARCH_PROTOCOL *This,
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ IN UINT64 Length,
+ IN UINT64 Attributes
+ )
+{
+ DEBUG ((DEBUG_INFO, "%a: Set memory attributes not supported yet\n", __FUNCTION__));
+ return EFI_UNSUPPORTED;
+}
+
+/**
+ Initialize the state information for the CPU Architectural Protocol.
+
+ @param ImageHandle Image handle this driver.
+ @param SystemTable Pointer to the System Table.
+
+ @retval EFI_SUCCESS Thread can be successfully created
+ @retval EFI_OUT_OF_RESOURCES Cannot allocate protocol data structure
+ @retval EFI_DEVICE_ERROR Cannot create the thread
+
+**/
+EFI_STATUS
+EFIAPI
+InitializeCpu (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+
+ //
+ // Machine mode handler is initiated in CpuExceptionHandlerLibConstructor in
+ // CpuExecptionHandlerLib.
+ //
+
+ //
+ // Make sure interrupts are disabled
+ //
+ DisableInterrupts ();
+
+ //
+ // Install CPU Architectural Protocol
+ //
+ Status = gBS->InstallMultipleProtocolInterfaces (
+ &mCpuHandle,
+ &gEfiCpuArchProtocolGuid, &gCpu,
+ NULL
+ );
+ ASSERT_EFI_ERROR (Status);
+ return Status;
+}
+
diff --git a/Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxe.uni b/Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxe.uni
new file mode 100644
index 0000000000..460141a1aa
--- /dev/null
+++ b/Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxe.uni
@@ -0,0 +1,13 @@
+// /** @file
+//
+// Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+//
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+// **/
+
+
+#string STR_MODULE_ABSTRACT #language en-US "Installs RISC-V CPU Architecture Protocol"
+
+#string STR_MODULE_DESCRIPTION #language en-US "RISC-V CPU driver installs CPU Architecture Protocol."
+
--git a/Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxeExtra.uni b/Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxeExtra.uni
new file mode 100644
index 0000000000..6f819f068e
--- /dev/null
+++ b/Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxeExtra.uni
@@ -0,0 +1,14 @@
+// /** @file
+// CpuDxe Localized Strings and Content
+//
+// Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+//
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+// **/
+
+#string STR_PROPERTIES_MODULE_NAME
+#language en-US
+"RISC-V Architectural DXE Driver"
+
+
--
2.31.1
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH 10/79] ProcessorPkg/SmbiosDxe: Generic SMBIOS DXE driver for RISC-V platforms.
2022-01-08 4:10 [PATCH 02/79] ProcessorPkg/Library: RISC-V CPU library Abner Chang
` (6 preceding siblings ...)
2022-01-08 4:10 ` [PATCH 09/79] ProcessorPkg/CpuDxe: Add RISC-V CPU DXE driver Abner Chang
@ 2022-01-08 4:10 ` Abner Chang
2022-01-08 4:10 ` [PATCH 11/79] ProcesorPkg/Library: NULL instance of RISC-V platform timer library Abner Chang
` (29 subsequent siblings)
37 siblings, 0 replies; 39+ messages in thread
From: Abner Chang @ 2022-01-08 4:10 UTC (permalink / raw)
To: devel; +Cc: abner.chang
(This is migrated from edk2-platforms:Silicon/RISC-V)
RISC-V generic SMBIOS DXE driver for building up SMBIOS type 4, type 7
and type 44 records.
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Co-authored-by: Gilbert Chen <gilbert.chen@hpe.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>
---
.../Universal/SmbiosDxe/RiscVSmbiosDxe.inf | 55 +++
.../Include/ProcessorSpecificHobData.h | 96 +++++
.../Include/SmbiosProcessorSpecificData.h | 57 +++
.../Universal/SmbiosDxe/RiscVSmbiosDxe.h | 23 ++
.../Universal/SmbiosDxe/RiscVSmbiosDxe.c | 327 ++++++++++++++++++
.../Universal/SmbiosDxe/RiscVSmbiosDxe.uni | 12 +
| 13 +
7 files changed, 583 insertions(+)
create mode 100644 Silicon/RISC-V/ProcessorPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.inf
create mode 100644 Silicon/RISC-V/ProcessorPkg/Include/ProcessorSpecificHobData.h
create mode 100644 Silicon/RISC-V/ProcessorPkg/Include/SmbiosProcessorSpecificData.h
create mode 100644 Silicon/RISC-V/ProcessorPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.h
create mode 100644 Silicon/RISC-V/ProcessorPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.c
create mode 100644 Silicon/RISC-V/ProcessorPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.uni
create mode 100644 Silicon/RISC-V/ProcessorPkg/Universal/SmbiosDxe/RiscVSmbiosDxeExtra.uni
diff --git a/Silicon/RISC-V/ProcessorPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.inf b/Silicon/RISC-V/ProcessorPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.inf
new file mode 100644
index 0000000000..0fcfe1d3ad
--- /dev/null
+++ b/Silicon/RISC-V/ProcessorPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.inf
@@ -0,0 +1,55 @@
+## @file
+# RISC-V SMBIOS DXE module.
+#
+# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001b
+ BASE_NAME = RiscVSmbiosDxe
+ MODULE_UNI_FILE = RiscVSmbiosDxe.uni
+ FILE_GUID = 5FC01647-AADD-42E1-AD99-DF4CB89F5A92
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ ENTRY_POINT = RiscVSmbiosBuilderEntry
+
+[Packages]
+ MdeModulePkg/MdeModulePkg.dec
+ MdePkg/MdePkg.dec
+ Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec
+
+[LibraryClasses]
+ BaseLib
+ BaseMemoryLib
+ DebugLib
+ HobLib
+ MemoryAllocationLib
+ UefiBootServicesTableLib
+ UefiDriverEntryPoint
+
+[Sources]
+ RiscVSmbiosDxe.c
+ RiscVSmbiosDxe.h
+
+[Protocols]
+ gEfiSmbiosProtocolGuid # Consumed
+
+[Guids]
+
+
+[Pcd]
+
+[FixedPcd]
+ gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSmbiosGuidHobGuid
+ gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSmbiosType4GuidHobGuid
+ gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSmbiosType7GuidHobGuid
+ gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSpecificDataGuidHobGuid
+
+[Depex]
+ gEfiSmbiosProtocolGuid
+
+[UserExtensions.TianoCore."ExtraFiles"]
+ RiscVSmbiosDxeExtra.uni
diff --git a/Silicon/RISC-V/ProcessorPkg/Include/ProcessorSpecificHobData.h b/Silicon/RISC-V/ProcessorPkg/Include/ProcessorSpecificHobData.h
new file mode 100644
index 0000000000..2f5847e53e
--- /dev/null
+++ b/Silicon/RISC-V/ProcessorPkg/Include/ProcessorSpecificHobData.h
@@ -0,0 +1,96 @@
+/** @file
+ Definition of Processor Specific Data HOB.
+
+ Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+#ifndef RISC_V_PROCESSOR_SPECIFIC_HOB_DATA_H_
+#define RISC_V_PROCESSOR_SPECIFIC_HOB_DATA_H_
+
+#include <Uefi.h>
+#include <IndustryStandard/SmBios.h>
+#include <SmbiosProcessorSpecificData.h>
+
+#define TO_BE_FILLED 0
+#define TO_BE_FILLED_BY_VENDOR 0
+#define TO_BE_FILLED_BY_RISC_V_SMBIOS_DXE_DRIVER 0
+#define TO_BE_FILLED_BY_CODE 0
+
+#pragma pack(1)
+
+///
+/// RISC-V processor specific data HOB
+///
+typedef struct {
+ EFI_GUID ParentPrcessorGuid;
+ UINTN ParentProcessorUid;
+ EFI_GUID CoreGuid;
+ VOID *Context; // The additional information of this core which
+ // built in PEI phase and carried to DXE phase.
+ // The content is pocessor or platform specific.
+ SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA ProcessorSpecificData;
+} RISC_V_PROCESSOR_SPECIFIC_HOB_DATA;
+
+///
+/// RISC-V SMBIOS type 4 (Processor) GUID data HOB
+///
+typedef struct {
+ EFI_GUID PrcessorGuid;
+ UINTN ProcessorUid;
+ SMBIOS_TABLE_TYPE4 SmbiosType4Processor;
+ UINT16 EndingZero;
+} RISC_V_PROCESSOR_TYPE4_HOB_DATA;
+
+#define RISC_V_CACHE_INFO_NOT_PROVIDED 0xFFFF
+
+#define RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_MASK 0x7
+ #define RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_1 0x01
+ #define RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_2 0x02
+ #define RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_3 0x03
+
+#define RISC_V_CACHE_CONFIGURATION_SOCKET_BIT_POSITION 3
+#define RISC_V_CACHE_CONFIGURATION_SOCKET_MASK (0x1 << RISC_V_CACHE_CONFIGURATION_SOCKET_BIT_POSITION)
+ #define RISC_V_CACHE_CONFIGURATION_SOCKET_SOCKETED (0x1 << RISC_V_CACHE_CONFIGURATION_SOCKET_BIT_POSITION)
+
+#define RISC_V_CACHE_CONFIGURATION_LOCATION_BIT_POSITION 5
+#define RISC_V_CACHE_CONFIGURATION_LOCATION_MASK (0x3 << RISC_V_CACHE_CONFIGURATION_LOCATION_BIT_POSITION)
+ #define RISC_V_CACHE_CONFIGURATION_LOCATION_INTERNAL (0x0 << RISC_V_CACHE_CONFIGURATION_LOCATION_BIT_POSITION)
+ #define RISC_V_CACHE_CONFIGURATION_LOCATION_EXTERNAL (0x1 << RISC_V_CACHE_CONFIGURATION_LOCATION_BIT_POSITION)
+ #define RISC_V_CACHE_CONFIGURATION_LOCATION_RESERVED (0x2 << RISC_V_CACHE_CONFIGURATION_LOCATION_BIT_POSITION)
+ #define RISC_V_CACHE_CONFIGURATION_LOCATION_UNKNOWN (0x3 << RISC_V_CACHE_CONFIGURATION_LOCATION_BIT_POSITION)
+
+#define RISC_V_CACHE_CONFIGURATION_ENABLE_BIT_POSITION 7
+#define RISC_V_CACHE_CONFIGURATION_ENABLE_MASK (0x1 << RISC_V_CACHE_CONFIGURATION_ENABLE_BIT_POSITION)
+ #define RISC_V_CACHE_CONFIGURATION_ENABLED (0x1 << RISC_V_CACHE_CONFIGURATION_ENABLE_BIT_POSITION)
+
+#define RISC_V_CACHE_CONFIGURATION_MODE_BIT_POSITION 8
+#define RISC_V_CACHE_CONFIGURATION_MODE_MASK (0x3 << RISC_V_CACHE_CONFIGURATION_MODE_BIT_POSITION)
+ #define RISC_V_CACHE_CONFIGURATION_MODE_WT (0x0 << RISC_V_CACHE_CONFIGURATION_MODE_BIT_POSITION)
+ #define RISC_V_CACHE_CONFIGURATION_MODE_WB (0x1 << RISC_V_CACHE_CONFIGURATION_MODE_BIT_POSITION)
+ #define RISC_V_CACHE_CONFIGURATION_MODE_VARIES (0x2 << RISC_V_CACHE_CONFIGURATION_MODE_BIT_POSITION)
+ #define RISC_V_CACHE_CONFIGURATION_MODE_UNKNOWN (0x3 << RISC_V_CACHE_CONFIGURATION_MODE_BIT_POSITION)
+///
+/// RISC-V SMBIOS type 7 (Cache) GUID data HOB
+///
+typedef struct {
+ EFI_GUID PrcessorGuid;
+ UINTN ProcessorUid;
+ SMBIOS_TABLE_TYPE7 SmbiosType7Cache;
+ UINT16 EndingZero;
+} RISC_V_PROCESSOR_TYPE7_HOB_DATA;
+
+///
+/// RISC-V SMBIOS type 7 (Cache) GUID data HOB
+///
+typedef struct {
+ RISC_V_PROCESSOR_TYPE4_HOB_DATA *Processor;
+ RISC_V_PROCESSOR_TYPE7_HOB_DATA *L1Cache;
+ RISC_V_PROCESSOR_TYPE7_HOB_DATA *L2Cache;
+ RISC_V_PROCESSOR_TYPE7_HOB_DATA *L3Cache;
+} RISC_V_PROCESSOR_SMBIOS_HOB_DATA;
+
+#pragma pack()
+
+#endif
diff --git a/Silicon/RISC-V/ProcessorPkg/Include/SmbiosProcessorSpecificData.h b/Silicon/RISC-V/ProcessorPkg/Include/SmbiosProcessorSpecificData.h
new file mode 100644
index 0000000000..81e48cd068
--- /dev/null
+++ b/Silicon/RISC-V/ProcessorPkg/Include/SmbiosProcessorSpecificData.h
@@ -0,0 +1,57 @@
+/** @file
+ Industry Standard Definitions of RISC-V Processor Specific data defined in
+ below link for complaiant with SMBIOS Table Specification v3.3.0.
+ https://github.com/riscv/riscv-smbios
+
+ Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+#ifndef SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA_H_
+#define SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA_H_
+
+#include <IndustryStandard/SmBios.h>
+#include <RiscVImpl.h>
+
+#pragma pack(1)
+
+typedef enum{
+ RegisterUnsupported = 0x00,
+ RegisterLen32 = 0x01,
+ RegisterLen64 = 0x02,
+ RegisterLen128 = 0x03
+} RISC_V_REGISTER_LENGTH;
+
+#define SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA_REVISION 0x100
+
+#define SMBIOS_RISC_V_PSD_MACHINE_MODE_SUPPORTED (0x01 << 0)
+#define SMBIOS_RISC_V_PSD_SUPERVISOR_MODE_SUPPORTED (0x01 << 2)
+#define SMBIOS_RISC_V_PSD_USER_MODE_SUPPORTED (0x01 << 3)
+#define SMBIOS_RISC_V_PSD_DEBUG_MODE_SUPPORTED (0x01 << 7)
+
+///
+/// RISC-V processor specific data for SMBIOS type 44
+///
+typedef struct {
+ UINT16 Revision;
+ UINT8 Length;
+ RISCV_UINT128 HartId;
+ UINT8 BootHartId;
+ RISCV_UINT128 MachineVendorId;
+ RISCV_UINT128 MachineArchId;
+ RISCV_UINT128 MachineImplId;
+ UINT32 InstSetSupported;
+ UINT8 PrivilegeModeSupported;
+ RISCV_UINT128 MModeExcepDelegation;
+ RISCV_UINT128 MModeInterruptDelegation;
+ UINT8 HartXlen;
+ UINT8 MachineModeXlen;
+ UINT8 Reserved;
+ UINT8 SupervisorModeXlen;
+ UINT8 UserModeXlen;
+} SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA;
+
+#pragma pack()
+#endif
+
diff --git a/Silicon/RISC-V/ProcessorPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.h b/Silicon/RISC-V/ProcessorPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.h
new file mode 100644
index 0000000000..1072877ad8
--- /dev/null
+++ b/Silicon/RISC-V/ProcessorPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.h
@@ -0,0 +1,23 @@
+/** @file
+ RISC-V SMBIOS Builder DXE module header file.
+
+ Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef RISC_V_SMBIOS_DXE_H_
+#define RISC_V_SMBIOS_DXE_H_
+
+#include <PiDxe.h>
+#include <Protocol/Smbios.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/HobLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <ProcessorSpecificHobData.h>
+#include <SmbiosProcessorSpecificData.h>
+#endif
+
diff --git a/Silicon/RISC-V/ProcessorPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.c b/Silicon/RISC-V/ProcessorPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.c
new file mode 100644
index 0000000000..6079513a55
--- /dev/null
+++ b/Silicon/RISC-V/ProcessorPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.c
@@ -0,0 +1,327 @@
+/** @file
+ RISC-V generic SMBIOS DXE driver to build up SMBIOS type 4, type 7 and type 44 records.
+
+ Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "RiscVSmbiosDxe.h"
+
+STATIC EFI_SMBIOS_PROTOCOL *mSmbios;
+
+/**
+ This function builds SMBIOS type 7 record according to
+ the given RISC_V_PROCESSOR_TYPE7_HOB_DATA.
+
+ @param Type4HobData Pointer to RISC_V_PROCESSOR_TYPE4_HOB_DATA
+ @param Type7DataHob Pointer to RISC_V_PROCESSOR_TYPE7_HOB_DATA
+ @param SmbiosHandle Pointer to SMBIOS_HANDLE
+
+ @retval EFI_STATUS
+
+**/
+STATIC
+EFI_STATUS
+BuildSmbiosType7 (
+ IN RISC_V_PROCESSOR_TYPE4_HOB_DATA *Type4HobData,
+ IN RISC_V_PROCESSOR_TYPE7_HOB_DATA *Type7DataHob,
+ OUT SMBIOS_HANDLE *SmbiosHandle
+)
+{
+ EFI_STATUS Status;
+ SMBIOS_HANDLE Handle;
+
+ if (!CompareGuid (&Type4HobData->PrcessorGuid, &Type7DataHob->PrcessorGuid) ||
+ Type4HobData->ProcessorUid != Type7DataHob->ProcessorUid) {
+ return EFI_INVALID_PARAMETER;
+ }
+ Handle = SMBIOS_HANDLE_PI_RESERVED;
+ Type7DataHob->SmbiosType7Cache.Hdr.Type = SMBIOS_TYPE_CACHE_INFORMATION;
+ Type7DataHob->SmbiosType7Cache.Hdr.Length = sizeof(SMBIOS_TABLE_TYPE7);
+ Type7DataHob->SmbiosType7Cache.Hdr.Handle = 0;
+ Type7DataHob->EndingZero = 0;
+ Status = mSmbios->Add (mSmbios, NULL, &Handle, &Type7DataHob->SmbiosType7Cache.Hdr);
+ if (EFI_ERROR(Status)) {
+ DEBUG ((DEBUG_ERROR, "%a: Fail to add SMBIOS Type 7\n", __FUNCTION__));
+ return Status;
+ }
+ DEBUG ((DEBUG_INFO, "SMBIOS Type 7 was added. SMBIOS Handle: 0x%x\n", Handle));
+ DEBUG ((DEBUG_VERBOSE, " Cache belone to processor GUID: %g\n", &Type7DataHob->PrcessorGuid));
+ DEBUG ((DEBUG_VERBOSE, " Cache belone processor UID: %d\n", Type7DataHob->ProcessorUid));
+ DEBUG ((DEBUG_VERBOSE, " ==============================\n"));
+ DEBUG ((DEBUG_VERBOSE, " Socket Designation: %d\n", Type7DataHob->SmbiosType7Cache.SocketDesignation));
+ DEBUG ((DEBUG_VERBOSE, " Cache Configuration: 0x%x\n", Type7DataHob->SmbiosType7Cache.CacheConfiguration));
+ DEBUG ((DEBUG_VERBOSE, " Maximum Cache Size: 0x%x\n", Type7DataHob->SmbiosType7Cache.MaximumCacheSize));
+ DEBUG ((DEBUG_VERBOSE, " Installed Size: 0x%x\n", Type7DataHob->SmbiosType7Cache.InstalledSize));
+ DEBUG ((DEBUG_VERBOSE, " Supported SRAM Type: 0x%x\n", Type7DataHob->SmbiosType7Cache.SupportedSRAMType));
+ DEBUG ((DEBUG_VERBOSE, " Current SRAMT ype: 0x%x\n", Type7DataHob->SmbiosType7Cache.CurrentSRAMType));
+ DEBUG ((DEBUG_VERBOSE, " Cache Speed: 0x%x\n", Type7DataHob->SmbiosType7Cache.CacheSpeed));
+ DEBUG ((DEBUG_VERBOSE, " Error Correction Type: 0x%x\n", Type7DataHob->SmbiosType7Cache.ErrorCorrectionType));
+ DEBUG ((DEBUG_VERBOSE, " System Cache Type: 0x%x\n", Type7DataHob->SmbiosType7Cache.SystemCacheType));
+ DEBUG ((DEBUG_VERBOSE, " Associativity: 0x%x\n", Type7DataHob->SmbiosType7Cache.Associativity));
+
+ *SmbiosHandle = Handle;
+ return EFI_SUCCESS;
+}
+
+/**
+ This function builds SMBIOS type 4 record according to
+ the given RISC_V_PROCESSOR_TYPE4_HOB_DATA.
+
+ @param Type4HobData Pointer to RISC_V_PROCESSOR_TYPE4_HOB_DATA
+ @param SmbiosHandle Pointer to SMBIOS_HANDLE
+
+ @retval EFI_STATUS
+
+**/
+STATIC
+EFI_STATUS
+BuildSmbiosType4 (
+ IN RISC_V_PROCESSOR_TYPE4_HOB_DATA *Type4HobData,
+ OUT SMBIOS_HANDLE *SmbiosHandle
+ )
+{
+ EFI_HOB_GUID_TYPE *GuidHob;
+ RISC_V_PROCESSOR_TYPE7_HOB_DATA *Type7HobData;
+ SMBIOS_HANDLE Cache;
+ SMBIOS_HANDLE Processor;
+ EFI_STATUS Status;
+
+ DEBUG ((DEBUG_INFO, "Building Type 4.\n"));
+ DEBUG ((DEBUG_INFO, " Processor GUID: %g\n", &Type4HobData->PrcessorGuid));
+ DEBUG ((DEBUG_INFO, " Processor UUID: %d\n", Type4HobData->ProcessorUid));
+
+ Type4HobData->SmbiosType4Processor.L1CacheHandle = RISC_V_CACHE_INFO_NOT_PROVIDED;
+ Type4HobData->SmbiosType4Processor.L2CacheHandle = RISC_V_CACHE_INFO_NOT_PROVIDED;
+ Type4HobData->SmbiosType4Processor.L3CacheHandle = RISC_V_CACHE_INFO_NOT_PROVIDED;
+ GuidHob = (EFI_HOB_GUID_TYPE *)GetFirstGuidHob ((EFI_GUID *)PcdGetPtr(PcdProcessorSmbiosType7GuidHobGuid));
+ if (GuidHob == NULL) {
+ DEBUG ((DEBUG_ERROR, "No RISC-V SMBIOS Type7 data HOB found.\n"));
+ return EFI_NOT_FOUND;
+ }
+ //
+ // Go through each RISC_V_PROCESSOR_TYPE4_HOB_DATA for multiple processors.
+ //
+ do {
+ Type7HobData = (RISC_V_PROCESSOR_TYPE7_HOB_DATA *)GET_GUID_HOB_DATA (GuidHob);
+ Status = BuildSmbiosType7 (Type4HobData, Type7HobData, &Cache);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+ if ((Type7HobData->SmbiosType7Cache.SystemCacheType & RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_MASK) ==
+ RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_1) {
+ Type4HobData->SmbiosType4Processor.L1CacheHandle = Cache;
+ } else if ((Type7HobData->SmbiosType7Cache.SystemCacheType & RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_MASK) ==
+ RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_2) {
+ Type4HobData->SmbiosType4Processor.L2CacheHandle = Cache;
+ } else if ((Type7HobData->SmbiosType7Cache.SystemCacheType & RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_MASK) ==
+ RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_3) {
+ Type4HobData->SmbiosType4Processor.L3CacheHandle = Cache;
+ } else {
+ DEBUG ((DEBUG_ERROR, "Improper cache level of SMBIOS handle %d\n", Cache));
+ }
+ GuidHob = GetNextGuidHob((EFI_GUID *)PcdGetPtr(PcdProcessorSmbiosType7GuidHobGuid), GET_NEXT_HOB(GuidHob));
+ } while (GuidHob != NULL);
+
+ //
+ // Build SMBIOS Type 4 record
+ //
+ Processor = SMBIOS_HANDLE_PI_RESERVED;
+ Type4HobData->SmbiosType4Processor.Hdr.Type = SMBIOS_TYPE_PROCESSOR_INFORMATION;
+ Type4HobData->SmbiosType4Processor.Hdr.Length = sizeof(SMBIOS_TABLE_TYPE4);
+ Type4HobData->SmbiosType4Processor.Hdr.Handle = 0;
+ Type4HobData->EndingZero = 0;
+ Status = mSmbios->Add (mSmbios, NULL, &Processor, &Type4HobData->SmbiosType4Processor.Hdr);
+ if (EFI_ERROR(Status)) {
+ DEBUG ((DEBUG_ERROR, "Fail to add SMBIOS Type 4\n"));
+ return Status;
+ }
+ DEBUG ((DEBUG_INFO, "SMBIOS Type 4 was added. SMBIOS Handle: 0x%x\n", Processor));
+ DEBUG ((DEBUG_VERBOSE, " Socket StringID: %d\n", Type4HobData->SmbiosType4Processor.Socket));
+ DEBUG ((DEBUG_VERBOSE, " Processor Type: 0x%x\n", Type4HobData->SmbiosType4Processor.ProcessorType));
+ DEBUG ((DEBUG_VERBOSE, " Processor Family: 0x%x\n", Type4HobData->SmbiosType4Processor.ProcessorFamily));
+ DEBUG ((DEBUG_VERBOSE, " Processor Manufacture StringID: %d\n", Type4HobData->SmbiosType4Processor.ProcessorManufacture));
+ DEBUG ((DEBUG_VERBOSE, " Processor Id: 0x%x:0x%x\n", \
+ Type4HobData->SmbiosType4Processor.ProcessorId.Signature, Type4HobData->SmbiosType4Processor.ProcessorId.FeatureFlags));
+ DEBUG ((DEBUG_VERBOSE, " Processor Version StringID: %d\n", Type4HobData->SmbiosType4Processor.ProcessorVersion));
+ DEBUG ((DEBUG_VERBOSE, " Voltage: 0x%x\n", Type4HobData->SmbiosType4Processor.Voltage));
+ DEBUG ((DEBUG_VERBOSE, " External Clock: 0x%x\n", Type4HobData->SmbiosType4Processor.ExternalClock));
+ DEBUG ((DEBUG_VERBOSE, " Max Speed: 0x%x\n", Type4HobData->SmbiosType4Processor.MaxSpeed));
+ DEBUG ((DEBUG_VERBOSE, " Current Speed: 0x%x\n", Type4HobData->SmbiosType4Processor.CurrentSpeed));
+ DEBUG ((DEBUG_VERBOSE, " Status: 0x%x\n", Type4HobData->SmbiosType4Processor.Status));
+ DEBUG ((DEBUG_VERBOSE, " ProcessorUpgrade: 0x%x\n", Type4HobData->SmbiosType4Processor.ProcessorUpgrade));
+ DEBUG ((DEBUG_VERBOSE, " L1 Cache Handle: 0x%x\n", Type4HobData->SmbiosType4Processor.L1CacheHandle));
+ DEBUG ((DEBUG_VERBOSE, " L2 Cache Handle: 0x%x\n",Type4HobData->SmbiosType4Processor.L2CacheHandle));
+ DEBUG ((DEBUG_VERBOSE, " L3 Cache Handle: 0x%x\n", Type4HobData->SmbiosType4Processor.L3CacheHandle));
+ DEBUG ((DEBUG_VERBOSE, " Serial Number StringID: %d\n", Type4HobData->SmbiosType4Processor.SerialNumber));
+ DEBUG ((DEBUG_VERBOSE, " Asset Tag StringID: %d\n", Type4HobData->SmbiosType4Processor.AssetTag));
+ DEBUG ((DEBUG_VERBOSE, " Part Number StringID: %d\n", Type4HobData->SmbiosType4Processor.PartNumber));
+ DEBUG ((DEBUG_VERBOSE, " Core Count: %d\n", Type4HobData->SmbiosType4Processor.CoreCount));
+ DEBUG ((DEBUG_VERBOSE, " Enabled CoreCount: %d\n", Type4HobData->SmbiosType4Processor.EnabledCoreCount));
+ DEBUG ((DEBUG_VERBOSE, " Thread Count: %d\n", Type4HobData->SmbiosType4Processor.ThreadCount));
+ DEBUG ((DEBUG_VERBOSE, " Processor Characteristics: 0x%x\n", Type4HobData->SmbiosType4Processor.ProcessorCharacteristics));
+ DEBUG ((DEBUG_VERBOSE, " Processor Family2: 0x%x\n", Type4HobData->SmbiosType4Processor.ProcessorFamily2));
+ DEBUG ((DEBUG_VERBOSE, " Core Count 2: %d\n", Type4HobData->SmbiosType4Processor.CoreCount2));
+ DEBUG ((DEBUG_VERBOSE, " Enabled CoreCount : %d\n", Type4HobData->SmbiosType4Processor.EnabledCoreCount2));
+ DEBUG ((DEBUG_VERBOSE, " Thread Count 2: %d\n", Type4HobData->SmbiosType4Processor.ThreadCount2));
+
+ *SmbiosHandle = Processor;
+ return EFI_SUCCESS;
+}
+
+/**
+ This function builds SMBIOS type 44 record according..
+
+ @param Type4HobData Pointer to RISC_V_PROCESSOR_TYPE4_HOB_DATA
+ @param Type4Handle SMBIOS handle of type 4
+
+ @retval EFI_STATUS
+
+**/
+EFI_STATUS
+BuildSmbiosType44 (
+ IN RISC_V_PROCESSOR_TYPE4_HOB_DATA *Type4HobData,
+ IN SMBIOS_HANDLE Type4Handle
+ )
+{
+ EFI_HOB_GUID_TYPE *GuidHob;
+ RISC_V_PROCESSOR_SPECIFIC_HOB_DATA *ProcessorSpecificData;
+ SMBIOS_HANDLE RiscVType44;
+ SMBIOS_TABLE_TYPE44 *Type44Ptr;
+ EFI_STATUS Status;
+
+ DEBUG ((DEBUG_INFO, "Building Type 44 for...\n"));
+ DEBUG ((DEBUG_VERBOSE, " Processor GUID: %g\n", &Type4HobData->PrcessorGuid));
+ DEBUG ((DEBUG_VERBOSE, " Processor UUID: %d\n", Type4HobData->ProcessorUid));
+
+ GuidHob = (EFI_HOB_GUID_TYPE *)GetFirstGuidHob ((EFI_GUID *)PcdGetPtr(PcdProcessorSpecificDataGuidHobGuid));
+ if (GuidHob == NULL) {
+ DEBUG ((DEBUG_ERROR, "No RISC_V_PROCESSOR_SPECIFIC_HOB_DATA found.\n"));
+ return EFI_NOT_FOUND;
+ }
+ //
+ // Go through each RISC_V_PROCESSOR_SPECIFIC_HOB_DATA for multiple cores.
+ //
+ do {
+ ProcessorSpecificData = (RISC_V_PROCESSOR_SPECIFIC_HOB_DATA *)GET_GUID_HOB_DATA (GuidHob);
+ if (!CompareGuid (&ProcessorSpecificData->ParentPrcessorGuid, &Type4HobData->PrcessorGuid) ||
+ ProcessorSpecificData->ParentProcessorUid != Type4HobData->ProcessorUid) {
+ GuidHob = GetNextGuidHob((EFI_GUID *)PcdGetPtr(PcdProcessorSpecificDataGuidHobGuid), GET_NEXT_HOB(GuidHob));
+ if (GuidHob == NULL) {
+ break;
+ }
+ continue;
+ }
+
+ DEBUG ((DEBUG_VERBOSE, "================================\n"));
+ DEBUG ((DEBUG_VERBOSE, "Core GUID: %g\n", &ProcessorSpecificData->CoreGuid));
+
+ Type44Ptr = AllocateZeroPool(sizeof(SMBIOS_TABLE_TYPE44) + sizeof(SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA) + 2); // Two ending zero.
+ if (Type44Ptr == NULL) {
+ return EFI_NOT_FOUND;
+ }
+ Type44Ptr->Hdr.Type = SMBIOS_TYPE_PROCESSOR_ADDITIONAL_INFORMATION;
+ Type44Ptr->Hdr.Handle = 0;
+ Type44Ptr->Hdr.Length = sizeof(SMBIOS_TABLE_TYPE44) + sizeof(SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA);
+ Type44Ptr->RefHandle = Type4Handle;
+ Type44Ptr->ProcessorSpecificBlock.Length = sizeof(SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA);
+ Type44Ptr->ProcessorSpecificBlock.ProcessorArchType = Type4HobData->SmbiosType4Processor.ProcessorFamily2 -
+ ProcessorFamilyRiscvRV32 + \
+ ProcessorSpecificBlockArchTypeRiscVRV32;
+ CopyMem ((VOID *)(Type44Ptr + 1), (VOID *)&ProcessorSpecificData->ProcessorSpecificData, sizeof (SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA));
+
+ DEBUG ((DEBUG_VERBOSE, "Core type: %d\n", Type44Ptr->ProcessorSpecificBlock.ProcessorArchType));
+ DEBUG ((DEBUG_VERBOSE, " HartId = 0x%x\n", ((SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA *)(Type44Ptr + 1))->HartId.Value64_L));
+ DEBUG ((DEBUG_VERBOSE, " Is Boot Hart? = 0x%x\n", ((SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA *)(Type44Ptr + 1))->BootHartId));
+ DEBUG ((DEBUG_VERBOSE, " PrivilegeModeSupported = 0x%x\n", ((SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA *)(Type44Ptr + 1))->PrivilegeModeSupported));
+ DEBUG ((DEBUG_VERBOSE, " MModeExcepDelegation = 0x%x\n", ((SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA *)(Type44Ptr + 1))->MModeExcepDelegation.Value64_L));
+ DEBUG ((DEBUG_VERBOSE, " MModeInterruptDelegation = 0x%x\n", ((SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA *)(Type44Ptr + 1))->MModeInterruptDelegation.Value64_L));
+ DEBUG ((DEBUG_VERBOSE, " HartXlen = 0x%x\n", ((SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA *)(Type44Ptr + 1))->HartXlen));
+ DEBUG ((DEBUG_VERBOSE, " MachineModeXlen = 0x%x\n", ((SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA *)(Type44Ptr + 1))->MachineModeXlen));
+ DEBUG ((DEBUG_VERBOSE, " SupervisorModeXlen = 0x%x\n", ((SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA *)(Type44Ptr + 1))->SupervisorModeXlen));
+ DEBUG ((DEBUG_VERBOSE, " UserModeXlen = 0x%x\n", ((SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA *)(Type44Ptr + 1))->UserModeXlen));
+ DEBUG ((DEBUG_VERBOSE, " InstSetSupported = 0x%x\n", ((SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA *)(Type44Ptr + 1))->InstSetSupported));
+ DEBUG ((DEBUG_VERBOSE, " MachineVendorId = 0x%x\n", ((SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA *)(Type44Ptr + 1))->MachineVendorId.Value64_L));
+ DEBUG ((DEBUG_VERBOSE, " MachineArchId = 0x%x\n", ((SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA *)(Type44Ptr + 1))->MachineArchId.Value64_L));
+ DEBUG ((DEBUG_VERBOSE, " MachineImplId = 0x%x\n", ((SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA *)(Type44Ptr + 1))->MachineImplId.Value64_L));
+
+ //
+ // Add to SMBIOS table.
+ //
+ RiscVType44 = SMBIOS_HANDLE_PI_RESERVED;
+ Status = mSmbios->Add (mSmbios, NULL, &RiscVType44, &Type44Ptr->Hdr);
+ if (EFI_ERROR(Status)) {
+ DEBUG ((DEBUG_ERROR, "Fail to add SMBIOS Type 44\n"));
+ return Status;
+ }
+ DEBUG ((DEBUG_INFO, "SMBIOS Type 44 was added. SMBIOS Handle: 0x%x\n", RiscVType44));
+
+ GuidHob = GetNextGuidHob((EFI_GUID *)PcdGetPtr(PcdProcessorSpecificDataGuidHobGuid), GET_NEXT_HOB(GuidHob));
+ } while (GuidHob != NULL);
+ return EFI_SUCCESS;
+}
+
+/**
+ Entry point of RISC-V SMBIOS builder.
+
+ @param ImageHandle Image handle this driver.
+ @param SystemTable Pointer to the System Table.
+
+ @retval EFI_SUCCESS Thread can be successfully created
+ @retval EFI_OUT_OF_RESOURCES Cannot allocate protocol data structure
+ @retval EFI_DEVICE_ERROR Cannot create the thread
+
+**/
+EFI_STATUS
+EFIAPI
+RiscVSmbiosBuilderEntry (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+ EFI_HOB_GUID_TYPE *GuidHob;
+ RISC_V_PROCESSOR_TYPE4_HOB_DATA *Type4HobData;
+ SMBIOS_HANDLE Processor;
+
+ DEBUG ((DEBUG_INFO, "%a: entry\n", __FUNCTION__));
+
+ Status = gBS->LocateProtocol (
+ &gEfiSmbiosProtocolGuid,
+ NULL,
+ (VOID **)&mSmbios
+ );
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "Locate SMBIOS Protocol fail\n"));
+ return Status;
+ }
+ GuidHob = (EFI_HOB_GUID_TYPE *)GetFirstGuidHob ((EFI_GUID *)PcdGetPtr(PcdProcessorSmbiosType4GuidHobGuid));
+ if (GuidHob == NULL) {
+ DEBUG ((DEBUG_ERROR, "No RISC-V SMBIOS information found.\n"));
+ return EFI_NOT_FOUND;
+ }
+ Type4HobData = (RISC_V_PROCESSOR_TYPE4_HOB_DATA *)GET_GUID_HOB_DATA (GuidHob);
+ Status = EFI_NOT_FOUND;
+ //
+ // Go through each RISC_V_PROCESSOR_TYPE4_HOB_DATA for multiple processors.
+ //
+ do {
+ Status = BuildSmbiosType4 (Type4HobData, &Processor);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "No RISC-V SMBIOS type 4 created.\n"));
+ ASSERT (FALSE);
+ }
+ Status = BuildSmbiosType44 (Type4HobData, Processor);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "No RISC-V SMBIOS type 44 found.\n"));
+ ASSERT (FALSE);
+ }
+
+ GuidHob = GetNextGuidHob((EFI_GUID *)PcdGetPtr(PcdProcessorSmbiosType4GuidHobGuid), GET_NEXT_HOB(GuidHob));
+ } while (GuidHob != NULL);
+ DEBUG ((DEBUG_INFO, "%a: exit\n", __FUNCTION__));
+ return Status;
+}
+
diff --git a/Silicon/RISC-V/ProcessorPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.uni b/Silicon/RISC-V/ProcessorPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.uni
new file mode 100644
index 0000000000..1bffe09fe7
--- /dev/null
+++ b/Silicon/RISC-V/ProcessorPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.uni
@@ -0,0 +1,12 @@
+// /** @file
+//
+// Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+//
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+// **/
+
+#string STR_MODULE_ABSTRACT #language en-US "RISC-V Processor SMBIOS Builder"
+
+#string STR_MODULE_DESCRIPTION #language en-US "Build RISC-V Processor SMBIOS Type 4, 7, 44 records."
+
--git a/Silicon/RISC-V/ProcessorPkg/Universal/SmbiosDxe/RiscVSmbiosDxeExtra.uni b/Silicon/RISC-V/ProcessorPkg/Universal/SmbiosDxe/RiscVSmbiosDxeExtra.uni
new file mode 100644
index 0000000000..4b37ca2bbb
--- /dev/null
+++ b/Silicon/RISC-V/ProcessorPkg/Universal/SmbiosDxe/RiscVSmbiosDxeExtra.uni
@@ -0,0 +1,13 @@
+// /** @file
+// RISC-V SMBIOS Builder Localized Strings and Content
+//
+// Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+//
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+// **/
+
+#string STR_PROPERTIES_MODULE_NAME
+#language en-US
+"RISC-V SMBIOS Record Builder DXE Driver"
+
--
2.31.1
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH 11/79] ProcesorPkg/Library: NULL instance of RISC-V platform timer library.
2022-01-08 4:10 [PATCH 02/79] ProcessorPkg/Library: RISC-V CPU library Abner Chang
` (7 preceding siblings ...)
2022-01-08 4:10 ` [PATCH 10/79] ProcessorPkg/SmbiosDxe: Generic SMBIOS DXE driver for RISC-V platforms Abner Chang
@ 2022-01-08 4:10 ` Abner Chang
2022-01-08 4:10 ` [PATCH 12/79] RISC-V/ProcessorPkg: RISC-V package Abner Chang
` (28 subsequent siblings)
37 siblings, 0 replies; 39+ messages in thread
From: Abner Chang @ 2022-01-08 4:10 UTC (permalink / raw)
To: devel; +Cc: abner.chang
(This is migrated from edk2-platforms:Silicon/RISC-V)
NULL instance of RISC-V platform timer library.
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Co-authored-by: Gilbert Chen <gilbert.chen@hpe.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>
---
.../RiscVPlatformTimerLib.inf | 35 ++++++++++++++++
.../RiscVPlatformTimerLibNull.S | 40 +++++++++++++++++++
2 files changed, 75 insertions(+)
create mode 100644 Silicon/RISC-V/ProcessorPkg/Library/RiscVPlatformTimerLibNull/RiscVPlatformTimerLib.inf
create mode 100644 Silicon/RISC-V/ProcessorPkg/Library/RiscVPlatformTimerLibNull/RiscVPlatformTimerLibNull.S
diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVPlatformTimerLibNull/RiscVPlatformTimerLib.inf b/Silicon/RISC-V/ProcessorPkg/Library/RiscVPlatformTimerLibNull/RiscVPlatformTimerLib.inf
new file mode 100644
index 0000000000..6bf168c72e
--- /dev/null
+++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVPlatformTimerLibNull/RiscVPlatformTimerLib.inf
@@ -0,0 +1,35 @@
+## @file
+# RISC-V CPU lib to override timer mechanism for U500 platform.
+#
+# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001b
+ BASE_NAME = RiscVPlatformTimerLibNull
+ FILE_GUID = 93FDB133-476E-4726-A65D-C10D5C9A68DE
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = RiscVPlatformTimerLib
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = RISCV64
+#
+
+[Sources]
+
+[Sources.RISCV64]
+ RiscVPlatformTimerLibNull.S
+
+[Packages]
+ MdeModulePkg/MdeModulePkg.dec
+ MdePkg/MdePkg.dec
+
+
+
+
diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVPlatformTimerLibNull/RiscVPlatformTimerLibNull.S b/Silicon/RISC-V/ProcessorPkg/Library/RiscVPlatformTimerLibNull/RiscVPlatformTimerLibNull.S
new file mode 100644
index 0000000000..815ab06bac
--- /dev/null
+++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVPlatformTimerLibNull/RiscVPlatformTimerLibNull.S
@@ -0,0 +1,40 @@
+//------------------------------------------------------------------------------
+//
+// Null instance of Timer CSR functions.
+//
+// Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+//
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+//------------------------------------------------------------------------------
+#include <Base.h>
+
+.data
+
+.text
+.align 3
+
+.global ASM_PFX(RiscVReadMachineTimer)
+.global ASM_PFX(RiscVSetMachineTimerCmp)
+.global ASM_PFX(RiscVReadMachineTimerCmp)
+
+//
+// Read machine timer CSR.
+// @retval a0 : 64-bit machine timer.
+//
+ASM_PFX (RiscVReadMachineTimer):
+ ret
+
+//
+// Set machine timer compare CSR.
+// @param a0 : UINT64
+//
+ASM_PFX (RiscVSetMachineTimerCmp):
+ ret
+
+//
+// Read machine timer compare CSR.
+// @param a0 : UINT64
+//
+ASM_PFX (RiscVReadMachineTimerCmp):
+ ret
--
2.31.1
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH 12/79] RISC-V/ProcessorPkg: RISC-V package.
2022-01-08 4:10 [PATCH 02/79] ProcessorPkg/Library: RISC-V CPU library Abner Chang
` (8 preceding siblings ...)
2022-01-08 4:10 ` [PATCH 11/79] ProcesorPkg/Library: NULL instance of RISC-V platform timer library Abner Chang
@ 2022-01-08 4:10 ` Abner Chang
2022-01-08 4:10 ` [PATCH 13/79] PlatformPkg/Library: RISC-V Platform Temporary Memory library Abner Chang
` (27 subsequent siblings)
37 siblings, 0 replies; 39+ messages in thread
From: Abner Chang @ 2022-01-08 4:10 UTC (permalink / raw)
To: devel; +Cc: abner.chang
(This is migrated from edk2-platforms:Silicon/RISC-V)
- Add RISC-V ProcessorPkg package which provides RISC-V processor related
drivers and libraries.
- Support RISC-V OpenSBI and RISC-V platforms
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Co-authored-by: Daniel Schaefer <daniel.schaefer@hpe.com>
Co-authored-by: Gilbert Chen <gilbert.chen@hpe.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>
---
.../RISC-V/ProcessorPkg/RiscVProcessorPkg.dec | 47 ++++++++
.../RISC-V/ProcessorPkg/RiscVProcessorPkg.dsc | 100 ++++++++++++++++++
.../RISC-V/ProcessorPkg/RiscVProcessorPkg.uni | 13 +++
| 13 +++
4 files changed, 173 insertions(+)
create mode 100644 Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec
create mode 100644 Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dsc
create mode 100644 Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.uni
create mode 100644 Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkgExtra.uni
diff --git a/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec b/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec
new file mode 100644
index 0000000000..0b64b33f0f
--- /dev/null
+++ b/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec
@@ -0,0 +1,47 @@
+## @file RiscVProcesssorPkg.dec
+# This Package provides UEFI RISC-V processor modules and libraries.
+#
+# Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ DEC_SPECIFICATION = 0x0001001b
+ PACKAGE_NAME = RiscVProcessorPkg
+ PACKAGE_UNI_FILE = RiscVProcessorPkg.uni
+ PACKAGE_GUID = 993C7CAC-C87C-4F08-A2CF-AD3AABA859D1
+ PACKAGE_VERSION = 1.0
+
+[Includes]
+ Include
+ Include/Library
+ Library/RiscVOpensbiLib/opensbi # OpenSBI header file reference ("include/sbi/...")
+ Library/RiscVOpensbiLib/opensbi/include # Header file reference from opensbi files, ("sbi/...")
+
+[LibraryClasses]
+ RiscVPlatformDxeIplLib|Include/Library/RiscVPlatformDxeIpl.h
+ RiscVCpuLib|Include/Library/RiscVCpuLib.h
+ RiscVEdk2SbiLib|Include/Library/RiscVEdk2SbiLib.h
+
+[Guids]
+ gUefiRiscVPkgTokenSpaceGuid = { 0x4261e9c8, 0x52c0, 0x4b34, { 0x85, 0x3d, 0x48, 0x46, 0xea, 0xd3, 0xb7, 0x2c}}
+
+[PcdsFixedAtBuild]
+ # Processor Specific Data GUID HOB GUID
+ gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSpecificDataGuidHobGuid|{0x20, 0x72, 0xD5, 0x2F, 0xCF, 0x3C, 0x4C, 0xBC, 0xB1, 0x65, 0x94, 0x90, 0xDC, 0xF2, 0xFA, 0x93}|VOID*|0x00001000
+ gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSmbiosGuidHobGuid|{0x0F, 0x34, 0x00, 0x92, 0x04, 0x12, 0x45, 0x4A, 0x9C, 0x11, 0xB8, 0x8B, 0xDF, 0xC6, 0xFA, 0x6F}|VOID*|0x00001001
+ gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSmbiosType4GuidHobGuid|{0x5B, 0x36, 0xEA, 0x23, 0x79, 0x6D, 0x4F, 0xCF, 0x9C, 0x22, 0x25, 0xC0, 0x89, 0x8C, 0x25, 0xB9}|VOID*|0x00001002
+ gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSmbiosType7GuidHobGuid|{0xBF, 0xB4, 0x6D, 0x1B, 0x7E, 0x10, 0x47, 0x44, 0xB8, 0xBD, 0xFF, 0x1E, 0xDD, 0xDF, 0x71, 0x65}|VOID*|0x00001003
+
+ #
+ # 1000000000
+ # PcdRiscVMachineTimerTickInNanoSecond = ---------------------------------------
+ # PcdRiscVMachineTimerFrequencyInHerz
+ #
+ gUefiRiscVPkgTokenSpaceGuid.PcdRiscVMachineTimerTickInNanoSecond|100|UINT64|0x00001010
+ gUefiRiscVPkgTokenSpaceGuid.PcdRiscVMachineTimerFrequencyInHerz|10000000|UINT64|0x00001011
+
+[UserExtensions.TianoCore."ExtraFiles"]
+ RiscVProcessorPkgExtra.uni
diff --git a/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dsc b/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dsc
new file mode 100644
index 0000000000..5f88f5e89f
--- /dev/null
+++ b/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dsc
@@ -0,0 +1,100 @@
+#/** @file
+# RISC-V processor package.
+#
+# Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#**/
+
+################################################################################
+#
+# Defines Section
+#
+################################################################################
+[Defines]
+ PLATFORM_NAME = RiscVProcessor
+ PLATFORM_GUID = 55D77916-B270-41B4-9325-2CE9DCE0926E
+ PLATFORM_VERSION = 0.1
+ DSC_SPECIFICATION = 0x0001001c
+ OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME)
+ SUPPORTED_ARCHITECTURES = RISCV64
+ BUILD_TARGETS = DEBUG|RELEASE|NOOPT
+ SKUID_IDENTIFIER = DEFAULT
+
+[BuildOptions]
+ GCC:RELEASE_*_*_CC_FLAGS = -DMDEPKG_NDEBUG
+!ifdef $(SOURCE_DEBUG_ENABLE)
+ GCC:*_*_RISCV64_GENFW_FLAGS = --keepexceptiontable
+!endif
+
+################################################################################
+#
+# SKU Identification section - list of all SKU IDs supported by this Platform.
+#
+################################################################################
+[SkuIds]
+ 0|DEFAULT
+
+[LibraryClasses.common]
+ CpuExceptionHandlerLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVExceptionLib/CpuExceptionHandlerDxeLib.inf
+ RiscVCpuLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVCpuLib/RiscVCpuLib.inf
+ RiscVEdk2SbiLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVEdk2SbiLib/RiscVEdk2SbiLib.inf
+ RiscVOpensbiLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVOpensbiLib/RiscVOpensbiLib.inf
+ TimerLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVTimerLib/BaseRiscVTimerLib.inf
+ BaseLib|MdePkg/Library/BaseLib/BaseLib.inf
+ BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
+ DebugAgentLib|MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLibNull.inf
+ DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf
+ HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
+ IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
+ MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
+ PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+ PeCoffExtraActionLib|MdePkg/Library/BasePeCoffExtraActionLibNull/BasePeCoffExtraActionLibNull.inf
+ PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
+ PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
+ SerialPortLib|MdePkg/Library/BaseSerialPortLibNull/BaseSerialPortLibNull.inf
+ PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
+ CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf
+ UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf
+ UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf
+ UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf
+ UefiApplicationEntryPoint|MdePkg/Library/UefiApplicationEntryPoint/UefiApplicationEntryPoint.inf
+ UefiLib|MdePkg/Library/UefiLib/UefiLib.inf
+ DevicePathLib|MdePkg/Library/UefiDevicePathLibDevicePathProtocol/UefiDevicePathLibDevicePathProtocol.inf
+ RiscVPlatformTimerLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVPlatformTimerLibNull/RiscVPlatformTimerLib.inf
+ PeiServicesTablePointerLib|Silicon/RISC-V/ProcessorPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerLibOpenSbi.inf
+
+[LibraryClasses.common.PEI_CORE]
+ PeiServicesTablePointerLib|Silicon/RISC-V/ProcessorPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerLibOpenSbi.inf
+
+[LibraryClasses.common.PEIM]
+ PeiServicesTablePointerLib|Silicon/RISC-V/ProcessorPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerLibOpenSbi.inf
+ HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
+ MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf
+ PeimEntryPoint|MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf
+
+[LibraryClasses.common.DXE_CORE]
+ TimerLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVTimerLib/BaseRiscVTimerLib.inf
+
+[LibraryClasses.common.DXE_DRIVER]
+ PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
+ PlatformBootManagerLib|Platform/RISC-V/PlatformPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
+
+[LibraryClasses.common.DXE_RUNTIME_DRIVER]
+ TimerLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVTimerLib/BaseRiscVTimerLib.inf
+
+[LibraryClasses.common.UEFI_DRIVER]
+ TimerLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVTimerLib/BaseRiscVTimerLib.inf
+
+[Components]
+ Silicon/RISC-V/ProcessorPkg/Library/RiscVTimerLib/BaseRiscVTimerLib.inf
+ Silicon/RISC-V/ProcessorPkg/Library/RiscVExceptionLib/CpuExceptionHandlerDxeLib.inf
+ Silicon/RISC-V/ProcessorPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerLibOpenSbi.inf
+ Silicon/RISC-V/ProcessorPkg/Library/RiscVOpensbiLib/RiscVOpensbiLib.inf
+ Silicon/RISC-V/ProcessorPkg/Library/RiscVPlatformTimerLibNull/RiscVPlatformTimerLib.inf
+ Silicon/RISC-V/ProcessorPkg/Library/RiscVCpuLib/RiscVCpuLib.inf
+ Silicon/RISC-V/ProcessorPkg/Library/RiscVEdk2SbiLib/RiscVEdk2SbiLib.inf
+
+ Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxe.inf
+ Silicon/RISC-V/ProcessorPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.inf
diff --git a/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.uni b/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.uni
new file mode 100644
index 0000000000..83da92fe40
--- /dev/null
+++ b/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.uni
@@ -0,0 +1,13 @@
+// /** @file
+// RISC-V Processor Package Localized Strings and Content.
+//
+// Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+//
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+// **/
+
+#string STR_PACKAGE_ABSTRACT #language en-US "Provides UEFI compatible RISC-V processor modules and libraries"
+
+#string STR_PACKAGE_DESCRIPTION #language en-US "This Package provides UEFI compatible RISC-V processor modules and libraries."
+
--git a/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkgExtra.uni b/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkgExtra.uni
new file mode 100644
index 0000000000..207adfb671
--- /dev/null
+++ b/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkgExtra.uni
@@ -0,0 +1,13 @@
+// /** @file
+// RISC-V Package Localized Strings and Content.
+//
+// Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+//
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+// **/
+
+#string STR_PROPERTIES_PACKAGE_NAME
+#language en-US
+"RISC-V processor package"
+
--
2.31.1
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH 13/79] PlatformPkg/Library: RISC-V Platform Temporary Memory library
2022-01-08 4:10 [PATCH 02/79] ProcessorPkg/Library: RISC-V CPU library Abner Chang
` (9 preceding siblings ...)
2022-01-08 4:10 ` [PATCH 12/79] RISC-V/ProcessorPkg: RISC-V package Abner Chang
@ 2022-01-08 4:10 ` Abner Chang
2022-01-08 4:10 ` [PATCH 14/79] PlatformPkg/Library: Add FirmwareContextProcessorSpecificLib module Abner Chang
` (26 subsequent siblings)
37 siblings, 0 replies; 39+ messages in thread
From: Abner Chang @ 2022-01-08 4:10 UTC (permalink / raw)
To: devel; +Cc: abner.chang
(This is migrated from edk2-platforms:Platform/RISC-V)
NULL instance of RISC-V Platform Temporary Memory library.
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Co-authored-by: Gilbert Chen <gilbert.chen@hpe.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>
---
.../RiscVPlatformTempMemoryInitLibNull.inf | 38 +++++++++++++++++++
.../Library/RiscVPlatformTempMemoryInitLib.h | 17 +++++++++
.../Riscv64/TempMemInit.S | 26 +++++++++++++
3 files changed, 81 insertions(+)
create mode 100644 Platform/RISC-V/PlatformPkg/Library/RiscVPlatformTempMemoryInitLibNull/RiscVPlatformTempMemoryInitLibNull.inf
create mode 100644 Platform/RISC-V/PlatformPkg/Include/Library/RiscVPlatformTempMemoryInitLib.h
create mode 100644 Platform/RISC-V/PlatformPkg/Library/RiscVPlatformTempMemoryInitLibNull/Riscv64/TempMemInit.S
diff --git a/Platform/RISC-V/PlatformPkg/Library/RiscVPlatformTempMemoryInitLibNull/RiscVPlatformTempMemoryInitLibNull.inf b/Platform/RISC-V/PlatformPkg/Library/RiscVPlatformTempMemoryInitLibNull/RiscVPlatformTempMemoryInitLibNull.inf
new file mode 100644
index 0000000000..1634a05f58
--- /dev/null
+++ b/Platform/RISC-V/PlatformPkg/Library/RiscVPlatformTempMemoryInitLibNull/RiscVPlatformTempMemoryInitLibNull.inf
@@ -0,0 +1,38 @@
+## @file
+# RISC-V platform temporary memory library.
+#
+# Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001b
+ BASE_NAME = RiscVPlatformTempMemoryInitLibNull
+ FILE_GUID = 67294857-C0F8-4ACB-8237-D91FE506B710
+ MODULE_TYPE = SEC
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = RiscVPlatformTempMemoryInitLib
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = RISCV64
+#
+
+[Sources]
+
+[Sources.RISCV64]
+ Riscv64/TempMemInit.S
+
+[Pcd]
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdTemporaryRamBase
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdTemporaryRamSize
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec
+
+
diff --git a/Platform/RISC-V/PlatformPkg/Include/Library/RiscVPlatformTempMemoryInitLib.h b/Platform/RISC-V/PlatformPkg/Include/Library/RiscVPlatformTempMemoryInitLib.h
new file mode 100644
index 0000000000..4f9f7950c1
--- /dev/null
+++ b/Platform/RISC-V/PlatformPkg/Include/Library/RiscVPlatformTempMemoryInitLib.h
@@ -0,0 +1,17 @@
+/** @file
+ RISC-V package definitions.
+
+ Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef RISCV_PLATFORM_TEMP_MEM_LIB_H_
+#define RISCV_PLATFORM_TEMP_MEM_LIB_H_
+
+#include "RiscVImpl.h"
+
+VOID EFIAPI RiscVPlatformTemporaryMemInit (VOID);
+UINT32 EFIAPI RiscVPlatformTemporaryMemSize (VOID);
+UINT32 EFIAPI RiscVPlatformTemporaryMemBase (VOID);
+#endif
diff --git a/Platform/RISC-V/PlatformPkg/Library/RiscVPlatformTempMemoryInitLibNull/Riscv64/TempMemInit.S b/Platform/RISC-V/PlatformPkg/Library/RiscVPlatformTempMemoryInitLibNull/Riscv64/TempMemInit.S
new file mode 100644
index 0000000000..c8fb43c604
--- /dev/null
+++ b/Platform/RISC-V/PlatformPkg/Library/RiscVPlatformTempMemoryInitLibNull/Riscv64/TempMemInit.S
@@ -0,0 +1,26 @@
+//------------------------------------------------------------------------------
+//
+// RISC-V RiscVPlatformTemporaryMemInit.
+//
+// Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+//
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+//------------------------------------------------------------------------------
+#include <Base.h>
+
+.data
+
+.text
+.align 3
+
+.global ASM_PFX(RiscVPlatformTemporaryMemInit)
+
+//
+// @retval a0 Temporary memory base.
+// a1 Temporary memory size.
+//
+ASM_PFX(RiscVPlatformTemporaryMemInit):
+ li a0, FixedPcdGet32 (PcdTemporaryRamBase)
+ li a1, FixedPcdGet32 (PcdTemporaryRamSize)
+ ret
--
2.31.1
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH 14/79] PlatformPkg/Library: Add FirmwareContextProcessorSpecificLib module
2022-01-08 4:10 [PATCH 02/79] ProcessorPkg/Library: RISC-V CPU library Abner Chang
` (10 preceding siblings ...)
2022-01-08 4:10 ` [PATCH 13/79] PlatformPkg/Library: RISC-V Platform Temporary Memory library Abner Chang
@ 2022-01-08 4:10 ` Abner Chang
2022-01-08 4:10 ` [PATCH 15/79] PlatformPkg/Library: NULL instance of RiscVOpensbiPlatformLib Abner Chang
` (25 subsequent siblings)
37 siblings, 0 replies; 39+ messages in thread
From: Abner Chang @ 2022-01-08 4:10 UTC (permalink / raw)
To: devel; +Cc: abner.chang
(This is migrated from edk2-platforms:Platform/RISC-V)
Add OpenSBI firmware context processor specific library which
provides interface to create processor specific firmware
context hob data.
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Co-authored-by: Gilbert Chen <gilbert.chen@hpe.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>
---
.../FirmwareContextProcessorSpecificLib.inf | 31 +++++
.../FirmwareContextProcessorSpecificLib.h | 53 ++++++++
.../FirmwareContextProcessorSpecificLib.c | 119 ++++++++++++++++++
3 files changed, 203 insertions(+)
create mode 100644 Platform/RISC-V/PlatformPkg/Library/FirmwareContextProcessorSpecificLib/FirmwareContextProcessorSpecificLib.inf
create mode 100644 Platform/RISC-V/PlatformPkg/Include/Library/FirmwareContextProcessorSpecificLib.h
create mode 100644 Platform/RISC-V/PlatformPkg/Library/FirmwareContextProcessorSpecificLib/FirmwareContextProcessorSpecificLib.c
diff --git a/Platform/RISC-V/PlatformPkg/Library/FirmwareContextProcessorSpecificLib/FirmwareContextProcessorSpecificLib.inf b/Platform/RISC-V/PlatformPkg/Library/FirmwareContextProcessorSpecificLib/FirmwareContextProcessorSpecificLib.inf
new file mode 100644
index 0000000000..69568511ce
--- /dev/null
+++ b/Platform/RISC-V/PlatformPkg/Library/FirmwareContextProcessorSpecificLib/FirmwareContextProcessorSpecificLib.inf
@@ -0,0 +1,31 @@
+#/** @file
+#
+# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#**/
+
+[Defines]
+ INF_VERSION = 0x0001001b
+ BASE_NAME = FirmwareContextProcessorSpecificLib
+ FILE_GUID = 8BEC9FD7-C554-403A-94F1-0EBBFD81A242
+ MODULE_TYPE = PEIM
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = FirmwareContextProcessorSpecificLib
+
+[Sources.common]
+ FirmwareContextProcessorSpecificLib.c
+
+[Packages]
+ MdeModulePkg/MdeModulePkg.dec
+ MdePkg/MdePkg.dec
+ Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec
+
+[LibraryClasses]
+ BaseLib
+ PcdLib
+ MemoryAllocationLib
+ PrintLib
+
+
diff --git a/Platform/RISC-V/PlatformPkg/Include/Library/FirmwareContextProcessorSpecificLib.h b/Platform/RISC-V/PlatformPkg/Include/Library/FirmwareContextProcessorSpecificLib.h
new file mode 100644
index 0000000000..f3b096c257
--- /dev/null
+++ b/Platform/RISC-V/PlatformPkg/Include/Library/FirmwareContextProcessorSpecificLib.h
@@ -0,0 +1,53 @@
+/** @file
+ Firmware Context Processor-specific common library
+
+ Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+#ifndef FIRMWARE_CONTEXT_PROCESSOR_SPECIFIC_LIB_H
+#define FIRMWARE_CONTEXT_PROCESSOR_SPECIFIC_LIB_H
+
+#include <IndustryStandard/RiscVOpensbi.h>
+#include <PiPei.h>
+#include <ProcessorSpecificHobData.h>
+
+/**
+ Build up common firmware context processor-specific information
+
+ @param FirmwareContextHartSpecific Pointer to EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC
+ @param ParentProcessorGuid Pointer to GUID of Processor which contains this core
+ @param ParentProcessorUid Unique ID of pysical processor which owns this core.
+ @param CoreGuid Pointer to GUID of core
+ @param HartId Hart ID of this core.
+ @param IsBootHart This is boot hart or not
+ @param ProcessorSpecDataHob Pointer to RISC_V_PROCESSOR_SPECIFIC_DATA_HOB
+
+ @return EFI_STATUS
+
+**/
+EFI_STATUS
+EFIAPI
+CommonFirmwareContextHartSpecificInfo (
+ EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC *FirmwareContextHartSpecific,
+ EFI_GUID *ParentProcessorGuid,
+ UINTN ParentProcessorUid,
+ EFI_GUID *CoreGuid,
+ UINTN HartId,
+ BOOLEAN IsBootHart,
+ RISC_V_PROCESSOR_SPECIFIC_HOB_DATA *ProcessorSpecDataHob
+ );
+
+/**
+ Print debug information of the processor specific data for a hart
+
+ @param ProcessorSpecificDataHob Pointer to RISC_V_PROCESSOR_SPECIFIC_DATA_HOB
+**/
+VOID
+EFIAPI
+DebugPrintHartSpecificInfo (
+ RISC_V_PROCESSOR_SPECIFIC_HOB_DATA *ProcessorSpecificDataHob
+ );
+
+#endif
diff --git a/Platform/RISC-V/PlatformPkg/Library/FirmwareContextProcessorSpecificLib/FirmwareContextProcessorSpecificLib.c b/Platform/RISC-V/PlatformPkg/Library/FirmwareContextProcessorSpecificLib/FirmwareContextProcessorSpecificLib.c
new file mode 100644
index 0000000000..c62f77bc49
--- /dev/null
+++ b/Platform/RISC-V/PlatformPkg/Library/FirmwareContextProcessorSpecificLib/FirmwareContextProcessorSpecificLib.c
@@ -0,0 +1,119 @@
+/**@file
+ Common library to build upfirmware context processor-specific information
+
+ Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+//
+// The package level header files this module uses
+//
+#include <PiPei.h>
+
+//
+// The Library classes this module consumes
+//
+#include <IndustryStandard/RiscVOpensbi.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/PeiServicesLib.h>
+#include <ProcessorSpecificHobData.h>
+#include <RiscVImpl.h>
+#include <sbi/sbi_hart.h>
+
+/**
+ Build up common firmware context processor-specific information
+
+ @param FirmwareContextHartSpecific Pointer to EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC
+ @param ParentProcessorGuid Pointer to GUID of Processor which contains this core
+ @param ParentProcessorUid Unique ID of pysical processor which owns this core.
+ @param CoreGuid Pointer to GUID of core
+ @param HartId Hart ID of this core.
+ @param IsBootHart This is boot hart or not
+ @param ProcessorSpecificDataHob Pointer to RISC_V_PROCESSOR_SPECIFIC_DATA_HOB
+
+ @return EFI_STATUS
+
+**/
+EFI_STATUS
+EFIAPI
+CommonFirmwareContextHartSpecificInfo (
+ EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC *FirmwareContextHartSpecific,
+ EFI_GUID *ParentProcessorGuid,
+ UINTN ParentProcessorUid,
+ EFI_GUID *CoreGuid,
+ UINTN HartId,
+ BOOLEAN IsBootHart,
+ RISC_V_PROCESSOR_SPECIFIC_HOB_DATA *ProcessorSpecificDataHob
+ )
+{
+ //
+ // Build up RISC_V_PROCESSOR_SPECIFIC_DATA_HOB.
+ //
+ CopyGuid (&ProcessorSpecificDataHob->ParentPrcessorGuid, ParentProcessorGuid);
+ ProcessorSpecificDataHob->ParentProcessorUid = ParentProcessorUid;
+ CopyGuid (&ProcessorSpecificDataHob->CoreGuid, CoreGuid);
+ ProcessorSpecificDataHob->Context = NULL;
+ ProcessorSpecificDataHob->ProcessorSpecificData.Revision =
+ SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA_REVISION;
+ ProcessorSpecificDataHob->ProcessorSpecificData.Length =
+ sizeof (SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA);
+ ProcessorSpecificDataHob->ProcessorSpecificData.HartId.Value64_L = (UINT64)HartId;
+ ProcessorSpecificDataHob->ProcessorSpecificData.HartId.Value64_H = 0;
+ ProcessorSpecificDataHob->ProcessorSpecificData.BootHartId = (UINT8)IsBootHart;
+ ProcessorSpecificDataHob->ProcessorSpecificData.InstSetSupported =
+ FirmwareContextHartSpecific->IsaExtensionSupported;
+ ProcessorSpecificDataHob->ProcessorSpecificData.PrivilegeModeSupported =
+ SMBIOS_RISC_V_PSD_MACHINE_MODE_SUPPORTED;
+ if ((ProcessorSpecificDataHob->ProcessorSpecificData.InstSetSupported &
+ RISC_V_ISA_SUPERVISOR_MODE_IMPLEMENTED) != 0) {
+ ProcessorSpecificDataHob->ProcessorSpecificData.PrivilegeModeSupported |=
+ SMBIOS_RISC_V_PSD_SUPERVISOR_MODE_SUPPORTED;
+ }
+ if ((ProcessorSpecificDataHob->ProcessorSpecificData.InstSetSupported &
+ RISC_V_ISA_USER_MODE_IMPLEMENTED) != 0) {
+ ProcessorSpecificDataHob->ProcessorSpecificData.PrivilegeModeSupported |=
+ SMBIOS_RISC_V_PSD_USER_MODE_SUPPORTED;
+ }
+ ProcessorSpecificDataHob->ProcessorSpecificData.MachineVendorId.Value64_L =
+ FirmwareContextHartSpecific->MachineVendorId.Value64_L;
+ ProcessorSpecificDataHob->ProcessorSpecificData.MachineVendorId.Value64_H =
+ FirmwareContextHartSpecific->MachineVendorId.Value64_H;
+ ProcessorSpecificDataHob->ProcessorSpecificData.MachineArchId.Value64_L =
+ FirmwareContextHartSpecific->MachineArchId.Value64_L;
+ ProcessorSpecificDataHob->ProcessorSpecificData.MachineArchId.Value64_H =
+ FirmwareContextHartSpecific->MachineArchId.Value64_H;
+ ProcessorSpecificDataHob->ProcessorSpecificData.MachineImplId.Value64_L =
+ FirmwareContextHartSpecific->MachineImplId.Value64_L;
+ ProcessorSpecificDataHob->ProcessorSpecificData.MachineImplId.Value64_H =
+ FirmwareContextHartSpecific->MachineImplId.Value64_H;
+ return EFI_SUCCESS;
+}
+
+/**
+ Print debug information of the processor specific data for a hart
+
+ @param ProcessorSpecificDataHob Pointer to RISC_V_PROCESSOR_SPECIFIC_DATA_HOB
+**/
+VOID
+EFIAPI
+DebugPrintHartSpecificInfo (
+ RISC_V_PROCESSOR_SPECIFIC_HOB_DATA *ProcessorSpecificDataHob
+ )
+{
+ DEBUG ((DEBUG_INFO, " *HartId = 0x%x\n", ProcessorSpecificDataHob->ProcessorSpecificData.HartId.Value64_L));
+ DEBUG ((DEBUG_INFO, " *Is Boot Hart? = 0x%x\n", ProcessorSpecificDataHob->ProcessorSpecificData.BootHartId));
+ DEBUG ((DEBUG_INFO, " *PrivilegeModeSupported = 0x%x\n", ProcessorSpecificDataHob->ProcessorSpecificData.PrivilegeModeSupported));
+ DEBUG ((DEBUG_INFO, " *MModeExcepDelegation = 0x%x\n", ProcessorSpecificDataHob->ProcessorSpecificData.MModeExcepDelegation.Value64_L));
+ DEBUG ((DEBUG_INFO, " *MModeInterruptDelegation = 0x%x\n", ProcessorSpecificDataHob->ProcessorSpecificData.MModeInterruptDelegation.Value64_L));
+ DEBUG ((DEBUG_INFO, " *HartXlen = 0x%x\n", ProcessorSpecificDataHob->ProcessorSpecificData.HartXlen ));
+ DEBUG ((DEBUG_INFO, " *MachineModeXlen = 0x%x\n", ProcessorSpecificDataHob->ProcessorSpecificData.MachineModeXlen));
+ DEBUG ((DEBUG_INFO, " *SupervisorModeXlen = 0x%x\n", ProcessorSpecificDataHob->ProcessorSpecificData.SupervisorModeXlen));
+ DEBUG ((DEBUG_INFO, " *UserModeXlen = 0x%x\n", ProcessorSpecificDataHob->ProcessorSpecificData.UserModeXlen));
+ DEBUG ((DEBUG_INFO, " *InstSetSupported = 0x%x\n", ProcessorSpecificDataHob->ProcessorSpecificData.InstSetSupported));
+ DEBUG ((DEBUG_INFO, " *MachineVendorId = 0x%x\n", ProcessorSpecificDataHob->ProcessorSpecificData.MachineVendorId.Value64_L));
+ DEBUG ((DEBUG_INFO, " *MachineArchId = 0x%x\n", ProcessorSpecificDataHob->ProcessorSpecificData.MachineArchId.Value64_L));
+ DEBUG ((DEBUG_INFO, " *MachineImplId = 0x%x\n", ProcessorSpecificDataHob->ProcessorSpecificData.MachineImplId.Value64_L));
+}
--
2.31.1
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH 15/79] PlatformPkg/Library: NULL instance of RiscVOpensbiPlatformLib
2022-01-08 4:10 [PATCH 02/79] ProcessorPkg/Library: RISC-V CPU library Abner Chang
` (11 preceding siblings ...)
2022-01-08 4:10 ` [PATCH 14/79] PlatformPkg/Library: Add FirmwareContextProcessorSpecificLib module Abner Chang
@ 2022-01-08 4:10 ` Abner Chang
2022-01-08 4:10 ` [PATCH 16/79] PlatformPkg/Library: NULL instance of PlatformMemoryTestLib Abner Chang
` (24 subsequent siblings)
37 siblings, 0 replies; 39+ messages in thread
From: Abner Chang @ 2022-01-08 4:10 UTC (permalink / raw)
To: devel; +Cc: abner.chang
(This is migrated from edk2-platforms:Platform/RISC-V)
NULL instance of RiscVOpensbiPlatformLib.
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Co-authored-by: Gilbert Chen <gilbert.chen@hpe.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>
---
.../OpensbiPlatformLibNull.inf | 38 ++++++++++++++++
.../Library/OpensbiPlatformLibNull/Platform.c | 44 +++++++++++++++++++
2 files changed, 82 insertions(+)
create mode 100644 Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLibNull/OpensbiPlatformLibNull.inf
create mode 100644 Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLibNull/Platform.c
diff --git a/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLibNull/OpensbiPlatformLibNull.inf b/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLibNull/OpensbiPlatformLibNull.inf
new file mode 100644
index 0000000000..125a1220bc
--- /dev/null
+++ b/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLibNull/OpensbiPlatformLibNull.inf
@@ -0,0 +1,38 @@
+## @file
+# RISC-V OpenSbi Platform NULL Library
+#
+# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001b
+ BASE_NAME = RiscVOpensbiPlatformLibNull
+ FILE_GUID = 9424ED54-EBDA-4FB5-8FF6-8291B07BB151
+ MODULE_TYPE = SEC
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = RiscVOpensbiPlatformLib
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = RISCV64
+#
+
+[Sources]
+ Platform.c
+
+[Packages]
+ MdeModulePkg/MdeModulePkg.dec
+ MdePkg/MdePkg.dec
+ Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec
+
+[LibraryClasses]
+ BaseLib
+ BaseMemoryLib
+ DebugLib
+ DebugAgentLib
+
+
diff --git a/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLibNull/Platform.c b/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLibNull/Platform.c
new file mode 100644
index 0000000000..e78d811f4c
--- /dev/null
+++ b/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLibNull/Platform.c
@@ -0,0 +1,44 @@
+/*
+ *
+ * Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+ *
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Copyright (c) 2019 Western Digital Corporation or its affiliates.
+ *
+ * Authors:
+ * Atish Patra <atish.patra@wdc.com>
+ */
+
+#include <sbi/sbi_const.h>
+#include <sbi/sbi_platform.h>
+
+const struct sbi_platform_operations platform_ops = {
+ .pmp_region_count = NULL,
+ .pmp_region_info = NULL,
+ .final_init = NULL,
+ .console_putc = NULL,
+ .console_getc = NULL,
+ .console_init = NULL,
+ .irqchip_init = NULL,
+ .ipi_send = NULL,
+ .ipi_clear = NULL,
+ .ipi_init = NULL,
+ .timer_value = NULL,
+ .timer_event_stop = NULL,
+ .timer_event_start = NULL,
+ .timer_init = NULL,
+ .system_reboot = NULL,
+ .system_shutdown = NULL
+};
+
+const struct sbi_platform platform = {
+ .opensbi_version = OPENSBI_VERSION, // The OpenSBI version this platform table is built bassed on.
+ .platform_version = SBI_PLATFORM_VERSION(0x0000, 0x0000), // SBI Platform version 1.0
+ .name = "NULL platform",
+ .features = 0,
+ .hart_count = 0,
+ .hart_stack_size = 0,
+ .disabled_hart_mask = 0,
+ .platform_ops_addr = 0
+};
--
2.31.1
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH 16/79] PlatformPkg/Library: NULL instance of PlatformMemoryTestLib
2022-01-08 4:10 [PATCH 02/79] ProcessorPkg/Library: RISC-V CPU library Abner Chang
` (12 preceding siblings ...)
2022-01-08 4:10 ` [PATCH 15/79] PlatformPkg/Library: NULL instance of RiscVOpensbiPlatformLib Abner Chang
@ 2022-01-08 4:10 ` Abner Chang
2022-01-08 4:10 ` [PATCH 17/79] PlatformPkg/Library: NULL instance of PlatformUpdateProgressLib Abner Chang
` (23 subsequent siblings)
37 siblings, 0 replies; 39+ messages in thread
From: Abner Chang @ 2022-01-08 4:10 UTC (permalink / raw)
To: devel; +Cc: abner.chang
(This is migrated from edk2-platforms:Platform/RISC-V)
NULL instance of PlatformMemoryTestLib.
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Co-authored-by: Gilbert Chen <gilbert.chen@hpe.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>
---
.../PlatformMemoryTestLibNull.inf | 29 +++++++++++++++++++
.../PlatformMemoryTestLibNull.c | 29 +++++++++++++++++++
2 files changed, 58 insertions(+)
create mode 100644 Platform/RISC-V/PlatformPkg/Library/PlatformMemoryTestLibNull/PlatformMemoryTestLibNull.inf
create mode 100644 Platform/RISC-V/PlatformPkg/Library/PlatformMemoryTestLibNull/PlatformMemoryTestLibNull.c
diff --git a/Platform/RISC-V/PlatformPkg/Library/PlatformMemoryTestLibNull/PlatformMemoryTestLibNull.inf b/Platform/RISC-V/PlatformPkg/Library/PlatformMemoryTestLibNull/PlatformMemoryTestLibNull.inf
new file mode 100644
index 0000000000..a1b503ebc2
--- /dev/null
+++ b/Platform/RISC-V/PlatformPkg/Library/PlatformMemoryTestLibNull/PlatformMemoryTestLibNull.inf
@@ -0,0 +1,29 @@
+#/** @file
+#
+# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#**/
+
+[Defines]
+ INF_VERSION = 0x0001001b
+ BASE_NAME = PlatformMemoryTestLibNull
+ FILE_GUID = 81EE52ED-3C6A-4A42-9564-5676766F5CE6
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = PlatformMemoryTestLib
+
+[Sources.common]
+ PlatformMemoryTestLibNull.c
+
+[Packages]
+ MdeModulePkg/MdeModulePkg.dec
+ MdePkg/MdePkg.dec
+
+[LibraryClasses]
+ UefiLib
+ DebugLib
+
+[Pcd]
+
diff --git a/Platform/RISC-V/PlatformPkg/Library/PlatformMemoryTestLibNull/PlatformMemoryTestLibNull.c b/Platform/RISC-V/PlatformPkg/Library/PlatformMemoryTestLibNull/PlatformMemoryTestLibNull.c
new file mode 100644
index 0000000000..9246070787
--- /dev/null
+++ b/Platform/RISC-V/PlatformPkg/Library/PlatformMemoryTestLibNull/PlatformMemoryTestLibNull.c
@@ -0,0 +1,29 @@
+/** @file
+ Platform Memory Test NULL library
+
+ Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Uefi.h>
+#include <Protocol/GenericMemoryTest.h>
+
+/**
+ Perform the memory test base on the memory test intensive level,
+ and update the memory resource.
+
+ @param Level The memory test intensive level.
+
+ @retval EFI_STATUS Success test all the system memory and update
+ the memory resource
+
+**/
+EFI_STATUS
+PlatformBootManagerMemoryTest (
+ IN EXTENDMEM_COVERAGE_LEVEL Level
+ )
+{
+ return EFI_SUCCESS;
+}
--
2.31.1
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH 17/79] PlatformPkg/Library: NULL instance of PlatformUpdateProgressLib
2022-01-08 4:10 [PATCH 02/79] ProcessorPkg/Library: RISC-V CPU library Abner Chang
` (13 preceding siblings ...)
2022-01-08 4:10 ` [PATCH 16/79] PlatformPkg/Library: NULL instance of PlatformMemoryTestLib Abner Chang
@ 2022-01-08 4:10 ` Abner Chang
2022-01-08 4:10 ` [PATCH 18/79] PlatformPkg/Library: Platform Boot Manager library Abner Chang
` (22 subsequent siblings)
37 siblings, 0 replies; 39+ messages in thread
From: Abner Chang @ 2022-01-08 4:10 UTC (permalink / raw)
To: devel; +Cc: abner.chang
(This is migrated from edk2-platforms:Platform/RISC-V)
NULL instance of PlatformUpdateProgressLib.
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Co-authored-by: Gilbert Chen <gilbert.chen@hpe.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>
---
.../PlatformUpdateProgressLibNull.inf | 29 +++++++++++
.../PlatformUpdateProgressLibNull.c | 52 +++++++++++++++++++
2 files changed, 81 insertions(+)
create mode 100644 Platform/RISC-V/PlatformPkg/Library/PlatformUpdateProgressLibNull/PlatformUpdateProgressLibNull.inf
create mode 100644 Platform/RISC-V/PlatformPkg/Library/PlatformUpdateProgressLibNull/PlatformUpdateProgressLibNull.c
diff --git a/Platform/RISC-V/PlatformPkg/Library/PlatformUpdateProgressLibNull/PlatformUpdateProgressLibNull.inf b/Platform/RISC-V/PlatformPkg/Library/PlatformUpdateProgressLibNull/PlatformUpdateProgressLibNull.inf
new file mode 100644
index 0000000000..fdba00c053
--- /dev/null
+++ b/Platform/RISC-V/PlatformPkg/Library/PlatformUpdateProgressLibNull/PlatformUpdateProgressLibNull.inf
@@ -0,0 +1,29 @@
+#/** @file
+#
+# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#**/
+
+[Defines]
+ INF_VERSION = 0x0001001b
+ BASE_NAME = PlatformUpdateProgressLibNull
+ FILE_GUID = BFC3E25A-8AD0-4201-8A75-F00DE7964370
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = PlatformUpdateProgressLib
+
+[Sources.common]
+ PlatformUpdateProgressLibNull.c
+
+[Packages]
+ MdeModulePkg/MdeModulePkg.dec
+ MdePkg/MdePkg.dec
+
+[LibraryClasses]
+ UefiLib
+ DebugLib
+
+[Pcd]
+
diff --git a/Platform/RISC-V/PlatformPkg/Library/PlatformUpdateProgressLibNull/PlatformUpdateProgressLibNull.c b/Platform/RISC-V/PlatformPkg/Library/PlatformUpdateProgressLibNull/PlatformUpdateProgressLibNull.c
new file mode 100644
index 0000000000..6b0bd056cc
--- /dev/null
+++ b/Platform/RISC-V/PlatformPkg/Library/PlatformUpdateProgressLibNull/PlatformUpdateProgressLibNull.c
@@ -0,0 +1,52 @@
+/** @file
+ Platform Update Progress NULL library
+
+ Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Uefi.h>
+#include <Protocol/GenericMemoryTest.h>
+#include <Protocol/GraphicsOutput.h>
+
+/**
+ This function is called each second during the boot manager waits the timeout.
+
+ @param TimeoutRemain The remaining timeout.
+**/
+VOID
+EFIAPI
+PlatformBootManagerWaitCallback (
+ UINT16 TimeoutRemain
+ )
+{
+ return;
+}
+/**
+
+ Show progress bar with title above it. It only works in Graphics mode.
+
+ @param TitleForeground Foreground color for Title.
+ @param TitleBackground Background color for Title.
+ @param Title Title above progress bar.
+ @param ProgressColor Progress bar color.
+ @param Progress Progress (0-100)
+ @param PreviousValue The previous value of the progress.
+
+ @retval EFI_STATUS Success update the progress bar
+
+**/
+EFI_STATUS
+PlatformBootManagerShowProgress (
+ IN EFI_GRAPHICS_OUTPUT_BLT_PIXEL TitleForeground,
+ IN EFI_GRAPHICS_OUTPUT_BLT_PIXEL TitleBackground,
+ IN CHAR16 *Title,
+ IN EFI_GRAPHICS_OUTPUT_BLT_PIXEL ProgressColor,
+ IN UINTN Progress,
+ IN UINTN PreviousValue
+ )
+{
+ return EFI_SUCCESS;
+}
--
2.31.1
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH 18/79] PlatformPkg/Library: Platform Boot Manager library.
2022-01-08 4:10 [PATCH 02/79] ProcessorPkg/Library: RISC-V CPU library Abner Chang
` (14 preceding siblings ...)
2022-01-08 4:10 ` [PATCH 17/79] PlatformPkg/Library: NULL instance of PlatformUpdateProgressLib Abner Chang
@ 2022-01-08 4:10 ` Abner Chang
2022-01-08 4:10 ` [PATCH 19/79] PlatformPkg/SecMain: RISC-V SecMain module Abner Chang
` (21 subsequent siblings)
37 siblings, 0 replies; 39+ messages in thread
From: Abner Chang @ 2022-01-08 4:10 UTC (permalink / raw)
To: devel; +Cc: abner.chang
(This is migrated from edk2-platforms:Platform/RISC-V)
Common Platform Boot Manager library for RISC-V platform.
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Co-authored-by: Gilbert Chen <gilbert.chen@hpe.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>
---
.../PlatformBootManagerLib.inf | 61 +++++
.../PlatformBootManager.h | 117 +++++++++
.../PlatformBootManager.c | 243 ++++++++++++++++++
.../PlatformBootManagerLib/PlatformData.c | 49 ++++
.../PlatformBootManagerLib/Strings.uni | 28 ++
5 files changed, 498 insertions(+)
create mode 100644 Platform/RISC-V/PlatformPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
create mode 100644 Platform/RISC-V/PlatformPkg/Library/PlatformBootManagerLib/PlatformBootManager.h
create mode 100644 Platform/RISC-V/PlatformPkg/Library/PlatformBootManagerLib/PlatformBootManager.c
create mode 100644 Platform/RISC-V/PlatformPkg/Library/PlatformBootManagerLib/PlatformData.c
create mode 100644 Platform/RISC-V/PlatformPkg/Library/PlatformBootManagerLib/Strings.uni
diff --git a/Platform/RISC-V/PlatformPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf b/Platform/RISC-V/PlatformPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
new file mode 100644
index 0000000000..afba07573f
--- /dev/null
+++ b/Platform/RISC-V/PlatformPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
@@ -0,0 +1,61 @@
+## @file
+# Include all platform action which can be customized by IBV/OEM.
+#
+# Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001b
+ BASE_NAME = PlatformBootManagerLib
+ FILE_GUID = 7DDA7916-6139-4D46-A415-30E854AF3BC7
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = PlatformBootManagerLib|DXE_DRIVER
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = RISCV64
+#
+
+[Sources]
+ PlatformData.c
+ PlatformBootManager.c
+ PlatformBootManager.h
+ Strings.uni
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec
+
+[LibraryClasses]
+ BaseLib
+ UefiBootServicesTableLib
+ UefiRuntimeServicesTableLib
+ UefiLib
+ UefiBootManagerLib
+ PcdLib
+ PlatformMemoryTestLib
+ PlatformUpdateProgressLib
+ DxeServicesLib
+ MemoryAllocationLib
+ DevicePathLib
+ HiiLib
+ PrintLib
+
+[Guids]
+
+[Protocols]
+ gEfiGenericMemTestProtocolGuid ## CONSUMES
+ gEfiGraphicsOutputProtocolGuid ## CONSUMES
+
+[Pcd]
+ gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut
+ gEfiMdeModulePkgTokenSpaceGuid.PcdConOutRow
+ gEfiMdeModulePkgTokenSpaceGuid.PcdConOutColumn
+ gEfiMdeModulePkgTokenSpaceGuid.PcdConInConnectOnDemand
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootlogoOnlyEnable
diff --git a/Platform/RISC-V/PlatformPkg/Library/PlatformBootManagerLib/PlatformBootManager.h b/Platform/RISC-V/PlatformPkg/Library/PlatformBootManagerLib/PlatformBootManager.h
new file mode 100644
index 0000000000..58c363a48b
--- /dev/null
+++ b/Platform/RISC-V/PlatformPkg/Library/PlatformBootManagerLib/PlatformBootManager.h
@@ -0,0 +1,117 @@
+/**@file
+ Head file for BDS Platform specific code
+
+Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
+
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef PLATFORM_BOOT_MANAGER_H_
+#define PLATFORM_BOOT_MANAGER_H_
+
+#include <PiDxe.h>
+#include <IndustryStandard/Bmp.h>
+#include <Protocol/GenericMemoryTest.h>
+#include <Protocol/LoadedImage.h>
+#include <Protocol/GraphicsOutput.h>
+#include <Protocol/BootLogo.h>
+#include <Protocol/DevicePath.h>
+
+#include <Library/DebugLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiRuntimeServicesTableLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/BaseLib.h>
+#include <Library/UefiLib.h>
+#include <Library/UefiBootManagerLib.h>
+#include <Library/PcdLib.h>
+#include <Library/DevicePathLib.h>
+#include <Library/HiiLib.h>
+#include <Library/PrintLib.h>
+
+typedef struct {
+ EFI_DEVICE_PATH_PROTOCOL *DevicePath;
+ UINTN ConnectType;
+} PLATFORM_CONSOLE_CONNECT_ENTRY;
+
+extern PLATFORM_CONSOLE_CONNECT_ENTRY gPlatformConsole[];
+
+#define gEndEntire \
+ { \
+ END_DEVICE_PATH_TYPE,\
+ END_ENTIRE_DEVICE_PATH_SUBTYPE,\
+ END_DEVICE_PATH_LENGTH,\
+ 0\
+ }
+
+#define CONSOLE_OUT BIT0
+#define CONSOLE_IN BIT1
+#define STD_ERROR BIT2
+
+//D3987D4B-971A-435F-8CAF-4967EB627241
+#define EFI_SERIAL_DXE_GUID \
+ { 0xD3987D4B, 0x971A, 0x435F, { 0x8C, 0xAF, 0x49, 0x67, 0xEB, 0x62, 0x72, 0x41 } }
+
+typedef struct {
+ VENDOR_DEVICE_PATH Guid;
+ UART_DEVICE_PATH Uart;
+ VENDOR_DEVICE_PATH TerminalType;
+ EFI_DEVICE_PATH_PROTOCOL End;
+} SERIAL_CONSOLE_DEVICE_PATH;
+
+/**
+ Use SystemTable Conout to turn on video based Simple Text Out consoles. The
+ Simple Text Out screens will now be synced up with all non video output devices
+
+ @retval EFI_SUCCESS UGA devices are back in text mode and synced up.
+
+**/
+EFI_STATUS
+PlatformBootManagerDisableQuietBoot (
+ VOID
+ );
+
+/**
+ Perform the memory test base on the memory test intensive level,
+ and update the memory resource.
+
+ @param Level The memory test intensive level.
+
+ @retval EFI_STATUS Success test all the system memory and update
+ the memory resource
+
+**/
+EFI_STATUS
+PlatformBootManagerMemoryTest (
+ IN EXTENDMEM_COVERAGE_LEVEL Level
+ );
+
+/**
+
+ Show progress bar with title above it. It only works in Graphics mode.
+
+
+ @param TitleForeground Foreground color for Title.
+ @param TitleBackground Background color for Title.
+ @param Title Title above progress bar.
+ @param ProgressColor Progress bar color.
+ @param Progress Progress (0-100)
+ @param PreviousValue The previous value of the progress.
+
+ @retval EFI_STATUS Success update the progress bar
+
+**/
+EFI_STATUS
+PlatformBootManagerShowProgress (
+ IN EFI_GRAPHICS_OUTPUT_BLT_PIXEL TitleForeground,
+ IN EFI_GRAPHICS_OUTPUT_BLT_PIXEL TitleBackground,
+ IN CHAR16 *Title,
+ IN EFI_GRAPHICS_OUTPUT_BLT_PIXEL ProgressColor,
+ IN UINTN Progress,
+ IN UINTN PreviousValue
+ );
+
+#endif // _PLATFORM_BOOT_MANAGER_H
diff --git a/Platform/RISC-V/PlatformPkg/Library/PlatformBootManagerLib/PlatformBootManager.c b/Platform/RISC-V/PlatformPkg/Library/PlatformBootManagerLib/PlatformBootManager.c
new file mode 100644
index 0000000000..82cd311df5
--- /dev/null
+++ b/Platform/RISC-V/PlatformPkg/Library/PlatformBootManagerLib/PlatformBootManager.c
@@ -0,0 +1,243 @@
+/** @file
+ This file include all platform actions
+
+Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
+
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "PlatformBootManager.h"
+
+
+EFI_GUID mUefiShellFileGuid = { 0x7C04A583, 0x9E3E, 0x4f1c, {0xAD, 0x65, 0xE0, 0x52, 0x68, 0xD0, 0xB4, 0xD1}};
+
+/**
+ Perform the platform diagnostic, such like test memory. OEM/IBV also
+ can customize this function to support specific platform diagnostic.
+
+ @param MemoryTestLevel The memory test intensive level
+ @param QuietBoot Indicate if need to enable the quiet boot
+
+**/
+VOID
+PlatformBootManagerDiagnostics (
+ IN EXTENDMEM_COVERAGE_LEVEL MemoryTestLevel,
+ IN BOOLEAN QuietBoot
+ )
+{
+ EFI_STATUS Status;
+
+ //
+ // Here we can decide if we need to show
+ // the diagnostics screen
+ // Notes: this quiet boot code should be remove
+ // from the graphic lib
+ //
+ if (QuietBoot) {
+
+ //
+ // Perform system diagnostic
+ //
+ Status = PlatformBootManagerMemoryTest (MemoryTestLevel);
+ return;
+ }
+
+ //
+ // Perform system diagnostic
+ //
+ Status = PlatformBootManagerMemoryTest (MemoryTestLevel);
+}
+
+/**
+ Return the index of the load option in the load option array.
+
+ The function consider two load options are equal when the
+ OptionType, Attributes, Description, FilePath and OptionalData are equal.
+
+ @param Key Pointer to the load option to be found.
+ @param Array Pointer to the array of load options to be found.
+ @param Count Number of entries in the Array.
+
+ @retval -1 Key wasn't found in the Array.
+ @retval 0 ~ Count-1 The index of the Key in the Array.
+**/
+INTN
+PlatformFindLoadOption (
+ IN CONST EFI_BOOT_MANAGER_LOAD_OPTION *Key,
+ IN CONST EFI_BOOT_MANAGER_LOAD_OPTION *Array,
+ IN UINTN Count
+ )
+{
+ UINTN Index;
+
+ for (Index = 0; Index < Count; Index++) {
+ if ((Key->OptionType == Array[Index].OptionType) &&
+ (Key->Attributes == Array[Index].Attributes) &&
+ (StrCmp (Key->Description, Array[Index].Description) == 0) &&
+ (CompareMem (Key->FilePath, Array[Index].FilePath, GetDevicePathSize (Key->FilePath)) == 0) &&
+ (Key->OptionalDataSize == Array[Index].OptionalDataSize) &&
+ (CompareMem (Key->OptionalData, Array[Index].OptionalData, Key->OptionalDataSize) == 0)) {
+ return (INTN) Index;
+ }
+ }
+
+ return -1;
+}
+
+VOID
+PlatformRegisterFvBootOption (
+ EFI_GUID *FileGuid,
+ CHAR16 *Description,
+ UINT32 Attributes
+ )
+{
+ EFI_STATUS Status;
+ UINTN OptionIndex;
+ EFI_BOOT_MANAGER_LOAD_OPTION NewOption;
+ EFI_BOOT_MANAGER_LOAD_OPTION *BootOptions;
+ UINTN BootOptionCount;
+ MEDIA_FW_VOL_FILEPATH_DEVICE_PATH FileNode;
+ EFI_LOADED_IMAGE_PROTOCOL *LoadedImage;
+ EFI_DEVICE_PATH_PROTOCOL *DevicePath;
+
+ Status = gBS->HandleProtocol (gImageHandle, &gEfiLoadedImageProtocolGuid, (VOID **) &LoadedImage);
+ ASSERT_EFI_ERROR (Status);
+
+ EfiInitializeFwVolDevicepathNode (&FileNode, FileGuid);
+ DevicePath = AppendDevicePathNode (
+ DevicePathFromHandle (LoadedImage->DeviceHandle),
+ (EFI_DEVICE_PATH_PROTOCOL *) &FileNode
+ );
+
+ Status = EfiBootManagerInitializeLoadOption (
+ &NewOption,
+ LoadOptionNumberUnassigned,
+ LoadOptionTypeBoot,
+ Attributes,
+ Description,
+ DevicePath,
+ NULL,
+ 0
+ );
+ if (!EFI_ERROR (Status)) {
+ BootOptions = EfiBootManagerGetLoadOptions (&BootOptionCount, LoadOptionTypeBoot);
+
+ OptionIndex = PlatformFindLoadOption (&NewOption, BootOptions, BootOptionCount);
+
+ if (OptionIndex == -1) {
+ Status = EfiBootManagerAddLoadOptionVariable (&NewOption, (UINTN) -1);
+ ASSERT_EFI_ERROR (Status);
+ }
+ EfiBootManagerFreeLoadOption (&NewOption);
+ EfiBootManagerFreeLoadOptions (BootOptions, BootOptionCount);
+ }
+}
+
+/**
+ Do the platform specific action before the console is connected.
+
+ Such as:
+ Update console variable;
+ Register new Driver#### or Boot####;
+ Signal ReadyToLock event.
+**/
+VOID
+EFIAPI
+PlatformBootManagerBeforeConsole (
+ VOID
+ )
+{
+ UINTN Index;
+ EFI_STATUS Status;
+ EFI_INPUT_KEY Enter;
+ EFI_INPUT_KEY F2;
+ EFI_BOOT_MANAGER_LOAD_OPTION BootOption;
+
+ //
+ // Update the console variables.
+ //
+ for (Index = 0; gPlatformConsole[Index].DevicePath != NULL; Index++) {
+ DEBUG ((DEBUG_INFO, "Check gPlatformConsole %d\n", Index));
+ if ((gPlatformConsole[Index].ConnectType & CONSOLE_IN) == CONSOLE_IN) {
+ Status = EfiBootManagerUpdateConsoleVariable (ConIn, gPlatformConsole[Index].DevicePath, NULL);
+ DEBUG ((DEBUG_INFO, "CONSOLE_IN variable set %s : %r\n", ConvertDevicePathToText (gPlatformConsole[Index].DevicePath, FALSE, FALSE), Status));
+ }
+
+ if ((gPlatformConsole[Index].ConnectType & CONSOLE_OUT) == CONSOLE_OUT) {
+ Status = EfiBootManagerUpdateConsoleVariable (ConOut, gPlatformConsole[Index].DevicePath, NULL);
+ DEBUG ((DEBUG_INFO, "CONSOLE_OUT variable set %s : %r\n", ConvertDevicePathToText (gPlatformConsole[Index].DevicePath, FALSE, FALSE), Status));
+ }
+
+ if ((gPlatformConsole[Index].ConnectType & STD_ERROR) == STD_ERROR) {
+ Status = EfiBootManagerUpdateConsoleVariable (ErrOut, gPlatformConsole[Index].DevicePath, NULL);
+ DEBUG ((DEBUG_INFO, "STD_ERROR variable set %r", Status));
+ }
+ }
+
+ //
+ // Register ENTER as CONTINUE key
+ //
+ Enter.ScanCode = SCAN_NULL;
+ Enter.UnicodeChar = CHAR_CARRIAGE_RETURN;
+ EfiBootManagerRegisterContinueKeyOption (0, &Enter, NULL);
+ //
+ // Map F2 to Boot Manager Menu
+ //
+ F2.ScanCode = SCAN_F2;
+ F2.UnicodeChar = CHAR_NULL;
+ EfiBootManagerGetBootManagerMenu (&BootOption);
+ EfiBootManagerAddKeyOptionVariable (NULL, (UINT16) BootOption.OptionNumber, 0, &F2, NULL);
+ //
+ // Register UEFI Shell
+ //
+ PlatformRegisterFvBootOption (&mUefiShellFileGuid, L"UEFI Shell", LOAD_OPTION_ACTIVE);
+}
+
+/**
+ Do the platform specific action after the console is connected.
+
+ Such as:
+ Dynamically switch output mode;
+ Signal console ready platform customized event;
+ Run diagnostics like memory testing;
+ Connect certain devices;
+ Dispatch aditional option roms.
+**/
+VOID
+EFIAPI
+PlatformBootManagerAfterConsole (
+ VOID
+ )
+{
+ EFI_GRAPHICS_OUTPUT_BLT_PIXEL Black;
+ EFI_GRAPHICS_OUTPUT_BLT_PIXEL White;
+
+ Black.Blue = Black.Green = Black.Red = Black.Reserved = 0;
+ White.Blue = White.Green = White.Red = White.Reserved = 0xFF;
+
+ EfiBootManagerConnectAll ();
+ EfiBootManagerRefreshAllBootOption ();
+
+ PlatformBootManagerDiagnostics (QUICK, TRUE);
+
+ PrintXY (10, 10, &White, &Black, L"F2 to enter Boot Manager Menu. ");
+ PrintXY (10, 30, &White, &Black, L"Enter to boot directly.");
+}
+
+/**
+ The function is called when no boot option could be launched,
+ including platform recovery options and options pointing to applications
+ built into firmware volumes.
+
+ If this function returns, BDS attempts to enter an infinite loop.
+**/
+VOID
+EFIAPI
+PlatformBootManagerUnableToBoot (
+ VOID
+ )
+{
+ return;
+}
diff --git a/Platform/RISC-V/PlatformPkg/Library/PlatformBootManagerLib/PlatformData.c b/Platform/RISC-V/PlatformPkg/Library/PlatformBootManagerLib/PlatformData.c
new file mode 100644
index 0000000000..3208051e16
--- /dev/null
+++ b/Platform/RISC-V/PlatformPkg/Library/PlatformBootManagerLib/PlatformData.c
@@ -0,0 +1,49 @@
+/**@file
+ Defined the platform specific device path which will be filled to
+ ConIn/ConOut variables.
+
+Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
+
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "PlatformBootManager.h"
+
+//
+// Platform specific serial device path
+//
+SERIAL_CONSOLE_DEVICE_PATH gSerialConsoleDevicePath0 = {
+ {
+ { HARDWARE_DEVICE_PATH, HW_VENDOR_DP, { sizeof (VENDOR_DEVICE_PATH), 0} },
+ EFI_SERIAL_DXE_GUID // Use the driver's GUID
+ },
+ {
+ { MESSAGING_DEVICE_PATH, MSG_UART_DP, { sizeof (UART_DEVICE_PATH), 0} },
+ 0, // Reserved
+ 115200, // BaudRate
+ 8, // DataBits
+ 1, // Parity
+ 1 // StopBits
+ },
+ {
+ { MESSAGING_DEVICE_PATH, MSG_VENDOR_DP, { sizeof (VENDOR_DEVICE_PATH), 0} },
+ DEVICE_PATH_MESSAGING_PC_ANSI
+ },
+ { END_DEVICE_PATH_TYPE, END_ENTIRE_DEVICE_PATH_SUBTYPE, { sizeof (EFI_DEVICE_PATH_PROTOCOL), 0 } }
+};
+
+//
+// Predefined platform default console device path
+//
+PLATFORM_CONSOLE_CONNECT_ENTRY gPlatformConsole[] = {
+ {
+ (EFI_DEVICE_PATH_PROTOCOL *) &gSerialConsoleDevicePath0,
+ CONSOLE_OUT | CONSOLE_IN
+ },
+ {
+ NULL,
+ 0
+ }
+};
diff --git a/Platform/RISC-V/PlatformPkg/Library/PlatformBootManagerLib/Strings.uni b/Platform/RISC-V/PlatformPkg/Library/PlatformBootManagerLib/Strings.uni
new file mode 100644
index 0000000000..357cced6d7
--- /dev/null
+++ b/Platform/RISC-V/PlatformPkg/Library/PlatformBootManagerLib/Strings.uni
@@ -0,0 +1,28 @@
+///** @file
+//
+// String definitions for PlatformBootManagerLib.
+//
+// Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+// Copyright (c) 2004 - 2015, Intel Corporation. All rights reserved.<BR>
+//
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+//**/
+
+/=#
+
+#langdef en-US "English"
+#langdef fr-FR "Français"
+
+#string STR_PERFORM_MEM_TEST #language en-US "Perform memory test (ESC to skip)"
+ #language fr-FR "Exécute l'examen de mémoire (ESC pour sauter)"
+#string STR_MEMORY_TEST_PERCENT #language en-US "% of the system memory tested OK"
+ #language fr-FR "% de la mémoire de système essayée D'ACCORD"
+#string STR_ESC_TO_SKIP_MEM_TEST #language en-US "Press ESC key to skip memory test"
+ #language fr-FR "Appuie sur ESC sauter examen de mémoire"
+#string STR_MEM_TEST_COMPLETED #language en-US " bytes of system memory tested OK\r\n"
+ #language fr-FR " octets dela mémoire de système essayée D'ACCORD\r\n"
+#string STR_SYSTEM_MEM_ERROR #language en-US "System encounters memory errors"
+ #language fr-FR "le Système rencontre les erreurs de mémoire"
+#string STR_START_BOOT_OPTION #language en-US "Start boot option"
+ #language fr-FR "l'option de botte de Début"
--
2.31.1
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH 19/79] PlatformPkg/SecMain: RISC-V SecMain module.
2022-01-08 4:10 [PATCH 02/79] ProcessorPkg/Library: RISC-V CPU library Abner Chang
` (15 preceding siblings ...)
2022-01-08 4:10 ` [PATCH 18/79] PlatformPkg/Library: Platform Boot Manager library Abner Chang
@ 2022-01-08 4:10 ` Abner Chang
2022-01-08 4:10 ` [PATCH 20/79] PlatformPkg: Add RiscVPlatformPkg Abner Chang
` (20 subsequent siblings)
37 siblings, 0 replies; 39+ messages in thread
From: Abner Chang @ 2022-01-08 4:10 UTC (permalink / raw)
To: devel; +Cc: abner.chang
(This is migrated from edk2-platforms:Platform/RISC-V)
SecMain module for RISC-V platform.
This was cloned from OpenSBI fw_base.S
(RiscVPkg/Library/RiscVOpensbiLib/opensbi/firmware/) and revised to
edk2 framework.
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Co-authored-by: Daniel Schaefer <daniel.schaefer@hpe.com>
Co-authored-by: Gilbert Chen <gilbert.chen@hpe.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>
---
.../PlatformPkg/Universal/Sec/SecMain.inf | 77 ++
.../PlatformPkg/Universal/Sec/SecMain.h | 57 ++
.../PlatformPkg/Universal/Sec/SecMain.c | 733 ++++++++++++++++++
.../Universal/Sec/Riscv64/SecEntry.S | 532 +++++++++++++
4 files changed, 1399 insertions(+)
create mode 100644 Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf
create mode 100644 Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.h
create mode 100644 Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c
create mode 100644 Platform/RISC-V/PlatformPkg/Universal/Sec/Riscv64/SecEntry.S
diff --git a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf
new file mode 100644
index 0000000000..89bcb039a6
--- /dev/null
+++ b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf
@@ -0,0 +1,77 @@
+## @file
+# RISC-V SEC module.
+#
+# Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001b
+ BASE_NAME = SecMain
+ FILE_GUID = 743467B0-849F-4ACE-9BFB-515CE6206388
+ MODULE_TYPE = SEC
+ VERSION_STRING = 1.0
+ ENTRY_POINT = SecMain
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = RISCV64
+#
+
+[Sources]
+ SecMain.c
+
+[Sources.RISCV64]
+ Riscv64/SecEntry.S
+
+[Packages]
+ MdeModulePkg/MdeModulePkg.dec
+ MdePkg/MdePkg.dec
+ Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec
+ Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec
+
+[LibraryClasses]
+ BaseLib
+ BaseMemoryLib
+ DebugAgentLib
+ DebugLib
+ ExtractGuidedSectionLib
+ IoLib
+ PcdLib
+ PeCoffLib
+ PeCoffGetEntryPointLib
+ PeCoffExtraActionLib
+ PrintLib
+ RiscVCpuLib
+ RiscVOpensbiLib
+ RiscVOpensbiPlatformLib
+ RiscVEdk2SbiLib
+
+[Ppis]
+ gEfiTemporaryRamSupportPpiGuid # PPI ALWAYS_PRODUCED
+ gEfiTemporaryRamDonePpiGuid # PPI ALWAYS_PRODUCED
+
+[FixedPcd]
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVPeiFvBase
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVPeiFvSize
+
+[Pcd]
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootHartId
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdHartCount
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootableHartNumber
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFwStartAddress
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFwEndAddress
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdOpenSbiStackSize
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdScratchRamBase
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdScratchRamSize
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdTemporaryRamBase
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdTemporaryRamSize
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPeiCorePrivilegeMode
+
+[BuildOptions]
+ GCC:*_*_*_PP_FLAGS = -D__ASSEMBLY__
+
+
diff --git a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.h b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.h
new file mode 100644
index 0000000000..94ea46263c
--- /dev/null
+++ b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.h
@@ -0,0 +1,57 @@
+/** @file
+ RISC-V SEC phase module definitions..
+
+ Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef SECMAIN_H_
+#define SECMAIN_H_
+
+#include <PiPei.h>
+#include <Library/PeimEntryPoint.h>
+#include <Library/BaseLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugAgentLib.h>
+#include <Library/DebugLib.h>
+#include <Library/ExtractGuidedSectionLib.h>
+#include <Library/IoLib.h>
+#include <Library/HobLib.h>
+#include <Library/PcdLib.h>
+#include <Library/PeCoffExtraActionLib.h>
+#include <Library/PeCoffGetEntryPointLib.h>
+#include <Library/PeCoffLib.h>
+#include <Library/PeiServicesLib.h>
+#include <Library/RiscVCpuLib.h>
+#include <Ppi/TemporaryRamDone.h>
+#include <Ppi/TemporaryRamSupport.h>
+
+VOID
+SecMachineModeTrapHandler (
+ IN VOID
+ );
+
+VOID
+EFIAPI
+SecStartupPhase2 (
+ IN VOID *Context
+ );
+
+EFI_STATUS
+EFIAPI
+TemporaryRamMigration (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PHYSICAL_ADDRESS TemporaryMemoryBase,
+ IN EFI_PHYSICAL_ADDRESS PermanentMemoryBase,
+ IN UINTN CopySize
+ );
+
+EFI_STATUS
+EFIAPI
+TemporaryRamDone (
+ VOID
+ );
+
+#endif // _SECMAIN_H_
diff --git a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c
new file mode 100644
index 0000000000..877777bfa1
--- /dev/null
+++ b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c
@@ -0,0 +1,733 @@
+/** @file
+ RISC-V SEC phase module.
+
+ Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <SecMain.h>
+#include <IndustryStandard/RiscVOpensbi.h>
+#include <Library/DebugPrintErrorLevelLib.h>
+#include <Library/PrintLib.h>
+#include <Library/RiscVEdk2SbiLib.h>
+#include <sbi/riscv_asm.h>
+#include <sbi/riscv_atomic.h>
+#include <sbi/sbi_console.h> // Reference to header file in opensbi
+#include <sbi/sbi_hart.h> // Reference to header file in opensbi
+#include <sbi/sbi_hartmask.h> // Reference to header file in opensbi
+#include <sbi/sbi_scratch.h> // Reference to header file in opensbi
+#include <sbi/sbi_platform.h> // Reference to header file in opensbi
+#include <sbi/sbi_init.h> // Reference to header file in opensbi
+#include <sbi/sbi_ecall.h> // Reference to header file in opensbi
+
+//
+// Indicates the boot hart (PcdBootHartId) OpenSBI initialization is done.
+//
+atomic_t BootHartDone = ATOMIC_INITIALIZER(0);
+atomic_t NonBootHartMessageLock = ATOMIC_INITIALIZER(0);
+
+typedef struct sbi_scratch *(*hartid2scratch)(ulong hartid, ulong hartindex);
+
+STATIC EFI_PEI_TEMPORARY_RAM_SUPPORT_PPI mTemporaryRamSupportPpi = {
+ TemporaryRamMigration
+};
+
+STATIC EFI_PEI_TEMPORARY_RAM_DONE_PPI mTemporaryRamDonePpi = {
+ TemporaryRamDone
+};
+
+STATIC EFI_PEI_PPI_DESCRIPTOR mPrivateDispatchTable[] = {
+ {
+ EFI_PEI_PPI_DESCRIPTOR_PPI,
+ &gEfiTemporaryRamSupportPpiGuid,
+ &mTemporaryRamSupportPpi
+ },
+ {
+ (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
+ &gEfiTemporaryRamDonePpiGuid,
+ &mTemporaryRamDonePpi
+ },
+};
+
+/**
+ Locates a section within a series of sections
+ with the specified section type.
+
+ The Instance parameter indicates which instance of the section
+ type to return. (0 is first instance, 1 is second...)
+
+ @param[in] Sections The sections to search
+ @param[in] SizeOfSections Total size of all sections
+ @param[in] SectionType The section type to locate
+ @param[in] Instance The section instance number
+ @param[out] FoundSection The FFS section if found
+
+ @retval EFI_SUCCESS The file and section was found
+ @retval EFI_NOT_FOUND The file and section was not found
+ @retval EFI_VOLUME_CORRUPTED The firmware volume was corrupted
+
+**/
+EFI_STATUS
+FindFfsSectionInstance (
+ IN VOID *Sections,
+ IN UINTN SizeOfSections,
+ IN EFI_SECTION_TYPE SectionType,
+ IN UINTN Instance,
+ OUT EFI_COMMON_SECTION_HEADER **FoundSection
+ )
+{
+ EFI_PHYSICAL_ADDRESS CurrentAddress;
+ UINT32 Size;
+ EFI_PHYSICAL_ADDRESS EndOfSections;
+ EFI_COMMON_SECTION_HEADER *Section;
+ EFI_PHYSICAL_ADDRESS EndOfSection;
+
+ //
+ // Loop through the FFS file sections within the PEI Core FFS file
+ //
+ EndOfSection = (EFI_PHYSICAL_ADDRESS)(UINTN) Sections;
+ EndOfSections = EndOfSection + SizeOfSections;
+ for (;;) {
+ if (EndOfSection == EndOfSections) {
+ break;
+ }
+ CurrentAddress = (EndOfSection + 3) & ~(3ULL);
+ if (CurrentAddress >= EndOfSections) {
+ return EFI_VOLUME_CORRUPTED;
+ }
+
+ Section = (EFI_COMMON_SECTION_HEADER*)(UINTN) CurrentAddress;
+
+ Size = SECTION_SIZE (Section);
+ if (Size < sizeof (*Section)) {
+ return EFI_VOLUME_CORRUPTED;
+ }
+
+ EndOfSection = CurrentAddress + Size;
+ if (EndOfSection > EndOfSections) {
+ return EFI_VOLUME_CORRUPTED;
+ }
+
+ //
+ // Look for the requested section type
+ //
+ if (Section->Type == SectionType) {
+ if (Instance == 0) {
+ *FoundSection = Section;
+ return EFI_SUCCESS;
+ } else {
+ Instance--;
+ }
+ }
+ }
+
+ return EFI_NOT_FOUND;
+}
+
+/**
+ Locates a section within a series of sections
+ with the specified section type.
+
+ @param[in] Sections The sections to search
+ @param[in] SizeOfSections Total size of all sections
+ @param[in] SectionType The section type to locate
+ @param[out] FoundSection The FFS section if found
+
+ @retval EFI_SUCCESS The file and section was found
+ @retval EFI_NOT_FOUND The file and section was not found
+ @retval EFI_VOLUME_CORRUPTED The firmware volume was corrupted
+
+**/
+EFI_STATUS
+FindFfsSectionInSections (
+ IN VOID *Sections,
+ IN UINTN SizeOfSections,
+ IN EFI_SECTION_TYPE SectionType,
+ OUT EFI_COMMON_SECTION_HEADER **FoundSection
+ )
+{
+ return FindFfsSectionInstance (
+ Sections,
+ SizeOfSections,
+ SectionType,
+ 0,
+ FoundSection
+ );
+}
+
+/**
+ Locates a FFS file with the specified file type and a section
+ within that file with the specified section type.
+
+ @param[in] Fv The firmware volume to search
+ @param[in] FileType The file type to locate
+ @param[in] SectionType The section type to locate
+ @param[out] FoundSection The FFS section if found
+
+ @retval EFI_SUCCESS The file and section was found
+ @retval EFI_NOT_FOUND The file and section was not found
+ @retval EFI_VOLUME_CORRUPTED The firmware volume was corrupted
+
+**/
+EFI_STATUS
+FindFfsFileAndSection (
+ IN EFI_FIRMWARE_VOLUME_HEADER *Fv,
+ IN EFI_FV_FILETYPE FileType,
+ IN EFI_SECTION_TYPE SectionType,
+ OUT EFI_COMMON_SECTION_HEADER **FoundSection
+ )
+{
+ EFI_STATUS Status;
+ EFI_PHYSICAL_ADDRESS CurrentAddress;
+ EFI_PHYSICAL_ADDRESS EndOfFirmwareVolume;
+ EFI_FFS_FILE_HEADER *File;
+ UINT32 Size;
+ EFI_PHYSICAL_ADDRESS EndOfFile;
+
+ if (Fv->Signature != EFI_FVH_SIGNATURE) {
+ DEBUG ((DEBUG_ERROR, "%a: FV at %p does not have FV header signature\n", __FUNCTION__, Fv));
+ return EFI_VOLUME_CORRUPTED;
+ }
+
+ CurrentAddress = (EFI_PHYSICAL_ADDRESS)(UINTN) Fv;
+ EndOfFirmwareVolume = CurrentAddress + Fv->FvLength;
+
+ //
+ // Loop through the FFS files in the Boot Firmware Volume
+ //
+ for (EndOfFile = CurrentAddress + Fv->HeaderLength; ; ) {
+
+ CurrentAddress = (EndOfFile + 7) & ~(7ULL);
+ if (CurrentAddress > EndOfFirmwareVolume) {
+ return EFI_VOLUME_CORRUPTED;
+ }
+
+ File = (EFI_FFS_FILE_HEADER*)(UINTN) CurrentAddress;
+ Size = *(UINT32*) File->Size & 0xffffff;
+ if (Size < (sizeof (*File) + sizeof (EFI_COMMON_SECTION_HEADER))) {
+ return EFI_VOLUME_CORRUPTED;
+ }
+
+ EndOfFile = CurrentAddress + Size;
+ if (EndOfFile > EndOfFirmwareVolume) {
+ return EFI_VOLUME_CORRUPTED;
+ }
+
+ //
+ // Look for the request file type
+ //
+ if (File->Type != FileType) {
+ continue;
+ }
+
+ Status = FindFfsSectionInSections (
+ (VOID*) (File + 1),
+ (UINTN) EndOfFile - (UINTN) (File + 1),
+ SectionType,
+ FoundSection
+ );
+ if (!EFI_ERROR (Status) || (Status == EFI_VOLUME_CORRUPTED)) {
+ return Status;
+ }
+ }
+}
+
+/**
+ Locates the PEI Core entry point address
+
+ @param[in] Fv The firmware volume to search
+ @param[out] PeiCoreEntryPoint The entry point of the PEI Core image
+
+ @retval EFI_SUCCESS The file and section was found
+ @retval EFI_NOT_FOUND The file and section was not found
+ @retval EFI_VOLUME_CORRUPTED The firmware volume was corrupted
+
+**/
+EFI_STATUS
+FindPeiCoreImageBaseInFv (
+ IN EFI_FIRMWARE_VOLUME_HEADER *Fv,
+ OUT EFI_PHYSICAL_ADDRESS *PeiCoreImageBase
+ )
+{
+ EFI_STATUS Status;
+ EFI_COMMON_SECTION_HEADER *Section;
+
+ Status = FindFfsFileAndSection (
+ Fv,
+ EFI_FV_FILETYPE_PEI_CORE,
+ EFI_SECTION_PE32,
+ &Section
+ );
+ if (EFI_ERROR (Status)) {
+ Status = FindFfsFileAndSection (
+ Fv,
+ EFI_FV_FILETYPE_PEI_CORE,
+ EFI_SECTION_TE,
+ &Section
+ );
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "%a: Unable to find PEI Core image\n", __FUNCTION__));
+ return Status;
+ }
+ }
+ DEBUG ((DEBUG_INFO, "%a: PeiCoreImageBase found\n", __FUNCTION__));
+ *PeiCoreImageBase = (EFI_PHYSICAL_ADDRESS)(UINTN)(Section + 1);
+ return EFI_SUCCESS;
+}
+
+/**
+ Locates the PEI Core entry point address
+
+ @param[in,out] Fv The firmware volume to search
+ @param[out] PeiCoreEntryPoint The entry point of the PEI Core image
+
+ @retval EFI_SUCCESS The file and section was found
+ @retval EFI_NOT_FOUND The file and section was not found
+ @retval EFI_VOLUME_CORRUPTED The firmware volume was corrupted
+
+**/
+VOID
+FindPeiCoreImageBase (
+ IN OUT EFI_FIRMWARE_VOLUME_HEADER **BootFv,
+ OUT EFI_PHYSICAL_ADDRESS *PeiCoreImageBase
+ )
+{
+ *PeiCoreImageBase = 0;
+
+ DEBUG ((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));
+ FindPeiCoreImageBaseInFv (*BootFv, PeiCoreImageBase);
+}
+
+/*
+ Find and return Pei Core entry point.
+
+ It also find SEC and PEI Core file debug inforamtion. It will report them if
+ remote debug is enabled.
+
+**/
+VOID
+FindAndReportEntryPoints (
+ IN EFI_FIRMWARE_VOLUME_HEADER **BootFirmwareVolumePtr,
+ OUT EFI_PEI_CORE_ENTRY_POINT *PeiCoreEntryPoint
+ )
+{
+ EFI_STATUS Status;
+ EFI_PHYSICAL_ADDRESS PeiCoreImageBase;
+
+ DEBUG ((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));
+
+ FindPeiCoreImageBase (BootFirmwareVolumePtr, &PeiCoreImageBase);
+ //
+ // Find PEI Core entry point
+ //
+ Status = PeCoffLoaderGetEntryPoint ((VOID *) (UINTN) PeiCoreImageBase, (VOID**) PeiCoreEntryPoint);
+ if (EFI_ERROR(Status)) {
+ *PeiCoreEntryPoint = 0;
+ }
+ DEBUG ((DEBUG_INFO, "%a: PeCoffLoaderGetEntryPoint success: %x\n", __FUNCTION__, *PeiCoreEntryPoint));
+
+ return;
+}
+/*
+ Print out the content of firmware context.
+
+**/
+VOID
+DebutPrintFirmwareContext (
+ EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *FirmwareContext
+ )
+{
+ DEBUG ((DEBUG_INFO, "%a: OpenSBI Firmware Context at 0x%x\n", __FUNCTION__, FirmwareContext));
+ DEBUG ((DEBUG_INFO, "%a: PEI Service at 0x%x\n\n", __FUNCTION__, FirmwareContext->PeiServiceTable));
+}
+/** Temporary RAM migration function.
+
+ This function migrates the data from temporary RAM to permanent
+ memory.
+
+ @param[in] PeiServices PEI service
+ @param[in] TemporaryMemoryBase Temporary memory base address
+ @param[in] PermanentMemoryBase Permanent memory base address
+ @param[in] CopySize Size to copy
+
+**/
+EFI_STATUS
+EFIAPI
+TemporaryRamMigration (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PHYSICAL_ADDRESS TemporaryMemoryBase,
+ IN EFI_PHYSICAL_ADDRESS PermanentMemoryBase,
+ IN UINTN CopySize
+ )
+{
+ VOID *OldHeap;
+ VOID *NewHeap;
+ VOID *OldStack;
+ VOID *NewStack;
+ EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *FirmwareContext;
+
+ DEBUG ((DEBUG_INFO,
+ "%a: Temp Mem Base:0x%Lx, Permanent Mem Base:0x%Lx, CopySize:0x%Lx\n",
+ __FUNCTION__,
+ TemporaryMemoryBase,
+ PermanentMemoryBase,
+ (UINT64)CopySize
+ ));
+
+ OldHeap = (VOID*)(UINTN)TemporaryMemoryBase;
+ NewHeap = (VOID*)((UINTN)PermanentMemoryBase + (CopySize >> 1));
+
+ OldStack = (VOID*)((UINTN)TemporaryMemoryBase + (CopySize >> 1));
+ NewStack = (VOID*)(UINTN)PermanentMemoryBase;
+
+ CopyMem (NewHeap, OldHeap, CopySize >> 1); // Migrate Heap
+ CopyMem (NewStack, OldStack, CopySize >> 1); // Migrate Stack
+
+ //
+ // Reset firmware context pointer
+ //
+ SbiGetFirmwareContext (&FirmwareContext);
+ FirmwareContext = (VOID *)FirmwareContext + (unsigned long)((UINTN)NewStack - (UINTN)OldStack);
+ SbiSetFirmwareContext (FirmwareContext);
+
+ //
+ // Relocate PEI Service **
+ //
+ FirmwareContext->PeiServiceTable += (unsigned long)((UINTN)NewStack - (UINTN)OldStack);
+ DEBUG ((DEBUG_INFO, "%a: OpenSBI Firmware Context is relocated to 0x%x\n", __FUNCTION__, FirmwareContext));
+ DebutPrintFirmwareContext ((EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *)FirmwareContext);
+
+ register uintptr_t a0 asm ("a0") = (uintptr_t)((UINTN)NewStack - (UINTN)OldStack);
+ asm volatile ("add sp, sp, a0"::"r"(a0):);
+ return EFI_SUCCESS;
+}
+
+/** Temprary RAM done function.
+
+**/
+EFI_STATUS EFIAPI TemporaryRamDone (
+ VOID
+ )
+{
+ DEBUG ((DEBUG_INFO, "%a: 2nd time PEI core, temporary ram done.\n", __FUNCTION__));
+ return EFI_SUCCESS;
+}
+
+/** Handles SBI calls of EDK2's SBI FW extension
+
+ @param[in] ExtId The extension ID of the FW extension.
+ @param[in] FuncId The called function ID.
+ @param[in] Args The args to the function.
+ @param[out] OutVal The value the function returns to the caller.
+ @param[out] OutTrap Trap info for trapping further, see OpenSBI code.
+ Is ignored if return value is not SBI_ETRAP.
+
+ @retval 0 If the handler succeeds.
+ @retval SBI_ENOTSUPP If there's no function with the given ID.
+ @retval SBI_ETRAP If the called SBI functions wants to trap further.
+**/
+STATIC int SbiEcallFirmwareHandler (
+ IN unsigned long ExtId,
+ IN unsigned long FuncId,
+ IN unsigned long *Args,
+ OUT unsigned long *OutVal,
+ OUT struct sbi_trap_info *OutTrap
+ )
+{
+ int Ret = 0;
+
+ switch (FuncId) {
+ case SBI_EXT_FW_MSCRATCH_FUNC:
+ *OutVal = (unsigned long) sbi_scratch_thishart_ptr();
+ break;
+ case SBI_EXT_FW_MSCRATCH_HARTID_FUNC:
+ *OutVal = (unsigned long) sbi_hartid_to_scratch (Args[0]);
+ break;
+ default:
+ Ret = SBI_ENOTSUPP;
+ };
+
+ return Ret;
+}
+
+struct sbi_ecall_extension FirmwareEcall = {
+ .extid_start = SBI_EDK2_FW_EXT,
+ .extid_end = SBI_EDK2_FW_EXT,
+ .handle = SbiEcallFirmwareHandler,
+};
+
+/** Register EDK2's SBI extension with OpenSBI
+
+ This function returns EFI_STATUS, even though it only ever returns
+ EFI_SUCCESS. On error it ASSERTs. Looking at OpenSBI code it appears that
+ registering an extension can only fail if the extension ID is invalid or was
+ already registered. Failure is therefore an error of the programmer.
+
+ @retval EFI_SUCCESS If the extension was successfully registered.
+**/
+EFI_STATUS
+EFIAPI
+RegisterFirmwareSbiExtension (
+ VOID
+ )
+{
+ UINTN Ret;
+ Ret = sbi_ecall_register_extension(&FirmwareEcall);
+ if (Ret) {
+ //
+ // Only fails if the extension ID is invalid or already is registered.
+ //
+ DEBUG ((DEBUG_ERROR, "Failed to register SBI Firmware Extension for EDK2\n"));
+ ASSERT(FALSE);
+ }
+
+ return EFI_SUCCESS;
+}
+/** Transion from SEC phase to PEI phase.
+
+ This function transits to S-mode PEI phase from M-mode SEC phase.
+
+ @param[in] BootHartId Hardware thread ID of boot hart.
+ @param[in] FuncArg1 Arg1 delivered from previous phase.
+
+**/
+VOID EFIAPI PeiCore (
+ IN UINTN BootHartId,
+ IN UINTN FuncArg1
+ )
+{
+ EFI_SEC_PEI_HAND_OFF SecCoreData;
+ EFI_PEI_CORE_ENTRY_POINT PeiCoreEntryPoint;
+ EFI_FIRMWARE_VOLUME_HEADER *BootFv = (EFI_FIRMWARE_VOLUME_HEADER *)FixedPcdGet32(PcdRiscVPeiFvBase);
+ EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT FirmwareContext;
+ struct sbi_scratch *ScratchSpace;
+ struct sbi_platform *ThisSbiPlatform;
+ UINT32 HartId;
+
+ FindAndReportEntryPoints (&BootFv, &PeiCoreEntryPoint);
+
+ SecCoreData.DataSize = sizeof(EFI_SEC_PEI_HAND_OFF);
+ SecCoreData.BootFirmwareVolumeBase = BootFv;
+ SecCoreData.BootFirmwareVolumeSize = (UINTN) BootFv->FvLength;
+ SecCoreData.TemporaryRamBase = (VOID*)(UINT64) FixedPcdGet32(PcdTemporaryRamBase);
+ SecCoreData.TemporaryRamSize = (UINTN) FixedPcdGet32(PcdTemporaryRamSize);
+ SecCoreData.PeiTemporaryRamBase = SecCoreData.TemporaryRamBase;
+ SecCoreData.PeiTemporaryRamSize = SecCoreData.TemporaryRamSize >> 1;
+ SecCoreData.StackBase = (UINT8 *)SecCoreData.TemporaryRamBase + (SecCoreData.TemporaryRamSize >> 1);
+ SecCoreData.StackSize = SecCoreData.TemporaryRamSize >> 1;
+
+ //
+ // Print out scratch address of each hart
+ //
+ DEBUG ((DEBUG_INFO, "%a: OpenSBI scratch address for each hart:\n", __FUNCTION__));
+ for (HartId = 0; HartId < SBI_HARTMASK_MAX_BITS; HartId ++) {
+ SbiGetMscratchHartid (HartId, &ScratchSpace);
+ if(ScratchSpace != NULL) {
+ DEBUG((DEBUG_INFO, " Hart %d: 0x%x\n", HartId, ScratchSpace));
+ }
+ }
+
+ //
+ // Set up OpepSBI firmware context pointer on boot hart OpenSbi scratch.
+ // Firmware context residents in stack and will be switched to memory when
+ // temporary RAM migration.
+ //
+ SbiGetMscratchHartid (BootHartId, &ScratchSpace);
+ ZeroMem ((VOID *)&FirmwareContext, sizeof (EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT));
+ ThisSbiPlatform = (struct sbi_platform *)sbi_platform_ptr(ScratchSpace);
+ if (ThisSbiPlatform->opensbi_version > OPENSBI_VERSION) {
+ DEBUG ((DEBUG_ERROR, "%a: OpenSBI platform table version 0x%x is newer than OpenSBI version 0x%x.\n"
+ "There maybe be some backward compatable issues.\n",
+ __FUNCTION__,
+ ThisSbiPlatform->opensbi_version,
+ OPENSBI_VERSION
+ ));
+ ASSERT(FALSE);
+ }
+ DEBUG ((DEBUG_INFO, "%a: OpenSBI platform table at address: 0x%x\nFirmware Context is located at 0x%x\n",
+ __FUNCTION__,
+ ThisSbiPlatform,
+ &FirmwareContext
+ ));
+ ThisSbiPlatform->firmware_context = (unsigned long)&FirmwareContext;
+ //
+ // Set firmware context Hart-specific pointer
+ //
+ for (HartId = 0; HartId < SBI_HARTMASK_MAX_BITS; HartId ++) {
+ SbiGetMscratchHartid (HartId, &ScratchSpace);
+ if (ScratchSpace != NULL) {
+ FirmwareContext.HartSpecific[HartId] =
+ (EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC *)((UINT8 *)ScratchSpace - FIRMWARE_CONTEXT_HART_SPECIFIC_SIZE);
+ DEBUG ((DEBUG_INFO, "%a: OpenSBI Hart %d Firmware Context Hart-specific at address: 0x%x\n",
+ __FUNCTION__,
+ HartId,
+ FirmwareContext.HartSpecific [HartId]
+ ));
+ }
+ }
+ //
+ // Set supervisor translation mode to Bare mode
+ //
+ DEBUG ((DEBUG_INFO, "%a: Set Supervisor address mode to Bare-mode.\n", __FUNCTION__));
+ RiscVSetSupervisorAddressTranslationRegister ((UINT64)RISCV_SATP_MODE_OFF << RISCV_SATP_MODE_BIT_POSITION);
+
+ //
+ // Transfer the control to the PEI core
+ //
+ (*PeiCoreEntryPoint) (&SecCoreData, (EFI_PEI_PPI_DESCRIPTOR *)&mPrivateDispatchTable);
+}
+
+/**
+ Register firmware SBI extension and launch PeiCore to the mode specified in
+ PcdPeiCorePrivilegeMode;
+
+ To register the SBI extension we stay in M-Mode and then transition here,
+ rather than before in sbi_init.
+
+ @param[in] ThisHartId Hardware thread ID.
+ @param[in] FuncArg1 Arg1 delivered from previous phase.
+
+**/
+VOID
+EFIAPI
+LaunchPeiCore (
+ IN UINTN ThisHartId,
+ IN UINTN FuncArg1
+ )
+{
+ UINT32 PeiCoreMode;
+
+ DEBUG ((DEBUG_INFO, "%a: Set boot hart done.\n", __FUNCTION__));
+ atomic_write (&BootHartDone, (UINT64)TRUE);
+ RegisterFirmwareSbiExtension ();
+
+ PeiCoreMode = FixedPcdGet32 (PcdPeiCorePrivilegeMode);
+ if (PeiCoreMode == PRV_S) {
+ DEBUG ((DEBUG_INFO, "%a: Switch to S-Mode for PeiCore.\n", __FUNCTION__));
+ sbi_hart_switch_mode (ThisHartId, FuncArg1, (UINTN)PeiCore, PRV_S, FALSE);
+ } else if (PeiCoreMode == PRV_M) {
+ DEBUG ((DEBUG_INFO, "%a: Switch to M-Mode for PeiCore.\n", __FUNCTION__));
+ PeiCore (ThisHartId, FuncArg1);
+ } else {
+ DEBUG ((DEBUG_INFO, "%a: The privilege mode specified in PcdPeiCorePrivilegeMode is not supported.\n", __FUNCTION__));
+ while (TRUE);
+ }
+}
+
+/**
+ Interface to invoke internal mode switch function.
+
+ To register the SBI extension we stay in M-Mode and then transition here,
+ rather than before in sbi_init.
+
+ @param[in] FuncArg0 Arg0 to pass to next phase entry point address.
+ @param[in] FuncArg1 Arg1 to pass to next phase entry point address.
+ @param[in] NextAddr Entry point of next phase.
+ @param[in] NextMode Privilege mode of next phase.
+ @param[in] NextVirt Next phase is in virtualiztion.
+
+**/
+VOID
+EFIAPI
+RiscVOpenSbiHartSwitchMode (
+ IN UINTN FuncArg0,
+ IN UINTN FuncArg1,
+ IN UINTN NextAddr,
+ IN UINTN NextMode,
+ IN BOOLEAN NextVirt
+ )
+{
+ sbi_hart_switch_mode(FuncArg0, FuncArg1, NextAddr, NextMode, NextVirt);
+}
+
+/**
+ This function initilizes hart specific information and SBI.
+ For the boot hart, it boots system through PEI core and initial SBI in the DXE IPL.
+ For others, it goes to initial SBI and halt.
+
+ the lay out of memory region for each hart is as below delineates,
+
+ _ ____
+ |----Scratch ends | |
+ | | sizeof (sbi_scratch) |
+ | _| |
+ |----Scratch buffer starts <----- *Scratch |
+ |----Firmware Context Hart-specific ends _ |
+ | | |
+ | | FIRMWARE_CONTEXT_HART_SPECIFIC_SIZE |
+ | | | PcdOpenSbiStackSize
+ | _| |
+ |----Firmware Context Hart-specific starts <----- **HartFirmwareContext |
+ |----Hart stack top _ |
+ | | |
+ | | |
+ | | Stack |
+ | | |
+ | _| ____|
+ |----Hart stack bottom
+
+ @param[in] HartId Hardware thread ID.
+ @param[in] Scratch Pointer to sbi_scratch structure.
+
+**/
+VOID EFIAPI SecCoreStartUpWithStack(
+ IN UINTN HartId,
+ IN struct sbi_scratch *Scratch
+ )
+{
+ UINT64 BootHartDoneSbiInit;
+ UINT64 NonBootHartMessageLockValue;
+ EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC *HartFirmwareContext;
+
+ //
+ // Setup EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC for each hart.
+ //
+ HartFirmwareContext = (EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC *)((UINT8 *)Scratch - FIRMWARE_CONTEXT_HART_SPECIFIC_SIZE);
+ HartFirmwareContext->IsaExtensionSupported = RiscVReadMachineIsa ();
+ HartFirmwareContext->MachineVendorId.Value64_L = RiscVReadMachineVendorId ();
+ HartFirmwareContext->MachineVendorId.Value64_H = 0;
+ HartFirmwareContext->MachineArchId.Value64_L = RiscVReadMachineArchitectureId ();
+ HartFirmwareContext->MachineArchId.Value64_H = 0;
+ HartFirmwareContext->MachineImplId.Value64_L = RiscVReadMachineImplementId ();
+ HartFirmwareContext->MachineImplId.Value64_H = 0;
+ HartFirmwareContext->HartSwitchMode = RiscVOpenSbiHartSwitchMode;
+
+ if (HartId == FixedPcdGet32(PcdBootHartId)) {
+ Scratch->next_addr = (UINTN)LaunchPeiCore;
+ Scratch->next_mode = PRV_M;
+ DEBUG ((DEBUG_INFO, "%a: Initializing OpenSBI library for booting hart %d\n", __FUNCTION__, HartId));
+ sbi_init(Scratch);
+ }
+
+ //
+ // Initialize the non boot harts
+ //
+ do {
+ BootHartDoneSbiInit = atomic_read (&BootHartDone);
+ //
+ // Below leave some memory cycles to boot hart
+ // for updating BootHartDone.
+ //
+ CpuPause ();
+ CpuPause ();
+ CpuPause ();
+ } while (BootHartDoneSbiInit != (UINT64)TRUE);
+
+ NonBootHartMessageLockValue = atomic_xchg(&NonBootHartMessageLock, TRUE);
+ while (NonBootHartMessageLockValue == TRUE) {
+ CpuPause ();
+ CpuPause ();
+ CpuPause ();
+ NonBootHartMessageLockValue = atomic_xchg(&NonBootHartMessageLock, TRUE);
+ };
+ DEBUG((DEBUG_INFO, "%a: Non boot hart %d initialization.\n", __FUNCTION__, HartId));
+ NonBootHartMessageLockValue = atomic_xchg(&NonBootHartMessageLock, FALSE);
+ //
+ // Non boot hart wiil be halted waiting for SBI_HART_STARTING.
+ // Use HSM ecall to start non boot hart (SBI_EXT_HSM_HART_START) later on,
+ //
+ sbi_init(Scratch);
+}
+
diff --git a/Platform/RISC-V/PlatformPkg/Universal/Sec/Riscv64/SecEntry.S b/Platform/RISC-V/PlatformPkg/Universal/Sec/Riscv64/SecEntry.S
new file mode 100644
index 0000000000..6b2cdb6c17
--- /dev/null
+++ b/Platform/RISC-V/PlatformPkg/Universal/Sec/Riscv64/SecEntry.S
@@ -0,0 +1,532 @@
+/*
+ * Copyright (c) 2020 , Hewlett Packard Enterprise Development LP. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Copyright (c) 2019 Western Digital Corporation or its affiliates.
+ *
+ */
+
+#include <IndustryStandard/RiscVOpensbi.h>
+#include <Base.h>
+#include <RiscVImpl.h>
+#include <sbi/riscv_asm.h>
+#include <sbi/riscv_encoding.h>
+#include <sbi/sbi_platform.h>
+#include <sbi/sbi_scratch.h>
+#include <sbi/sbi_trap.h>
+
+#include <SecMain.h>
+
+.text
+.align 3
+
+ASM_FUNC (_ModuleEntryPoint)
+ /*
+ * Jump to warm-boot if this is not the selected core booting,
+ */
+ csrr a6, CSR_MHARTID
+ li a5, FixedPcdGet32 (PcdBootHartId)
+ bne a6, a5, _wait_for_boot_hart
+
+ li ra, 0
+ call _reset_regs
+
+ /* Preload HART details
+ * s7 -> HART Count
+ * s8 -> HART Stack Size
+ */
+ li s7, FixedPcdGet32 (PcdHartCount)
+ li s8, FixedPcdGet32 (PcdOpenSbiStackSize)
+
+ /*
+ * Setup scratch space for all the HARTs
+ *
+ * Scratch buffer is on the top of stack buffer
+ * of each hart.
+ *
+ * tp : Base address of scratch buffer.
+ * s7 : HART Count
+ * s8 : HART Stack Size
+ */
+ li tp, FixedPcdGet32 (PcdScratchRamBase)
+ mul a5, s7, s8
+ add tp, tp, a5
+
+ /* Keep a copy of tp */
+ add t3, tp, zero
+ /* Counter */
+ li t2, 1
+ /* hartid 0 is mandated by ISA */
+ li t1, 0
+_scratch_init:
+ add tp, t3, zero
+ mul a5, s8, t1
+ sub tp, tp, a5
+ li a5, SBI_SCRATCH_SIZE
+ sub tp, tp, a5
+
+ /* Initialize scratch space */
+
+ /* Firmware range and size */
+ li a4, FixedPcdGet32 (PcdFwStartAddress)
+ li a5, FixedPcdGet32 (PcdFwEndAddress)
+ sub a5, a5, a4
+ sd a4, SBI_SCRATCH_FW_START_OFFSET(tp)
+ sd a5, SBI_SCRATCH_FW_SIZE_OFFSET(tp)
+
+ /*
+ * Note: fw_next_arg1() uses a0, a1, and ra
+ */
+ call fw_next_arg1
+ sd a0, SBI_SCRATCH_NEXT_ARG1_OFFSET(tp) /* Save agr1 in scratch buffer*/
+ /*
+ Note: fw_next_addr()uses a0, a1, and ra
+ */
+ call fw_next_addr
+ sd a0, SBI_SCRATCH_NEXT_ADDR_OFFSET(tp) /* Save next address in scratch buffer*/
+ li a4, PRV_S
+ sd a4, SBI_SCRATCH_NEXT_MODE_OFFSET(tp) /* Save next mode in scratch buffer*/
+ la a4, _start_warm
+ sd a4, SBI_SCRATCH_WARMBOOT_ADDR_OFFSET(tp) /* Save warm boot address in scratch buffer*/
+ la a4, platform
+ sd a4, SBI_SCRATCH_PLATFORM_ADDR_OFFSET(tp) /* Save platfrom table in scratch buffer*/
+ la a4, _hartid_to_scratch
+ sd a4, SBI_SCRATCH_HARTID_TO_SCRATCH_OFFSET(tp) /* Save _hartid_to_scratch function in scratch buffer*/
+ sd zero, SBI_SCRATCH_TMP0_OFFSET(tp)
+
+#ifdef FW_OPTIONS
+ li a4, FW_OPTIONS
+ sd a4, SBI_SCRATCH_OPTIONS_OFFSET(tp)
+#else
+ sd zero, SBI_SCRATCH_OPTIONS_OFFSET(tp)
+#endif
+ add t1, t1, t2
+ /* Loop to next hart */
+ blt t1, s7, _scratch_init
+
+ /* Fill-out temporary memory with 55aa*/
+ li a4, FixedPcdGet32 (PcdTemporaryRamBase)
+ li a5, FixedPcdGet32 (PcdTemporaryRamSize)
+ add a5, a4, a5
+1:
+ li a3, 0x5AA55AA55AA55AA5
+ sd a3, (a4)
+ add a4, a4, __SIZEOF_POINTER__
+ blt a4, a5, 1b
+
+ /* Update boot hart flag */
+ la a4, _boot_hart_done
+ li a5, 1
+ sd a5, (a4)
+
+ /* Wait for boot hart */
+_wait_for_boot_hart:
+ la a4, _boot_hart_done
+ ld a5, (a4)
+
+ /* Reduce the bus traffic so that boot hart may proceed faster */
+ nop
+ nop
+ nop
+ beqz a5, _wait_for_boot_hart
+
+_start_warm:
+ li ra, 0
+ call _reset_regs
+
+ /* Disable and clear all interrupts */
+ csrw CSR_MIE, zero
+ csrw CSR_MIP, zero
+
+ li s7, FixedPcdGet32 (PcdBootableHartNumber)
+ li s8, FixedPcdGet32 (PcdOpenSbiStackSize)
+ la a4, platform
+
+ /* s9 is hart_index2id array */
+ REG_L s9, SBI_PLATFORM_HART_INDEX2ID_OFFSET(a4)
+
+ /* s6 is this hart ID */
+ csrr s6, CSR_MHARTID
+
+ /*
+ * Convert hart ID to scratch buffer
+ * Because the hert ID maybe not in sequentially
+ */
+ beqz s9, 3f
+ li a4, 0
+1:
+#if __riscv_xlen == 64
+ lwu a5, (s9)
+#else
+ lw a5, (s9)
+#endif
+ /* Branch if hart ID is matched */
+ beq a5, s6, 2f
+ add s9, s9, 4
+ add a4, a4, 1
+ /* Loop to next index */
+ blt a4, s7, 1b
+ li a4, -1
+2:
+ add s6, a4, zero
+3:
+ /* Jump to UninitializedHartWait for the non-bootable harts.
+ Be aware that the stack and scratch is not set
+ at this moment for this hart even the resource
+ is preserved eariler for it.
+ */
+ bltu s6, s7, 4f
+ csrr a0, CSR_MHARTID
+ j _uninitialized_hart_wait
+4:
+ li s7, FixedPcdGet32 (PcdHartCount)
+ /* Find the scratch space for this hart
+ *
+ * Scratch buffer is on the top of stack buffer
+ * reserved for opensbi.
+ *
+ * tp: The base address of scratch buffer
+ * s6: Index to scratch buffer fot this hart
+ * s7: Total hart number
+ * s8: Stack size for opebsbi.
+ */
+ li tp, FixedPcdGet32 (PcdScratchRamBase)
+ mul a5, s7, s8
+ add tp, tp, a5
+ mul a5, s8, s6
+ sub tp, tp, a5
+ li a5, SBI_SCRATCH_SIZE
+ sub tp, tp, a5
+
+ /* update the mscratch */
+ csrw CSR_MSCRATCH, tp
+
+ /*make room for Hart specific Firmware Context*/
+ li a5, FIRMWARE_CONTEXT_HART_SPECIFIC_SIZE
+ sub tp, tp, a5
+
+ /* Setup stack */
+ add sp, tp, zero
+
+ /* Setup stack for the Hart executing EFI to top of temporary ram*/
+ csrr a6, CSR_MHARTID
+ li a5, FixedPcdGet32 (PcdBootHartId)
+ bne a6, a5, 1f
+
+ li a4, FixedPcdGet32(PcdTemporaryRamBase)
+ li a5, FixedPcdGet32(PcdTemporaryRamSize)
+ add sp, a4, a5
+1:
+
+ /* Setup trap handler */
+ la a4, _trap_handler
+ csrw CSR_MTVEC, a4
+
+ /* Make sure that mtvec is updated */
+ 1:
+ csrr a5, CSR_MTVEC
+ bne a4, a5, 1b
+
+ /* Call library constructors before jup to SEC core */
+ call ProcessLibraryConstructorList
+
+ /* Jump to SEC Core C
+ * a0: HART ID
+ * a1: Scratch pointer
+ */
+ csrr a0, CSR_MHARTID
+ csrr a1, CSR_MSCRATCH
+ call SecCoreStartUpWithStack
+
+ /* We do not expect to reach here hence just hang */
+ j _start_hang
+
+ .align 3
+ .section .data, "aw"
+_boot_hart_done:
+ RISCV_PTR 0
+
+ .align 3
+ .section .entry, "ax", %progbits
+ .globl _hartid_to_scratch
+
+ /*
+ * a0 -> HART id (Obsoleted, keep this for the backward compatible)
+ * a1 -> HART index (0-based) of this hart id
+ */
+_hartid_to_scratch:
+ add sp, sp, -(3 * __SIZEOF_POINTER__)
+ sd s0, (sp)
+ sd s1, (__SIZEOF_POINTER__)(sp)
+ sd s2, (__SIZEOF_POINTER__ * 2)(sp)
+
+ /*
+ * s0 -> HART Stack Size
+ * s1 -> HART Stack End
+ * s2 -> Temporary
+ */
+ la s2, platform
+#if __riscv_xlen == 64
+ lwu s0, SBI_PLATFORM_HART_STACK_SIZE_OFFSET(s2)
+#else
+ lw s0, SBI_PLATFORM_HART_STACK_SIZE_OFFSET(s2)
+#endif
+ li s2, FixedPcdGet32 (PcdHartCount)
+
+ mul s2, s2, s0
+ li s1, FixedPcdGet32 (PcdScratchRamBase)
+ add s1, s1, s2
+ mul s2, s0, a1
+ sub s1, s1, s2
+ li s2, SBI_SCRATCH_SIZE
+ sub a0, s1, s2
+ ld s0, (sp)
+ ld s1, (__SIZEOF_POINTER__)(sp)
+ ld s2, (__SIZEOF_POINTER__ * 2)(sp)
+ add sp, sp, (3 * __SIZEOF_POINTER__)
+ ret
+
+ .align 3
+ .section .entry, "ax", %progbits
+ .globl _start_hang
+_start_hang:
+ wfi
+ j _start_hang
+
+ /*
+ * Uninitialized hart comes here and wait
+ * for the further process.
+ * a0: hart ID.
+ */
+_uninitialized_hart_wait:
+ wfi
+ j _uninitialized_hart_wait
+
+ .align 3
+ .section .entry, "ax", %progbits
+ .align 3
+ .globl _trap_handler
+_trap_handler:
+
+ /* Swap TP and MSCRATCH */
+ csrrw tp, CSR_MSCRATCH, tp
+
+ /* Save T0 in scratch space */
+ REG_S t0, SBI_SCRATCH_TMP0_OFFSET(tp)
+
+ /* Check which mode we came from */
+ csrr t0, CSR_MSTATUS
+ srl t0, t0, MSTATUS_MPP_SHIFT
+ and t0, t0, PRV_M
+ xori t0, t0, PRV_M
+ beq t0, zero, _trap_handler_m_mode
+
+ /* We came from S-mode or U-mode */
+_trap_handler_s_mode:
+ /* Set T0 to original SP */
+ add t0, sp, zero
+
+ /* Setup exception stack */
+ add sp, tp, -(SBI_TRAP_REGS_SIZE)
+
+ /* Jump to code common for all modes */
+ j _trap_handler_all_mode
+
+ /* We came from M-mode */
+_trap_handler_m_mode:
+ /* Set T0 to original SP */
+ add t0, sp, zero
+
+ /* Re-use current SP as exception stack */
+ add sp, sp, -(SBI_TRAP_REGS_SIZE)
+
+_trap_handler_all_mode:
+ /* Save original SP (from T0) on stack */
+ REG_S t0, SBI_TRAP_REGS_OFFSET(sp)(sp)
+
+ /* Restore T0 from scratch space */
+ REG_L t0, SBI_SCRATCH_TMP0_OFFSET(tp)
+
+ /* Save T0 on stack */
+ REG_S t0, SBI_TRAP_REGS_OFFSET(t0)(sp)
+
+ /* Swap TP and MSCRATCH */
+ csrrw tp, CSR_MSCRATCH, tp
+
+ /* Save MEPC and MSTATUS CSRs */
+ csrr t0, CSR_MEPC
+ REG_S t0, SBI_TRAP_REGS_OFFSET(mepc)(sp)
+ csrr t0, CSR_MSTATUS
+ REG_S t0, SBI_TRAP_REGS_OFFSET(mstatus)(sp)
+ REG_S zero, SBI_TRAP_REGS_OFFSET(mstatusH)(sp)
+#if __riscv_xlen == 32
+ csrr t0, CSR_MISA
+ srli t0, t0, ('H' - 'A')
+ andi t0, t0, 0x1
+ beq t0, zero, _skip_mstatush_save
+ csrr t0, CSR_MSTATUSH
+ REG_S t0, SBI_TRAP_REGS_OFFSET(mstatusH)(sp)
+_skip_mstatush_save:
+#endif
+
+ /* Save all general registers except SP and T0 */
+ REG_S zero, SBI_TRAP_REGS_OFFSET(zero)(sp)
+ REG_S ra, SBI_TRAP_REGS_OFFSET(ra)(sp)
+ REG_S gp, SBI_TRAP_REGS_OFFSET(gp)(sp)
+ REG_S tp, SBI_TRAP_REGS_OFFSET(tp)(sp)
+ REG_S t1, SBI_TRAP_REGS_OFFSET(t1)(sp)
+ REG_S t2, SBI_TRAP_REGS_OFFSET(t2)(sp)
+ REG_S s0, SBI_TRAP_REGS_OFFSET(s0)(sp)
+ REG_S s1, SBI_TRAP_REGS_OFFSET(s1)(sp)
+ REG_S a0, SBI_TRAP_REGS_OFFSET(a0)(sp)
+ REG_S a1, SBI_TRAP_REGS_OFFSET(a1)(sp)
+ REG_S a2, SBI_TRAP_REGS_OFFSET(a2)(sp)
+ REG_S a3, SBI_TRAP_REGS_OFFSET(a3)(sp)
+ REG_S a4, SBI_TRAP_REGS_OFFSET(a4)(sp)
+ REG_S a5, SBI_TRAP_REGS_OFFSET(a5)(sp)
+ REG_S a6, SBI_TRAP_REGS_OFFSET(a6)(sp)
+ REG_S a7, SBI_TRAP_REGS_OFFSET(a7)(sp)
+ REG_S s2, SBI_TRAP_REGS_OFFSET(s2)(sp)
+ REG_S s3, SBI_TRAP_REGS_OFFSET(s3)(sp)
+ REG_S s4, SBI_TRAP_REGS_OFFSET(s4)(sp)
+ REG_S s5, SBI_TRAP_REGS_OFFSET(s5)(sp)
+ REG_S s6, SBI_TRAP_REGS_OFFSET(s6)(sp)
+ REG_S s7, SBI_TRAP_REGS_OFFSET(s7)(sp)
+ REG_S s8, SBI_TRAP_REGS_OFFSET(s8)(sp)
+ REG_S s9, SBI_TRAP_REGS_OFFSET(s9)(sp)
+ REG_S s10, SBI_TRAP_REGS_OFFSET(s10)(sp)
+ REG_S s11, SBI_TRAP_REGS_OFFSET(s11)(sp)
+ REG_S t3, SBI_TRAP_REGS_OFFSET(t3)(sp)
+ REG_S t4, SBI_TRAP_REGS_OFFSET(t4)(sp)
+ REG_S t5, SBI_TRAP_REGS_OFFSET(t5)(sp)
+ REG_S t6, SBI_TRAP_REGS_OFFSET(t6)(sp)
+
+ /* Call C routine */
+ add a0, sp, zero
+ call sbi_trap_handler
+
+ /* Restore all general registers except SP and T0 */
+ REG_L ra, SBI_TRAP_REGS_OFFSET(ra)(sp)
+ REG_L gp, SBI_TRAP_REGS_OFFSET(gp)(sp)
+ REG_L tp, SBI_TRAP_REGS_OFFSET(tp)(sp)
+ REG_L t1, SBI_TRAP_REGS_OFFSET(t1)(sp)
+ REG_L t2, SBI_TRAP_REGS_OFFSET(t2)(sp)
+ REG_L s0, SBI_TRAP_REGS_OFFSET(s0)(sp)
+ REG_L s1, SBI_TRAP_REGS_OFFSET(s1)(sp)
+ REG_L a0, SBI_TRAP_REGS_OFFSET(a0)(sp)
+ REG_L a1, SBI_TRAP_REGS_OFFSET(a1)(sp)
+ REG_L a2, SBI_TRAP_REGS_OFFSET(a2)(sp)
+ REG_L a3, SBI_TRAP_REGS_OFFSET(a3)(sp)
+ REG_L a4, SBI_TRAP_REGS_OFFSET(a4)(sp)
+ REG_L a5, SBI_TRAP_REGS_OFFSET(a5)(sp)
+ REG_L a6, SBI_TRAP_REGS_OFFSET(a6)(sp)
+ REG_L a7, SBI_TRAP_REGS_OFFSET(a7)(sp)
+ REG_L s2, SBI_TRAP_REGS_OFFSET(s2)(sp)
+ REG_L s3, SBI_TRAP_REGS_OFFSET(s3)(sp)
+ REG_L s4, SBI_TRAP_REGS_OFFSET(s4)(sp)
+ REG_L s5, SBI_TRAP_REGS_OFFSET(s5)(sp)
+ REG_L s6, SBI_TRAP_REGS_OFFSET(s6)(sp)
+ REG_L s7, SBI_TRAP_REGS_OFFSET(s7)(sp)
+ REG_L s8, SBI_TRAP_REGS_OFFSET(s8)(sp)
+ REG_L s9, SBI_TRAP_REGS_OFFSET(s9)(sp)
+ REG_L s10, SBI_TRAP_REGS_OFFSET(s10)(sp)
+ REG_L s11, SBI_TRAP_REGS_OFFSET(s11)(sp)
+ REG_L t3, SBI_TRAP_REGS_OFFSET(t3)(sp)
+ REG_L t4, SBI_TRAP_REGS_OFFSET(t4)(sp)
+ REG_L t5, SBI_TRAP_REGS_OFFSET(t5)(sp)
+ REG_L t6, SBI_TRAP_REGS_OFFSET(t6)(sp)
+
+ /* Restore MEPC and MSTATUS CSRs */
+ REG_L t0, SBI_TRAP_REGS_OFFSET(mepc)(sp)
+ csrw CSR_MEPC, t0
+ REG_L t0, SBI_TRAP_REGS_OFFSET(mstatus)(sp)
+ csrw CSR_MSTATUS, t0
+#if __riscv_xlen == 32
+ csrr t0, CSR_MISA
+ srli t0, t0, ('H' - 'A')
+ andi t0, t0, 0x1
+ beq t0, zero, _skip_mstatush_restore
+ REG_L t0, SBI_TRAP_REGS_OFFSET(mstatusH)(sp)
+ csrw CSR_MSTATUSH, t0
+_skip_mstatush_restore:
+#endif
+
+ /* Restore T0 */
+ REG_L t0, SBI_TRAP_REGS_OFFSET(t0)(sp)
+
+ /* Restore SP */
+ REG_L sp, SBI_TRAP_REGS_OFFSET(sp)(sp)
+
+ mret
+
+ .align 3
+ .section .entry, "ax", %progbits
+ .globl _reset_regs
+_reset_regs:
+
+ /* flush the instruction cache */
+ fence.i
+
+ /* Reset all registers except ra, a0,a1 */
+ li sp, 0
+ li gp, 0
+ li tp, 0
+ li t0, 0
+ li t1, 0
+ li t2, 0
+ li s0, 0
+ li s1, 0
+ li a2, 0
+ li a3, 0
+ li a4, 0
+ li a5, 0
+ li a6, 0
+ li a7, 0
+ li s2, 0
+ li s3, 0
+ li s4, 0
+ li s5, 0
+ li s6, 0
+ li s7, 0
+ li s8, 0
+ li s9, 0
+ li s10, 0
+ li s11, 0
+ li t3, 0
+ li t4, 0
+ li t5, 0
+ li t6, 0
+ csrw CSR_MSCRATCH, 0
+ ret
+
+ .align 3
+ .section .entry, "ax", %progbits
+ .global fw_prev_arg1
+fw_prev_arg1:
+
+ /* We return previous arg1 in 'a0' */
+ add a0, zero, zero
+ ret
+
+ .align 3
+ .section .entry, "ax", %progbits
+ .global fw_next_arg1
+fw_next_arg1:
+ /* We return next arg1 in 'a0' */
+ li a0, FixedPcdGet32(PcdRiscVPeiFvBase)
+ ret
+
+ .align 3
+ .section .entry, "ax", %progbits
+ .global fw_next_addr
+fw_next_addr:
+ /* We return next address in 'a0' */
+ la a0, _jump_addr
+ ld a0, (a0)
+ ret
+
+ .align 3
+ .section .entry, "ax", %progbits
+_jump_addr:
+RISCV_PTR SecCoreStartUpWithStack
--
2.31.1
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH 20/79] PlatformPkg: Add RiscVPlatformPkg
2022-01-08 4:10 [PATCH 02/79] ProcessorPkg/Library: RISC-V CPU library Abner Chang
` (16 preceding siblings ...)
2022-01-08 4:10 ` [PATCH 19/79] PlatformPkg/SecMain: RISC-V SecMain module Abner Chang
@ 2022-01-08 4:10 ` Abner Chang
2022-01-08 4:10 ` [PATCH 21/79] RISC-V/PlatformPkg: Revise Readme.md Abner Chang
` (19 subsequent siblings)
37 siblings, 0 replies; 39+ messages in thread
From: Abner Chang @ 2022-01-08 4:10 UTC (permalink / raw)
To: devel; +Cc: abner.chang
(This is migrated from edk2-platforms:Platform/RISC-V)
Add RISC-V platform package.
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Co-authored-by: Daniel Schaefer <daniel.schaefer@hpe.com>
Co-authored-by: Gilbert Chen <gilbert.chen@hpe.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>
---
.../RISC-V/PlatformPkg/RiscVPlatformPkg.dec | 77 +++++++++++++
.../RISC-V/PlatformPkg/RiscVPlatformPkg.dsc | 81 ++++++++++++++
Platform/RISC-V/PlatformPkg/Readme.md | 104 ++++++++++++++++++
.../RISC-V/PlatformPkg/RiscVPlatformPkg.uni | 15 +++
| 12 ++
5 files changed, 289 insertions(+)
create mode 100644 Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec
create mode 100644 Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dsc
create mode 100644 Platform/RISC-V/PlatformPkg/Readme.md
create mode 100644 Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.uni
create mode 100644 Platform/RISC-V/PlatformPkg/RiscVPlatformPkgExtra.uni
diff --git a/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec b/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec
new file mode 100644
index 0000000000..48aeb97431
--- /dev/null
+++ b/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec
@@ -0,0 +1,77 @@
+## @file RiscVPlatformPkg.dec
+# This Package provides UEFI RISC-V platform modules and libraries.
+#
+# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ DEC_SPECIFICATION = 0x0001001b
+ PACKAGE_NAME = RiscVPlatformPkg
+ PACKAGE_UNI_FILE = RiscVPlatformPkg.uni
+ PACKAGE_GUID = B51DBDBB-B43D-4D45-8CDD-1D6D1C691003
+ PACKAGE_VERSION = 1.0
+
+[Includes]
+ Include
+
+[LibraryClasses]
+ FirmwareContextProcessorSpecificLib|Include/Library/FirmwareContextProcessorSpecificLib.h
+ RiscVPlatformTempMemoryInitLib|Include/Library/RiscVPlatformTempMemoryInitLib.h
+
+[Guids]
+ gUefiRiscVPlatformPkgTokenSpaceGuid = {0x6A67AF99, 0x4592, 0x40F8, { 0xB6, 0xBE, 0x62, 0xBC, 0xA1, 0x0D, 0xA1, 0xEC}}
+
+[PcdsFixedAtBuild]
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVSecFvBase|0x0|UINT32|0x00001000
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVSecFvSize|0x0|UINT32|0x00001001
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVPeiFvBase|0x0|UINT32|0x00001002
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVPeiFvSize|0x0|UINT32|0x00001003
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVDxeFvBase|0x0|UINT32|0x00001004
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVDxeFvSize|0x0|UINT32|0x00001005
+
+#
+# Definition of EFI Variable region
+#
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFdBaseAddress|0|UINT32|0x00001010
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFdSize|0|UINT32|0x00001011
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFdBlockSize|0|UINT32|0x00001012
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPlatformFlashNvStorageVariableBase|0|UINT32|0x00001013
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPlatformFlashNvStorageFtwWorkingBase|0|UINT32|0x00001014
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPlatformFlashNvStorageFtwSpareBase|0|UINT32|0x00001015
+#
+# Firmware region which is protected by PMP.
+#
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFwBlockSize|0|UINT32|0x00001020
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFwStartAddress|0|UINT32|0x00001021
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFwEndAddress|0|UINT32|0x00001022
+#
+# Definition of RISC-V Hart
+#
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdHartCount|0|UINT32|0x00001023
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootHartId|0|UINT32|0x00001024
+#
+# The bootable hart core number, which is incorporate with OpenSBI platform hart_index2id value.
+#
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootableHartNumber|0|UINT32|0x00001025
+#
+# Definitions for OpenSbi
+#
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdScratchRamBase|0|UINT32|0x00001100
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdScratchRamSize|0|UINT32|0x00001101
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdOpenSbiStackSize|0|UINT32|0x00001102
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdTemporaryRamBase|0|UINT32|0x00001103
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdTemporaryRamSize|0|UINT32|0x00001104
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPeiCorePrivilegeMode|0|UINT32|0x00001105
+
+[PcdsPatchableInModule]
+
+[PcdsFeatureFlag]
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootlogoOnlyEnable|FALSE|BOOLEAN|0x00001006
+
+[PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx]
+
+[UserExtensions.TianoCore."ExtraFiles"]
+ RiscVPlatformPkgExtra.uni
diff --git a/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dsc b/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dsc
new file mode 100644
index 0000000000..092717d2ef
--- /dev/null
+++ b/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dsc
@@ -0,0 +1,81 @@
+#/** @file
+# RISC-V platform package.
+#
+# Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#**/
+
+################################################################################
+#
+# Defines Section
+#
+################################################################################
+[Defines]
+ PLATFORM_NAME = RiscVPlatform
+ PLATFORM_GUID = 840A9576-5869-491E-9210-89769DED4650
+ PLATFORM_VERSION = 0.1
+ DSC_SPECIFICATION = 0x0001001c
+ OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME)
+ SUPPORTED_ARCHITECTURES = RISCV64
+ BUILD_TARGETS = DEBUG|RELEASE|NOOPT
+ SKUID_IDENTIFIER = DEFAULT
+
+[BuildOptions]
+ GCC:RELEASE_*_*_CC_FLAGS = -DMDEPKG_NDEBUG
+!ifdef $(SOURCE_DEBUG_ENABLE)
+ GCC:*_*_RISCV64_GENFW_FLAGS = --keepexceptiontable
+!endif
+
+################################################################################
+#
+# SKU Identification section - list of all SKU IDs supported by this Platform.
+#
+################################################################################
+[SkuIds]
+ 0|DEFAULT
+
+[LibraryClasses.common]
+ RiscVOpensbiPlatformLib|Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLibNull/OpensbiPlatformLibNull.inf
+ RiscVCpuLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVCpuLib/RiscVCpuLib.inf
+ RiscVEdk2SbiLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVEdk2SbiLib/RiscVEdk2SbiLib.inf
+ RiscVOpensbiLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVOpensbiLib/RiscVOpensbiLib.inf
+ BaseLib|MdePkg/Library/BaseLib/BaseLib.inf
+ BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
+ DebugAgentLib|MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLibNull.inf
+ DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf
+ HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
+ IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
+ MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
+ PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+ PeCoffExtraActionLib|MdePkg/Library/BasePeCoffExtraActionLibNull/BasePeCoffExtraActionLibNull.inf
+ PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
+ PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
+ SerialPortLib|MdePkg/Library/BaseSerialPortLibNull/BaseSerialPortLibNull.inf
+ TimerLib|MdePkg/Library/BaseTimerLibNullTemplate/BaseTimerLibNullTemplate.inf
+ PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
+
+[LibraryClasses.common.PEIM]
+ FirmwareContextProcessorSpecificLib|Platform/RISC-V/PlatformPkg/Library/FirmwareContextProcessorSpecificLib/FirmwareContextProcessorSpecificLib.inf
+ HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
+ MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf
+ PeimEntryPoint|MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf
+
+[LibraryClasses.common.SEC]
+ ExtractGuidedSectionLib|MdePkg/Library/BaseExtractGuidedSectionLib/BaseExtractGuidedSectionLib.inf
+
+[LibraryClasses.common.DXE_DRIVER]
+ PlatformBootManagerLib|Platform/RISC-V/PlatformPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
+
+[Components.common]
+ Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLibNull/OpensbiPlatformLibNull.inf
+ Platform/RISC-V/PlatformPkg/Library/PlatformMemoryTestLibNull/PlatformMemoryTestLibNull.inf
+ Platform/RISC-V/PlatformPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
+ Platform/RISC-V/PlatformPkg/Library/PlatformUpdateProgressLibNull/PlatformUpdateProgressLibNull.inf
+ Platform/RISC-V/PlatformPkg/Library/FirmwareContextProcessorSpecificLib/FirmwareContextProcessorSpecificLib.inf
+ Platform/RISC-V/PlatformPkg/Library/RiscVPlatformTempMemoryInitLibNull/RiscVPlatformTempMemoryInitLibNull.inf
+
+[Components.common.SEC]
+ Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf
+
diff --git a/Platform/RISC-V/PlatformPkg/Readme.md b/Platform/RISC-V/PlatformPkg/Readme.md
new file mode 100644
index 0000000000..2632ebeb28
--- /dev/null
+++ b/Platform/RISC-V/PlatformPkg/Readme.md
@@ -0,0 +1,104 @@
+# Introduction
+
+## EDK2 RISC-V Platform Packages
+RISC-V platform package provides the generic and common modules for RISC-V
+platforms. RISC-V platform package could include RiscPlatformPkg.dec to
+use the common drivers, libraries, definitions, PCDs and etc. for the
+platform development.
+
+There are two packages to support RISC-V:
+- `edk2-platforms/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec`
+- `edk2-platforms/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec`
+
+`RiscVPlatformPkg` provides SEC phase and NULL libs.
+`RiscVProcessorPkg` provides many libraries, PEIMs and DXE drivers.
+
+### Download the sources ###
+```
+git clone https://github.com/tianocore/edk2.git
+
+git clone https://github.com/changab/edk2-platforms.git
+# Check out branch: riscv-smode-lib
+```
+
+To build it, you have to follow the regular steps for EDK2 and additionally set
+an environmen variable to point to your RISC-V toolchain installation,
+including the binary prefixes:
+
+```
+export GCC5_RISCV64_PREFIX=/riscv-gnu-toolchain-binaries/bin/riscv64-unknown-elf-
+```
+
+Then you can build the image for the SiFive HifiveUnleashed platform:
+
+```
+build -a RISCV64 -t GCC5 -p Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.dsc
+```
+
+### EDK2 project
+All changes in edk2 are upstream, however, most of the RISC-V code is in
+edk2-platforms. Therefore you have to check out the branch `riscv-smode-lib` on
+`github.com/changab/edk2-platforms`.
+
+The build architecture which is supported and verified so far is `RISCV64`.
+The latest master of the RISC-V toolchain https://github.com/riscv/riscv-gnu-toolchain
+should work but the latest verified commit is `b468107e701433e1caca3dbc8aef8d40`.
+Toolchain tag is "GCC5" declared in `tools_def.txt`
+
+## RISC-V Platform PCD settings
+### EDK2 Firmware Volume Settings
+EDK2 Firmware volume related PCDs which declared in platform FDF file.
+
+| **PCD name** |**Usage**|
+|--------------|---------|
+|PcdRiscVSecFvBase| The base address of SEC Firmware Volume|
+|PcdRiscVSecFvSize| The size of SEC Firmware Volume|
+|PcdRiscVPeiFvBase| The base address of PEI Firmware Volume|
+|PcdRiscVPeiFvSize| The size of SEC Firmware Volume|
+|PcdRiscVDxeFvBase| The base address of DXE Firmware Volume|
+|PcdRiscVDxeFvSize| The size of SEC Firmware Volume|
+
+### EDK2 EFI Variable Region Settings
+The PCD settings regard to EFI Variable
+
+| **PCD name** |**Usage**|
+|--------------|---------|
+|PcdVariableFdBaseAddress| The EFI variable firmware device base address|
+|PcdVariableFdSize| The EFI variable firmware device size|
+|PcdVariableFdBlockSize| The block size of EFI variable firmware device|
+|PcdPlatformFlashNvStorageVariableBase| EFI variable base address within firmware device|
+|PcdPlatformFlashNvStorageFtwWorkingBase| The base address of EFI variable fault tolerance worksapce (FTW) within firmware device|
+|PcdPlatformFlashNvStorageFtwSpareBase| The base address of EFI variable spare FTW within firmware device|
+
+### RISC-V Physical Memory Protection (PMP) Region Settings
+Below PCDs could be set in platform FDF file.
+
+| **PCD name** |**Usage**|
+|--------------|---------|
+|PcdFwStartAddress| The starting address of firmware region to protected by PMP|
+|PcdFwEndAddress| The ending address of firmware region to protected by PMP|
+
+### RISC-V Processor HART Settings
+
+| **PCD name** |**Usage**|
+|--------------|---------|
+|PcdHartCount| Number of RISC-V HARTs, the value is processor-implementation specific|
+|PcdBootHartId| The ID of RISC-V HART to execute main fimrware code and boot system to OS|
+
+### RISC-V OpenSBI Settings
+
+| **PCD name** |**Usage**|
+|--------------|---------|
+|PcdScratchRamBase| The base address of OpenSBI scratch buffer for all RISC-V HARTs|
+|PcdScratchRamSize| The total size of OpenSBI scratch buffer for all RISC-V HARTs|
+|PcdOpenSbiStackSize| The size of initial stack of each RISC-V HART for booting system use OpenSBI|
+|PcdTemporaryRamBase| The base address of temporary memory for PEI phase|
+|PcdTemporaryRamSize| The temporary memory size for PEI phase|
+
+## Supported Operating Systems
+Only support to boot to EFI Shell so far.
+
+Porting GRUB2 and Linux EFISTUB is in progress.
+
+## Known Issues and Limitations
+Only RISC-V RV64 is verified.
diff --git a/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.uni b/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.uni
new file mode 100644
index 0000000000..deb91fa10c
--- /dev/null
+++ b/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.uni
@@ -0,0 +1,15 @@
+// /** @file
+// RISC-V Package Localized Strings and Content.
+//
+// Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+//
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+// **/
+
+
+#string STR_PACKAGE_ABSTRACT #language en-US "Provides UEFI compatible RISC-V platform modules and libraries"
+
+#string STR_PACKAGE_DESCRIPTION #language en-US "This Package provides UEFI compatible RISC-V platform modules and libraries."
+
+
--git a/Platform/RISC-V/PlatformPkg/RiscVPlatformPkgExtra.uni b/Platform/RISC-V/PlatformPkg/RiscVPlatformPkgExtra.uni
new file mode 100644
index 0000000000..493f5f42fe
--- /dev/null
+++ b/Platform/RISC-V/PlatformPkg/RiscVPlatformPkgExtra.uni
@@ -0,0 +1,12 @@
+// /** @file
+// RISC-V Package Localized Strings and Content.
+//
+// Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+//
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+// **/
+
+#string STR_PROPERTIES_PACKAGE_NAME
+#language en-US
+"RISC-V platform package"
--
2.31.1
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH 21/79] RISC-V/PlatformPkg: Revise Readme.md
2022-01-08 4:10 [PATCH 02/79] ProcessorPkg/Library: RISC-V CPU library Abner Chang
` (17 preceding siblings ...)
2022-01-08 4:10 ` [PATCH 20/79] PlatformPkg: Add RiscVPlatformPkg Abner Chang
@ 2022-01-08 4:10 ` Abner Chang
2022-01-08 4:10 ` [PATCH 22/79] Silicon/SiFive: Handle case of NULL FirmwareContext Abner Chang
` (18 subsequent siblings)
37 siblings, 0 replies; 39+ messages in thread
From: Abner Chang @ 2022-01-08 4:10 UTC (permalink / raw)
To: devel; +Cc: abner.chang
(This is migrated from edk2-platforms:Platform)
Update RISC-V PlatformPkg Readme.md to align with the latest implementation.
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Co-authored-by: Daniel Schaefer <daniel.schaefer@hpe.com>
Reviewed-by: Daniel Schaefer <daniel.schaefer@hpe.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Daniel Schaefer <daniel.schaefer@hpe.com>
---
Platform/RISC-V/PlatformPkg/Readme.md | 88 ++++++++++++++++-----------
1 file changed, 52 insertions(+), 36 deletions(-)
diff --git a/Platform/RISC-V/PlatformPkg/Readme.md b/Platform/RISC-V/PlatformPkg/Readme.md
index 2632ebeb28..4b933a2e0f 100644
--- a/Platform/RISC-V/PlatformPkg/Readme.md
+++ b/Platform/RISC-V/PlatformPkg/Readme.md
@@ -1,49 +1,62 @@
# Introduction
-## EDK2 RISC-V Platform Packages
-RISC-V platform package provides the generic and common modules for RISC-V
-platforms. RISC-V platform package could include RiscPlatformPkg.dec to
-use the common drivers, libraries, definitions, PCDs and etc. for the
-platform development.
+## EDK2 RISC-V Platform Project
-There are two packages to support RISC-V:
-- `edk2-platforms/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec`
-- `edk2-platforms/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec`
+### EDK2 Build Architecture for RISC-V
+The edk2 build architecture which is supported and verified on edk2 code base for
+RISC-V platforms is `RISCV64`.
-`RiscVPlatformPkg` provides SEC phase and NULL libs.
-`RiscVProcessorPkg` provides many libraries, PEIMs and DXE drivers.
+### Toolchain for RISC-V
+The toolchain is on RISC-V GitHub (https://github.com/riscv/riscv-gnu-toolchain)
+for building edk2 RISC-V binary. The corresponding edk2 Toolchain tag for building
+RISC-V platform is "GCC5" declared in `tools_def.txt`.
-### Download the sources ###
+### Packages
+There are two packages to support RISC-V edk2 platforms:
+- `Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec`
+- `Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec`
+
+`RiscVPlatformPkg` currently provides the generic SEC driver for all RISC-V platforms,
+and some platform level libraries.
+`RiscVProcessorPkg` currently provides RISC-V processor related libraries, PEI modules,
+DXE drivers and industrial standard header files.
+
+## EDK2 RISC-V Platform Package
+RISC-V platform package provides the common modules for RISC-V platforms. RISC-V
+platform vendors could include RiscPlatformPkg.dec to use the common drivers, libraries,
+definitions, PCDs and etc. for the RISC-V platforms development.
+
+### Download the Source Code ###
```
git clone https://github.com/tianocore/edk2.git
+git clone https://github.com/tianocore/edk2-platforms.git
-git clone https://github.com/changab/edk2-platforms.git
-# Check out branch: riscv-smode-lib
```
-To build it, you have to follow the regular steps for EDK2 and additionally set
-an environmen variable to point to your RISC-V toolchain installation,
-including the binary prefixes:
-
+You have to follow the build steps for
+EDK2 (https://github.com/tianocore/tianocore.github.io/wiki/Getting-Started-with-EDK-II)
+and additionally set an environment variable to point to your RISC-V toolchain binaries
+for building RISC-V platforms,
```
+# e.g. If the toolchain binaries are under /riscv-gnu-toolchain-binaries/bin
export GCC5_RISCV64_PREFIX=/riscv-gnu-toolchain-binaries/bin/riscv64-unknown-elf-
```
-Then you can build the image for the SiFive HifiveUnleashed platform:
+Then you can build the edk2 firmware image for RISC-V platforms.
```
+# e.g. For building SiFive Hifive Unleashed platform:
build -a RISCV64 -t GCC5 -p Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.dsc
```
-### EDK2 project
-All changes in edk2 are upstream, however, most of the RISC-V code is in
-edk2-platforms. Therefore you have to check out the branch `riscv-smode-lib` on
-`github.com/changab/edk2-platforms`.
-
-The build architecture which is supported and verified so far is `RISCV64`.
-The latest master of the RISC-V toolchain https://github.com/riscv/riscv-gnu-toolchain
-should work but the latest verified commit is `b468107e701433e1caca3dbc8aef8d40`.
-Toolchain tag is "GCC5" declared in `tools_def.txt`
+## RISC-V OpenSBI Library
+RISC-V [OpenSBI](https://github.com/riscv/opensbi) is the implementation of
+[RISC-V SBI (Supervisor Binary Interface) specification](https://github.com/riscv/riscv-sbi-doc).
+For EDK2 UEFI firmware solution, RISC-V OpenSBI is integrated as a library
+[(submoudule)](Silicon/RISC-V/ProcessorPkg/Library/RiscVOpensbiLib/opensbi) in EDK2
+RISC-V Processor Package. The RISC-V OpenSBI library is built in SEC driver without
+any modifications and provides the interfaces for supervisor mode execution environment
+to execute privileged operations.
## RISC-V Platform PCD settings
### EDK2 Firmware Volume Settings
@@ -54,9 +67,9 @@ EDK2 Firmware volume related PCDs which declared in platform FDF file.
|PcdRiscVSecFvBase| The base address of SEC Firmware Volume|
|PcdRiscVSecFvSize| The size of SEC Firmware Volume|
|PcdRiscVPeiFvBase| The base address of PEI Firmware Volume|
-|PcdRiscVPeiFvSize| The size of SEC Firmware Volume|
+|PcdRiscVPeiFvSize| The size of PEI Firmware Volume|
|PcdRiscVDxeFvBase| The base address of DXE Firmware Volume|
-|PcdRiscVDxeFvSize| The size of SEC Firmware Volume|
+|PcdRiscVDxeFvSize| The size of DXE Firmware Volume|
### EDK2 EFI Variable Region Settings
The PCD settings regard to EFI Variable
@@ -84,21 +97,24 @@ Below PCDs could be set in platform FDF file.
|--------------|---------|
|PcdHartCount| Number of RISC-V HARTs, the value is processor-implementation specific|
|PcdBootHartId| The ID of RISC-V HART to execute main fimrware code and boot system to OS|
+|PcdBootableHartNumber|The bootable HART number, which is incorporate with RISC-V OpenSBI platform hart_index2id value|
### RISC-V OpenSBI Settings
| **PCD name** |**Usage**|
|--------------|---------|
-|PcdScratchRamBase| The base address of OpenSBI scratch buffer for all RISC-V HARTs|
-|PcdScratchRamSize| The total size of OpenSBI scratch buffer for all RISC-V HARTs|
-|PcdOpenSbiStackSize| The size of initial stack of each RISC-V HART for booting system use OpenSBI|
+|PcdScratchRamBase| The base address of RISC-V OpenSBI scratch buffer for all RISC-V HARTs|
+|PcdScratchRamSize| The total size of RISC-V OpenSBI scratch buffer for all RISC-V HARTs|
+|PcdOpenSbiStackSize| The size of initial stack of each RISC-V HART for booting system use RISC-V OpenSBI|
|PcdTemporaryRamBase| The base address of temporary memory for PEI phase|
|PcdTemporaryRamSize| The temporary memory size for PEI phase|
+|PcdPeiCorePrivilegeMode|The target RISC-V privilege mode for edk2 PEI phase|
## Supported Operating Systems
-Only support to boot to EFI Shell so far.
-
-Porting GRUB2 and Linux EFISTUB is in progress.
+Currently support boot to EFI Shell and Linux kernel.
+Refer to below link for more information,
+https://github.com/riscv/riscv-uefi-edk2-docs
## Known Issues and Limitations
-Only RISC-V RV64 is verified.
+Only RISC-V RV64 is verified on edk2.
+
--
2.31.1
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH 22/79] Silicon/SiFive: Handle case of NULL FirmwareContext
2022-01-08 4:10 [PATCH 02/79] ProcessorPkg/Library: RISC-V CPU library Abner Chang
` (18 preceding siblings ...)
2022-01-08 4:10 ` [PATCH 21/79] RISC-V/PlatformPkg: Revise Readme.md Abner Chang
@ 2022-01-08 4:10 ` Abner Chang
2022-01-08 4:10 ` [PATCH 23/79] Silicon/RISC-V: Update old SMBIOS struct filed name Abner Chang
` (17 subsequent siblings)
37 siblings, 0 replies; 39+ messages in thread
From: Abner Chang @ 2022-01-08 4:10 UTC (permalink / raw)
To: devel; +Cc: abner.chang
(This is migrated from edk2-platforms:Silicon)
Abort creating the SMBIOS HOBs if there's no firmware context to get the
information from.
Turn SbiLib functions for getting mscratch into VOID since they can never
practically fail.
Signed-off-by: Daniel Schaefer <daniel.schaefer@hpe.com>
Reviewed-by: Abner Chang <abner.chang@hpe.com>
Cc: Abner Chang <abner.chang@hpe.com>
Cc: Leif Lindholm <leif@nuviainc.com>
---
.../Include/Library/RiscVEdk2SbiLib.h | 12 ++---
.../PlatformPkg/Universal/Sec/SecMain.c | 11 +++--
.../Library/RiscVEdk2SbiLib/RiscVEdk2SbiLib.c | 46 +++++++------------
3 files changed, 28 insertions(+), 41 deletions(-)
diff --git a/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVEdk2SbiLib.h b/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVEdk2SbiLib.h
index 558841a970..f81ea06b05 100644
--- a/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVEdk2SbiLib.h
+++ b/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVEdk2SbiLib.h
@@ -514,9 +514,8 @@ SbiVendorCall (
access the firmware context.
@param[out] ScratchSpace The scratch space pointer.
- @retval EFI_SUCCESS The operation succeeds.
**/
-EFI_STATUS
+VOID
EFIAPI
SbiGetMscratch (
OUT SBI_SCRATCH **ScratchSpace
@@ -527,9 +526,8 @@ SbiGetMscratch (
@param[in] HartId The hart id.
@param[out] ScratchSpace The scratch space pointer.
- @retval EFI_SUCCESS The operation succeeds.
**/
-EFI_STATUS
+VOID
EFIAPI
SbiGetMscratchHartid (
IN UINTN HartId,
@@ -540,9 +538,8 @@ SbiGetMscratchHartid (
Get firmware context of the calling hart.
@param[out] FirmwareContext The firmware context pointer.
- @retval EFI_SUCCESS The operation succeeds.
**/
-EFI_STATUS
+VOID
EFIAPI
SbiGetFirmwareContext (
OUT EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT **FirmwareContext
@@ -552,9 +549,8 @@ SbiGetFirmwareContext (
Set firmware context of the calling hart.
@param[in] FirmwareContext The firmware context pointer.
- @retval EFI_SUCCESS The operation succeeds.
**/
-EFI_STATUS
+VOID
EFIAPI
SbiSetFirmwareContext (
IN EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *FirmwareContext
diff --git a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c
index 877777bfa1..fa9ecd789a 100644
--- a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c
+++ b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c
@@ -415,7 +415,10 @@ EFI_STATUS EFIAPI TemporaryRamDone (
return EFI_SUCCESS;
}
-/** Handles SBI calls of EDK2's SBI FW extension
+/**
+ Handles SBI calls of EDK2's SBI FW extension.
+
+ The return value is the error code returned by the SBI call.
@param[in] ExtId The extension ID of the FW extension.
@param[in] FuncId The called function ID.
@@ -424,7 +427,7 @@ EFI_STATUS EFIAPI TemporaryRamDone (
@param[out] OutTrap Trap info for trapping further, see OpenSBI code.
Is ignored if return value is not SBI_ETRAP.
- @retval 0 If the handler succeeds.
+ @retval SBI_OK If the handler succeeds.
@retval SBI_ENOTSUPP If there's no function with the given ID.
@retval SBI_ETRAP If the called SBI functions wants to trap further.
**/
@@ -436,7 +439,7 @@ STATIC int SbiEcallFirmwareHandler (
OUT struct sbi_trap_info *OutTrap
)
{
- int Ret = 0;
+ int Ret = SBI_OK;
switch (FuncId) {
case SBI_EXT_FW_MSCRATCH_FUNC:
@@ -447,6 +450,8 @@ STATIC int SbiEcallFirmwareHandler (
break;
default:
Ret = SBI_ENOTSUPP;
+ DEBUG ((DEBUG_ERROR, "%a: Called SBI firmware ecall with invalid function ID\n", __FUNCTION__));
+ ASSERT (FALSE);
};
return Ret;
diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVEdk2SbiLib/RiscVEdk2SbiLib.c b/Silicon/RISC-V/ProcessorPkg/Library/RiscVEdk2SbiLib/RiscVEdk2SbiLib.c
index 0df505d267..9bbeaaec3f 100644
--- a/Silicon/RISC-V/ProcessorPkg/Library/RiscVEdk2SbiLib/RiscVEdk2SbiLib.c
+++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVEdk2SbiLib/RiscVEdk2SbiLib.c
@@ -801,9 +801,8 @@ SbiVendorCall (
access the firmware context.
@param[out] ScratchSpace The scratch space pointer.
- @retval EFI_SUCCESS The operation succeeds.
**/
-EFI_STATUS
+VOID
EFIAPI
SbiGetMscratch (
OUT SBI_SCRATCH **ScratchSpace
@@ -811,11 +810,10 @@ SbiGetMscratch (
{
SbiRet Ret = SbiCall (SBI_EDK2_FW_EXT, SBI_EXT_FW_MSCRATCH_FUNC, 0);
- if (!Ret.Error) {
- *ScratchSpace = (SBI_SCRATCH *)Ret.Value;
- }
+ // Our ecall handler never returns an error, only when the func id is invalid
+ ASSERT (Ret.Error == SBI_OK);
- return EFI_SUCCESS;
+ *ScratchSpace = (SBI_SCRATCH *)Ret.Value;
}
/**
@@ -823,9 +821,8 @@ SbiGetMscratch (
@param[in] HartId The hart id.
@param[out] ScratchSpace The scratch space pointer.
- @retval EFI_SUCCESS The operation succeeds.
**/
-EFI_STATUS
+VOID
EFIAPI
SbiGetMscratchHartid (
IN UINTN HartId,
@@ -839,11 +836,10 @@ SbiGetMscratchHartid (
HartId
);
- if (!Ret.Error) {
- *ScratchSpace = (SBI_SCRATCH *)Ret.Value;
- }
+ // Our ecall handler never returns an error, only when the func id is invalid
+ ASSERT (Ret.Error == SBI_OK);
- return EFI_SUCCESS;
+ *ScratchSpace = (SBI_SCRATCH *)Ret.Value;
}
/**
@@ -852,7 +848,7 @@ SbiGetMscratchHartid (
@param[out] FirmwareContext The firmware context pointer.
@retval EFI_SUCCESS The operation succeeds.
**/
-EFI_STATUS
+VOID
EFIAPI
SbiGetFirmwareContext (
OUT EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT **FirmwareContext
@@ -860,24 +856,18 @@ SbiGetFirmwareContext (
{
SBI_SCRATCH *ScratchSpace;
SBI_PLATFORM *SbiPlatform;
- SbiRet Ret = SbiCall (SBI_EDK2_FW_EXT, SBI_EXT_FW_MSCRATCH_FUNC, 0);
-
- if (!Ret.Error) {
- ScratchSpace = (SBI_SCRATCH *)Ret.Value;
- SbiPlatform = (SBI_PLATFORM *)sbi_platform_ptr(ScratchSpace);
- *FirmwareContext = (EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *)SbiPlatform->firmware_context;
- }
- return EFI_SUCCESS;
+ SbiGetMscratch(&ScratchSpace);
+ SbiPlatform = (SBI_PLATFORM *)sbi_platform_ptr(ScratchSpace);
+ *FirmwareContext = (EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *)SbiPlatform->firmware_context;
}
/**
Set firmware context of the calling hart.
@param[in] FirmwareContext The firmware context pointer.
- @retval EFI_SUCCESS The operation succeeds.
**/
-EFI_STATUS
+VOID
EFIAPI
SbiSetFirmwareContext (
IN EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *FirmwareContext
@@ -885,13 +875,9 @@ SbiSetFirmwareContext (
{
SBI_SCRATCH *ScratchSpace;
SBI_PLATFORM *SbiPlatform;
- SbiRet Ret = SbiCall (SBI_EDK2_FW_EXT, SBI_EXT_FW_MSCRATCH_FUNC, 0);
- if (!Ret.Error) {
- ScratchSpace = (SBI_SCRATCH *)Ret.Value;
- SbiPlatform = (SBI_PLATFORM *)sbi_platform_ptr (ScratchSpace);
- SbiPlatform->firmware_context = (UINTN)FirmwareContext;
- }
+ SbiGetMscratch(&ScratchSpace);
- return EFI_SUCCESS;
+ SbiPlatform = (SBI_PLATFORM *)sbi_platform_ptr (ScratchSpace);
+ SbiPlatform->firmware_context = (UINTN)FirmwareContext;
}
--
2.31.1
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH 23/79] Silicon/RISC-V: Update old SMBIOS struct filed name
2022-01-08 4:10 [PATCH 02/79] ProcessorPkg/Library: RISC-V CPU library Abner Chang
` (19 preceding siblings ...)
2022-01-08 4:10 ` [PATCH 22/79] Silicon/SiFive: Handle case of NULL FirmwareContext Abner Chang
@ 2022-01-08 4:10 ` Abner Chang
2022-01-08 4:10 ` [PATCH 24/79] Platform/RISC-V: Consume MdeLibs.dsc.inc for RegisterFilterLib Abner Chang
` (16 subsequent siblings)
37 siblings, 0 replies; 39+ messages in thread
From: Abner Chang @ 2022-01-08 4:10 UTC (permalink / raw)
To: devel; +Cc: abner.chang
(This is migrated from edk2-platforms:Silicon)
The "ProcessorManufacture" field of SMBIOS_TABLE_TYPE4 was recently
renamed to "ProcessorManufacturer". This is causing a compilation
error for RISC-V/SiFive builds. Switch to the new name.
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Abner Chang <abner.chang@hpe.com>
Cc: Daniel Schaefer <daniel.schaefer@hpe.com>
Cc: Gilbert Chen <gilbert.chen@hpe.com>
Signed-off-by: Mark Salter <msalter@redhat.com>
Reviewed-by: Abner Chang <abner.chang@hpe.com>
---
.../RISC-V/ProcessorPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Silicon/RISC-V/ProcessorPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.c b/Silicon/RISC-V/ProcessorPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.c
index 6079513a55..b30f9d7f6a 100644
--- a/Silicon/RISC-V/ProcessorPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.c
+++ b/Silicon/RISC-V/ProcessorPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.c
@@ -142,7 +142,7 @@ BuildSmbiosType4 (
DEBUG ((DEBUG_VERBOSE, " Socket StringID: %d\n", Type4HobData->SmbiosType4Processor.Socket));
DEBUG ((DEBUG_VERBOSE, " Processor Type: 0x%x\n", Type4HobData->SmbiosType4Processor.ProcessorType));
DEBUG ((DEBUG_VERBOSE, " Processor Family: 0x%x\n", Type4HobData->SmbiosType4Processor.ProcessorFamily));
- DEBUG ((DEBUG_VERBOSE, " Processor Manufacture StringID: %d\n", Type4HobData->SmbiosType4Processor.ProcessorManufacture));
+ DEBUG ((DEBUG_VERBOSE, " Processor Manufacture StringID: %d\n", Type4HobData->SmbiosType4Processor.ProcessorManufacturer));
DEBUG ((DEBUG_VERBOSE, " Processor Id: 0x%x:0x%x\n", \
Type4HobData->SmbiosType4Processor.ProcessorId.Signature, Type4HobData->SmbiosType4Processor.ProcessorId.FeatureFlags));
DEBUG ((DEBUG_VERBOSE, " Processor Version StringID: %d\n", Type4HobData->SmbiosType4Processor.ProcessorVersion));
--
2.31.1
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH 24/79] Platform/RISC-V: Consume MdeLibs.dsc.inc for RegisterFilterLib
2022-01-08 4:10 [PATCH 02/79] ProcessorPkg/Library: RISC-V CPU library Abner Chang
` (20 preceding siblings ...)
2022-01-08 4:10 ` [PATCH 23/79] Silicon/RISC-V: Update old SMBIOS struct filed name Abner Chang
@ 2022-01-08 4:10 ` Abner Chang
2022-01-08 4:10 ` [PATCH 25/79] Silicon/RISC_V: " Abner Chang
` (15 subsequent siblings)
37 siblings, 0 replies; 39+ messages in thread
From: Abner Chang @ 2022-01-08 4:10 UTC (permalink / raw)
To: devel; +Cc: abner.chang
From: Dandan Bi <dandan.bi@intel.com>
(This is migrated from edk2-platforms:Platform)
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3246
MdeLibs.dsc.inc was added for some basic/default library
instances provided by MdePkg and RegisterFilterLibNull Library
was also added into it as the first version of MdeLibs.dsc.inc.
So update platform dsc to consume MdeLibs.dsc.inc for
RegisterFilterLibNull which will be consumed by IoLib and BaseLib.
Cc: Abner Chang <abner.chang@hpe.com>
Cc: Daniel Schaefer <daniel.schaefer@hpe.com>
Cc: Gilbert Chen <gilbert.chen@hpe.com>
Signed-off-by: Dandan Bi <dandan.bi@intel.com>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Abner Chang <abner.chang@hpe.com>
---
Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dsc | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dsc b/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dsc
index 092717d2ef..5d9674a965 100644
--- a/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dsc
+++ b/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dsc
@@ -36,6 +36,8 @@
[SkuIds]
0|DEFAULT
+!include MdePkg/MdeLibs.dsc.inc
+
[LibraryClasses.common]
RiscVOpensbiPlatformLib|Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLibNull/OpensbiPlatformLibNull.inf
RiscVCpuLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVCpuLib/RiscVCpuLib.inf
--
2.31.1
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH 25/79] Silicon/RISC_V: Consume MdeLibs.dsc.inc for RegisterFilterLib
2022-01-08 4:10 [PATCH 02/79] ProcessorPkg/Library: RISC-V CPU library Abner Chang
` (21 preceding siblings ...)
2022-01-08 4:10 ` [PATCH 24/79] Platform/RISC-V: Consume MdeLibs.dsc.inc for RegisterFilterLib Abner Chang
@ 2022-01-08 4:10 ` Abner Chang
2022-01-08 4:10 ` [PATCH 26/79] RISC-V/CpuDxe: Ignore set memory attributes failure Abner Chang
` (14 subsequent siblings)
37 siblings, 0 replies; 39+ messages in thread
From: Abner Chang @ 2022-01-08 4:10 UTC (permalink / raw)
To: devel; +Cc: abner.chang
From: Dandan Bi <dandan.bi@intel.com>
(This is migrated from edk2-platforms:Silicon)
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3246
MdeLibs.dsc.inc was added for some basic/default library
instances provided by MdePkg and RegisterFilterLibNull Library
was also added into it as the first version of MdeLibs.dsc.inc.
So update platform dsc to consume MdeLibs.dsc.inc for
RegisterFilterLibNull which will be consumed by IoLib and BaseLib.
Cc: Abner Chang <abner.chang@hpe.com>
Cc: Daniel Schaefer <daniel.schaefer@hpe.com>
Cc: Gilbert Chen <gilbert.chen@hpe.com>
Signed-off-by: Dandan Bi <dandan.bi@intel.com>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Abner Chang <abner.chang@hpe.com>
---
Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dsc | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dsc b/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dsc
index 5f88f5e89f..5c5cfcb525 100644
--- a/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dsc
+++ b/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dsc
@@ -36,6 +36,8 @@
[SkuIds]
0|DEFAULT
+!include MdePkg/MdeLibs.dsc.inc
+
[LibraryClasses.common]
CpuExceptionHandlerLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVExceptionLib/CpuExceptionHandlerDxeLib.inf
RiscVCpuLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVCpuLib/RiscVCpuLib.inf
--
2.31.1
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH 26/79] RISC-V/CpuDxe: Ignore set memory attributes failure
2022-01-08 4:10 [PATCH 02/79] ProcessorPkg/Library: RISC-V CPU library Abner Chang
` (22 preceding siblings ...)
2022-01-08 4:10 ` [PATCH 25/79] Silicon/RISC_V: " Abner Chang
@ 2022-01-08 4:10 ` Abner Chang
2022-01-08 4:10 ` [PATCH 27/79] Signal EndOfDxe in boot manager Abner Chang
` (13 subsequent siblings)
37 siblings, 0 replies; 39+ messages in thread
From: Abner Chang @ 2022-01-08 4:10 UTC (permalink / raw)
To: devel; +Cc: abner.chang
From: Daniel Schaefer <daniel.schaefer@hpe.com>
(This is migrated from edk2-platforms:Silicon)
While enumerating the PCIe devices, the driver tries to set some caching
attributes on the memory.
Cc: Abner Chang <abner.chang@hpe.com>
Cc: Sunil V L <sunilvl@ventanamicro.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
Reviewed-by: Abner Chang <abner.chang@hpe.com>
Signed-off-by: Daniel Schaefer <daniel.schaefer@hpe.com>
---
Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxe.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxe.c b/Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxe.c
index 27a07b1561..b8b8e91a6c 100644
--- a/Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxe.c
+++ b/Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxe.c
@@ -1,7 +1,7 @@
/** @file
RISC-V CPU DXE driver.
- Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+ Copyright (c) 2016 - 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -269,7 +269,7 @@ CpuSetMemoryAttributes (
)
{
DEBUG ((DEBUG_INFO, "%a: Set memory attributes not supported yet\n", __FUNCTION__));
- return EFI_UNSUPPORTED;
+ return EFI_SUCCESS;
}
/**
--
2.31.1
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH 27/79] Signal EndOfDxe in boot manager
2022-01-08 4:10 [PATCH 02/79] ProcessorPkg/Library: RISC-V CPU library Abner Chang
` (23 preceding siblings ...)
2022-01-08 4:10 ` [PATCH 26/79] RISC-V/CpuDxe: Ignore set memory attributes failure Abner Chang
@ 2022-01-08 4:10 ` Abner Chang
2022-01-08 4:10 ` [PATCH 28/79] U5SeriesPkg: Deduplicate PlatformPei Abner Chang
` (12 subsequent siblings)
37 siblings, 0 replies; 39+ messages in thread
From: Abner Chang @ 2022-01-08 4:10 UTC (permalink / raw)
To: devel; +Cc: abner.chang
From: Daniel Schaefer <daniel.schaefer@hpe.com>
(This is migrated from edk2-platforms:Platform)
Otherwise we can't load a 3rd party image because we're still in DXE.
MdeModulePkg/Universal/SecurityStubDxe/Defer3rdPartyImageLoad.c prevents
that.
Cc: Abner Chang <abner.chang@hpe.com>
Cc: Sunil V L <sunilvl@ventanamicro.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
Reviewed-by: Abner Chang <abner.chang@hpe.com>
Signed-off-by: Daniel Schaefer <daniel.schaefer@hpe.com>
---
.../PlatformBootManagerLib/PlatformBootManagerLib.inf | 3 ++-
.../Library/PlatformBootManagerLib/PlatformBootManager.c | 7 ++++++-
2 files changed, 8 insertions(+), 2 deletions(-)
diff --git a/Platform/RISC-V/PlatformPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf b/Platform/RISC-V/PlatformPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
index afba07573f..2bf89a3c44 100644
--- a/Platform/RISC-V/PlatformPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
+++ b/Platform/RISC-V/PlatformPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
@@ -1,7 +1,7 @@
## @file
# Include all platform action which can be customized by IBV/OEM.
#
-# Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -48,6 +48,7 @@
PrintLib
[Guids]
+ gEfiEndOfDxeEventGroupGuid
[Protocols]
gEfiGenericMemTestProtocolGuid ## CONSUMES
diff --git a/Platform/RISC-V/PlatformPkg/Library/PlatformBootManagerLib/PlatformBootManager.c b/Platform/RISC-V/PlatformPkg/Library/PlatformBootManagerLib/PlatformBootManager.c
index 82cd311df5..d67f4836fc 100644
--- a/Platform/RISC-V/PlatformPkg/Library/PlatformBootManagerLib/PlatformBootManager.c
+++ b/Platform/RISC-V/PlatformPkg/Library/PlatformBootManagerLib/PlatformBootManager.c
@@ -1,7 +1,7 @@
/** @file
This file include all platform actions
-Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -155,6 +155,11 @@ PlatformBootManagerBeforeConsole (
EFI_INPUT_KEY F2;
EFI_BOOT_MANAGER_LOAD_OPTION BootOption;
+ //
+ // Signal EndOfDxe PI Event
+ //
+ EfiEventGroupSignal (&gEfiEndOfDxeEventGroupGuid);
+
//
// Update the console variables.
//
--
2.31.1
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH 28/79] U5SeriesPkg: Deduplicate PlatformPei
2022-01-08 4:10 [PATCH 02/79] ProcessorPkg/Library: RISC-V CPU library Abner Chang
` (24 preceding siblings ...)
2022-01-08 4:10 ` [PATCH 27/79] Signal EndOfDxe in boot manager Abner Chang
@ 2022-01-08 4:10 ` Abner Chang
2022-01-08 4:10 ` [PATCH 29/79] RISC-V: Split SMBIOS out of PlatformPei Abner Chang
` (11 subsequent siblings)
37 siblings, 0 replies; 39+ messages in thread
From: Abner Chang @ 2022-01-08 4:10 UTC (permalink / raw)
To: devel; +Cc: abner.chang
(This is migrated from edk2-platforms)
The current (and future) RISC-V platforms share a lot of PlatformPei
code that does not need to be duplicated. If we see that they need to
have different behavior in the future, we can add platform specific
libraires for that specific code.
The upcoming RiscvVirt is only 1205 lines with this patch.
Still way too much. Hopefully MinPlatform will help.
26 ./RiscvVirt.dec
13 ./RiscvVirt.uni
12 ./RiscvVirtPkgExtra.uni
78 ./VarStore.fdf.inc
66 ./RiscvVirt.fdf.inc
654 ./RiscvVirt.dsc
356 ./RiscvVirt.fdf
1205 total
Cc: Abner Chang <abner.chang@hpe.com>
Cc: Sunil V L <sunilvl@ventanamicro.com>
Reviewed-by: Abner Chang <abner.chang@hpe.com>
Signed-off-by: Daniel Schaefer <daniel.schaefer@hpe.com>
---
.../Universal/Pei/PlatformPei/PlatformPei.inf | 74 +++++
.../Universal/Pei/PlatformPei/Platform.h | 86 +++++
.../Universal/Pei/PlatformPei/Fv.c | 51 +++
.../Universal/Pei/PlatformPei/MemDetect.c | 81 +++++
.../Universal/Pei/PlatformPei/Platform.c | 314 ++++++++++++++++++
5 files changed, 606 insertions(+)
create mode 100644 Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei/PlatformPei.inf
create mode 100644 Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei/Platform.h
create mode 100644 Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei/Fv.c
create mode 100644 Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei/MemDetect.c
create mode 100644 Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei/Platform.c
diff --git a/Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei/PlatformPei.inf b/Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei/PlatformPei.inf
new file mode 100644
index 0000000000..e7f5eef630
--- /dev/null
+++ b/Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei/PlatformPei.inf
@@ -0,0 +1,74 @@
+## @file
+# Platform PEI driver
+#
+# This module provides platform specific function to detect boot mode.
+#
+# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001b
+ BASE_NAME = PlatformPei
+ FILE_GUID = 5592FC16-8FEF-4DE3-A6CF-6C59081E4EB7
+ MODULE_TYPE = PEIM
+ VERSION_STRING = 1.0
+ ENTRY_POINT = InitializePlatform
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = RISCV64
+#
+
+[Sources]
+ Fv.c
+ MemDetect.c
+ Platform.c
+
+[Packages]
+ MdeModulePkg/MdeModulePkg.dec
+ MdePkg/MdePkg.dec
+ Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec
+ Platform/SiFive/U5SeriesPkg/U5SeriesPkg.dec
+ Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec
+ Silicon/SiFive/SiFive.dec
+ UefiCpuPkg/UefiCpuPkg.dec
+
+[Guids]
+ gEfiMemoryTypeInformationGuid
+ gSiFiveU5SeriesPlatformsPkgTokenSpaceGuid
+
+[LibraryClasses]
+ DebugLib
+ HobLib
+ IoLib
+ PciLib
+ PeiResourcePublicationLib
+ PeiServicesLib
+ PeiServicesTablePointerLib
+ PeimEntryPoint
+ PcdLib
+ SiliconSiFiveU5MCCoreplexInfoLib
+
+[Pcd]
+ gEfiMdeModulePkgTokenSpaceGuid.PcdEmuVariableNvStoreReserved
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
+ gEfiMdeModulePkgTokenSpaceGuid.PcdPciDisableBusEnumeration
+ gEfiMdeModulePkgTokenSpaceGuid.PcdVariableStoreSize
+ gEfiMdePkgTokenSpaceGuid.PcdGuidedExtractHandlerTableAddress
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVDxeFvBase
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVDxeFvSize
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdTemporaryRamBase
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdTemporaryRamSize
+ gSiFiveU5SeriesPlatformsPkgTokenSpaceGuid.PcdNumberofU5Cores
+ gSiFiveU5SeriesPlatformsPkgTokenSpaceGuid.PcdE5MCSupported
+
+[Ppis]
+ gEfiPeiMasterBootModePpiGuid
+
+[Depex]
+ TRUE
diff --git a/Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei/Platform.h b/Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei/Platform.h
new file mode 100644
index 0000000000..c2cdd6d75b
--- /dev/null
+++ b/Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei/Platform.h
@@ -0,0 +1,86 @@
+/** @file
+ Platform PEI module include file.
+
+ Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+ Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef PLATFORM_PEI_H_INCLUDED_
+#define PLATFORM_PEI_H_INCLUDED_
+
+VOID
+AddIoMemoryBaseSizeHob (
+ EFI_PHYSICAL_ADDRESS MemoryBase,
+ UINT64 MemorySize
+ );
+
+VOID
+AddIoMemoryRangeHob (
+ EFI_PHYSICAL_ADDRESS MemoryBase,
+ EFI_PHYSICAL_ADDRESS MemoryLimit
+ );
+
+VOID
+AddMemoryBaseSizeHob (
+ EFI_PHYSICAL_ADDRESS MemoryBase,
+ UINT64 MemorySize
+ );
+
+VOID
+AddMemoryRangeHob (
+ EFI_PHYSICAL_ADDRESS MemoryBase,
+ EFI_PHYSICAL_ADDRESS MemoryLimit
+ );
+
+VOID
+AddUntestedMemoryBaseSizeHob (
+ EFI_PHYSICAL_ADDRESS MemoryBase,
+ UINT64 MemorySize
+ );
+
+VOID
+AddReservedMemoryBaseSizeHob (
+ EFI_PHYSICAL_ADDRESS MemoryBase,
+ UINT64 MemorySize
+ );
+
+VOID
+AddUntestedMemoryRangeHob (
+ EFI_PHYSICAL_ADDRESS MemoryBase,
+ EFI_PHYSICAL_ADDRESS MemoryLimit
+ );
+
+VOID
+AddressWidthInitialization (
+ VOID
+ );
+
+EFI_STATUS
+PublishPeiMemory (
+ VOID
+ );
+
+UINT32
+GetSystemMemorySizeBelow4gb (
+ VOID
+ );
+
+VOID
+InitializeRamRegions (
+ VOID
+ );
+
+EFI_STATUS
+PeiFvInitialization (
+ VOID
+ );
+
+EFI_STATUS
+InitializeXen (
+ VOID
+ );
+
+#endif // _PLATFORM_PEI_H_INCLUDED_
diff --git a/Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei/Fv.c b/Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei/Fv.c
new file mode 100644
index 0000000000..060d66238d
--- /dev/null
+++ b/Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei/Fv.c
@@ -0,0 +1,51 @@
+/** @file
+ Build FV related hobs for platform.
+
+ Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+ Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "PiPei.h"
+#include "Platform.h"
+#include <Library/DebugLib.h>
+#include <Library/HobLib.h>
+#include <Library/PcdLib.h>
+#include <Library/PeiServicesLib.h>
+
+/**
+ Publish PEI & DXE (Decompressed) Memory based FVs to let PEI
+ and DXE know about them.
+
+ @retval EFI_SUCCESS Platform PEI FVs were initialized successfully.
+
+**/
+EFI_STATUS
+PeiFvInitialization (
+ VOID
+ )
+{
+ DEBUG ((DEBUG_INFO, "Platform PEI Firmware Volume Initialization\n"));
+ //
+ // Let DXE know about the DXE FV
+ //
+ BuildFvHob (PcdGet32 (PcdRiscVDxeFvBase), PcdGet32 (PcdRiscVDxeFvSize));
+ DEBUG ((DEBUG_INFO, "Platform builds DXE FV at %x, size %x.\n",
+ PcdGet32 (PcdRiscVDxeFvBase),
+ PcdGet32 (PcdRiscVDxeFvSize)));
+
+ //
+ // Let PEI know about the DXE FV so it can find the DXE Core
+ //
+ PeiServicesInstallFvInfoPpi (
+ NULL,
+ (VOID *)(UINTN) PcdGet32 (PcdRiscVDxeFvBase),
+ PcdGet32 (PcdRiscVDxeFvSize),
+ NULL,
+ NULL
+ );
+
+ return EFI_SUCCESS;
+}
diff --git a/Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei/MemDetect.c b/Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei/MemDetect.c
new file mode 100644
index 0000000000..c15d6bb5d4
--- /dev/null
+++ b/Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei/MemDetect.c
@@ -0,0 +1,81 @@
+/**@file
+ Memory Detection for Virtual Machines.
+
+ Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+ Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+Module Name:
+
+ MemDetect.c
+
+**/
+
+//
+// The package level header files this module uses
+//
+#include <PiPei.h>
+
+//
+// The Library classes this module consumes
+//
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/HobLib.h>
+#include <Library/IoLib.h>
+#include <Library/PcdLib.h>
+#include <Library/PeimEntryPoint.h>
+#include <Library/ResourcePublicationLib.h>
+
+#include "Platform.h"
+
+
+/**
+ Publish PEI core memory
+
+ @return EFI_SUCCESS The PEIM initialized successfully.
+
+**/
+EFI_STATUS
+PublishPeiMemory (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+ EFI_PHYSICAL_ADDRESS MemoryBase;
+ UINT64 MemorySize;
+
+ //
+ // TODO: This value should come from platform
+ // configuration or the memory sizing code.
+ //
+ MemoryBase = 0x80000000UL + 0x1000000UL;
+ MemorySize = 0x40000000UL - 0x1000000UL; //1GB - 16MB
+
+ DEBUG((DEBUG_INFO, "%a: MemoryBase:0x%x MemorySize:%x\n", __FUNCTION__, MemoryBase, MemorySize));
+
+ //
+ // Publish this memory to the PEI Core
+ //
+ Status = PublishSystemMemory(MemoryBase, MemorySize);
+ ASSERT_EFI_ERROR (Status);
+
+ return Status;
+}
+
+/**
+ Publish system RAM and reserve memory regions
+
+**/
+VOID
+InitializeRamRegions (
+ VOID
+ )
+{
+ //
+ // TODO: This value should come from platform
+ // configuration or the memory sizing code.
+ //
+ AddMemoryRangeHob(0x81000000UL, 0x81000000UL + 0x3F000000UL);
+}
diff --git a/Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei/Platform.c b/Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei/Platform.c
new file mode 100644
index 0000000000..24192c692b
--- /dev/null
+++ b/Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei/Platform.c
@@ -0,0 +1,314 @@
+/**@file
+ Platform PEI driver
+
+ Copyright (c) 2019-2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+ Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2011, Andrei Warkentin <andreiw@motorola.com>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+//
+// The package level header files this module uses
+//
+#include <PiPei.h>
+
+//
+// The Library classes this module consumes
+//
+#include <Library/DebugLib.h>
+#include <Library/HobLib.h>
+#include <Library/IoLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/PcdLib.h>
+#include <Library/PciLib.h>
+#include <Library/PeimEntryPoint.h>
+#include <Library/PeiServicesLib.h>
+#include <Library/ResourcePublicationLib.h>
+#include <Guid/MemoryTypeInformation.h>
+#include <Ppi/MasterBootMode.h>
+#include <IndustryStandard/Pci22.h>
+
+#include <SiFiveU5MCCoreplex.h>
+
+#include "Platform.h"
+
+EFI_MEMORY_TYPE_INFORMATION mDefaultMemoryTypeInformation[] = {
+ { EfiACPIMemoryNVS, 0x004 },
+ { EfiACPIReclaimMemory, 0x008 },
+ { EfiReservedMemoryType, 0x004 },
+ { EfiRuntimeServicesData, 0x024 },
+ { EfiRuntimeServicesCode, 0x030 },
+ { EfiBootServicesCode, 0x180 },
+ { EfiBootServicesData, 0xF00 },
+ { EfiMaxMemoryType, 0x000 }
+};
+
+
+EFI_PEI_PPI_DESCRIPTOR mPpiBootMode[] = {
+ {
+ EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,
+ &gEfiPeiMasterBootModePpiGuid,
+ NULL
+ }
+};
+
+STATIC EFI_BOOT_MODE mBootMode = BOOT_WITH_FULL_CONFIGURATION;
+
+VOID
+AddIoMemoryBaseSizeHob (
+ EFI_PHYSICAL_ADDRESS MemoryBase,
+ UINT64 MemorySize
+ )
+{
+ BuildResourceDescriptorHob (
+ EFI_RESOURCE_MEMORY_MAPPED_IO,
+ EFI_RESOURCE_ATTRIBUTE_PRESENT |
+ EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
+ EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
+ EFI_RESOURCE_ATTRIBUTE_TESTED,
+ MemoryBase,
+ MemorySize
+ );
+}
+
+VOID
+AddReservedMemoryBaseSizeHob (
+ EFI_PHYSICAL_ADDRESS MemoryBase,
+ UINT64 MemorySize
+ )
+{
+ BuildResourceDescriptorHob (
+ EFI_RESOURCE_MEMORY_RESERVED,
+ EFI_RESOURCE_ATTRIBUTE_PRESENT |
+ EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
+ EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
+ EFI_RESOURCE_ATTRIBUTE_TESTED,
+ MemoryBase,
+ MemorySize
+ );
+}
+
+VOID
+AddIoMemoryRangeHob (
+ EFI_PHYSICAL_ADDRESS MemoryBase,
+ EFI_PHYSICAL_ADDRESS MemoryLimit
+ )
+{
+ AddIoMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));
+}
+
+
+VOID
+AddMemoryBaseSizeHob (
+ EFI_PHYSICAL_ADDRESS MemoryBase,
+ UINT64 MemorySize
+ )
+{
+ BuildResourceDescriptorHob (
+ EFI_RESOURCE_SYSTEM_MEMORY,
+ EFI_RESOURCE_ATTRIBUTE_PRESENT |
+ EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
+ EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
+ EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
+ EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
+ EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |
+ EFI_RESOURCE_ATTRIBUTE_TESTED,
+ MemoryBase,
+ MemorySize
+ );
+}
+
+
+VOID
+AddMemoryRangeHob (
+ EFI_PHYSICAL_ADDRESS MemoryBase,
+ EFI_PHYSICAL_ADDRESS MemoryLimit
+ )
+{
+ AddMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));
+}
+
+
+VOID
+AddUntestedMemoryBaseSizeHob (
+ EFI_PHYSICAL_ADDRESS MemoryBase,
+ UINT64 MemorySize
+ )
+{
+ BuildResourceDescriptorHob (
+ EFI_RESOURCE_SYSTEM_MEMORY,
+ EFI_RESOURCE_ATTRIBUTE_PRESENT |
+ EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
+ EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
+ EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
+ EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
+ EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE,
+ MemoryBase,
+ MemorySize
+ );
+}
+
+VOID
+AddUntestedMemoryRangeHob (
+ EFI_PHYSICAL_ADDRESS MemoryBase,
+ EFI_PHYSICAL_ADDRESS MemoryLimit
+ )
+{
+ AddUntestedMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));
+}
+
+VOID
+AddPciResource (
+ VOID
+ )
+{
+ //
+ // Platform-specific
+ //
+}
+
+VOID
+MemMapInitialization (
+ VOID
+ )
+{
+ //
+ // Create Memory Type Information HOB
+ //
+ BuildGuidDataHob (
+ &gEfiMemoryTypeInformationGuid,
+ mDefaultMemoryTypeInformation,
+ sizeof(mDefaultMemoryTypeInformation)
+ );
+
+ //
+ // Add PCI IO Port space available for PCI resource allocations.
+ //
+ AddPciResource ();
+}
+
+VOID
+MiscInitialization (
+ VOID
+ )
+{
+ //
+ // Build the CPU HOB with guest RAM size dependent address width and 16-bits
+ // of IO space. (Side note: unlike other HOBs, the CPU HOB is needed during
+ // S3 resume as well, so we build it unconditionally.)
+ //
+ // TODO: Determine this dynamically from the platform
+ // setting or the HART configuration.
+ //
+ BuildCpuHob (48, 32);
+}
+
+/**
+ Check if system returns from S3.
+
+ @return BOOLEAN TRUE, system returned from S3
+ FALSE, system is not returned from S3
+
+**/
+BOOLEAN
+CheckResumeFromS3 (
+ VOID
+ )
+{
+ //
+ //Platform implementation-specific
+ //
+ return FALSE;
+}
+
+
+VOID
+BootModeInitialization (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+
+ if (CheckResumeFromS3 () == TRUE) {
+ DEBUG ((DEBUG_INFO, "This is wake from S3\n"));
+ } else {
+ DEBUG ((DEBUG_INFO, "This is normal boot\n"));
+ }
+ Status = PeiServicesSetBootMode (mBootMode);
+ ASSERT_EFI_ERROR (Status);
+
+ Status = PeiServicesInstallPpi (mPpiBootMode);
+ ASSERT_EFI_ERROR (Status);
+}
+
+/**
+ Build processor information for U54 Coreplex processor.
+
+ @return EFI_SUCCESS Status.
+
+**/
+EFI_STATUS
+BuildCoreInformationHob (
+ VOID
+)
+{
+ EFI_STATUS Status;
+ RISC_V_PROCESSOR_SMBIOS_HOB_DATA *SmbiosHobPtr;
+
+ // TODO: Create SMBIOS libs for non-U540 platforms
+ Status = CreateU5MCCoreplexProcessorSpecificDataHob (0);
+ if (EFI_ERROR (Status)) {
+ ASSERT(FALSE);
+ }
+ Status = CreateU5MCProcessorSmbiosDataHob (0, &SmbiosHobPtr);
+ if (EFI_ERROR (Status)) {
+ ASSERT(FALSE);
+ }
+
+ DEBUG ((DEBUG_INFO, "U5 MC Coreplex SMBIOS DATA HOB at address 0x%x\n", SmbiosHobPtr));
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Perform Platform PEI initialization.
+
+ @param FileHandle Handle of the file being invoked.
+ @param PeiServices Describes the list of possible PEI Services.
+
+ @return EFI_SUCCESS The PEIM initialized successfully.
+
+**/
+EFI_STATUS
+EFIAPI
+InitializePlatform (
+ IN EFI_PEI_FILE_HANDLE FileHandle,
+ IN CONST EFI_PEI_SERVICES **PeiServices
+ )
+{
+ EFI_STATUS Status;
+
+ DEBUG ((DEBUG_INFO, "Platform PEIM Loaded\n"));
+
+ BootModeInitialization ();
+ DEBUG ((DEBUG_INFO, "Platform BOOT mode initiated.\n"));
+ PublishPeiMemory ();
+ DEBUG ((DEBUG_INFO, "PEI memory published.\n"));
+ InitializeRamRegions ();
+ DEBUG ((DEBUG_INFO, "Platform RAM regions initiated.\n"));
+
+ if (mBootMode != BOOT_ON_S3_RESUME) {
+ PeiFvInitialization ();
+ MemMapInitialization ();
+ }
+
+ MiscInitialization ();
+ Status = BuildCoreInformationHob ();
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "Fail to build processor informstion HOB.\n"));
+ ASSERT(FALSE);
+ }
+ return EFI_SUCCESS;
+}
--
2.31.1
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH 29/79] RISC-V: Split SMBIOS out of PlatformPei
2022-01-08 4:10 [PATCH 02/79] ProcessorPkg/Library: RISC-V CPU library Abner Chang
` (25 preceding siblings ...)
2022-01-08 4:10 ` [PATCH 28/79] U5SeriesPkg: Deduplicate PlatformPei Abner Chang
@ 2022-01-08 4:10 ` Abner Chang
2022-01-08 4:10 ` [PATCH 30/79] RISC-V: Use U5 SMBIOS library only for those platforms Abner Chang
` (10 subsequent siblings)
37 siblings, 0 replies; 39+ messages in thread
From: Abner Chang @ 2022-01-08 4:10 UTC (permalink / raw)
To: devel; +Cc: abner.chang
(This is migrated from edk2-platforms)
Cc: Abner Chang <abner.chang@hpe.com>
Cc: Sunil V L <sunilvl@ventanamicro.com>
Reviewed-by: Abner Chang <abner.chang@hpe.com>
Signed-off-by: Daniel Schaefer <daniel.schaefer@hpe.com>
---
.../Universal/Pei/PlatformPei/Platform.c | 17 +----------------
1 file changed, 1 insertion(+), 16 deletions(-)
diff --git a/Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei/Platform.c b/Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei/Platform.c
index 24192c692b..8586a94b62 100644
--- a/Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei/Platform.c
+++ b/Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei/Platform.c
@@ -254,22 +254,7 @@ BuildCoreInformationHob (
VOID
)
{
- EFI_STATUS Status;
- RISC_V_PROCESSOR_SMBIOS_HOB_DATA *SmbiosHobPtr;
-
- // TODO: Create SMBIOS libs for non-U540 platforms
- Status = CreateU5MCCoreplexProcessorSpecificDataHob (0);
- if (EFI_ERROR (Status)) {
- ASSERT(FALSE);
- }
- Status = CreateU5MCProcessorSmbiosDataHob (0, &SmbiosHobPtr);
- if (EFI_ERROR (Status)) {
- ASSERT(FALSE);
- }
-
- DEBUG ((DEBUG_INFO, "U5 MC Coreplex SMBIOS DATA HOB at address 0x%x\n", SmbiosHobPtr));
-
- return EFI_SUCCESS;
+ return BuildRiscVSmbiosHobs ();
}
/**
--
2.31.1
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH 30/79] RISC-V: Use U5 SMBIOS library only for those platforms
2022-01-08 4:10 [PATCH 02/79] ProcessorPkg/Library: RISC-V CPU library Abner Chang
` (26 preceding siblings ...)
2022-01-08 4:10 ` [PATCH 29/79] RISC-V: Split SMBIOS out of PlatformPei Abner Chang
@ 2022-01-08 4:10 ` Abner Chang
2022-01-08 4:10 ` [PATCH 31/79] Silicon/RISC-V: Introduce FirmwareContext library Abner Chang
` (9 subsequent siblings)
37 siblings, 0 replies; 39+ messages in thread
From: Abner Chang @ 2022-01-08 4:10 UTC (permalink / raw)
To: devel; +Cc: abner.chang
(This is migrated from edk2-platforms)
Cc: Abner Chang <abner.chang@hpe.com>
Cc: Sunil V L <sunilvl@ventanamicro.com>
Reviewed-by: Abner Chang <abner.chang@hpe.com>
Signed-off-by: Daniel Schaefer <daniel.schaefer@hpe.com>
---
.../PeiCoreInfoHobLib.inf | 43 +++++++++++++++++++
.../Universal/Pei/PlatformPei/PlatformPei.inf | 2 +-
.../PeiCoreInfoHobLibNull/CoreInfoHob.c | 37 ++++++++++++++++
3 files changed, 81 insertions(+), 1 deletion(-)
create mode 100644 Platform/RISC-V/PlatformPkg/Library/PeiCoreInfoHobLibNull/PeiCoreInfoHobLib.inf
create mode 100644 Platform/RISC-V/PlatformPkg/Library/PeiCoreInfoHobLibNull/CoreInfoHob.c
diff --git a/Platform/RISC-V/PlatformPkg/Library/PeiCoreInfoHobLibNull/PeiCoreInfoHobLib.inf b/Platform/RISC-V/PlatformPkg/Library/PeiCoreInfoHobLibNull/PeiCoreInfoHobLib.inf
new file mode 100644
index 0000000000..5a8db5071f
--- /dev/null
+++ b/Platform/RISC-V/PlatformPkg/Library/PeiCoreInfoHobLibNull/PeiCoreInfoHobLib.inf
@@ -0,0 +1,43 @@
+## @file
+# Library instance to create core information HOB
+#
+# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001b
+ BASE_NAME = RiscVCoreplexInfoLibNull
+ FILE_GUID = E5783AF0-B7C5-4FAA-BAB4-D52C06B98BBE
+ MODULE_TYPE = PEIM
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = RiscVCoreplexInfoLib
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = RISCV64
+#
+
+[Sources]
+ CoreInfoHob.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec
+ Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec
+
+[LibraryClasses]
+ BaseLib
+ PcdLib
+ MemoryAllocationLib
+ PrintLib
+
+[Guids]
+
+[Ppis]
+
+[FixedPcd]
diff --git a/Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei/PlatformPei.inf b/Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei/PlatformPei.inf
index e7f5eef630..0db88abba4 100644
--- a/Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei/PlatformPei.inf
+++ b/Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei/PlatformPei.inf
@@ -51,7 +51,7 @@
PeiServicesTablePointerLib
PeimEntryPoint
PcdLib
- SiliconSiFiveU5MCCoreplexInfoLib
+ RiscVCoreplexInfoLib
[Pcd]
gEfiMdeModulePkgTokenSpaceGuid.PcdEmuVariableNvStoreReserved
diff --git a/Platform/RISC-V/PlatformPkg/Library/PeiCoreInfoHobLibNull/CoreInfoHob.c b/Platform/RISC-V/PlatformPkg/Library/PeiCoreInfoHobLibNull/CoreInfoHob.c
new file mode 100644
index 0000000000..9aad7991bc
--- /dev/null
+++ b/Platform/RISC-V/PlatformPkg/Library/PeiCoreInfoHobLibNull/CoreInfoHob.c
@@ -0,0 +1,37 @@
+/**@file
+ Build up platform processor information.
+
+ Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+//
+// The package level header files this module uses
+//
+#include <PiPei.h>
+
+//
+// The Library classes this module consumes
+//
+#include <Library/DebugLib.h>
+#include <Library/HobLib.h>
+#include <Library/BaseMemoryLib.h>
+
+#include <ProcessorSpecificHobData.h>
+
+
+/**
+ Build processor and platform information for a generic RISC-V
+
+ @return EFI_SUCCESS Status.
+
+**/
+EFI_STATUS
+BuildRiscVSmbiosHobs (
+ VOID
+)
+{
+ return EFI_SUCCESS;
+}
--
2.31.1
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH 31/79] Silicon/RISC-V: Introduce FirmwareContext library
2022-01-08 4:10 [PATCH 02/79] ProcessorPkg/Library: RISC-V CPU library Abner Chang
` (27 preceding siblings ...)
2022-01-08 4:10 ` [PATCH 30/79] RISC-V: Use U5 SMBIOS library only for those platforms Abner Chang
@ 2022-01-08 4:10 ` Abner Chang
2022-01-08 4:10 ` [PATCH 32/79] Silicon/RISC-V: PeiServiceTableLib uses RiscVFirmwareContextLib Abner Chang
` (8 subsequent siblings)
37 siblings, 0 replies; 39+ messages in thread
From: Abner Chang @ 2022-01-08 4:10 UTC (permalink / raw)
To: devel; +Cc: abner.chang
(This is migrated from edk2-platforms:Silicon)
Add RISC-V FirmwareContext library for different FirmwareContext
implementations. This instance uses SBI firmware extension to
get the pointer to FirmwareContext.
Cc: Sunil V L <sunilvl@ventanamicro.com>
Cc: Daniel Schaefer <daniel.schaefer@hpe.com>
Reviewed-by: Abner Chang <abner.chang@hpe.com>
Reviewed-by: Daniel Schaefer <daniel.schaefer@hpe.com>
Signed-off-by: Abner Chang <abner.chang@hpe.com>
---
.../RISC-V/ProcessorPkg/RiscVProcessorPkg.dec | 1 +
.../RISC-V/ProcessorPkg/RiscVProcessorPkg.dsc | 4 +-
.../RiscVFirmwareContextSbiLib.inf | 34 ++++++++++++
.../RiscVFirmwareContextSscratchLib.inf | 33 ++++++++++++
.../RiscVFirmwareContextStvecLib.inf | 34 ++++++++++++
.../Include/IndustryStandard/RiscV.h | 3 +-
.../Include/Library/RiscVCpuLib.h | 14 ++++-
.../Include/Library/RiscVFirmwareContextLib.h | 43 +++++++++++++++
.../RiscVFirmwareContextSbiLib.c | 52 +++++++++++++++++++
.../RiscVFirmwareContextSscratchLib.c | 48 +++++++++++++++++
.../RiscVFirmwareContextStvecLib.c | 48 +++++++++++++++++
.../ProcessorPkg/Library/RiscVCpuLib/Cpu.S | 34 +++++++++++-
12 files changed, 344 insertions(+), 4 deletions(-)
create mode 100644 Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSbiLib/RiscVFirmwareContextSbiLib.inf
create mode 100644 Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSscratchLib/RiscVFirmwareContextSscratchLib.inf
create mode 100644 Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextStvecLib/RiscVFirmwareContextStvecLib.inf
create mode 100644 Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVFirmwareContextLib.h
create mode 100644 Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSbiLib/RiscVFirmwareContextSbiLib.c
create mode 100644 Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSscratchLib/RiscVFirmwareContextSscratchLib.c
create mode 100644 Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextStvecLib/RiscVFirmwareContextStvecLib.c
diff --git a/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec b/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec
index 0b64b33f0f..08279a97b1 100644
--- a/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec
+++ b/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec
@@ -24,6 +24,7 @@
RiscVPlatformDxeIplLib|Include/Library/RiscVPlatformDxeIpl.h
RiscVCpuLib|Include/Library/RiscVCpuLib.h
RiscVEdk2SbiLib|Include/Library/RiscVEdk2SbiLib.h
+ RiscVFirmwareContextLib|Include/Library/RiscVFirmwareContextLib.h
[Guids]
gUefiRiscVPkgTokenSpaceGuid = { 0x4261e9c8, 0x52c0, 0x4b34, { 0x85, 0x3d, 0x48, 0x46, 0xea, 0xd3, 0xb7, 0x2c}}
diff --git a/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dsc b/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dsc
index 5c5cfcb525..1292ba1bea 100644
--- a/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dsc
+++ b/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dsc
@@ -65,13 +65,14 @@
UefiLib|MdePkg/Library/UefiLib/UefiLib.inf
DevicePathLib|MdePkg/Library/UefiDevicePathLibDevicePathProtocol/UefiDevicePathLibDevicePathProtocol.inf
RiscVPlatformTimerLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVPlatformTimerLibNull/RiscVPlatformTimerLib.inf
- PeiServicesTablePointerLib|Silicon/RISC-V/ProcessorPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerLibOpenSbi.inf
[LibraryClasses.common.PEI_CORE]
PeiServicesTablePointerLib|Silicon/RISC-V/ProcessorPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerLibOpenSbi.inf
+ RiscVFirmwareContextLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSbiLib/RiscVFirmwareContextSbiLib.inf
[LibraryClasses.common.PEIM]
PeiServicesTablePointerLib|Silicon/RISC-V/ProcessorPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerLibOpenSbi.inf
+ RiscVFirmwareContextLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSbiLib/RiscVFirmwareContextSbiLib.inf
HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf
PeimEntryPoint|MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf
@@ -92,6 +93,7 @@
[Components]
Silicon/RISC-V/ProcessorPkg/Library/RiscVTimerLib/BaseRiscVTimerLib.inf
Silicon/RISC-V/ProcessorPkg/Library/RiscVExceptionLib/CpuExceptionHandlerDxeLib.inf
+ Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSbiLib/RiscVFirmwareContextSbiLib.inf
Silicon/RISC-V/ProcessorPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerLibOpenSbi.inf
Silicon/RISC-V/ProcessorPkg/Library/RiscVOpensbiLib/RiscVOpensbiLib.inf
Silicon/RISC-V/ProcessorPkg/Library/RiscVPlatformTimerLibNull/RiscVPlatformTimerLib.inf
diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSbiLib/RiscVFirmwareContextSbiLib.inf b/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSbiLib/RiscVFirmwareContextSbiLib.inf
new file mode 100644
index 0000000000..168b705453
--- /dev/null
+++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSbiLib/RiscVFirmwareContextSbiLib.inf
@@ -0,0 +1,34 @@
+## @file
+# Instance of OpebSBI Firmware Conext Library
+#
+# This iinstance uses RISC-V OpenSBI Firmware Extension SBI.
+#
+# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001b
+ BASE_NAME = RiscVFirmwareContextSbiLib
+ FILE_GUID = 3709E048-6794-427A-B728-BFE3FFD6D461
+ MODULE_TYPE = PEIM
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = RiscVFirmwareContextLib|PEIM PEI_CORE
+
+#
+# VALID_ARCHITECTURES = RISCV64
+#
+[Sources]
+ RiscVFirmwareContextSbiLib.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec
+
+[LibraryClasses]
+ DebugLib
+ RiscVCpuLib
+ RiscVEdk2SbiLib
+
diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSscratchLib/RiscVFirmwareContextSscratchLib.inf b/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSscratchLib/RiscVFirmwareContextSscratchLib.inf
new file mode 100644
index 0000000000..750c1cf51f
--- /dev/null
+++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSscratchLib/RiscVFirmwareContextSscratchLib.inf
@@ -0,0 +1,33 @@
+## @file
+# Instance of OpebSBI Firmware Conext Library
+#
+# This instance uses RISC-V Supervisor mode SCRATCH CSR
+#
+# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001b
+ BASE_NAME = RiscVFirmwareContextSscratchLib
+ FILE_GUID = 3709E048-6794-427A-B728-BFE3FFD6D461
+ MODULE_TYPE = PEIM
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = RiscVFirmwareContextLib|PEIM PEI_CORE
+
+#
+# VALID_ARCHITECTURES = RISCV64
+#
+[Sources]
+ RiscVFirmwareContextSscratchLib.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec
+
+[LibraryClasses]
+ DebugLib
+ RiscVCpuLib
+
diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextStvecLib/RiscVFirmwareContextStvecLib.inf b/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextStvecLib/RiscVFirmwareContextStvecLib.inf
new file mode 100644
index 0000000000..fa894cda91
--- /dev/null
+++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextStvecLib/RiscVFirmwareContextStvecLib.inf
@@ -0,0 +1,34 @@
+## @file
+# Instance of OpebSBI Firmware Conext Library
+#
+# This iinstance Supervisor mode STVEC CSR
+#
+# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001b
+ BASE_NAME = RiscVFirmwareContextStvecLib
+ FILE_GUID = 42DCFFAC-1DBD-4264-80A3-85CC7167AC82
+ MODULE_TYPE = PEIM
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = RiscVFirmwareContextLib|PEIM PEI_CORE
+
+#
+# VALID_ARCHITECTURES = RISCV64
+#
+[Sources]
+ RiscVFirmwareContextStvecLib.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec
+
+[LibraryClasses]
+ DebugLib
+ RiscVCpuLib
+
+
diff --git a/Silicon/RISC-V/ProcessorPkg/Include/IndustryStandard/RiscV.h b/Silicon/RISC-V/ProcessorPkg/Include/IndustryStandard/RiscV.h
index 2a992394ed..f6726bda24 100644
--- a/Silicon/RISC-V/ProcessorPkg/Include/IndustryStandard/RiscV.h
+++ b/Silicon/RISC-V/ProcessorPkg/Include/IndustryStandard/RiscV.h
@@ -1,7 +1,7 @@
/** @file
RISC-V package definitions.
- Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+ Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -96,6 +96,7 @@
#define SSTATUS_SIE_BIT_POSITION 1
#define SSTATUS_SPP_BIT_POSITION 8
#define RISCV_CSR_SUPERVISOR_SIE 0x104
+#define RISCV_CSR_SUPERVISOR_STVEC 0x105
#define RISCV_CSR_SUPERVISOR_SSCRATCH 0x140
#define RISCV_CSR_SUPERVISOR_SEPC 0x141
#define RISCV_CSR_SUPERVISOR_SCAUSE 0x142
diff --git a/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVCpuLib.h b/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVCpuLib.h
index f37d4c20d0..f70723567e 100644
--- a/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVCpuLib.h
+++ b/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVCpuLib.h
@@ -1,7 +1,7 @@
/** @file
RISC-V CPU library definitions.
- Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+ Copyright (c) 2016 - 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@@ -68,4 +68,16 @@ RiscVReadMachineImplementId (VOID);
VOID
RiscVSetSupervisorAddressTranslationRegister(UINT64);
+VOID
+RiscVSetSupervisorScratch (UINT64);
+
+UINT64
+RiscVGetSupervisorScratch (VOID);
+
+VOID
+RiscVSetSupervisorStvec (UINT64);
+
+UINT64
+RiscVGetSupervisorStvec (VOID);
+
#endif
diff --git a/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVFirmwareContextLib.h b/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVFirmwareContextLib.h
new file mode 100644
index 0000000000..f35c4e0c51
--- /dev/null
+++ b/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVFirmwareContextLib.h
@@ -0,0 +1,43 @@
+/** @file
+ Library to get/set Firmware Context.
+
+ Copyright (c) 2021, Hewlett Packard Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef RISCV_FIRMWARE_CONTEXT_LIB_H_
+#define RISCV_FIRMWARE_CONTEXT_LIB_H_
+
+#include <Uefi.h>
+#include <IndustryStandard/RiscVOpensbi.h>
+
+/**
+ Get pointer to OpenSBI Firmware Context
+
+ Get the pointer of firmware context.
+
+ @param FirmwareContextPtr Pointer to retrieve pointer to the
+ Firmware Context.
+**/
+VOID
+EFIAPI
+GetFirmwareContextPointer (
+ IN OUT EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT **FirmwareContextPtr
+ );
+
+/**
+ Set pointer to OpenSBI Firmware Context
+
+ Set the pointer of firmware context.
+
+ @param FirmwareContextPtr Pointer to Firmware Context.
+**/
+VOID
+EFIAPI
+SetFirmwareContextPointer (
+ IN EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *FirmwareContextPtr
+ );
+
+#endif
diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSbiLib/RiscVFirmwareContextSbiLib.c b/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSbiLib/RiscVFirmwareContextSbiLib.c
new file mode 100644
index 0000000000..6125618eaf
--- /dev/null
+++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSbiLib/RiscVFirmwareContextSbiLib.c
@@ -0,0 +1,52 @@
+/** @file
+ This iinstance uses RISC-V OpenSBI Firmware Extension SBI to
+ get the pointer of firmware context.
+
+ Copyright (c) 2021 Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <PiPei.h>
+#include <Library/DebugLib.h>
+#include <Library/RiscVCpuLib.h>
+#include <Library/RiscVEdk2SbiLib.h>
+#include <sbi/sbi_scratch.h>
+#include <sbi/sbi_platform.h>
+
+/**
+ Get pointer to OpenSBI Firmware Context
+
+ Get the pointer of firmware context through OpenSBI FW Extension SBI.
+
+ @param FirmwareContextPtr Pointer to retrieve pointer to the
+ Firmware Context.
+**/
+VOID
+EFIAPI
+GetFirmwareContextPointer (
+ IN OUT EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT **FirmwareContextPtr
+ )
+{
+ SbiGetFirmwareContext (FirmwareContextPtr);
+}
+
+/**
+ Set the pointer to OpenSBI Firmware Context
+
+ Set the pointer of firmware context through OpenSBI FW Extension SBI.
+
+ @param FirmwareContextPtr Pointer to Firmware Context.
+**/
+VOID
+EFIAPI
+SetFirmwareContextPointer (
+ IN EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *FirmwareContextPtr
+ )
+{
+ //
+ // We don't have to set firmware context pointer using
+ // OpenSBI FW Extension SBI.
+ //
+}
+
diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSscratchLib/RiscVFirmwareContextSscratchLib.c b/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSscratchLib/RiscVFirmwareContextSscratchLib.c
new file mode 100644
index 0000000000..2504e17132
--- /dev/null
+++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSscratchLib/RiscVFirmwareContextSscratchLib.c
@@ -0,0 +1,48 @@
+/** @file
+ This instance uses Supervisor mode SCRATCH CSR to get/set the
+ pointer of firmware context.
+
+ Copyright (c) 2021 Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <PiPei.h>
+
+#include <IndustryStandard/RiscVOpensbi.h>
+
+#include <Library/DebugLib.h>
+#include <Library/RiscVCpuLib.h>
+
+/**
+ Get pointer to OpenSBI Firmware Context
+
+ Get the pointer of firmware context through Supervisor mode SCRATCH CSR.
+
+ @param FirmwareContextPtr Pointer to retrieve pointer to the
+ Firmware Context.
+**/
+VOID
+EFIAPI
+GetFirmwareContextPointer (
+ IN OUT EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT **FirmwareContextPtr
+ )
+{
+ *FirmwareContextPtr = (EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *)RiscVGetSupervisorScratch ();
+}
+
+/**
+ Set the pointer to OpenSBI Firmware Context
+
+ Set the pointer of firmware context through Supervisor mode SCRATCH CSR.
+
+ @param FirmwareContextPtr Pointer to Firmware Context.
+**/
+VOID
+EFIAPI
+SetFirmwareContextPointer (
+ IN EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *FirmwareContextPtr
+ )
+{
+ RiscVSetSupervisorScratch ((UINT64)FirmwareContextPtr);
+}
diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextStvecLib/RiscVFirmwareContextStvecLib.c b/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextStvecLib/RiscVFirmwareContextStvecLib.c
new file mode 100644
index 0000000000..7d1675355a
--- /dev/null
+++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextStvecLib/RiscVFirmwareContextStvecLib.c
@@ -0,0 +1,48 @@
+/** @file
+ This instance uses This iinstance Supervisor mode STVEC CSR to
+ get/set the pointer of firmware context.
+
+ Copyright (c) 2021 Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <PiPei.h>
+
+#include <IndustryStandard/RiscVOpensbi.h>
+
+#include <Library/DebugLib.h>
+#include <Library/RiscVCpuLib.h>
+
+/**
+ Get pointer to OpenSBI Firmware Context
+
+ Get the pointer of firmware context through Supervisor mode STVEC CSR.
+
+ @param FirmwareContextPtr Pointer to retrieve pointer to the
+ Firmware Context.
+**/
+VOID
+EFIAPI
+GetFirmwareContextPointer (
+ IN OUT EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT **FirmwareContextPtr
+ )
+{
+ *FirmwareContextPtr = (EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *)RiscVGetSupervisorStvec ();
+}
+
+/**
+ Set pointer to OpenSBI Firmware Context
+
+ Set the pointer of firmware context through Supervisor mode STVEC CSR
+
+ @param FirmwareContextPtr Pointer to Firmware Context.
+**/
+VOID
+EFIAPI
+SetFirmwareContextPointer (
+ IN EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *FirmwareContextPtr
+ )
+{
+ RiscVSetSupervisorStvec ((UINT64)FirmwareContextPtr);
+}
diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVCpuLib/Cpu.S b/Silicon/RISC-V/ProcessorPkg/Library/RiscVCpuLib/Cpu.S
index 06ba80cb5f..e242c9b866 100644
--- a/Silicon/RISC-V/ProcessorPkg/Library/RiscVCpuLib/Cpu.S
+++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVCpuLib/Cpu.S
@@ -2,7 +2,7 @@
//
// RISC-V CPU functions.
//
-// Copyright (c) 2016 - 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+// Copyright (c) 2016 - 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
//
// SPDX-License-Identifier: BSD-2-Clause-Patent
//
@@ -101,6 +101,38 @@ ASM_FUNC (RiscVReadMachineImplementId)
csrr a0, RISCV_CSR_MACHINE_MIMPID
ret
+//
+// Set Supervisor mode scratch.
+// @param a0 : Value set to Supervisor mode scratch
+//
+ASM_FUNC (RiscVSetSupervisorScratch)
+ csrrw a1, RISCV_CSR_SUPERVISOR_SSCRATCH, a0
+ ret
+
+//
+// Get Supervisor mode scratch.
+// @retval a0 : Value in Supervisor mode scratch
+//
+ASM_FUNC (RiscVGetSupervisorScratch)
+ csrr a0, RISCV_CSR_SUPERVISOR_SSCRATCH
+ ret
+
+//
+// Set Supervisor mode trap vector.
+// @param a0 : Value set to Supervisor mode trap vector
+//
+ASM_FUNC (RiscVSetSupervisorStvec)
+ csrrw a1, RISCV_CSR_SUPERVISOR_STVEC, a0
+ ret
+
+//
+// Get Supervisor mode scratch.
+// @retval a0 : Value in Supervisor mode trap vector
+//
+ASM_FUNC (RiscVGetSupervisorStvec)
+ csrr a0, RISCV_CSR_SUPERVISOR_STVEC
+ ret
+
//
// Set Supervisor Address Translation and
// Protection Register.
--
2.31.1
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH 32/79] Silicon/RISC-V: PeiServiceTableLib uses RiscVFirmwareContextLib
2022-01-08 4:10 [PATCH 02/79] ProcessorPkg/Library: RISC-V CPU library Abner Chang
` (28 preceding siblings ...)
2022-01-08 4:10 ` [PATCH 31/79] Silicon/RISC-V: Introduce FirmwareContext library Abner Chang
@ 2022-01-08 4:10 ` Abner Chang
2022-01-08 4:10 ` [PATCH 33/79] RISC-V/PlatformPkg: Build DeviceTree and use that in SEC Abner Chang
` (7 subsequent siblings)
37 siblings, 0 replies; 39+ messages in thread
From: Abner Chang @ 2022-01-08 4:10 UTC (permalink / raw)
To: devel; +Cc: abner.chang
(This is migrated from edk2-platforms:Silicon)
Use RISC-V FirmwareContext library to set and get the
pointer of PeiService.
Cc: Sunil V L <sunilvl@ventanamicro.com>
Cc: Daniel Schaefer <daniel.schaefer@hpe.com>
Reviewed-by: Daniel Schaefer <daniel.schaefer@hpe.com>
Signed-off-by: Abner Chang <abner.chang@hpe.com>
---
.../PeiServicesTablePointerLibOpenSbi.inf | 4 ++--
.../PeiServicesTablePointerOpenSbi.c | 8 ++++----
2 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/Silicon/RISC-V/ProcessorPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerLibOpenSbi.inf b/Silicon/RISC-V/ProcessorPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerLibOpenSbi.inf
index f23272016b..fa9fe78518 100644
--- a/Silicon/RISC-V/ProcessorPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerLibOpenSbi.inf
+++ b/Silicon/RISC-V/ProcessorPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerLibOpenSbi.inf
@@ -4,7 +4,7 @@
# PEI Services Table Pointer Library implementation that retrieves a pointer to the
# PEI Services Table from a RISC-V OpenSBI sbi_platform firmware context structure.
#
-# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -35,5 +35,5 @@
[LibraryClasses]
DebugLib
RiscVCpuLib
- RiscVEdk2SbiLib
+ RiscVFirmwareContextLib
diff --git a/Silicon/RISC-V/ProcessorPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerOpenSbi.c b/Silicon/RISC-V/ProcessorPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerOpenSbi.c
index 0c1473e932..9aa74b4f9f 100644
--- a/Silicon/RISC-V/ProcessorPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerOpenSbi.c
+++ b/Silicon/RISC-V/ProcessorPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerOpenSbi.c
@@ -1,7 +1,7 @@
/** @file
PEI Services Table Pointer Library.
- Copyright (c) 2019 - 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+ Copyright (c) 2019 - 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@@ -9,7 +9,7 @@
#include <PiPei.h>
#include <Library/DebugLib.h>
#include <Library/RiscVCpuLib.h>
-#include <Library/RiscVEdk2SbiLib.h>
+#include <Library/RiscVFirmwareContextLib.h>
#include <Library/PeiServicesTablePointerLib.h>
#include <sbi/sbi_scratch.h>
#include <sbi/sbi_platform.h>
@@ -32,8 +32,8 @@ SetPeiServicesTablePointer (
)
{
EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *FirmwareContext;
- SbiGetFirmwareContext (&FirmwareContext);
+ GetFirmwareContextPointer (&FirmwareContext);
FirmwareContext->PeiServiceTable = (VOID *)(UINTN)PeiServicesTablePointer;
DEBUG ((DEBUG_INFO, "Set PEI Service 0x%x at OpenSBI Firmware Context at 0x%x\n",
@@ -61,8 +61,8 @@ GetPeiServicesTablePointer (
)
{
EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *FirmwareContext;
- SbiGetFirmwareContext (&FirmwareContext);
+ GetFirmwareContextPointer (&FirmwareContext);
return (CONST EFI_PEI_SERVICES **)FirmwareContext->PeiServiceTable;
}
--
2.31.1
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH 33/79] RISC-V/PlatformPkg: Build DeviceTree and use that in SEC
2022-01-08 4:10 [PATCH 02/79] ProcessorPkg/Library: RISC-V CPU library Abner Chang
` (29 preceding siblings ...)
2022-01-08 4:10 ` [PATCH 32/79] Silicon/RISC-V: PeiServiceTableLib uses RiscVFirmwareContextLib Abner Chang
@ 2022-01-08 4:10 ` Abner Chang
2022-01-08 4:10 ` [PATCH 34/79] RISC-V/PlatformPkg: Add FdtPeim to pass DTB from PEI to DXE via HOB Abner Chang
` (6 subsequent siblings)
37 siblings, 0 replies; 39+ messages in thread
From: Abner Chang @ 2022-01-08 4:10 UTC (permalink / raw)
To: devel; +Cc: abner.chang
From: Daniel Schaefer <daniel.schaefer@hpe.com>
(This is migrated from edk2-platforms)
OpenSBI uses the device tree for platform specific initialization, so we
need to have it already in SEC.
Cc: Daniel Schaefer <daniel.schaefer@hpe.com>
Cc: Abner Chang <abner.chang@hpe.com>
Cc: Sunil V L <sunilvl@ventanamicro.com>
Reviewed-by: Abner Chang <abner.chang@hpe.com>
Signed-off-by: Daniel Schaefer <daniel.schaefer@hpe.com>
---
.../RISC-V/PlatformPkg/RiscVPlatformPkg.dec | 4 ++
.../PlatformPkg/Universal/Sec/SecMain.inf | 2 +
.../Include/IndustryStandard/RiscVOpensbi.h | 1 +
.../PlatformPkg/Universal/Sec/SecMain.c | 49 +++++++++++++++++++
.../Universal/Sec/Riscv64/SecEntry.S | 22 ---------
5 files changed, 56 insertions(+), 22 deletions(-)
diff --git a/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec b/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec
index 48aeb97431..ad15a155fe 100644
--- a/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec
+++ b/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec
@@ -31,6 +31,8 @@
gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVPeiFvSize|0x0|UINT32|0x00001003
gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVDxeFvBase|0x0|UINT32|0x00001004
gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVDxeFvSize|0x0|UINT32|0x00001005
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVDtbFvBase|0x0|UINT32|0x00001016
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVDtbFvSize|0x0|UINT32|0x00001017
#
# Definition of EFI Variable region
@@ -66,6 +68,8 @@
gUefiRiscVPlatformPkgTokenSpaceGuid.PcdTemporaryRamSize|0|UINT32|0x00001104
gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPeiCorePrivilegeMode|0|UINT32|0x00001105
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdDeviceTreeAddress|0|UINT32|0x00001106
+
[PcdsPatchableInModule]
[PcdsFeatureFlag]
diff --git a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf
index 89bcb039a6..78bd75e3ac 100644
--- a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf
+++ b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf
@@ -57,6 +57,8 @@
[FixedPcd]
gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVPeiFvBase
gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVPeiFvSize
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVDtbFvBase
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdDeviceTreeAddress
[Pcd]
gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootHartId
diff --git a/Silicon/RISC-V/ProcessorPkg/Include/IndustryStandard/RiscVOpensbi.h b/Silicon/RISC-V/ProcessorPkg/Include/IndustryStandard/RiscVOpensbi.h
index 2dab696af8..e7ac6d26ee 100644
--- a/Silicon/RISC-V/ProcessorPkg/Include/IndustryStandard/RiscVOpensbi.h
+++ b/Silicon/RISC-V/ProcessorPkg/Include/IndustryStandard/RiscVOpensbi.h
@@ -47,6 +47,7 @@ typedef struct {
typedef struct {
VOID *PeiServiceTable; // PEI Service table
+ UINT64 FlattenedDeviceTree; // Pointer to Flattened Device tree
EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC *HartSpecific[RISC_V_MAX_HART_SUPPORTED];
} EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT;
diff --git a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c
index fa9ecd789a..0af0b4bac8 100644
--- a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c
+++ b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c
@@ -557,6 +557,12 @@ VOID EFIAPI PeiCore (
&FirmwareContext
));
ThisSbiPlatform->firmware_context = (unsigned long)&FirmwareContext;
+
+ //
+ // Save Flattened Device tree in firmware context
+ //
+ FirmwareContext.FlattenedDeviceTree = FuncArg1;
+
//
// Set firmware context Hart-specific pointer
//
@@ -647,6 +653,42 @@ RiscVOpenSbiHartSwitchMode (
sbi_hart_switch_mode(FuncArg0, FuncArg1, NextAddr, NextMode, NextVirt);
}
+/**
+ Get device tree address
+
+ @retval The address of Device Tree binary.
+**/
+VOID *
+EFIAPI
+GetDeviceTreeAddress (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+ EFI_COMMON_SECTION_HEADER *FoundSection;
+
+ if (FixedPcdGet32 (PcdDeviceTreeAddress)) {
+ return (VOID *)*((unsigned long *)FixedPcdGet32 (PcdDeviceTreeAddress));
+ } else if (FixedPcdGet32 (PcdRiscVDtbFvBase)) {
+ Status = FindFfsFileAndSection (
+ (EFI_FIRMWARE_VOLUME_HEADER *)FixedPcdGet32 (PcdRiscVDtbFvBase),
+ EFI_FV_FILETYPE_FREEFORM,
+ EFI_SECTION_RAW,
+ &FoundSection
+ );
+ if (EFI_ERROR(Status)) {
+ DEBUG ((DEBUG_ERROR, "Platform Device Tree is not found from FV.\n"));
+ return NULL;
+ }
+ FoundSection ++;
+ return (VOID *)FoundSection;
+ } else {
+ DEBUG ((DEBUG_ERROR, "Must use DTB either from memory or compiled in FW. PCDs configured incorrectly.\n"));
+ ASSERT (FALSE);
+ }
+ return NULL;
+}
+
/**
This function initilizes hart specific information and SBI.
For the boot hart, it boots system through PEI core and initial SBI in the DXE IPL.
@@ -686,6 +728,13 @@ VOID EFIAPI SecCoreStartUpWithStack(
UINT64 NonBootHartMessageLockValue;
EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC *HartFirmwareContext;
+ Scratch->next_arg1 = (unsigned long)GetDeviceTreeAddress ();
+ if (Scratch->next_arg1 == (unsigned long)NULL) {
+ DEBUG ((DEBUG_ERROR, "Platform Device Tree is not found\n"));
+ ASSERT (FALSE);
+ }
+ DEBUG ((DEBUG_INFO, "DTB address: 0x%08x\n", Scratch->next_arg1));
+
//
// Setup EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC for each hart.
//
diff --git a/Platform/RISC-V/PlatformPkg/Universal/Sec/Riscv64/SecEntry.S b/Platform/RISC-V/PlatformPkg/Universal/Sec/Riscv64/SecEntry.S
index 6b2cdb6c17..d3d589aefc 100644
--- a/Platform/RISC-V/PlatformPkg/Universal/Sec/Riscv64/SecEntry.S
+++ b/Platform/RISC-V/PlatformPkg/Universal/Sec/Riscv64/SecEntry.S
@@ -75,11 +75,6 @@ _scratch_init:
sd a4, SBI_SCRATCH_FW_START_OFFSET(tp)
sd a5, SBI_SCRATCH_FW_SIZE_OFFSET(tp)
- /*
- * Note: fw_next_arg1() uses a0, a1, and ra
- */
- call fw_next_arg1
- sd a0, SBI_SCRATCH_NEXT_ARG1_OFFSET(tp) /* Save agr1 in scratch buffer*/
/*
Note: fw_next_addr()uses a0, a1, and ra
*/
@@ -500,23 +495,6 @@ _reset_regs:
csrw CSR_MSCRATCH, 0
ret
- .align 3
- .section .entry, "ax", %progbits
- .global fw_prev_arg1
-fw_prev_arg1:
-
- /* We return previous arg1 in 'a0' */
- add a0, zero, zero
- ret
-
- .align 3
- .section .entry, "ax", %progbits
- .global fw_next_arg1
-fw_next_arg1:
- /* We return next arg1 in 'a0' */
- li a0, FixedPcdGet32(PcdRiscVPeiFvBase)
- ret
-
.align 3
.section .entry, "ax", %progbits
.global fw_next_addr
--
2.31.1
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH 34/79] RISC-V/PlatformPkg: Add FdtPeim to pass DTB from PEI to DXE via HOB
2022-01-08 4:10 [PATCH 02/79] ProcessorPkg/Library: RISC-V CPU library Abner Chang
` (30 preceding siblings ...)
2022-01-08 4:10 ` [PATCH 33/79] RISC-V/PlatformPkg: Build DeviceTree and use that in SEC Abner Chang
@ 2022-01-08 4:10 ` Abner Chang
2022-01-08 4:10 ` [PATCH 35/79] RISC-V/PlatformPkg: Fixup FDT from HOB and install into config table Abner Chang
` (5 subsequent siblings)
37 siblings, 0 replies; 39+ messages in thread
From: Abner Chang @ 2022-01-08 4:10 UTC (permalink / raw)
To: devel; +Cc: abner.chang
(This is migrated from edk2-platforms)
Cc: Daniel Schaefer <daniel.schaefer>
Cc: Abner Chang <abner.chang@hpe.com>
Cc: Sunil V L <sunilvl@ventanamicro.com>
Reviewed-by: Abner Chang <abner.chang@hpe.com>
Signed-off-by: Daniel Schaefer <daniel.schaefer@hpe.com>
---
.../PlatformPkg/Universal/FdtPeim/FdtPeim.inf | 49 +++++++++++++
.../PlatformPkg/Universal/FdtPeim/FdtPeim.c | 70 +++++++++++++++++++
2 files changed, 119 insertions(+)
create mode 100644 Platform/RISC-V/PlatformPkg/Universal/FdtPeim/FdtPeim.inf
create mode 100644 Platform/RISC-V/PlatformPkg/Universal/FdtPeim/FdtPeim.c
diff --git a/Platform/RISC-V/PlatformPkg/Universal/FdtPeim/FdtPeim.inf b/Platform/RISC-V/PlatformPkg/Universal/FdtPeim/FdtPeim.inf
new file mode 100644
index 0000000000..8dc58f0a8b
--- /dev/null
+++ b/Platform/RISC-V/PlatformPkg/Universal/FdtPeim/FdtPeim.inf
@@ -0,0 +1,49 @@
+## @file
+# The FDT Peim driver is used to pass the device tree to DXE phase.
+#
+# Copyright (c) 2021, Hewlett Packard Enterprise Developmente LP. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = FdtPei
+ MODULE_UNI_FILE = FdtPei.uni
+ FILE_GUID = 724FD5E9-F35E-4386-B1E1-2ADA6103C4F9
+ MODULE_TYPE = PEIM
+ VERSION_STRING = 1.0
+
+ ENTRY_POINT = PeimPassFdt
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = RISCV64
+#
+
+[Sources]
+ FdtPeim.c
+
+[Packages]
+ EmbeddedPkg/EmbeddedPkg.dec
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec
+
+[LibraryClasses]
+ DebugLib
+ DebugLib
+ HobLib
+ FdtLib
+ PcdLib
+ PeiServicesLib
+ PeimEntryPoint
+ RiscVFirmwareContextLib
+
+[Guids]
+ gFdtHobGuid ## PRODUCES
+
+[Depex]
+ TRUE
diff --git a/Platform/RISC-V/PlatformPkg/Universal/FdtPeim/FdtPeim.c b/Platform/RISC-V/PlatformPkg/Universal/FdtPeim/FdtPeim.c
new file mode 100644
index 0000000000..2cd94f291c
--- /dev/null
+++ b/Platform/RISC-V/PlatformPkg/Universal/FdtPeim/FdtPeim.c
@@ -0,0 +1,70 @@
+/** @file
+The module to pass the device tree to DXE via HOB.
+
+Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Library/DebugLib.h>
+#include <Library/HobLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/RiscVFirmwareContextLib.h>
+
+#include <libfdt.h>
+
+#include <Guid/FdtHob.h>
+
+/**
+ The entrypoint of the module, it will pass the FDT via a HOB.
+
+ @param FileHandle Handle of the file being invoked.
+ @param PeiServices Describes the list of possible PEI Services.
+
+ @retval TODO
+**/
+EFI_STATUS
+EFIAPI
+PeimPassFdt (
+ IN EFI_PEI_FILE_HANDLE FileHandle,
+ IN CONST EFI_PEI_SERVICES **PeiServices
+ )
+{
+ VOID *FdtPointer;
+ VOID *Base;
+ VOID *NewBase;
+ UINTN FdtSize;
+ UINTN FdtPages;
+ UINT64 *FdtHobData;
+ EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *FirmwareContext;
+
+ FirmwareContext = NULL;
+ GetFirmwareContextPointer (&FirmwareContext);
+
+ if (FirmwareContext == NULL) {
+ DEBUG((DEBUG_ERROR, "%a: OpenSBI Firmware Context is NULL\n", __FUNCTION__));
+ return EFI_UNSUPPORTED;
+ }
+ FdtPointer = (VOID *)FirmwareContext->FlattenedDeviceTree;
+ if (FdtPointer == NULL) {
+ DEBUG((DEBUG_ERROR, "%a: Invalid FDT pointer\n", __FUNCTION__));
+ return EFI_UNSUPPORTED;
+ }
+ DEBUG((DEBUG_ERROR, "%a: Build FDT HOB - FDT at address: 0x%x \n", __FUNCTION__, FdtPointer));
+ Base = FdtPointer;
+ ASSERT (Base != NULL);
+ ASSERT (fdt_check_header (Base) == 0);
+
+ FdtSize = fdt_totalsize (Base);
+ FdtPages = EFI_SIZE_TO_PAGES (FdtSize);
+ NewBase = AllocatePages (FdtPages);
+ ASSERT (NewBase != NULL);
+ fdt_open_into (Base, NewBase, EFI_PAGES_TO_SIZE (FdtPages));
+
+ FdtHobData = BuildGuidHob (&gFdtHobGuid, sizeof *FdtHobData);
+ ASSERT (FdtHobData != NULL);
+ *FdtHobData = (UINTN)NewBase;
+
+ return EFI_SUCCESS;
+}
--
2.31.1
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH 35/79] RISC-V/PlatformPkg: Fixup FDT from HOB and install into config table
2022-01-08 4:10 [PATCH 02/79] ProcessorPkg/Library: RISC-V CPU library Abner Chang
` (31 preceding siblings ...)
2022-01-08 4:10 ` [PATCH 34/79] RISC-V/PlatformPkg: Add FdtPeim to pass DTB from PEI to DXE via HOB Abner Chang
@ 2022-01-08 4:10 ` Abner Chang
2022-01-08 4:10 ` [PATCH 36/79] RISC-V: Switch to latest OpenSBI Abner Chang
` (4 subsequent siblings)
37 siblings, 0 replies; 39+ messages in thread
From: Abner Chang @ 2022-01-08 4:10 UTC (permalink / raw)
To: devel; +Cc: abner.chang
(This is migrated from edk2-platforms)
The Linux EFISTUB reads the FDT from the EFI system configuration
table. Before installing the FDT needs to be patched with the booting
hartid, because the kernel in S-Mode cannot determine it.
Cc: Daniel Schaefer <daniel.schaefer@hpe.com>
Cc: Abner Chang <abner.chang@hpe.com>
Cc: Sunil V L <sunilvl@ventanamicro.com>
Reviewed-by: Abner Chang <abner.chang@hpe.com>
Signed-off-by: Daniel Schaefer <daniel.schaefer@hpe.com>
---
.../RISC-V/ProcessorPkg/RiscVProcessorPkg.dsc | 3 +-
.../ProcessorPkg/Universal/FdtDxe/FdtDxe.inf | 53 ++++++++
.../ProcessorPkg/Universal/FdtDxe/FdtDxe.c | 116 ++++++++++++++++++
3 files changed, 171 insertions(+), 1 deletion(-)
create mode 100644 Silicon/RISC-V/ProcessorPkg/Universal/FdtDxe/FdtDxe.inf
create mode 100644 Silicon/RISC-V/ProcessorPkg/Universal/FdtDxe/FdtDxe.c
diff --git a/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dsc b/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dsc
index 1292ba1bea..531319322c 100644
--- a/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dsc
+++ b/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dsc
@@ -1,7 +1,7 @@
#/** @file
# RISC-V processor package.
#
-# Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -102,3 +102,4 @@
Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxe.inf
Silicon/RISC-V/ProcessorPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.inf
+ Silicon/RISC-V/ProcessorPkg/Universal/FdtDxe/FdtDxe.inf
diff --git a/Silicon/RISC-V/ProcessorPkg/Universal/FdtDxe/FdtDxe.inf b/Silicon/RISC-V/ProcessorPkg/Universal/FdtDxe/FdtDxe.inf
new file mode 100644
index 0000000000..ae6468f9f5
--- /dev/null
+++ b/Silicon/RISC-V/ProcessorPkg/Universal/FdtDxe/FdtDxe.inf
@@ -0,0 +1,53 @@
+## @file
+# RISC-V Flattened Device Tree DXE module.
+#
+# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001b
+ BASE_NAME = FdtDxe
+ FILE_GUID = a7d8f3f7-d8a7-47df-b3ec-9E5A693C380C
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ ENTRY_POINT = InstallFdt
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = RISCV64
+#
+
+
+[Packages]
+ EmbeddedPkg/EmbeddedPkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ MdePkg/MdePkg.dec
+ Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec
+ EmbeddedPkg/EmbeddedPkg.dec
+
+[LibraryClasses]
+ BaseLib
+ BaseMemoryLib
+ DebugLib
+ FdtLib
+ HobLib
+ MemoryAllocationLib
+ RiscVCpuLib
+ UefiBootServicesTableLib
+ UefiDriverEntryPoint
+
+[Sources]
+ FdtDxe.c
+
+[Guids]
+ gFdtHobGuid
+ gFdtTableGuid
+
+[Pcd]
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootHartId ## CONSUMES
+
+[Depex]
+ TRUE
diff --git a/Silicon/RISC-V/ProcessorPkg/Universal/FdtDxe/FdtDxe.c b/Silicon/RISC-V/ProcessorPkg/Universal/FdtDxe/FdtDxe.c
new file mode 100644
index 0000000000..22b12027d3
--- /dev/null
+++ b/Silicon/RISC-V/ProcessorPkg/Universal/FdtDxe/FdtDxe.c
@@ -0,0 +1,116 @@
+/** @file
+ RISC-V Flattened Device Tree DXE module
+
+ The Linux booting protocol on RISC-V requires the id of the booting hart to
+ be passed as a0. Therefore the EFISTUB needs to get this information. Because
+ it runs in S-Mode, it cannot get this information from mhartid. Instead we
+ insert the id into the device tree, that the EFIFSTUB can read from the config table.
+
+ Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/DebugLib.h>
+#include <Library/HobLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/PcdLib.h>
+#include <libfdt.h>
+
+/**
+ Fix up the device tree with booting hartid for the kernel
+
+ @param DtbBlob The device tree. Is extended to fit the hart id.
+
+ @retval EFI_SUCCESS The device tree was success fixed up with the hart id.
+ @retval EFI_OUT_OF_RESOURCES There is not enough memory available to complete the operation.
+**/
+EFI_STATUS
+EFIAPI
+FixDtb (
+ IN OUT VOID *DtbBlob,
+ IN UINTN BootingHartId
+ )
+{
+ fdt32_t Size;
+ UINT32 ChosenOffset, Err;
+
+ DEBUG ((DEBUG_INFO, "Fixing up device tree with boot hart id: %d\n",
+ BootingHartId));
+
+ Size = fdt_totalsize(DtbBlob);
+ Err = fdt_open_into(DtbBlob, DtbBlob, Size + 32);
+ if (Err < 0) {
+ DEBUG ((DEBUG_ERROR,
+ "Device Tree can't be expanded to accommodate new node\n", __FUNCTION__));
+ return EFI_OUT_OF_RESOURCES;
+ }
+ ChosenOffset = fdt_path_offset(DtbBlob, "/chosen");
+ fdt_setprop_u32(DtbBlob, ChosenOffset, "boot-hartid", BootingHartId);
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Install the FDT passed in HOB into EFI system configuration table.
+
+ @retval EFI_SUCCESS Successfully installed fixed up FDT in config table.
+ @retval EFI_NOT_FOUND Did not find FDT HOB.
+ @retval EFI_OUT_OF_RESOURCES There is not enough memory available to complete the operation.
+**/
+EFI_STATUS
+EFIAPI
+InstallFdtFromHob (VOID)
+{
+ EFI_STATUS Status;
+ EFI_HOB_GUID_TYPE *GuidHob;
+ VOID *DataInHob;
+ UINTN DataSize;
+
+ GuidHob = GetFirstGuidHob (&gFdtHobGuid);
+ if (GuidHob == NULL) {
+ DEBUG ((DEBUG_ERROR, "Failed to find RISC-V DTB Hob\n",
+ __FUNCTION__));
+ return EFI_NOT_FOUND;
+ }
+ DataInHob = (VOID *) *((UINTN *) GET_GUID_HOB_DATA (GuidHob));
+ DataSize = GET_GUID_HOB_DATA_SIZE (GuidHob);
+
+ Status = FixDtb (DataInHob, PcdGet32(PcdBootHartId));
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ Status = gBS->InstallConfigurationTable (&gFdtTableGuid, DataInHob);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "%a: failed to install FDT configuration table\n",
+ __FUNCTION__));
+ }
+ return Status;
+}
+
+/**
+ Install the FDT from the HOB into the EFI system configuration table.
+
+ @param ImageHandle Image handle of this driver.
+ @param SystemTable Pointer to the System Table.
+
+ @retval EFI_SUCCESS FDT successfully installed into config table.
+ @retval EFI_NOT_FOUND Did not find FDT HOB.
+ @retval EFI_OUT_OF_RESOURCES There is not enough memory available to complete the operation.
+
+**/
+EFI_STATUS
+EFIAPI
+InstallFdt (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+
+ Status = InstallFdtFromHob ();
+
+ return Status;
+}
--
2.31.1
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH 36/79] RISC-V: Switch to latest OpenSBI
2022-01-08 4:10 [PATCH 02/79] ProcessorPkg/Library: RISC-V CPU library Abner Chang
` (32 preceding siblings ...)
2022-01-08 4:10 ` [PATCH 35/79] RISC-V/PlatformPkg: Fixup FDT from HOB and install into config table Abner Chang
@ 2022-01-08 4:10 ` Abner Chang
2022-01-08 4:10 ` [PATCH 37/79] RISC-V: Implement ResetSystem RT call Abner Chang
` (3 subsequent siblings)
37 siblings, 0 replies; 39+ messages in thread
From: Abner Chang @ 2022-01-08 4:10 UTC (permalink / raw)
To: devel; +Cc: abner.chang
(This is migrated from edk2-platforms)
Cc: Daniel Schaefer <daniel.schaefer@hpe.com>
Cc: Abner Chang <abner.chang@hpe.com>
Cc: Sunil V L <sunilvl@ventanamicro.com>
Reviewed-by: Abner Chang <abner.chang@hpe.com>
Signed-off-by: Daniel Schaefer <daniel.schaefer@hpe.com>
---
.../RiscVOpensbiLib/RiscVOpensbiLib.inf | 13 ++++++---
.../Include/Library/RiscVEdk2SbiLib.h | 1 +
.../ProcessorPkg/Include/OpensbiTypes.h | 1 +
.../Library/OpensbiPlatformLibNull/Platform.c | 27 ++++++++++++-------
.../PlatformPkg/Universal/Sec/SecMain.c | 5 ++--
.../Universal/Sec/Riscv64/SecEntry.S | 2 ++
6 files changed, 34 insertions(+), 15 deletions(-)
diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVOpensbiLib/RiscVOpensbiLib.inf b/Silicon/RISC-V/ProcessorPkg/Library/RiscVOpensbiLib/RiscVOpensbiLib.inf
index 71cc76444e..e40a797896 100644
--- a/Silicon/RISC-V/ProcessorPkg/Library/RiscVOpensbiLib/RiscVOpensbiLib.inf
+++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVOpensbiLib/RiscVOpensbiLib.inf
@@ -23,6 +23,7 @@
opensbi/lib/sbi/sbi_bitmap.c
opensbi/lib/sbi/sbi_bitops.c
opensbi/lib/sbi/sbi_console.c
+ opensbi/lib/sbi/sbi_domain.c
opensbi/lib/sbi/sbi_ecall.c
opensbi/lib/sbi/sbi_ecall_base.c
opensbi/lib/sbi/sbi_ecall_hsm.c
@@ -51,27 +52,33 @@
opensbi/lib/utils/fdt/fdt_helper.c
opensbi/lib/utils/fdt/fdt_fixup.c
+ opensbi/lib/utils/fdt/fdt_domain.c
opensbi/lib/utils/ipi/fdt_ipi.c
- opensbi/lib/utils/ipi/fdt_ipi_clint.c
+ opensbi/lib/utils/ipi/aclint_mswi.c
+ opensbi/lib/utils/ipi/fdt_ipi_mswi.c
opensbi/lib/utils/irqchip/fdt_irqchip.c
opensbi/lib/utils/irqchip/fdt_irqchip_plic.c
opensbi/lib/utils/irqchip/plic.c
opensbi/lib/utils/reset/fdt_reset.c
opensbi/lib/utils/reset/fdt_reset_htif.c
opensbi/lib/utils/reset/fdt_reset_sifive.c
+ opensbi/lib/utils/reset/fdt_reset_thead.c
+ opensbi/lib/utils/reset/fdt_reset_thead_asm.S
opensbi/lib/utils/serial/fdt_serial.c
opensbi/lib/utils/serial/fdt_serial_htif.c
opensbi/lib/utils/serial/fdt_serial_shakti.c
opensbi/lib/utils/serial/fdt_serial_sifive.c
opensbi/lib/utils/serial/fdt_serial_uart8250.c
+ opensbi/lib/utils/serial/fdt_serial_gaisler.c
+ opensbi/lib/utils/serial/gaisler-uart.c
opensbi/lib/utils/serial/shakti-uart.c
opensbi/lib/utils/serial/sifive-uart.c
opensbi/lib/utils/serial/uart8250.c
- opensbi/lib/utils/sys/clint.c
opensbi/lib/utils/sys/htif.c
opensbi/lib/utils/sys/sifive_test.c
opensbi/lib/utils/timer/fdt_timer.c
- opensbi/lib/utils/timer/fdt_timer_clint.c
+ opensbi/lib/utils/timer/aclint_mtimer.c
+ opensbi/lib/utils/timer/fdt_timer_mtimer.c
[Packages]
EmbeddedPkg/EmbeddedPkg.dec # For libfdt.
diff --git a/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVEdk2SbiLib.h b/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVEdk2SbiLib.h
index f81ea06b05..66a87cb8c3 100644
--- a/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVEdk2SbiLib.h
+++ b/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVEdk2SbiLib.h
@@ -16,6 +16,7 @@
#include <IndustryStandard/RiscVOpensbi.h>
#include <sbi/sbi_scratch.h>
#include <sbi/sbi_platform.h>
+#include <sbi/sbi_ecall.h>
//
// EDK2 OpenSBI Firmware extension.
diff --git a/Silicon/RISC-V/ProcessorPkg/Include/OpensbiTypes.h b/Silicon/RISC-V/ProcessorPkg/Include/OpensbiTypes.h
index 37e407908a..8a6ea97708 100644
--- a/Silicon/RISC-V/ProcessorPkg/Include/OpensbiTypes.h
+++ b/Silicon/RISC-V/ProcessorPkg/Include/OpensbiTypes.h
@@ -49,6 +49,7 @@ typedef UINT64 physical_size_t;
#define __packed __attribute__((packed))
#define __noreturn __attribute__((noreturn))
+#define __aligned(x) __attribute__((aligned(x)))
#if defined(__GNUC__) || defined(__clang__)
#define likely(x) __builtin_expect((x), 1)
diff --git a/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLibNull/Platform.c b/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLibNull/Platform.c
index e78d811f4c..b7e39d19c1 100644
--- a/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLibNull/Platform.c
+++ b/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLibNull/Platform.c
@@ -14,31 +14,38 @@
#include <sbi/sbi_platform.h>
const struct sbi_platform_operations platform_ops = {
- .pmp_region_count = NULL,
- .pmp_region_info = NULL,
+ .early_init = NULL,
.final_init = NULL,
+ .early_exit = NULL,
+ .final_exit = NULL,
+ .domains_root_regions = NULL,
+ .domains_init = NULL,
.console_putc = NULL,
.console_getc = NULL,
.console_init = NULL,
.irqchip_init = NULL,
+ .irqchip_exit = NULL,
.ipi_send = NULL,
.ipi_clear = NULL,
.ipi_init = NULL,
+ .ipi_exit = NULL,
+ .get_tlbr_flush_limit = NULL,
.timer_value = NULL,
.timer_event_stop = NULL,
.timer_event_start = NULL,
.timer_init = NULL,
- .system_reboot = NULL,
- .system_shutdown = NULL
+ .timer_exit = NULL,
+ .system_reset_check = NULL,
+ .system_reset = NULL,
};
-const struct sbi_platform platform = {
- .opensbi_version = OPENSBI_VERSION, // The OpenSBI version this platform table is built bassed on.
- .platform_version = SBI_PLATFORM_VERSION(0x0000, 0x0000), // SBI Platform version 1.0
- .name = "NULL platform",
+struct sbi_platform platform = {
+ .opensbi_version = OPENSBI_VERSION,
+ .platform_version = SBI_PLATFORM_VERSION(0x0, 0x01),
+ .name = "NULL Platform",
.features = 0,
.hart_count = 0,
+ .hart_index2id = 0,
.hart_stack_size = 0,
- .disabled_hart_mask = 0,
- .platform_ops_addr = 0
+ .platform_ops_addr = 0,
};
diff --git a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c
index 0af0b4bac8..e9f030f352 100644
--- a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c
+++ b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c
@@ -21,6 +21,7 @@
#include <sbi/sbi_platform.h> // Reference to header file in opensbi
#include <sbi/sbi_init.h> // Reference to header file in opensbi
#include <sbi/sbi_ecall.h> // Reference to header file in opensbi
+#include <sbi/sbi_trap.h> // Reference to header file in opensbi
//
// Indicates the boot hart (PcdBootHartId) OpenSBI initialization is done.
@@ -434,7 +435,7 @@ EFI_STATUS EFIAPI TemporaryRamDone (
STATIC int SbiEcallFirmwareHandler (
IN unsigned long ExtId,
IN unsigned long FuncId,
- IN unsigned long *Args,
+ IN CONST struct sbi_trap_regs *TrapRegs,
OUT unsigned long *OutVal,
OUT struct sbi_trap_info *OutTrap
)
@@ -446,7 +447,7 @@ STATIC int SbiEcallFirmwareHandler (
*OutVal = (unsigned long) sbi_scratch_thishart_ptr();
break;
case SBI_EXT_FW_MSCRATCH_HARTID_FUNC:
- *OutVal = (unsigned long) sbi_hartid_to_scratch (Args[0]);
+ *OutVal = (unsigned long) sbi_hartid_to_scratch (TrapRegs->a0);
break;
default:
Ret = SBI_ENOTSUPP;
diff --git a/Platform/RISC-V/PlatformPkg/Universal/Sec/Riscv64/SecEntry.S b/Platform/RISC-V/PlatformPkg/Universal/Sec/Riscv64/SecEntry.S
index d3d589aefc..692985cefb 100644
--- a/Platform/RISC-V/PlatformPkg/Universal/Sec/Riscv64/SecEntry.S
+++ b/Platform/RISC-V/PlatformPkg/Universal/Sec/Riscv64/SecEntry.S
@@ -21,6 +21,8 @@
.text
.align 3
+ .globl _start_warm
+
ASM_FUNC (_ModuleEntryPoint)
/*
* Jump to warm-boot if this is not the selected core booting,
--
2.31.1
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH 37/79] RISC-V: Implement ResetSystem RT call
2022-01-08 4:10 [PATCH 02/79] ProcessorPkg/Library: RISC-V CPU library Abner Chang
` (33 preceding siblings ...)
2022-01-08 4:10 ` [PATCH 36/79] RISC-V: Switch to latest OpenSBI Abner Chang
@ 2022-01-08 4:10 ` Abner Chang
2022-01-08 4:10 ` [PATCH 38/79] Move OpenSbiPlatformLib to RISC-V/PlatformPkg Abner Chang
` (2 subsequent siblings)
37 siblings, 0 replies; 39+ messages in thread
From: Abner Chang @ 2022-01-08 4:10 UTC (permalink / raw)
To: devel; +Cc: abner.chang
(This is migrated from edk2-platforms)
Cc: Daniel Schaefer <daniel.schaefer@hpe.com>
Cc: Abner Chang <abner.chang@hpe.com>
Cc: Sunil V L <sunilvl@ventanamicro.com>
Reviewed-by: Abner Chang <abner.chang@hpe.com>
Signed-off-by: Daniel Schaefer <daniel.schaefer@hpe.com>
---
.../Library/ResetSystemLib/ResetSystemLib.inf | 33 +++++
.../Include/Library/RiscVEdk2SbiLib.h | 38 +++++-
.../Library/ResetSystemLib/ResetSystemLib.c | 128 ++++++++++++++++++
.../Library/RiscVEdk2SbiLib/RiscVEdk2SbiLib.c | 44 +++++-
4 files changed, 241 insertions(+), 2 deletions(-)
create mode 100644 Platform/RISC-V/PlatformPkg/Library/ResetSystemLib/ResetSystemLib.inf
create mode 100644 Platform/RISC-V/PlatformPkg/Library/ResetSystemLib/ResetSystemLib.c
diff --git a/Platform/RISC-V/PlatformPkg/Library/ResetSystemLib/ResetSystemLib.inf b/Platform/RISC-V/PlatformPkg/Library/ResetSystemLib/ResetSystemLib.inf
new file mode 100644
index 0000000000..f876ae2056
--- /dev/null
+++ b/Platform/RISC-V/PlatformPkg/Library/ResetSystemLib/ResetSystemLib.inf
@@ -0,0 +1,33 @@
+## @file
+# Library instance for ResetSystem library class for RISC-V using SBI ecalls
+#
+# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = ResetSystemLib
+ FILE_GUID = 3eff6057-1116-4dcb-837e-c0ef1a120ab1
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = ResetSystemLib
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = RISCV64
+#
+
+[Sources]
+ ResetSystemLib.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec
+
+[LibraryClasses]
+ DebugLib
+ RiscVEdk2SbiLib
diff --git a/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVEdk2SbiLib.h b/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVEdk2SbiLib.h
index 66a87cb8c3..88d957f002 100644
--- a/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVEdk2SbiLib.h
+++ b/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVEdk2SbiLib.h
@@ -1,7 +1,7 @@
/** @file
Library to call the RISC-V SBI ecalls
- Copyright (c) 2020, Hewlett Packard Development LP. All rights reserved.<BR>
+ Copyright (c) 2021, Hewlett Packard Development LP. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -474,6 +474,42 @@ SbiRemoteHfenceVvma (
IN UINTN Size
);
+///
+/// Firmware System Reset (SRST) Extension
+///
+
+/**
+ Reset the system
+
+ The System Reset Extension provides a function that allow the supervisor
+ software to request system-level reboot or shutdown. The term "system" refers
+ to the world-view of supervisor software and the underlying SBI
+ implementation could be machine mode firmware or hypervisor.
+
+ Valid parameters for ResetType and ResetReason are defined in sbi_ecall_interface.h
+
+ #define SBI_SRST_RESET_TYPE_SHUTDOWN 0x0
+ #define SBI_SRST_RESET_TYPE_COLD_REBOOT 0x1
+ #define SBI_SRST_RESET_TYPE_WARM_REBOOT 0x2
+
+ #define SBI_SRST_RESET_REASON_NONE 0x0
+ #define SBI_SRST_RESET_REASON_SYSFAIL 0x1
+
+ When the call is successful, it will not return.
+
+ @param[in] ResetType Typ of reset: Shutdown, cold-, or warm-reset.
+ @param[in] ResetReason Why the system resets. No reason or system failure.
+ @retval EFI_INVALID_PARAMETER Either ResetType or ResetReason is invalid.
+ @retval EFI_UNSUPPORTED ResetType is valid but not implemented on the platform.
+ @retval EFI_DEVICE_ERROR Unknown error.
+**/
+EFI_STATUS
+EFIAPI
+SbiSystemReset (
+ IN UINTN ResetType,
+ IN UINTN ResetReason
+ );
+
///
/// Vendor Specific extension space: Extension Ids 0x09000000 through 0x09FFFFFF
///
diff --git a/Platform/RISC-V/PlatformPkg/Library/ResetSystemLib/ResetSystemLib.c b/Platform/RISC-V/PlatformPkg/Library/ResetSystemLib/ResetSystemLib.c
new file mode 100644
index 0000000000..67e40151d1
--- /dev/null
+++ b/Platform/RISC-V/PlatformPkg/Library/ResetSystemLib/ResetSystemLib.c
@@ -0,0 +1,128 @@
+/** @file
+ Reset System Library functions for RISC-V
+
+ Copyright (c) 2021, Hewlett Packard Development LP. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Library/DebugLib.h>
+#include <Library/ResetSystemLib.h>
+#include <Library/RiscVEdk2SbiLib.h>
+
+/**
+ This function causes a system-wide reset (cold reset), in which
+ all circuitry within the system returns to its initial state. This type of reset
+ is asynchronous to system operation and operates without regard to
+ cycle boundaries.
+
+ If this function returns, it means that the system does not support cold reset.
+**/
+VOID
+EFIAPI
+ResetCold (
+ VOID
+ )
+{
+ // Warm Reset via SBI ecall
+ SbiSystemReset (SBI_SRST_RESET_TYPE_COLD_REBOOT, SBI_SRST_RESET_REASON_NONE);
+}
+
+/**
+ This function causes a system-wide initialization (warm reset), in which all processors
+ are set to their initial state. Pending cycles are not corrupted.
+
+ If this function returns, it means that the system does not support warm reset.
+**/
+VOID
+EFIAPI
+ResetWarm (
+ VOID
+ )
+{
+ // Warm Reset via SBI ecall
+ SbiSystemReset (SBI_SRST_RESET_TYPE_WARM_REBOOT, SBI_SRST_RESET_REASON_NONE);
+}
+
+/**
+ This function causes the system to enter a power state equivalent
+ to the ACPI G2/S5 or G3 states.
+
+ If this function returns, it means that the system does not support shutdown reset.
+**/
+VOID
+EFIAPI
+ResetShutdown (
+ VOID
+ )
+{
+ // Shut down via SBI ecall
+ SbiSystemReset (SBI_SRST_RESET_TYPE_SHUTDOWN, SBI_SRST_RESET_REASON_NONE);
+}
+
+/**
+ This function causes a systemwide reset. The exact type of the reset is
+ defined by the EFI_GUID that follows the Null-terminated Unicode string passed
+ into ResetData. If the platform does not recognize the EFI_GUID in ResetData
+ the platform must pick a supported reset type to perform. The platform may
+ optionally log the parameters from any non-normal reset that occurs.
+
+ @param[in] DataSize The size, in bytes, of ResetData.
+ @param[in] ResetData The data buffer starts with a Null-terminated string,
+ followed by the EFI_GUID.
+**/
+VOID
+EFIAPI
+ResetPlatformSpecific (
+ IN UINTN DataSize,
+ IN VOID *ResetData
+ )
+{
+ //
+ // Can map to OpenSBI vendor or platform specific reset type.
+ //
+ return;
+}
+
+/**
+ The ResetSystem function resets the entire platform.
+
+ @param[in] ResetType The type of reset to perform.
+ @param[in] ResetStatus The status code for the reset.
+ @param[in] DataSize The size, in bytes, of ResetData.
+ @param[in] ResetData For a ResetType of EfiResetCold, EfiResetWarm, or EfiResetShutdown
+ the data buffer starts with a Null-terminated string, optionally
+ followed by additional binary data. The string is a description
+ that the caller may use to further indicate the reason for the
+ system reset.
+**/
+VOID
+EFIAPI
+ResetSystem (
+ IN EFI_RESET_TYPE ResetType,
+ IN EFI_STATUS ResetStatus,
+ IN UINTN DataSize,
+ IN VOID *ResetData OPTIONAL
+ )
+{
+ switch (ResetType) {
+ case EfiResetWarm:
+ ResetWarm ();
+ break;
+
+ case EfiResetCold:
+ ResetCold ();
+ break;
+
+ case EfiResetShutdown:
+ ResetShutdown ();
+ return;
+
+ case EfiResetPlatformSpecific:
+ ResetPlatformSpecific (DataSize, ResetData);
+ return;
+
+ default:
+ return;
+ }
+}
diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVEdk2SbiLib/RiscVEdk2SbiLib.c b/Silicon/RISC-V/ProcessorPkg/Library/RiscVEdk2SbiLib/RiscVEdk2SbiLib.c
index 9bbeaaec3f..319526ed8f 100644
--- a/Silicon/RISC-V/ProcessorPkg/Library/RiscVEdk2SbiLib/RiscVEdk2SbiLib.c
+++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVEdk2SbiLib/RiscVEdk2SbiLib.c
@@ -15,7 +15,7 @@
- SbiLegacyRemoteSfenceVmaAsid -> Use SbiRemoteSfenceVmaAsid
- SbiLegacyShutdown -> Wait for new System Reset extension
- Copyright (c) 2020, Hewlett Packard Development LP. All rights reserved.<BR>
+ Copyright (c) 2021, Hewlett Packard Development LP. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@par Revision Reference:
@@ -715,6 +715,48 @@ SbiRemoteHFenceVvma (
return TranslateError (Ret.Error);
}
+/**
+ Reset the system
+
+ The System Reset Extension provides a function that allow the supervisor
+ software to request system-level reboot or shutdown. The term "system" refers
+ to the world-view of supervisor software and the underlying SBI
+ implementation could be machine mode firmware or hypervisor.
+
+ Valid parameters for ResetType and ResetReason are defined in sbi_ecall_interface.h
+
+ #define SBI_SRST_RESET_TYPE_SHUTDOWN 0x0
+ #define SBI_SRST_RESET_TYPE_COLD_REBOOT 0x1
+ #define SBI_SRST_RESET_TYPE_WARM_REBOOT 0x2
+
+ #define SBI_SRST_RESET_REASON_NONE 0x0
+ #define SBI_SRST_RESET_REASON_SYSFAIL 0x1
+
+ When the call is successful, it will not return.
+
+ @param[in] ResetType Typ of reset: Shutdown, cold-, or warm-reset.
+ @param[in] ResetReason Why the system resets. No reason or system failure.
+ @retval EFI_INVALID_PARAMETER Either ResetType or ResetReason is invalid.
+ @retval EFI_UNSUPPORTED ResetType is valid but not implemented on the platform.
+ @retval EFI_DEVICE_ERROR Unknown error.
+**/
+EFI_STATUS
+EFIAPI
+SbiSystemReset (
+ IN UINTN ResetType,
+ IN UINTN ResetReason
+ )
+{
+ SbiRet Ret = SbiCall (
+ SBI_EXT_SRST,
+ SBI_EXT_SRST_RESET,
+ 2,
+ ResetType,
+ ResetReason
+ );
+ return TranslateError (Ret.Error);
+}
+
//
// SBI interface function for the vendor extension
//
--
2.31.1
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH 38/79] Move OpenSbiPlatformLib to RISC-V/PlatformPkg
2022-01-08 4:10 [PATCH 02/79] ProcessorPkg/Library: RISC-V CPU library Abner Chang
` (34 preceding siblings ...)
2022-01-08 4:10 ` [PATCH 37/79] RISC-V: Implement ResetSystem RT call Abner Chang
@ 2022-01-08 4:10 ` Abner Chang
2022-01-08 4:10 ` [PATCH 39/79] RISC-V/PlatformPkg: Update document Abner Chang
2022-01-08 4:11 ` [PATCH 40/79] RISC-V: Add RISC-V PeiCoreEntryPoint library Abner Chang
37 siblings, 0 replies; 39+ messages in thread
From: Abner Chang @ 2022-01-08 4:10 UTC (permalink / raw)
To: devel; +Cc: abner.chang
(This is migrated from edk2-platforms)
It's a generic platform file. Only the device tree decides what happens.
Cc: Daniel Schaefer <daniel.schaefer@hpe.com>
Cc: Abner Chang <abner.chang@hpe.com>
Cc: Sunil V L <sunilvl@ventanamicro.com>
Reviewed-by: Abner Chang <abner.chang@hpe.com>
Signed-off-by: Daniel Schaefer <daniel.schaefer@hpe.com>
---
.../OpensbiPlatformLib/OpensbiPlatformLib.inf | 56 +++++
.../OpensbiPlatformLib/PlatformOverride.h | 30 +++
.../Library/OpensbiPlatformLib/Platform.c | 224 ++++++++++++++++++
.../Library/OpensbiPlatformLib/SifiveFu540.c | 47 ++++
4 files changed, 357 insertions(+)
create mode 100644 Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/OpensbiPlatformLib.inf
create mode 100644 Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/PlatformOverride.h
create mode 100644 Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/Platform.c
create mode 100644 Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/SifiveFu540.c
diff --git a/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/OpensbiPlatformLib.inf b/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/OpensbiPlatformLib.inf
new file mode 100644
index 0000000000..f9f2073a5b
--- /dev/null
+++ b/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/OpensbiPlatformLib.inf
@@ -0,0 +1,56 @@
+## @file
+# RISC-V OpenSBI Platform Library
+# This is the the library which provides platform
+# level opensbi functions follow RISC-V OpenSBI implementation.
+#
+# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001b
+ BASE_NAME = RiscVOpensbiPlatformLib
+ FILE_GUID = 80C09428-44DD-437F-8252-F7AB64711AA5
+ MODULE_TYPE = SEC
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = RiscVOpensbiPlatformLib
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = RISCV64
+#
+
+[Sources]
+ Platform.c
+ SifiveFu540.c
+ PlatformOverride.h
+
+[Packages]
+ EmbeddedPkg/EmbeddedPkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ MdePkg/MdePkg.dec
+ Platform/SiFive/U5SeriesPkg/U5SeriesPkg.dec
+ Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec
+ Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec
+
+[LibraryClasses]
+ BaseLib
+ BaseMemoryLib
+ DebugLib
+ DebugAgentLib
+ FdtLib
+ PcdLib
+ PrintLib
+ RiscVCpuLib
+
+[FixedPcd]
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootHartId
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdHartCount
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootableHartNumber
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdOpenSbiStackSize
+
+ gSiFiveU5SeriesPlatformsPkgTokenSpaceGuid.PcdU5UartBase
+ gSiFiveU5SeriesPlatformsPkgTokenSpaceGuid.PcdU5PlatformSystemClock
diff --git a/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/PlatformOverride.h b/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/PlatformOverride.h
new file mode 100644
index 0000000000..2fbb8ca45d
--- /dev/null
+++ b/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/PlatformOverride.h
@@ -0,0 +1,30 @@
+/*
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Copyright (c) 2020 Western Digital Corporation or its affiliates.
+ *
+ * Authors:
+ * Anup Patel <anup.patel@wdc.com>
+ */
+
+#ifndef __PLATFORM_OVERRIDE_H__
+#define __PLATFORM_OVERRIDE_H__
+
+#include <sbi/sbi_types.h>
+
+struct platform_override {
+ const struct fdt_match *match_table;
+ u64 (*features)(const struct fdt_match *match);
+ u64 (*tlbr_flush_limit)(const struct fdt_match *match);
+ int (*early_init)(bool cold_boot, const struct fdt_match *match);
+ int (*final_init)(bool cold_boot, const struct fdt_match *match);
+ void (*early_exit)(const struct fdt_match *match);
+ void (*final_exit)(const struct fdt_match *match);
+ int (*system_reset_check)(u32 reset_type, u32 reset_reason,
+ const struct fdt_match *match);
+ void (*system_reset)(u32 reset_type, u32 reset_reason,
+ const struct fdt_match *match);
+ int (*fdt_fixup)(void *fdt, const struct fdt_match *match);
+};
+
+#endif
diff --git a/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/Platform.c b/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/Platform.c
new file mode 100644
index 0000000000..79a78b834e
--- /dev/null
+++ b/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/Platform.c
@@ -0,0 +1,224 @@
+/*
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Copyright (c) 2020 Western Digital Corporation or its affiliates.
+ *
+ * Authors:
+ * Anup Patel <anup.patel@wdc.com>
+ */
+
+#include <libfdt.h>
+#include <PlatformOverride.h>
+#include <sbi/riscv_asm.h>
+#include <sbi/sbi_hartmask.h>
+#include <sbi/sbi_platform.h>
+#include <sbi/sbi_string.h>
+#include <sbi/sbi_math.h>
+#include <sbi_utils/fdt/fdt_domain.h>
+#include <sbi_utils/fdt/fdt_fixup.h>
+#include <sbi_utils/fdt/fdt_helper.h>
+#include <sbi_utils/irqchip/fdt_irqchip.h>
+#include <sbi_utils/serial/fdt_serial.h>
+#include <sbi_utils/timer/fdt_timer.h>
+#include <sbi_utils/ipi/fdt_ipi.h>
+#include <sbi_utils/reset/fdt_reset.h>
+
+extern const struct platform_override sifive_fu540;
+
+static const struct platform_override *special_platforms[] = {
+ &sifive_fu540,
+};
+
+static const struct platform_override *generic_plat = NULL;
+static const struct fdt_match *generic_plat_match = NULL;
+
+static void fw_platform_lookup_special(void *fdt, int root_offset)
+{
+ int pos, noff;
+ const struct platform_override *plat;
+ const struct fdt_match *match;
+
+ for (pos = 0; pos < array_size(special_platforms); pos++) {
+ plat = special_platforms[pos];
+ if (!plat->match_table)
+ continue;
+
+ noff = fdt_find_match(fdt, -1, plat->match_table, &match);
+ if (noff < 0)
+ continue;
+
+ generic_plat = plat;
+ generic_plat_match = match;
+ break;
+ }
+}
+
+extern struct sbi_platform platform;
+static u32 generic_hart_index2id[SBI_HARTMASK_MAX_BITS] = { 0 };
+
+/*
+ * The fw_platform_init() function is called very early on the boot HART
+ * OpenSBI reference firmwares so that platform specific code get chance
+ * to update "platform" instance before it is used.
+ *
+ * The arguments passed to fw_platform_init() function are boot time state
+ * of A0 to A4 register. The "arg0" will be boot HART id and "arg1" will
+ * be address of FDT passed by previous booting stage.
+ *
+ * The return value of fw_platform_init() function is the FDT location. If
+ * FDT is unchanged (or FDT is modified in-place) then fw_platform_init()
+ * can always return the original FDT location (i.e. 'arg1') unmodified.
+ */
+unsigned long fw_platform_init(unsigned long arg0, unsigned long arg1,
+ unsigned long arg2, unsigned long arg3,
+ unsigned long arg4)
+{
+ const char *model;
+ void *fdt = (void *)arg1;
+ u32 hartid, hart_count = 0;
+ int rc, root_offset, cpus_offset, cpu_offset, len;
+
+ root_offset = fdt_path_offset(fdt, "/");
+ if (root_offset < 0)
+ goto fail;
+
+ fw_platform_lookup_special(fdt, root_offset);
+
+ model = fdt_getprop(fdt, root_offset, "model", &len);
+ if (model)
+ sbi_strncpy(platform.name, model, sizeof(platform.name));
+
+ if (generic_plat && generic_plat->features)
+ platform.features = generic_plat->features(generic_plat_match);
+
+ cpus_offset = fdt_path_offset(fdt, "/cpus");
+ if (cpus_offset < 0)
+ goto fail;
+
+ fdt_for_each_subnode(cpu_offset, fdt, cpus_offset) {
+ rc = fdt_parse_hart_id(fdt, cpu_offset, &hartid);
+ if (rc)
+ continue;
+
+ if (SBI_HARTMASK_MAX_BITS <= hartid)
+ continue;
+
+ generic_hart_index2id[hart_count++] = hartid;
+ }
+
+ platform.hart_count = hart_count;
+
+ /* Return original FDT pointer */
+ return arg1;
+
+fail:
+ while (1)
+ wfi();
+}
+
+static int generic_early_init(bool cold_boot)
+{
+ int rc;
+
+ if (generic_plat && generic_plat->early_init) {
+ rc = generic_plat->early_init(cold_boot, generic_plat_match);
+ if (rc)
+ return rc;
+ }
+
+ if (!cold_boot)
+ return 0;
+
+ return fdt_reset_init();
+}
+
+static int generic_final_init(bool cold_boot)
+{
+ void *fdt;
+ int rc;
+
+ if (generic_plat && generic_plat->final_init) {
+ rc = generic_plat->final_init(cold_boot, generic_plat_match);
+ if (rc)
+ return rc;
+ }
+
+ if (!cold_boot)
+ return 0;
+
+ fdt = sbi_scratch_thishart_arg1_ptr();
+
+ fdt_cpu_fixup(fdt);
+ fdt_fixups(fdt);
+ fdt_domain_fixup(fdt);
+
+ if (generic_plat && generic_plat->fdt_fixup) {
+ rc = generic_plat->fdt_fixup(fdt, generic_plat_match);
+ if (rc)
+ return rc;
+ }
+
+ return 0;
+}
+
+static void generic_early_exit(void)
+{
+ if (generic_plat && generic_plat->early_exit)
+ generic_plat->early_exit(generic_plat_match);
+}
+
+static void generic_final_exit(void)
+{
+ if (generic_plat && generic_plat->final_exit)
+ generic_plat->final_exit(generic_plat_match);
+}
+
+static int generic_domains_init(void)
+{
+ return fdt_domains_populate(sbi_scratch_thishart_arg1_ptr());
+}
+
+static u64 generic_tlbr_flush_limit(void)
+{
+ if (generic_plat && generic_plat->tlbr_flush_limit)
+ return generic_plat->tlbr_flush_limit(generic_plat_match);
+ return SBI_PLATFORM_TLB_RANGE_FLUSH_LIMIT_DEFAULT;
+}
+
+const struct sbi_platform_operations platform_ops = {
+ .early_init = generic_early_init,
+ .final_init = generic_final_init,
+ .early_exit = generic_early_exit,
+ .final_exit = generic_final_exit,
+ .domains_init = generic_domains_init,
+ .console_init = fdt_serial_init,
+ .irqchip_init = fdt_irqchip_init,
+ .irqchip_exit = fdt_irqchip_exit,
+ .ipi_init = fdt_ipi_init,
+ .ipi_exit = fdt_ipi_exit,
+ .get_tlbr_flush_limit = generic_tlbr_flush_limit,
+ .timer_init = fdt_timer_init,
+ .timer_exit = fdt_timer_exit,
+};
+
+#if FixedPcdGet32(PcdBootableHartNumber) == 4
+#define U540_BOOTABLE_HART_COUNT FixedPcdGet32(PcdBootableHartNumber)
+static u32 U540_hart_index2id[U540_BOOTABLE_HART_COUNT] = {1, 2, 3, 4};
+#endif
+
+struct sbi_platform platform = {
+ .opensbi_version = OPENSBI_VERSION,
+ .platform_version = SBI_PLATFORM_VERSION(0x0, 0x01),
+ .name = "Generic",
+ .features = SBI_PLATFORM_DEFAULT_FEATURES,
+ .hart_count = SBI_HARTMASK_MAX_BITS,
+// TODO: Workaround for U540. Not sure why we need this. OpenSBI doesn't need it.
+#if FixedPcdGet32(PcdBootableHartNumber) == 4
+ .hart_index2id = U540_hart_index2id,
+#else
+ .hart_index2id = generic_hart_index2id,
+#endif
+ // TODO: Any reason why it shouldn't just be SBI_PLATFORM_DEFAULT_HART_STACK_SIZE?
+ .hart_stack_size = FixedPcdGet32(PcdOpenSbiStackSize),
+ .platform_ops_addr = (unsigned long)&platform_ops
+};
diff --git a/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/SifiveFu540.c b/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/SifiveFu540.c
new file mode 100644
index 0000000000..748b058840
--- /dev/null
+++ b/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/SifiveFu540.c
@@ -0,0 +1,47 @@
+/*
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Copyright (c) 2020 Western Digital Corporation or its affiliates.
+ *
+ * Authors:
+ * Anup Patel <anup.patel@wdc.com>
+ */
+
+#include <PlatformOverride.h>
+#include <sbi_utils/fdt/fdt_helper.h>
+#include <sbi_utils/fdt/fdt_fixup.h>
+
+static u64 sifive_fu540_tlbr_flush_limit(const struct fdt_match *match)
+{
+ /*
+ * The sfence.vma by virtual address does not work on
+ * SiFive FU540 so we return remote TLB flush limit as zero.
+ */
+ return 0;
+}
+
+static int sifive_fu540_fdt_fixup(void *fdt, const struct fdt_match *match)
+{
+ /*
+ * SiFive Freedom U540 has an erratum that prevents S-mode software
+ * to access a PMP protected region using 1GB page table mapping, so
+ * always add the no-map attribute on this platform.
+ */
+ fdt_reserved_memory_nomap_fixup(fdt);
+
+ return 0;
+}
+
+static const struct fdt_match sifive_fu540_match[] = {
+ { .compatible = "sifive,fu540" },
+ { .compatible = "sifive,fu540g" },
+ { .compatible = "sifive,fu540-c000" },
+ { .compatible = "sifive,hifive-unleashed-a00" },
+ { },
+};
+
+const struct platform_override sifive_fu540 = {
+ .match_table = sifive_fu540_match,
+ .tlbr_flush_limit = sifive_fu540_tlbr_flush_limit,
+ .fdt_fixup = sifive_fu540_fdt_fixup,
+};
--
2.31.1
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH 39/79] RISC-V/PlatformPkg: Update document
2022-01-08 4:10 [PATCH 02/79] ProcessorPkg/Library: RISC-V CPU library Abner Chang
` (35 preceding siblings ...)
2022-01-08 4:10 ` [PATCH 38/79] Move OpenSbiPlatformLib to RISC-V/PlatformPkg Abner Chang
@ 2022-01-08 4:10 ` Abner Chang
2022-01-08 4:11 ` [PATCH 40/79] RISC-V: Add RISC-V PeiCoreEntryPoint library Abner Chang
37 siblings, 0 replies; 39+ messages in thread
From: Abner Chang @ 2022-01-08 4:10 UTC (permalink / raw)
To: devel; +Cc: abner.chang
(This is migrated from edk2-platforms:Platform)
Update EDK2 RISC-V port architectural diagrams.
Cc: Daniel Schaefer <daniel.schaefer@hpe.com>
Cc: Sunil V L <sunilvl@ventanamicro.com>
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Reviewed-by: Daniel Schaefer <daniel.schaefer@hpe.com>
Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
---
Platform/RISC-V/PlatformPkg/Readme.md | 132 +-
.../Documents/Media/RiscVEdk2BootProcess.svg | 1928 +++++++++++++++++
.../Documents/Media/RiscVEdk2FwDomain.svg | 1290 +++++++++++
3 files changed, 3336 insertions(+), 14 deletions(-)
create mode 100644 Platform/RISC-V/PlatformPkg/Documents/Media/RiscVEdk2BootProcess.svg
create mode 100644 Platform/RISC-V/PlatformPkg/Documents/Media/RiscVEdk2FwDomain.svg
diff --git a/Platform/RISC-V/PlatformPkg/Readme.md b/Platform/RISC-V/PlatformPkg/Readme.md
index 4b933a2e0f..66fba15544 100644
--- a/Platform/RISC-V/PlatformPkg/Readme.md
+++ b/Platform/RISC-V/PlatformPkg/Readme.md
@@ -2,6 +2,113 @@
## EDK2 RISC-V Platform Project
+### EDK2 RISC-V Design and the Boot Processes
+RISC-V edk2 port is designed base on edk2 boot phases and leverage [RISC-V OpenSBI](https://github.com/riscv/opensbi) (which is the implementation of [RISC-V SBI](https://github.com/riscv/riscv-sbi-doc)) as an edk2 library. The design concept is to leverage RISC-V SBI implementation, the basic RISC-V HARTs and the platform initialization. However, it still keeps the edk2 build mechanism and the boot processes. RISC-V OpenSBI is built as
+an library and linked with edk2 SEC module. The design diagram and the boot flow is shown in below figure,
+
+#### RISC-V EDK2 Port Design Diagrams
+
+
+#### SEC Phase
+As the most of edk2 platforms SEC implementations, RISC-V edk2 port SEC module initiates the fundamental platform
+boot environment. RISC-V edk2 SEC module linked with [RiscVOpensbiLib](#riscvopensbilib-library) that pulls in the OpenSBI core source files into the build as a library. SEC module invokes sbi_init() to execute through the OpenSBI
+initialization flow. Afterwards, SEC phase hands off to PEI phase via OpenSBI with the ***NextAddress*** and ***NextMode*** are configured.
+The entire SEC phase with ***RiscVOpensbiLib*** is executed in the Machine-mode (M-mode) which is the highest
+and the mandatory privilege mode of RISC-V HART. The SBI implementation is also executed in the M-mode that
+provides the Supervisor Binary Interface for the entities run in the Supervisor-mode (S-mode). The default
+privilege mode is configured to S-mode for the next phase after SEC, that says the PEI, DXE and BDS phases are
+default executed in S-mode unless the corresponding [PCDs](#risc-v-platform-pcd-settings) are configured
+differently from the default settings according to the OEM platform design.
+
+##### RiscVOpensbiLib Library
+[Indicated as #1 in the figure](#risc-v-edk2-port-design-diagrams)
+> ***RiscVOpensbiLib*** is a edk2 wrapper library of OpenSBI. SEC module is the only consumer of ***RiscVOpensbiLib*** across the entire edk2 boot processes. The sub-module under ***RiscVOpensbiLib*** is updated
+to align with OpenSBI project. As mentioned earlier, ***RiscVOpensbiLib*** provides the RISC-V SBI
+implementation and initialize the OpenSBI boot flow. SEC module is also linked with below libraries,
+- edk2 [OpenSbiPlatformLib](#OpenSbiPlatformLib-library) library that provides the generic RISC-V platform initialization code.
+- edk2 [RiscVSpecifialPlatformLib](#RiscVSpecifialPlatformLib-library) library which is provided by the RISC-V
+platform vendor for the platform-specific initialization. The underlying implementation of above two edk2 libraries
+are from OpenSBI project. edk2 libraries are introduced as the wrapper libraries that separates and organizes OpenSBI core and platform code based on edk2 framework and the the build mechanism for edk2 RISC-V platforms. ***RiscVOpensbiLib*** library is located under [RISC-V ProcessorPkg](https://github.com/tianocore/edk2-platforms/tree/master/Silicon/RISC-V/ProcessorPkg) while the platform code (e.g. OpenSbiPlatformLib) is located under [RISC-V PlatformPkg](https://github.com/tianocore/edk2-platforms/tree/master/Platform/RISC-V/PlatformPkg).
+- edk2 [RiscVSpecifialPlatformLib](#riscvspecifialplatformlib) library is provided by the platform vendor and located under edk2 RISC-V platform-specific folder.
+
+##### OpenSbiPlatformLib Library
+[Indicated as #2 in the figure](#risc-v-edk2-port-design-diagrams)
+> ***OpenSbiPlatformLib*** provides the generic RISC-V platform initialization code. Platform vendor can just utilize this library if they don't have additional requirements on the platform initialization.
+
+##### RiscVSpecifialPlatformLib Library
+[Indicated as #3 in the figure](#risc-v-edk2-port-design-diagrams)
+> The major use case of this library is to facilitate the interfaces for platform vendors to provide the special
+platform initialization based on the generic platform initialization library.
+
+##### Edk2OpensbiPlatformWrapperLib Library
+[Indicated as #4 in the figure](#risc-v-edk2-port-design-diagrams)
+> In order to providing the flexibility to edk2 RISC-V firmware solution, ***Edk2OpensbiPlatformWrapperLib*** is the wrapper library of [OpenSbiPlatformLib](#OpenSbiPlatformLib-library) to provide the interfaces for OEM. The ***platform_ops_address***in the generic platform structure is replaced with ***Edk2OpensbiplatformOps*** in SEC
+module. The platform function invoked by OpenSBI core is hooked to ***Edk2OpensbiPlatformWrapperLib***. This gives
+a change to OEM for implementing platform-specific initialization before and after the generic platform code. OEM
+can override this library under their platform folder on demand without touching ***RiscVOpensbiLib*** library
+source files and other common source files.
+
+##### Next Phase Address and Privilege Mode
+[Indicated as #5 in the figure](#risc-v-edk2-port-design-diagrams)
+> Once OpenSBI finishes the boot initialization, it will jump to the next phase with the default privilege set to
+S-mode. In order to facilitate the flexibility for a variant of platform demands. EDK2 RISC-V provides the [PCDs](#risc-v-platform-pcd-settings) as the configurable privilege for the next phase. Whether to have PEI or later
+phases executed in the default S-mode or to keep the RISC-V edk2 boot phase privilege in M-mode is at platform design discretion. The SEC module sets the next phase address to the PEI Core entry point with a configurable
+privilege according to the PCD.
+
+#### PEI Phase
+SEC module hands off the boot process to PEI core in the privilege configured by ***PcdPeiCorePrivilegeMode*** PCD *(TODO, currently the privilege is forced to S-mode)*. PEI and later phases are allowed to executed in M-mode
+if the platform doesn't require Hypervisor-extended Supervisor mode (HS-mode) for the virtualization. RISC-V edk2 port provides its own instance ***PeiCoreEntryPoint*** library [(indicated as #7 in the figure)](#risc-v-edk2-port-design-diagrams) and linked with [PlatformSecPpiLib](#platformsecppilib-library) in order to support the S-mode PEI phase. PEI core requires [RiscVFirmwareContextLib](#riscVfirmwarecontextlib-library) library to retrieve the information of RISC-V HARTs and platform (e.g. FDT) configurations that built up in SEC phase. ***PeiServicePointer*** is also maintained in the ***RISC-V OpenSBI FirmwareContext*** structure and the pointer is retrieved by [PeiServiceTablePointerOpensbi](#peiservicetablepointeropensbi-library) library.
+
+##### PlatformSecPpiLib Library
+[Indicated as #8 in the figure](#risc-v-edk2-port-design-diagrams)
+
+> Some platform has the PEI protocol interface (PPI) prepared in SEC phase and pass the PPI description to PEI phase for the installation. That means the PPI code resides in SEC module and executed in PEI phase. Due to the SEC
+(with OpenSBI) is protected by the RISC-V Physical Memory Protection (PMP) through [OpenSBI firmware domain](#edk2-opensbi-firmware-domain), the SEC can be only accessed and executed when RISC-V HART is operated in M-mode. The SEC PPI passed to PEI is not able to be executed by any PEI modules. Thus we have ***PlatformSecPpiLib*** library for the platforms that requires to install the PPI at the early stage of PEI core instead of installing PPI
+during PEI dispatcher that maybe too late for some platform use cases. ***PlatformSecPpiLib*** is currently
+executed in S-mode because we force to switch RISC-V boot HART to S-mode when SEC hands of boot process to PEI
+phase. ***PlatformSecPpiLib*** can also executed in M-mode once we have the full implementation of [***PcdPeiCorePrivilegeMode***.](#risc-v-platform-pcd-settings)
+
+##### RiscVFirmwareContextLib Library
+[Indicated as #9 in the figure](#risc-v-edk2-port-design-diagrams)
+
+> The ***OpenSBI FirmwareContext*** is a structure member in sbi_platform, that can carry the firmware
+solution-defined information to edk2 boot phases after SEC. edk2 defines its own ***FirmwareContext*** as below in
+the current implementation.
+
+ typedef struct {
+ UINT64 BootHartId;
+ VOID *PeiServiceTable; // PEI Service table
+ UINT64 FlattenedDeviceTree; // Pointer to Flattened Device tree
+ UINT64 SecPeiHandOffData; // This is EFI_SEC_PEI_HAND_OFF passed to PEI Core.
+ EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC *HartSpecific[RISC_V_MAX_HART_SUPPORTED];
+ } EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT;
+
+> ***RiscVFirmwareContextLib*** library is used by PEI module for obtaining the ***FirmwareContext*** pointer.
+
+##### PeiServiceTablePointerOpensbi Library
+[Indicated as #10 in the figure](#risc-v-edk2-port-design-diagrams)
+
+> ***PeiServiceTablePointerOpensbi*** is the library that provides Get/Set PeiServiceTablePointer. ***RiscVFirmwareContextLib*** is the underlying library for the operations on PEI service table pointer.
+
+##### PEI OpenSBI PPI
+[Indicated as #11 in the figure](#risc-v-edk2-port-design-diagrams)
+
+> edk2 PEI OpenSBI PPI *(TODO)* provides the unified interface for all PEI drivers to invoke SBI services.
+
+#### DXE Phase
+DXE IPL PEI module hands off the boot process to DXE Core in the privilege configured by PcdDxeCorePrivilegeMode PCD *(TODO, currently is not implemented yet)*. edk2 DXE OpenSBI protocol *(TODO, indicated as #12 in the figure)* provides the unified interface for all DXE drivers to invoke SBI services.
+
+#### BDS Phase
+The implementation of RISC-V edk2 port in BDS phase is the same as it is in DXE phase which is executed in the
+privilege configured by PcdDxeCorePrivilegeMode PCD *(TODO, currently the privilege is forced to S-mode)*. The
+OpenSBI is also provided through edk2 DXE OpenSBI Protocol*(TODO, indicated as #12 in the figure)*. However, BDS must transits the privilege mode to S-mode before it handing off the boot process to S-mode OS, OS boot loader or EFI application.
+
+#### EDK2 OpenSBI Firmware Domain
+
+
+
+OpenSBI implements the firmware domain mechanism to protect the root firmware (which is the OpenSBI itself) as the M-mode only access and execute region. RISC-V edk2 port configures the root firmware domain via [PCDs](#risc-v-platform-pcd-settings) to protect SEC firmware volume, memory and OpenSBI stuff. The firmware region (non-root firmware) that accommodates PEI and DXE phase FV regions, while EFI variable region is reported as a separate firmware region as it shows in above figure.
+
### EDK2 Build Architecture for RISC-V
The edk2 build architecture which is supported and verified on edk2 code base for
RISC-V platforms is `RISCV64`.
@@ -49,18 +156,9 @@ Then you can build the edk2 firmware image for RISC-V platforms.
build -a RISCV64 -t GCC5 -p Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.dsc
```
-## RISC-V OpenSBI Library
-RISC-V [OpenSBI](https://github.com/riscv/opensbi) is the implementation of
-[RISC-V SBI (Supervisor Binary Interface) specification](https://github.com/riscv/riscv-sbi-doc).
-For EDK2 UEFI firmware solution, RISC-V OpenSBI is integrated as a library
-[(submoudule)](Silicon/RISC-V/ProcessorPkg/Library/RiscVOpensbiLib/opensbi) in EDK2
-RISC-V Processor Package. The RISC-V OpenSBI library is built in SEC driver without
-any modifications and provides the interfaces for supervisor mode execution environment
-to execute privileged operations.
-
## RISC-V Platform PCD settings
### EDK2 Firmware Volume Settings
-EDK2 Firmware volume related PCDs which declared in platform FDF file.
+EDK2 Firmware volume related PCDs which is declared in platform FDF file.
| **PCD name** |**Usage**|
|--------------|---------|
@@ -86,10 +184,14 @@ The PCD settings regard to EFI Variable
### RISC-V Physical Memory Protection (PMP) Region Settings
Below PCDs could be set in platform FDF file.
-| **PCD name** |**Usage**|
-|--------------|---------|
-|PcdFwStartAddress| The starting address of firmware region to protected by PMP|
-|PcdFwEndAddress| The ending address of firmware region to protected by PMP|
+| **PCD name** |**Usage**|**Access Permission in M-mode**|**Access Permission in S-mode**|
+|--------------|---------|---------|---------|
+|PcdRootFirmwareDomainBaseAddress| The starting address of root firmware domain protected by PMP|Full access|No Access|
+|PcdRootFirmwareDomainSize| The size of root firmware domain|-|-|
+|PcdFirmwareDomainBaseAddress| The starting address of firmware domain that can be accessed and executed in S-mode|Full access|Readable and Executable|
+|PcdFirmwareDomainSize| The size of firmware domain|-|-|
+|PcdVariableFirmwareRegionBaseAddress| The starting address of EFI variable region that can be accessed in S-mode|Full access|Readale and Writable|
+|PcdVariableFirmwareRegionSize| The size of EFI variable firmware region|-|-|
### RISC-V Processor HART Settings
@@ -98,6 +200,7 @@ Below PCDs could be set in platform FDF file.
|PcdHartCount| Number of RISC-V HARTs, the value is processor-implementation specific|
|PcdBootHartId| The ID of RISC-V HART to execute main fimrware code and boot system to OS|
|PcdBootableHartNumber|The bootable HART number, which is incorporate with RISC-V OpenSBI platform hart_index2id value|
+|PcdBootableHartIndexToId| if PcdBootableHartNumber == 0, hart_index2id is built from Device Tree, otherwise this is an array of HART index to HART ID|
### RISC-V OpenSBI Settings
@@ -109,6 +212,7 @@ Below PCDs could be set in platform FDF file.
|PcdTemporaryRamBase| The base address of temporary memory for PEI phase|
|PcdTemporaryRamSize| The temporary memory size for PEI phase|
|PcdPeiCorePrivilegeMode|The target RISC-V privilege mode for edk2 PEI phase|
+|PcdDxeCorePrivilegeMode (TODO)|The target RISC-V privilege mode for edk2 DXE phase|
## Supported Operating Systems
Currently support boot to EFI Shell and Linux kernel.
diff --git a/Platform/RISC-V/PlatformPkg/Documents/Media/RiscVEdk2BootProcess.svg b/Platform/RISC-V/PlatformPkg/Documents/Media/RiscVEdk2BootProcess.svg
new file mode 100644
index 0000000000..dfd47a75b9
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+ <desc>DXE SBI Procotol</desc>
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--
2.31.1
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH 40/79] RISC-V: Add RISC-V PeiCoreEntryPoint library
2022-01-08 4:10 [PATCH 02/79] ProcessorPkg/Library: RISC-V CPU library Abner Chang
` (36 preceding siblings ...)
2022-01-08 4:10 ` [PATCH 39/79] RISC-V/PlatformPkg: Update document Abner Chang
@ 2022-01-08 4:11 ` Abner Chang
37 siblings, 0 replies; 39+ messages in thread
From: Abner Chang @ 2022-01-08 4:11 UTC (permalink / raw)
To: devel; +Cc: abner.chang
(This is migrated from edk2-platforms:Platform)
- Add RISC-V PeiCoreEntryPoint library that incorporates with
opensbi next phase switching mechanism.
- Use RiscVFirmwareContext library to get the pointer of
opensbi FirmwareContext.
Cc: Sunil V L <sunilvl@ventanamicro.com>
Cc: Daniel Schaefer <daniel.schaefer@hpe.com>
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Reviewed-by: Daniel Schaefer <daniel.schaefer@hpe.com>
Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
---
.../RISC-V/PlatformPkg/RiscVPlatformPkg.dsc | 7 +-
.../PeiCoreEntryPoint/PeiCoreEntryPoint.inf | 36 +++++++
.../PeiCoreEntryPoint/PeiCoreEntryPoint.c | 97 +++++++++++++++++++
.../PeiCoreEntryPoint/PeiCoreEntryPoint.uni | 14 +++
4 files changed, 153 insertions(+), 1 deletion(-)
create mode 100644 Platform/RISC-V/PlatformPkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.inf
create mode 100644 Platform/RISC-V/PlatformPkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.c
create mode 100644 Platform/RISC-V/PlatformPkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.uni
diff --git a/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dsc b/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dsc
index 5d9674a965..8eec09549f 100644
--- a/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dsc
+++ b/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dsc
@@ -1,7 +1,7 @@
#/** @file
# RISC-V platform package.
#
-# Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -58,6 +58,10 @@
TimerLib|MdePkg/Library/BaseTimerLibNullTemplate/BaseTimerLibNullTemplate.inf
PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
+[LibraryClasses.common.PEI_CORE]
+ # RISC-V platform PEI core entry point.
+ PeiCoreEntryPoint|Platform/RISC-V/PlatformPkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.inf
+
[LibraryClasses.common.PEIM]
FirmwareContextProcessorSpecificLib|Platform/RISC-V/PlatformPkg/Library/FirmwareContextProcessorSpecificLib/FirmwareContextProcessorSpecificLib.inf
HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
@@ -77,6 +81,7 @@
Platform/RISC-V/PlatformPkg/Library/PlatformUpdateProgressLibNull/PlatformUpdateProgressLibNull.inf
Platform/RISC-V/PlatformPkg/Library/FirmwareContextProcessorSpecificLib/FirmwareContextProcessorSpecificLib.inf
Platform/RISC-V/PlatformPkg/Library/RiscVPlatformTempMemoryInitLibNull/RiscVPlatformTempMemoryInitLibNull.inf
+ Platform/RISC-V/PlatformPkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.inf
[Components.common.SEC]
Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf
diff --git a/Platform/RISC-V/PlatformPkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.inf b/Platform/RISC-V/PlatformPkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.inf
new file mode 100644
index 0000000000..e16a974636
--- /dev/null
+++ b/Platform/RISC-V/PlatformPkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.inf
@@ -0,0 +1,36 @@
+## @file
+# Module entry point library for PEI core on RISC-V with RISC-V OpenSBI.
+#
+# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = PeiCoreEntryPoint
+ MODULE_UNI_FILE = PeiCoreEntryPoint.uni
+ FILE_GUID = 2EBF4D2C-99B2-4A09-8C5C-318FB0EF7250
+ MODULE_TYPE = PEI_CORE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = PeiCoreEntryPoint|PEI_CORE
+
+#
+# VALID_ARCHITECTURES = RISCV64
+#
+
+[Sources]
+ PeiCoreEntryPoint.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec
+ Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec
+
+[LibraryClasses]
+ BaseLib
+ DebugLib
+ RiscVFirmwareContextLib
+
diff --git a/Platform/RISC-V/PlatformPkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.c b/Platform/RISC-V/PlatformPkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.c
new file mode 100644
index 0000000000..2fd0f2315b
--- /dev/null
+++ b/Platform/RISC-V/PlatformPkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.c
@@ -0,0 +1,97 @@
+/** @file
+ Entry point to a the PEI Core on RISC-V platform with RISC-V OpenSBI.
+
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+
+#include <PiPei.h>
+#include <IndustryStandard/RiscVOpensbi.h>
+//
+// The Library classes this module produced
+//
+#include <Library/BaseLib.h>
+#include <Library/DebugLib.h>
+#include <Library/PeiCoreEntryPoint.h>
+#include <Library/RiscVFirmwareContextLib.h>
+
+/**
+ The entry point of PE/COFF Image for the PEI Core.
+
+ This function is the entry point for the PEI Foundation, which allows the SEC phase
+ to pass information about the stack, temporary RAM and the Boot Firmware Volume.
+ In addition, it also allows the SEC phase to pass services and data forward for use
+ during the PEI phase in the form of one or more PPIs.
+ There is no limit to the number of additional PPIs that can be passed from SEC into
+ the PEI Foundation. As part of its initialization phase, the PEI Foundation will add
+ these SEC-hosted PPIs to its PPI database such that both the PEI Foundation and any
+ modules can leverage the associated service calls and/or code in these early PPIs.
+ This function is required to call ProcessModuleEntryPointList() with the Context
+ parameter set to NULL. ProcessModuleEntryPoint() is never expected to return.
+ The PEI Core is responsible for calling ProcessLibraryConstructorList() as soon as
+ the PEI Services Table and the file handle for the PEI Core itself have been established.
+ If ProcessModuleEntryPointList() returns, then ASSERT() and halt the system.
+
+ @param SecCoreData This is actually the RISC-V boot HART ID passed in a0 register.
+
+ @param PpiList This is actually the EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT passed
+ in a1 register.
+
+**/
+VOID
+EFIAPI
+_ModuleEntryPoint(
+ IN CONST EFI_SEC_PEI_HAND_OFF *SecCoreData,
+ IN CONST EFI_PEI_PPI_DESCRIPTOR *PpiList
+)
+{
+ EFI_SEC_PEI_HAND_OFF *ThisSecCoreData;
+ EFI_PEI_PPI_DESCRIPTOR *ThisPpiList;
+ EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *FirmwareContext;
+
+ FirmwareContext = (EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *)PpiList;
+ SetFirmwareContextPointer (FirmwareContext);
+ ThisSecCoreData = (EFI_SEC_PEI_HAND_OFF *)FirmwareContext->SecPeiHandOffData;
+ ThisPpiList = (EFI_PEI_PPI_DESCRIPTOR *)FirmwareContext->SecPeiHandoffPpi;
+ ProcessModuleEntryPointList (ThisSecCoreData, ThisPpiList, NULL);
+
+ //
+ // Should never return
+ //
+ ASSERT(FALSE);
+ CpuDeadLoop ();
+}
+
+
+/**
+ Required by the EBC compiler and identical in functionality to _ModuleEntryPoint().
+
+ This function is required to call _ModuleEntryPoint() passing in SecCoreData and PpiList.
+
+ @param SecCoreData Points to a data structure containing information about the PEI core's
+ operating environment, such as the size and location of temporary RAM,
+ the stack location and the BFV location.
+
+ @param PpiList Points to a list of one or more PPI descriptors to be installed
+ initially by the PEI core. An empty PPI list consists of
+ a single descriptor with the end-tag
+ EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST.
+ As part of its initialization phase, the PEI Foundation will
+ add these SEC-hosted PPIs to its PPI database, such that both
+ the PEI Foundationand any modules can leverage the associated
+ service calls and/or code in these early PPIs.
+
+**/
+VOID
+EFIAPI
+EfiMain (
+ IN CONST EFI_SEC_PEI_HAND_OFF *SecCoreData,
+ IN CONST EFI_PEI_PPI_DESCRIPTOR *PpiList
+ )
+{
+ _ModuleEntryPoint (SecCoreData, PpiList);
+}
diff --git a/Platform/RISC-V/PlatformPkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.uni b/Platform/RISC-V/PlatformPkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.uni
new file mode 100644
index 0000000000..1955b7a05b
--- /dev/null
+++ b/Platform/RISC-V/PlatformPkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.uni
@@ -0,0 +1,14 @@
+// /** @file
+// Module entry point library for PEI core on RISC-V with RISC-V OpenSBI.
+//
+// Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+//
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+// **/
+
+
+#string STR_MODULE_ABSTRACT #language en-US "RISC-V module entry point library for PEI core"
+
+#string STR_MODULE_DESCRIPTION #language en-US "RISC-V module entry point library for PEI core."
+
--
2.31.1
^ permalink raw reply related [flat|nested] 39+ messages in thread
end of thread, other threads:[~2022-01-08 5:13 UTC | newest]
Thread overview: 39+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2022-01-08 4:10 [PATCH 02/79] ProcessorPkg/Library: RISC-V CPU library Abner Chang
2022-01-08 4:10 ` [PATCH 03/79] ProcessorPkg/Library: Add RISC-V exception library Abner Chang
2022-01-08 4:10 ` [PATCH 04/79] ProcessorPkg/Library: Add RISC-V timer library Abner Chang
2022-01-08 4:10 ` [PATCH 05/79] ProcessorPkg/RiscVOpensbLib: Add opensbi submodule Abner Chang
2022-01-08 4:10 ` [PATCH 06/79] ProcessorPkg/Library: Add RiscVOpensbiLib Abner Chang
2022-01-08 4:10 ` [PATCH 07/79] ProcessorPkg/Library: Add RiscVEdk2SbiLib Abner Chang
2022-01-08 4:10 ` [PATCH 08/79] ProcessorPkg/Library: RISC-V PEI Service Table Pointer library Abner Chang
2022-01-08 4:10 ` [PATCH 09/79] ProcessorPkg/CpuDxe: Add RISC-V CPU DXE driver Abner Chang
2022-01-08 4:10 ` [PATCH 10/79] ProcessorPkg/SmbiosDxe: Generic SMBIOS DXE driver for RISC-V platforms Abner Chang
2022-01-08 4:10 ` [PATCH 11/79] ProcesorPkg/Library: NULL instance of RISC-V platform timer library Abner Chang
2022-01-08 4:10 ` [PATCH 12/79] RISC-V/ProcessorPkg: RISC-V package Abner Chang
2022-01-08 4:10 ` [PATCH 13/79] PlatformPkg/Library: RISC-V Platform Temporary Memory library Abner Chang
2022-01-08 4:10 ` [PATCH 14/79] PlatformPkg/Library: Add FirmwareContextProcessorSpecificLib module Abner Chang
2022-01-08 4:10 ` [PATCH 15/79] PlatformPkg/Library: NULL instance of RiscVOpensbiPlatformLib Abner Chang
2022-01-08 4:10 ` [PATCH 16/79] PlatformPkg/Library: NULL instance of PlatformMemoryTestLib Abner Chang
2022-01-08 4:10 ` [PATCH 17/79] PlatformPkg/Library: NULL instance of PlatformUpdateProgressLib Abner Chang
2022-01-08 4:10 ` [PATCH 18/79] PlatformPkg/Library: Platform Boot Manager library Abner Chang
2022-01-08 4:10 ` [PATCH 19/79] PlatformPkg/SecMain: RISC-V SecMain module Abner Chang
2022-01-08 4:10 ` [PATCH 20/79] PlatformPkg: Add RiscVPlatformPkg Abner Chang
2022-01-08 4:10 ` [PATCH 21/79] RISC-V/PlatformPkg: Revise Readme.md Abner Chang
2022-01-08 4:10 ` [PATCH 22/79] Silicon/SiFive: Handle case of NULL FirmwareContext Abner Chang
2022-01-08 4:10 ` [PATCH 23/79] Silicon/RISC-V: Update old SMBIOS struct filed name Abner Chang
2022-01-08 4:10 ` [PATCH 24/79] Platform/RISC-V: Consume MdeLibs.dsc.inc for RegisterFilterLib Abner Chang
2022-01-08 4:10 ` [PATCH 25/79] Silicon/RISC_V: " Abner Chang
2022-01-08 4:10 ` [PATCH 26/79] RISC-V/CpuDxe: Ignore set memory attributes failure Abner Chang
2022-01-08 4:10 ` [PATCH 27/79] Signal EndOfDxe in boot manager Abner Chang
2022-01-08 4:10 ` [PATCH 28/79] U5SeriesPkg: Deduplicate PlatformPei Abner Chang
2022-01-08 4:10 ` [PATCH 29/79] RISC-V: Split SMBIOS out of PlatformPei Abner Chang
2022-01-08 4:10 ` [PATCH 30/79] RISC-V: Use U5 SMBIOS library only for those platforms Abner Chang
2022-01-08 4:10 ` [PATCH 31/79] Silicon/RISC-V: Introduce FirmwareContext library Abner Chang
2022-01-08 4:10 ` [PATCH 32/79] Silicon/RISC-V: PeiServiceTableLib uses RiscVFirmwareContextLib Abner Chang
2022-01-08 4:10 ` [PATCH 33/79] RISC-V/PlatformPkg: Build DeviceTree and use that in SEC Abner Chang
2022-01-08 4:10 ` [PATCH 34/79] RISC-V/PlatformPkg: Add FdtPeim to pass DTB from PEI to DXE via HOB Abner Chang
2022-01-08 4:10 ` [PATCH 35/79] RISC-V/PlatformPkg: Fixup FDT from HOB and install into config table Abner Chang
2022-01-08 4:10 ` [PATCH 36/79] RISC-V: Switch to latest OpenSBI Abner Chang
2022-01-08 4:10 ` [PATCH 37/79] RISC-V: Implement ResetSystem RT call Abner Chang
2022-01-08 4:10 ` [PATCH 38/79] Move OpenSbiPlatformLib to RISC-V/PlatformPkg Abner Chang
2022-01-08 4:10 ` [PATCH 39/79] RISC-V/PlatformPkg: Update document Abner Chang
2022-01-08 4:11 ` [PATCH 40/79] RISC-V: Add RISC-V PeiCoreEntryPoint library Abner Chang
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