From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mx0b-002e3701.pphosted.com (mx0b-002e3701.pphosted.com [148.163.143.35]) by mx.groups.io with SMTP id smtpd.web11.2718.1641618774189414717 for ; Fri, 07 Jan 2022 21:12:54 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@hpe.com header.s=pps0720 header.b=lCmWqrXm; spf=permerror, err=parse error for token &{10 18 %{ir}.%{v}.%{d}.spf.has.pphosted.com}: invalid domain name (domain: hpe.com, ip: 148.163.143.35, mailfrom: prvs=000704d8ca=abner.chang@hpe.com) Received: from pps.filterd (m0150245.ppops.net [127.0.0.1]) by mx0b-002e3701.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 2084fiZ7020987 for ; Sat, 8 Jan 2022 05:12:53 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=hpe.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding; s=pps0720; bh=33EMiDzjrbXIVQnngEdvIQbFQrfX0xSpP25LW+M9yGs=; b=lCmWqrXmbqcmDw2UAy/2+KkA2WlIjK/Y1u+Ipt6Lrbg24ZeDIOq77RxcIVzB8T5MY4Wv LZur4af0B0WCVTH4FwEKQGNRuEEa/Yc7+xjnHmMwoGtv8KJ6D4R4xXKs0BV2a2uI9uCg mbLxPEVr46zjuVip8PFPBZVvwD//e0wyc4ogZgh4dHD94/f3HdT0Wk9qlbWSdh6DjCOT Ouz9BhQfh+TAUynuJwWsadAnUAMoCC4E9ECM9vVPkrB+UX5nhuG03EADRBxUSqmGhCsD 7fnt3HtgMXvolLKF/d1DUYi6HuYlsHekuNmmXbbd/AcSSkQ6HgJ8qzO0+LNcFyfEeVC/ PA== Received: from g2t2353.austin.hpe.com (g2t2353.austin.hpe.com [15.233.44.26]) by mx0b-002e3701.pphosted.com (PPS) with ESMTPS id 3df3tfg4ce-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Sat, 08 Jan 2022 05:12:53 +0000 Received: from g2t2360.austin.hpecorp.net (g2t2360.austin.hpecorp.net [16.196.225.135]) by g2t2353.austin.hpe.com (Postfix) with ESMTP id A162A82 for ; Sat, 8 Jan 2022 05:12:52 +0000 (UTC) Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.229]) by g2t2360.austin.hpecorp.net (Postfix) with ESMTP id E9B0C3D; Sat, 8 Jan 2022 05:12:51 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com Subject: [PATCH 31/79] Silicon/RISC-V: Introduce FirmwareContext library Date: Sat, 8 Jan 2022 12:10:51 +0800 Message-Id: <20220108041121.16005-30-abner.chang@hpe.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20220108041121.16005-1-abner.chang@hpe.com> References: <20220108041121.16005-1-abner.chang@hpe.com> MIME-Version: 1.0 X-Proofpoint-GUID: D7vDiSaZo2xmnNLtbM_kOF5dmm10I8Qa X-Proofpoint-ORIG-GUID: D7vDiSaZo2xmnNLtbM_kOF5dmm10I8Qa X-HPE-SCL: -1 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.790,Hydra:6.0.425,FMLib:17.11.62.513 definitions=2022-01-08_01,2022-01-07_01,2021-12-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 malwarescore=0 phishscore=0 spamscore=0 mlxscore=0 lowpriorityscore=0 impostorscore=0 mlxlogscore=999 adultscore=0 clxscore=1015 priorityscore=1501 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2110150000 definitions=main-2201080036 Content-Transfer-Encoding: quoted-printable (This is migrated from edk2-platforms:Silicon) Add RISC-V FirmwareContext library for different FirmwareContext implementations. This instance uses SBI firmware extension to get the pointer to FirmwareContext. Cc: Sunil V L Cc: Daniel Schaefer Reviewed-by: Abner Chang Reviewed-by: Daniel Schaefer Signed-off-by: Abner Chang --- .../RISC-V/ProcessorPkg/RiscVProcessorPkg.dec | 1 + .../RISC-V/ProcessorPkg/RiscVProcessorPkg.dsc | 4 +- .../RiscVFirmwareContextSbiLib.inf | 34 ++++++++++++ .../RiscVFirmwareContextSscratchLib.inf | 33 ++++++++++++ .../RiscVFirmwareContextStvecLib.inf | 34 ++++++++++++ .../Include/IndustryStandard/RiscV.h | 3 +- .../Include/Library/RiscVCpuLib.h | 14 ++++- .../Include/Library/RiscVFirmwareContextLib.h | 43 +++++++++++++++ .../RiscVFirmwareContextSbiLib.c | 52 +++++++++++++++++++ .../RiscVFirmwareContextSscratchLib.c | 48 +++++++++++++++++ .../RiscVFirmwareContextStvecLib.c | 48 +++++++++++++++++ .../ProcessorPkg/Library/RiscVCpuLib/Cpu.S | 34 +++++++++++- 12 files changed, 344 insertions(+), 4 deletions(-) create mode 100644 Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContex= tSbiLib/RiscVFirmwareContextSbiLib.inf create mode 100644 Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContex= tSscratchLib/RiscVFirmwareContextSscratchLib.inf create mode 100644 Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContex= tStvecLib/RiscVFirmwareContextStvecLib.inf create mode 100644 Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVFirmwa= reContextLib.h create mode 100644 Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContex= tSbiLib/RiscVFirmwareContextSbiLib.c create mode 100644 Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContex= tSscratchLib/RiscVFirmwareContextSscratchLib.c create mode 100644 Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContex= tStvecLib/RiscVFirmwareContextStvecLib.c diff --git a/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec b/Silicon/RI= SC-V/ProcessorPkg/RiscVProcessorPkg.dec index 0b64b33f0f..08279a97b1 100644 --- a/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec +++ b/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec @@ -24,6 +24,7 @@ RiscVPlatformDxeIplLib|Include/Library/RiscVPlatformDxeIpl.h=0D RiscVCpuLib|Include/Library/RiscVCpuLib.h=0D RiscVEdk2SbiLib|Include/Library/RiscVEdk2SbiLib.h=0D + RiscVFirmwareContextLib|Include/Library/RiscVFirmwareContextLib.h=0D =0D [Guids]=0D gUefiRiscVPkgTokenSpaceGuid =3D { 0x4261e9c8, 0x52c0, 0x4b34, { 0x85, 0= x3d, 0x48, 0x46, 0xea, 0xd3, 0xb7, 0x2c}}=0D diff --git a/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dsc b/Silicon/RI= SC-V/ProcessorPkg/RiscVProcessorPkg.dsc index 5c5cfcb525..1292ba1bea 100644 --- a/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dsc +++ b/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dsc @@ -65,13 +65,14 @@ UefiLib|MdePkg/Library/UefiLib/UefiLib.inf=0D DevicePathLib|MdePkg/Library/UefiDevicePathLibDevicePathProtocol/UefiDev= icePathLibDevicePathProtocol.inf=0D RiscVPlatformTimerLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVPlatformT= imerLibNull/RiscVPlatformTimerLib.inf=0D - PeiServicesTablePointerLib|Silicon/RISC-V/ProcessorPkg/Library/PeiServic= esTablePointerLibOpenSbi/PeiServicesTablePointerLibOpenSbi.inf=0D =0D [LibraryClasses.common.PEI_CORE]=0D PeiServicesTablePointerLib|Silicon/RISC-V/ProcessorPkg/Library/PeiServic= esTablePointerLibOpenSbi/PeiServicesTablePointerLibOpenSbi.inf=0D + RiscVFirmwareContextLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwar= eContextSbiLib/RiscVFirmwareContextSbiLib.inf=0D =0D [LibraryClasses.common.PEIM]=0D PeiServicesTablePointerLib|Silicon/RISC-V/ProcessorPkg/Library/PeiServic= esTablePointerLibOpenSbi/PeiServicesTablePointerLibOpenSbi.inf=0D + RiscVFirmwareContextLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwar= eContextSbiLib/RiscVFirmwareContextSbiLib.inf=0D HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf=0D MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAlloc= ationLib.inf=0D PeimEntryPoint|MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf=0D @@ -92,6 +93,7 @@ [Components]=0D Silicon/RISC-V/ProcessorPkg/Library/RiscVTimerLib/BaseRiscVTimerLib.inf= =0D Silicon/RISC-V/ProcessorPkg/Library/RiscVExceptionLib/CpuExceptionHandle= rDxeLib.inf=0D + Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSbiLib/RiscVFirm= wareContextSbiLib.inf=0D Silicon/RISC-V/ProcessorPkg/Library/PeiServicesTablePointerLibOpenSbi/Pe= iServicesTablePointerLibOpenSbi.inf=0D Silicon/RISC-V/ProcessorPkg/Library/RiscVOpensbiLib/RiscVOpensbiLib.inf= =0D Silicon/RISC-V/ProcessorPkg/Library/RiscVPlatformTimerLibNull/RiscVPlatf= ormTimerLib.inf=0D diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSbiLib= /RiscVFirmwareContextSbiLib.inf b/Silicon/RISC-V/ProcessorPkg/Library/RiscV= FirmwareContextSbiLib/RiscVFirmwareContextSbiLib.inf new file mode 100644 index 0000000000..168b705453 --- /dev/null +++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSbiLib/RiscVF= irmwareContextSbiLib.inf @@ -0,0 +1,34 @@ +## @file=0D +# Instance of OpebSBI Firmware Conext Library=0D +#=0D +# This iinstance uses RISC-V OpenSBI Firmware Extension SBI.=0D +#=0D +# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
=0D +#=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +##=0D +=0D +[Defines]=0D + INF_VERSION =3D 0x0001001b=0D + BASE_NAME =3D RiscVFirmwareContextSbiLib=0D + FILE_GUID =3D 3709E048-6794-427A-B728-BFE3FFD6D461= =0D + MODULE_TYPE =3D PEIM=0D + VERSION_STRING =3D 1.0=0D + LIBRARY_CLASS =3D RiscVFirmwareContextLib|PEIM PEI_CORE= =0D +=0D +#=0D +# VALID_ARCHITECTURES =3D RISCV64=0D +#=0D +[Sources]=0D + RiscVFirmwareContextSbiLib.c=0D +=0D +[Packages]=0D + MdePkg/MdePkg.dec=0D + Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec=0D +=0D +[LibraryClasses]=0D + DebugLib=0D + RiscVCpuLib=0D + RiscVEdk2SbiLib=0D +=0D diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSscrat= chLib/RiscVFirmwareContextSscratchLib.inf b/Silicon/RISC-V/ProcessorPkg/Lib= rary/RiscVFirmwareContextSscratchLib/RiscVFirmwareContextSscratchLib.inf new file mode 100644 index 0000000000..750c1cf51f --- /dev/null +++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSscratchLib/R= iscVFirmwareContextSscratchLib.inf @@ -0,0 +1,33 @@ +## @file=0D +# Instance of OpebSBI Firmware Conext Library=0D +#=0D +# This instance uses RISC-V Supervisor mode SCRATCH CSR=0D +#=0D +# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
=0D +#=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +##=0D +=0D +[Defines]=0D + INF_VERSION =3D 0x0001001b=0D + BASE_NAME =3D RiscVFirmwareContextSscratchLib=0D + FILE_GUID =3D 3709E048-6794-427A-B728-BFE3FFD6D461= =0D + MODULE_TYPE =3D PEIM=0D + VERSION_STRING =3D 1.0=0D + LIBRARY_CLASS =3D RiscVFirmwareContextLib|PEIM PEI_CORE= =0D +=0D +#=0D +# VALID_ARCHITECTURES =3D RISCV64=0D +#=0D +[Sources]=0D + RiscVFirmwareContextSscratchLib.c=0D +=0D +[Packages]=0D + MdePkg/MdePkg.dec=0D + Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec=0D +=0D +[LibraryClasses]=0D + DebugLib=0D + RiscVCpuLib=0D +=0D diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextStvecL= ib/RiscVFirmwareContextStvecLib.inf b/Silicon/RISC-V/ProcessorPkg/Library/R= iscVFirmwareContextStvecLib/RiscVFirmwareContextStvecLib.inf new file mode 100644 index 0000000000..fa894cda91 --- /dev/null +++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextStvecLib/Risc= VFirmwareContextStvecLib.inf @@ -0,0 +1,34 @@ +## @file=0D +# Instance of OpebSBI Firmware Conext Library=0D +#=0D +# This iinstance Supervisor mode STVEC CSR=0D +#=0D +# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
=0D +#=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +##=0D +=0D +[Defines]=0D + INF_VERSION =3D 0x0001001b=0D + BASE_NAME =3D RiscVFirmwareContextStvecLib=0D + FILE_GUID =3D 42DCFFAC-1DBD-4264-80A3-85CC7167AC82= =0D + MODULE_TYPE =3D PEIM=0D + VERSION_STRING =3D 1.0=0D + LIBRARY_CLASS =3D RiscVFirmwareContextLib|PEIM PEI_CORE= =0D +=0D +#=0D +# VALID_ARCHITECTURES =3D RISCV64=0D +#=0D +[Sources]=0D + RiscVFirmwareContextStvecLib.c=0D +=0D +[Packages]=0D + MdePkg/MdePkg.dec=0D + Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec=0D +=0D +[LibraryClasses]=0D + DebugLib=0D + RiscVCpuLib=0D +=0D +=0D diff --git a/Silicon/RISC-V/ProcessorPkg/Include/IndustryStandard/RiscV.h b= /Silicon/RISC-V/ProcessorPkg/Include/IndustryStandard/RiscV.h index 2a992394ed..f6726bda24 100644 --- a/Silicon/RISC-V/ProcessorPkg/Include/IndustryStandard/RiscV.h +++ b/Silicon/RISC-V/ProcessorPkg/Include/IndustryStandard/RiscV.h @@ -1,7 +1,7 @@ /** @file=0D RISC-V package definitions.=0D =0D - Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All right= s reserved.
=0D + Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All right= s reserved.
=0D =0D SPDX-License-Identifier: BSD-2-Clause-Patent=0D =0D @@ -96,6 +96,7 @@ #define SSTATUS_SIE_BIT_POSITION 1=0D #define SSTATUS_SPP_BIT_POSITION 8=0D #define RISCV_CSR_SUPERVISOR_SIE 0x104=0D +#define RISCV_CSR_SUPERVISOR_STVEC 0x105=0D #define RISCV_CSR_SUPERVISOR_SSCRATCH 0x140=0D #define RISCV_CSR_SUPERVISOR_SEPC 0x141=0D #define RISCV_CSR_SUPERVISOR_SCAUSE 0x142=0D diff --git a/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVCpuLib.h b/Si= licon/RISC-V/ProcessorPkg/Include/Library/RiscVCpuLib.h index f37d4c20d0..f70723567e 100644 --- a/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVCpuLib.h +++ b/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVCpuLib.h @@ -1,7 +1,7 @@ /** @file=0D RISC-V CPU library definitions.=0D =0D - Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. Al= l rights reserved.
=0D + Copyright (c) 2016 - 2021, Hewlett Packard Enterprise Development LP. Al= l rights reserved.
=0D =0D SPDX-License-Identifier: BSD-2-Clause-Patent=0D **/=0D @@ -68,4 +68,16 @@ RiscVReadMachineImplementId (VOID); VOID=0D RiscVSetSupervisorAddressTranslationRegister(UINT64);=0D =0D +VOID=0D +RiscVSetSupervisorScratch (UINT64);=0D +=0D +UINT64=0D +RiscVGetSupervisorScratch (VOID);=0D +=0D +VOID=0D +RiscVSetSupervisorStvec (UINT64);=0D +=0D +UINT64=0D +RiscVGetSupervisorStvec (VOID);=0D +=0D #endif=0D diff --git a/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVFirmwareConte= xtLib.h b/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVFirmwareContextL= ib.h new file mode 100644 index 0000000000..f35c4e0c51 --- /dev/null +++ b/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVFirmwareContextLib.h @@ -0,0 +1,43 @@ +/** @file=0D + Library to get/set Firmware Context.=0D +=0D + Copyright (c) 2021, Hewlett Packard Development LP. All rights reserved.=
=0D +=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +=0D +#ifndef RISCV_FIRMWARE_CONTEXT_LIB_H_=0D +#define RISCV_FIRMWARE_CONTEXT_LIB_H_=0D +=0D +#include =0D +#include =0D +=0D +/**=0D + Get pointer to OpenSBI Firmware Context=0D +=0D + Get the pointer of firmware context.=0D +=0D + @param FirmwareContextPtr Pointer to retrieve pointer to the=0D + Firmware Context.=0D +**/=0D +VOID=0D +EFIAPI=0D +GetFirmwareContextPointer (=0D + IN OUT EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT **FirmwareContextPtr=0D + );=0D +=0D +/**=0D + Set pointer to OpenSBI Firmware Context=0D +=0D + Set the pointer of firmware context.=0D +=0D + @param FirmwareContextPtr Pointer to Firmware Context.=0D +**/=0D +VOID=0D +EFIAPI=0D +SetFirmwareContextPointer (=0D + IN EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *FirmwareContextPtr=0D + );=0D +=0D +#endif=0D diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSbiLib= /RiscVFirmwareContextSbiLib.c b/Silicon/RISC-V/ProcessorPkg/Library/RiscVFi= rmwareContextSbiLib/RiscVFirmwareContextSbiLib.c new file mode 100644 index 0000000000..6125618eaf --- /dev/null +++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSbiLib/RiscVF= irmwareContextSbiLib.c @@ -0,0 +1,52 @@ +/** @file=0D + This iinstance uses RISC-V OpenSBI Firmware Extension SBI to=0D + get the pointer of firmware context.=0D +=0D + Copyright (c) 2021 Hewlett Packard Enterprise Development LP. All rights= reserved.
=0D +=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +=0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +=0D +/**=0D + Get pointer to OpenSBI Firmware Context=0D +=0D + Get the pointer of firmware context through OpenSBI FW Extension SBI.=0D +=0D + @param FirmwareContextPtr Pointer to retrieve pointer to the=0D + Firmware Context.=0D +**/=0D +VOID=0D +EFIAPI=0D +GetFirmwareContextPointer (=0D + IN OUT EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT **FirmwareContextPtr=0D + )=0D +{=0D + SbiGetFirmwareContext (FirmwareContextPtr);=0D +}=0D +=0D +/**=0D + Set the pointer to OpenSBI Firmware Context=0D +=0D + Set the pointer of firmware context through OpenSBI FW Extension SBI.=0D +=0D + @param FirmwareContextPtr Pointer to Firmware Context.=0D +**/=0D +VOID=0D +EFIAPI=0D +SetFirmwareContextPointer (=0D + IN EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *FirmwareContextPtr=0D + )=0D +{=0D + //=0D + // We don't have to set firmware context pointer using=0D + // OpenSBI FW Extension SBI.=0D + //=0D +}=0D +=0D diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSscrat= chLib/RiscVFirmwareContextSscratchLib.c b/Silicon/RISC-V/ProcessorPkg/Libra= ry/RiscVFirmwareContextSscratchLib/RiscVFirmwareContextSscratchLib.c new file mode 100644 index 0000000000..2504e17132 --- /dev/null +++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSscratchLib/R= iscVFirmwareContextSscratchLib.c @@ -0,0 +1,48 @@ +/** @file=0D + This instance uses Supervisor mode SCRATCH CSR to get/set the=0D + pointer of firmware context.=0D +=0D + Copyright (c) 2021 Hewlett Packard Enterprise Development LP. All rights= reserved.
=0D +=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +=0D +#include =0D +=0D +#include =0D +=0D +#include =0D +#include =0D +=0D +/**=0D + Get pointer to OpenSBI Firmware Context=0D +=0D + Get the pointer of firmware context through Supervisor mode SCRATCH CSR.= =0D +=0D + @param FirmwareContextPtr Pointer to retrieve pointer to the=0D + Firmware Context.=0D +**/=0D +VOID=0D +EFIAPI=0D +GetFirmwareContextPointer (=0D + IN OUT EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT **FirmwareContextPtr=0D + )=0D +{=0D + *FirmwareContextPtr =3D (EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *)RiscVGetSu= pervisorScratch ();=0D +}=0D +=0D +/**=0D + Set the pointer to OpenSBI Firmware Context=0D +=0D + Set the pointer of firmware context through Supervisor mode SCRATCH CSR.= =0D +=0D + @param FirmwareContextPtr Pointer to Firmware Context.=0D +**/=0D +VOID=0D +EFIAPI=0D +SetFirmwareContextPointer (=0D + IN EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *FirmwareContextPtr=0D + )=0D +{=0D + RiscVSetSupervisorScratch ((UINT64)FirmwareContextPtr);=0D +}=0D diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextStvecL= ib/RiscVFirmwareContextStvecLib.c b/Silicon/RISC-V/ProcessorPkg/Library/Ris= cVFirmwareContextStvecLib/RiscVFirmwareContextStvecLib.c new file mode 100644 index 0000000000..7d1675355a --- /dev/null +++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextStvecLib/Risc= VFirmwareContextStvecLib.c @@ -0,0 +1,48 @@ +/** @file=0D + This instance uses This iinstance Supervisor mode STVEC CSR to=0D + get/set the pointer of firmware context.=0D +=0D + Copyright (c) 2021 Hewlett Packard Enterprise Development LP. All rights= reserved.
=0D +=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +=0D +#include =0D +=0D +#include =0D +=0D +#include =0D +#include =0D +=0D +/**=0D + Get pointer to OpenSBI Firmware Context=0D +=0D + Get the pointer of firmware context through Supervisor mode STVEC CSR.=0D +=0D + @param FirmwareContextPtr Pointer to retrieve pointer to the=0D + Firmware Context.=0D +**/=0D +VOID=0D +EFIAPI=0D +GetFirmwareContextPointer (=0D + IN OUT EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT **FirmwareContextPtr=0D + )=0D +{=0D + *FirmwareContextPtr =3D (EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *)RiscVGetSu= pervisorStvec ();=0D +}=0D +=0D +/**=0D + Set pointer to OpenSBI Firmware Context=0D +=0D + Set the pointer of firmware context through Supervisor mode STVEC CSR=0D +=0D + @param FirmwareContextPtr Pointer to Firmware Context.=0D +**/=0D +VOID=0D +EFIAPI=0D +SetFirmwareContextPointer (=0D + IN EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *FirmwareContextPtr=0D + )=0D +{=0D + RiscVSetSupervisorStvec ((UINT64)FirmwareContextPtr);=0D +}=0D diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVCpuLib/Cpu.S b/Silico= n/RISC-V/ProcessorPkg/Library/RiscVCpuLib/Cpu.S index 06ba80cb5f..e242c9b866 100644 --- a/Silicon/RISC-V/ProcessorPkg/Library/RiscVCpuLib/Cpu.S +++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVCpuLib/Cpu.S @@ -2,7 +2,7 @@ //=0D // RISC-V CPU functions.=0D //=0D -// Copyright (c) 2016 - 2020, Hewlett Packard Enterprise Development LP. A= ll rights reserved.
=0D +// Copyright (c) 2016 - 2021, Hewlett Packard Enterprise Development LP. A= ll rights reserved.
=0D //=0D // SPDX-License-Identifier: BSD-2-Clause-Patent=0D //=0D @@ -101,6 +101,38 @@ ASM_FUNC (RiscVReadMachineImplementId) csrr a0, RISCV_CSR_MACHINE_MIMPID=0D ret=0D =0D +//=0D +// Set Supervisor mode scratch.=0D +// @param a0 : Value set to Supervisor mode scratch=0D +//=0D +ASM_FUNC (RiscVSetSupervisorScratch)=0D + csrrw a1, RISCV_CSR_SUPERVISOR_SSCRATCH, a0=0D + ret=0D +=0D +//=0D +// Get Supervisor mode scratch.=0D +// @retval a0 : Value in Supervisor mode scratch=0D +//=0D +ASM_FUNC (RiscVGetSupervisorScratch)=0D + csrr a0, RISCV_CSR_SUPERVISOR_SSCRATCH=0D + ret=0D +=0D +//=0D +// Set Supervisor mode trap vector.=0D +// @param a0 : Value set to Supervisor mode trap vector=0D +//=0D +ASM_FUNC (RiscVSetSupervisorStvec)=0D + csrrw a1, RISCV_CSR_SUPERVISOR_STVEC, a0=0D + ret=0D +=0D +//=0D +// Get Supervisor mode scratch.=0D +// @retval a0 : Value in Supervisor mode trap vector=0D +//=0D +ASM_FUNC (RiscVGetSupervisorStvec)=0D + csrr a0, RISCV_CSR_SUPERVISOR_STVEC=0D + ret=0D +=0D //=0D // Set Supervisor Address Translation and=0D // Protection Register.=0D --=20 2.31.1