From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mx0a-002e3701.pphosted.com (mx0a-002e3701.pphosted.com [148.163.147.86]) by mx.groups.io with SMTP id smtpd.web10.2667.1641618776762725565 for ; Fri, 07 Jan 2022 21:12:56 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@hpe.com header.s=pps0720 header.b=eFM83CbN; spf=permerror, err=parse error for token &{10 18 %{ir}.%{v}.%{d}.spf.has.pphosted.com}: invalid domain name (domain: hpe.com, ip: 148.163.147.86, mailfrom: prvs=000704d8ca=abner.chang@hpe.com) Received: from pps.filterd (m0148663.ppops.net [127.0.0.1]) by mx0a-002e3701.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 2083Xatf021070 for ; Sat, 8 Jan 2022 05:12:55 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=hpe.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding; s=pps0720; bh=Yi/33VJe1vqKx0nX2r9wZCHJgVag6kXFFfBXhQlBz+w=; b=eFM83CbNpRfQC/YE4/4tX1uKXalDEEyxcx+CUYppCaMDgnVkvnSFEX+oAO9oyPyPzUjf h/aoLEFAiWE0sNNGZd4bQA9ygAGqrkb52fnZ9ppSXYW/sn7c79uFlDA1B7jvWN54RBO7 tgCL5NoFRGmVl1MFmjx+FzF3cF4Lh/Ow2RY2PN5BNY43oNKEbAy6Q6T8zhR2yDLOmZ6r wPfblB7wKpev/euXgpSLkDbSoGjgIVAtvaBZ/DCCAGnSyXOf0hn1+VQe7d3DjumcTOwH +8yqAewc1zGS9JlUlIr63+oPjxY7JVOQ+jlQMQ+coeti7Fd46Tafjrf6ZzWM8rXGKeNI ng== Received: from g2t2354.austin.hpe.com (g2t2354.austin.hpe.com [15.233.44.27]) by mx0a-002e3701.pphosted.com (PPS) with ESMTPS id 3df2tk0bgb-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Sat, 08 Jan 2022 05:12:55 +0000 Received: from g2t2360.austin.hpecorp.net (g2t2360.austin.hpecorp.net [16.196.225.135]) by g2t2354.austin.hpe.com (Postfix) with ESMTP id B676D81 for ; Sat, 8 Jan 2022 05:12:54 +0000 (UTC) Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.229]) by g2t2360.austin.hpecorp.net (Postfix) with ESMTP id 0B73439; Sat, 8 Jan 2022 05:12:53 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com Subject: [PATCH 33/79] RISC-V/PlatformPkg: Build DeviceTree and use that in SEC Date: Sat, 8 Jan 2022 12:10:53 +0800 Message-Id: <20220108041121.16005-32-abner.chang@hpe.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20220108041121.16005-1-abner.chang@hpe.com> References: <20220108041121.16005-1-abner.chang@hpe.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: FKA-ZgsDuRYkzIpyqJZIpVptrVf2Zk3t X-Proofpoint-GUID: FKA-ZgsDuRYkzIpyqJZIpVptrVf2Zk3t X-HPE-SCL: -1 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.790,Hydra:6.0.425,FMLib:17.11.62.513 definitions=2022-01-08_01,2022-01-07_01,2021-12-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=999 spamscore=0 mlxscore=0 lowpriorityscore=0 clxscore=1015 malwarescore=0 priorityscore=1501 suspectscore=0 impostorscore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2110150000 definitions=main-2201080036 Content-Transfer-Encoding: quoted-printable From: Daniel Schaefer (This is migrated from edk2-platforms) OpenSBI uses the device tree for platform specific initialization, so we need to have it already in SEC. Cc: Daniel Schaefer Cc: Abner Chang Cc: Sunil V L Reviewed-by: Abner Chang Signed-off-by: Daniel Schaefer --- .../RISC-V/PlatformPkg/RiscVPlatformPkg.dec | 4 ++ .../PlatformPkg/Universal/Sec/SecMain.inf | 2 + .../Include/IndustryStandard/RiscVOpensbi.h | 1 + .../PlatformPkg/Universal/Sec/SecMain.c | 49 +++++++++++++++++++ .../Universal/Sec/Riscv64/SecEntry.S | 22 --------- 5 files changed, 56 insertions(+), 22 deletions(-) diff --git a/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec b/Platform/RI= SC-V/PlatformPkg/RiscVPlatformPkg.dec index 48aeb97431..ad15a155fe 100644 --- a/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec +++ b/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec @@ -31,6 +31,8 @@ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVPeiFvSize|0x0|UINT32|0x00001= 003=0D gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVDxeFvBase|0x0|UINT32|0x00001= 004=0D gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVDxeFvSize|0x0|UINT32|0x00001= 005=0D + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVDtbFvBase|0x0|UINT32|0x00001= 016=0D + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVDtbFvSize|0x0|UINT32|0x00001= 017=0D =0D #=0D # Definition of EFI Variable region=0D @@ -66,6 +68,8 @@ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdTemporaryRamSize|0|UINT32|0x00001= 104=0D gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPeiCorePrivilegeMode|0|UINT32|0x0= 0001105=0D =0D + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdDeviceTreeAddress|0|UINT32|0x0000= 1106=0D +=0D [PcdsPatchableInModule]=0D =0D [PcdsFeatureFlag]=0D diff --git a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf b/Platfo= rm/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf index 89bcb039a6..78bd75e3ac 100644 --- a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf +++ b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf @@ -57,6 +57,8 @@ [FixedPcd]=0D gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVPeiFvBase=0D gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVPeiFvSize=0D + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVDtbFvBase=0D + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdDeviceTreeAddress=0D =0D [Pcd]=0D gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootHartId=0D diff --git a/Silicon/RISC-V/ProcessorPkg/Include/IndustryStandard/RiscVOpen= sbi.h b/Silicon/RISC-V/ProcessorPkg/Include/IndustryStandard/RiscVOpensbi.h index 2dab696af8..e7ac6d26ee 100644 --- a/Silicon/RISC-V/ProcessorPkg/Include/IndustryStandard/RiscVOpensbi.h +++ b/Silicon/RISC-V/ProcessorPkg/Include/IndustryStandard/RiscVOpensbi.h @@ -47,6 +47,7 @@ typedef struct { =0D typedef struct {=0D VOID *PeiServiceTable; // PEI Service table=0D + UINT64 FlattenedDeviceTree; // Pointer to Flattened Device t= ree=0D EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC *HartSpecific[RISC_V_MAX_HART_= SUPPORTED];=0D } EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT;=0D =0D diff --git a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c b/Platform= /RISC-V/PlatformPkg/Universal/Sec/SecMain.c index fa9ecd789a..0af0b4bac8 100644 --- a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c +++ b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c @@ -557,6 +557,12 @@ VOID EFIAPI PeiCore ( &FirmwareContext=0D ));=0D ThisSbiPlatform->firmware_context =3D (unsigned long)&FirmwareContext;=0D +=0D + //=0D + // Save Flattened Device tree in firmware context=0D + //=0D + FirmwareContext.FlattenedDeviceTree =3D FuncArg1;=0D +=0D //=0D // Set firmware context Hart-specific pointer=0D //=0D @@ -647,6 +653,42 @@ RiscVOpenSbiHartSwitchMode ( sbi_hart_switch_mode(FuncArg0, FuncArg1, NextAddr, NextMode, NextVirt);= =0D }=0D =0D +/**=0D + Get device tree address=0D +=0D + @retval The address of Device Tree binary.=0D +**/=0D +VOID *=0D +EFIAPI=0D +GetDeviceTreeAddress (=0D + VOID=0D + )=0D +{=0D + EFI_STATUS Status;=0D + EFI_COMMON_SECTION_HEADER *FoundSection;=0D +=0D + if (FixedPcdGet32 (PcdDeviceTreeAddress)) {=0D + return (VOID *)*((unsigned long *)FixedPcdGet32 (PcdDeviceTreeAddres= s));=0D + } else if (FixedPcdGet32 (PcdRiscVDtbFvBase)) {=0D + Status =3D FindFfsFileAndSection (=0D + (EFI_FIRMWARE_VOLUME_HEADER *)FixedPcdGet32 (PcdRiscVDtbF= vBase),=0D + EFI_FV_FILETYPE_FREEFORM,=0D + EFI_SECTION_RAW,=0D + &FoundSection=0D + );=0D + if (EFI_ERROR(Status)) {=0D + DEBUG ((DEBUG_ERROR, "Platform Device Tree is not found from FV.\n= "));=0D + return NULL;=0D + }=0D + FoundSection ++;=0D + return (VOID *)FoundSection;=0D + } else {=0D + DEBUG ((DEBUG_ERROR, "Must use DTB either from memory or compiled in= FW. PCDs configured incorrectly.\n"));=0D + ASSERT (FALSE);=0D + }=0D + return NULL;=0D +}=0D +=0D /**=0D This function initilizes hart specific information and SBI.=0D For the boot hart, it boots system through PEI core and initial SBI in t= he DXE IPL.=0D @@ -686,6 +728,13 @@ VOID EFIAPI SecCoreStartUpWithStack( UINT64 NonBootHartMessageLockValue;=0D EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC *HartFirmwareContext;=0D =0D + Scratch->next_arg1 =3D (unsigned long)GetDeviceTreeAddress ();=0D + if (Scratch->next_arg1 =3D=3D (unsigned long)NULL) {=0D + DEBUG ((DEBUG_ERROR, "Platform Device Tree is not found\n"));=0D + ASSERT (FALSE);=0D + }=0D + DEBUG ((DEBUG_INFO, "DTB address: 0x%08x\n", Scratch->next_arg1));=0D +=0D //=0D // Setup EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC for each hart.=0D //=0D diff --git a/Platform/RISC-V/PlatformPkg/Universal/Sec/Riscv64/SecEntry.S b= /Platform/RISC-V/PlatformPkg/Universal/Sec/Riscv64/SecEntry.S index 6b2cdb6c17..d3d589aefc 100644 --- a/Platform/RISC-V/PlatformPkg/Universal/Sec/Riscv64/SecEntry.S +++ b/Platform/RISC-V/PlatformPkg/Universal/Sec/Riscv64/SecEntry.S @@ -75,11 +75,6 @@ _scratch_init: sd a4, SBI_SCRATCH_FW_START_OFFSET(tp)=0D sd a5, SBI_SCRATCH_FW_SIZE_OFFSET(tp)=0D =0D - /*=0D - * Note: fw_next_arg1() uses a0, a1, and ra=0D - */=0D - call fw_next_arg1=0D - sd a0, SBI_SCRATCH_NEXT_ARG1_OFFSET(tp) /* Save agr1 in scratch buffe= r*/=0D /*=0D Note: fw_next_addr()uses a0, a1, and ra=0D */=0D @@ -500,23 +495,6 @@ _reset_regs: csrw CSR_MSCRATCH, 0=0D ret=0D =0D - .align 3=0D - .section .entry, "ax", %progbits=0D - .global fw_prev_arg1=0D -fw_prev_arg1:=0D -=0D - /* We return previous arg1 in 'a0' */=0D - add a0, zero, zero=0D - ret=0D -=0D - .align 3=0D - .section .entry, "ax", %progbits=0D - .global fw_next_arg1=0D -fw_next_arg1:=0D - /* We return next arg1 in 'a0' */=0D - li a0, FixedPcdGet32(PcdRiscVPeiFvBase)=0D - ret=0D -=0D .align 3=0D .section .entry, "ax", %progbits=0D .global fw_next_addr=0D --=20 2.31.1