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Sat, 08 Jan 2022 05:12:58 +0000 Received: from g2t2360.austin.hpecorp.net (g2t2360.austin.hpecorp.net [16.196.225.135]) by g2t2354.austin.hpe.com (Postfix) with ESMTP id D34D581 for ; Sat, 8 Jan 2022 05:12:57 +0000 (UTC) Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.229]) by g2t2360.austin.hpecorp.net (Postfix) with ESMTP id 2832137; Sat, 8 Jan 2022 05:12:56 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com Subject: [PATCH 36/79] RISC-V: Switch to latest OpenSBI Date: Sat, 8 Jan 2022 12:10:56 +0800 Message-Id: <20220108041121.16005-35-abner.chang@hpe.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20220108041121.16005-1-abner.chang@hpe.com> References: <20220108041121.16005-1-abner.chang@hpe.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: vnlVlLDB-gtAgII0srzahzJGZdjT9T3w X-Proofpoint-GUID: vnlVlLDB-gtAgII0srzahzJGZdjT9T3w X-HPE-SCL: -1 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.790,Hydra:6.0.425,FMLib:17.11.62.513 definitions=2022-01-08_01,2022-01-07_01,2021-12-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 adultscore=0 priorityscore=1501 malwarescore=0 spamscore=0 clxscore=1015 phishscore=0 impostorscore=0 mlxscore=0 mlxlogscore=999 bulkscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2110150000 definitions=main-2201080036 Content-Transfer-Encoding: quoted-printable (This is migrated from edk2-platforms) Cc: Daniel Schaefer Cc: Abner Chang Cc: Sunil V L Reviewed-by: Abner Chang Signed-off-by: Daniel Schaefer --- .../RiscVOpensbiLib/RiscVOpensbiLib.inf | 13 ++++++--- .../Include/Library/RiscVEdk2SbiLib.h | 1 + .../ProcessorPkg/Include/OpensbiTypes.h | 1 + .../Library/OpensbiPlatformLibNull/Platform.c | 27 ++++++++++++------- .../PlatformPkg/Universal/Sec/SecMain.c | 5 ++-- .../Universal/Sec/Riscv64/SecEntry.S | 2 ++ 6 files changed, 34 insertions(+), 15 deletions(-) diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVOpensbiLib/RiscVOpens= biLib.inf b/Silicon/RISC-V/ProcessorPkg/Library/RiscVOpensbiLib/RiscVOpensb= iLib.inf index 71cc76444e..e40a797896 100644 --- a/Silicon/RISC-V/ProcessorPkg/Library/RiscVOpensbiLib/RiscVOpensbiLib.i= nf +++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVOpensbiLib/RiscVOpensbiLib.i= nf @@ -23,6 +23,7 @@ opensbi/lib/sbi/sbi_bitmap.c=0D opensbi/lib/sbi/sbi_bitops.c=0D opensbi/lib/sbi/sbi_console.c=0D + opensbi/lib/sbi/sbi_domain.c=0D opensbi/lib/sbi/sbi_ecall.c=0D opensbi/lib/sbi/sbi_ecall_base.c=0D opensbi/lib/sbi/sbi_ecall_hsm.c=0D @@ -51,27 +52,33 @@ =0D opensbi/lib/utils/fdt/fdt_helper.c=0D opensbi/lib/utils/fdt/fdt_fixup.c=0D + opensbi/lib/utils/fdt/fdt_domain.c=0D opensbi/lib/utils/ipi/fdt_ipi.c=0D - opensbi/lib/utils/ipi/fdt_ipi_clint.c=0D + opensbi/lib/utils/ipi/aclint_mswi.c=0D + opensbi/lib/utils/ipi/fdt_ipi_mswi.c=0D opensbi/lib/utils/irqchip/fdt_irqchip.c=0D opensbi/lib/utils/irqchip/fdt_irqchip_plic.c=0D opensbi/lib/utils/irqchip/plic.c=0D opensbi/lib/utils/reset/fdt_reset.c=0D opensbi/lib/utils/reset/fdt_reset_htif.c=0D opensbi/lib/utils/reset/fdt_reset_sifive.c=0D + opensbi/lib/utils/reset/fdt_reset_thead.c=0D + opensbi/lib/utils/reset/fdt_reset_thead_asm.S=0D opensbi/lib/utils/serial/fdt_serial.c=0D opensbi/lib/utils/serial/fdt_serial_htif.c=0D opensbi/lib/utils/serial/fdt_serial_shakti.c=0D opensbi/lib/utils/serial/fdt_serial_sifive.c=0D opensbi/lib/utils/serial/fdt_serial_uart8250.c=0D + opensbi/lib/utils/serial/fdt_serial_gaisler.c=0D + opensbi/lib/utils/serial/gaisler-uart.c=0D opensbi/lib/utils/serial/shakti-uart.c=0D opensbi/lib/utils/serial/sifive-uart.c=0D opensbi/lib/utils/serial/uart8250.c=0D - opensbi/lib/utils/sys/clint.c=0D opensbi/lib/utils/sys/htif.c=0D opensbi/lib/utils/sys/sifive_test.c=0D opensbi/lib/utils/timer/fdt_timer.c=0D - opensbi/lib/utils/timer/fdt_timer_clint.c=0D + opensbi/lib/utils/timer/aclint_mtimer.c=0D + opensbi/lib/utils/timer/fdt_timer_mtimer.c=0D =0D [Packages]=0D EmbeddedPkg/EmbeddedPkg.dec # For libfdt.=0D diff --git a/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVEdk2SbiLib.h = b/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVEdk2SbiLib.h index f81ea06b05..66a87cb8c3 100644 --- a/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVEdk2SbiLib.h +++ b/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVEdk2SbiLib.h @@ -16,6 +16,7 @@ #include =0D #include =0D #include =0D +#include =0D =0D //=0D // EDK2 OpenSBI Firmware extension.=0D diff --git a/Silicon/RISC-V/ProcessorPkg/Include/OpensbiTypes.h b/Silicon/R= ISC-V/ProcessorPkg/Include/OpensbiTypes.h index 37e407908a..8a6ea97708 100644 --- a/Silicon/RISC-V/ProcessorPkg/Include/OpensbiTypes.h +++ b/Silicon/RISC-V/ProcessorPkg/Include/OpensbiTypes.h @@ -49,6 +49,7 @@ typedef UINT64 physical_size_t; =0D #define __packed __attribute__((packed))=0D #define __noreturn __attribute__((noreturn))=0D +#define __aligned(x) __attribute__((aligned(x)))=0D =0D #if defined(__GNUC__) || defined(__clang__)=0D #define likely(x) __builtin_expect((x), 1)=0D diff --git a/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLibNull/Pla= tform.c b/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLibNull/Platfo= rm.c index e78d811f4c..b7e39d19c1 100644 --- a/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLibNull/Platform.c +++ b/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLibNull/Platform.c @@ -14,31 +14,38 @@ #include =0D =0D const struct sbi_platform_operations platform_ops =3D {=0D - .pmp_region_count =3D NULL,=0D - .pmp_region_info =3D NULL,=0D + .early_init =3D NULL,=0D .final_init =3D NULL,=0D + .early_exit =3D NULL,=0D + .final_exit =3D NULL,=0D + .domains_root_regions =3D NULL,=0D + .domains_init =3D NULL,=0D .console_putc =3D NULL,=0D .console_getc =3D NULL,=0D .console_init =3D NULL,=0D .irqchip_init =3D NULL,=0D + .irqchip_exit =3D NULL,=0D .ipi_send =3D NULL,=0D .ipi_clear =3D NULL,=0D .ipi_init =3D NULL,=0D + .ipi_exit =3D NULL,=0D + .get_tlbr_flush_limit =3D NULL,=0D .timer_value =3D NULL,=0D .timer_event_stop =3D NULL,=0D .timer_event_start =3D NULL,=0D .timer_init =3D NULL,=0D - .system_reboot =3D NULL,=0D - .system_shutdown =3D NULL=0D + .timer_exit =3D NULL,=0D + .system_reset_check =3D NULL,=0D + .system_reset =3D NULL,=0D };=0D =0D -const struct sbi_platform platform =3D {=0D - .opensbi_version =3D OPENSBI_VERSION, // The O= penSBI version this platform table is built bassed on.=0D - .platform_version =3D SBI_PLATFORM_VERSION(0x0000, 0x0000), // SBI P= latform version 1.0=0D - .name =3D "NULL platform",=0D +struct sbi_platform platform =3D {=0D + .opensbi_version =3D OPENSBI_VERSION,=0D + .platform_version =3D SBI_PLATFORM_VERSION(0x0, 0x01),=0D + .name =3D "NULL Platform",=0D .features =3D 0,=0D .hart_count =3D 0,=0D + .hart_index2id =3D 0,=0D .hart_stack_size =3D 0,=0D - .disabled_hart_mask =3D 0,=0D - .platform_ops_addr =3D 0=0D + .platform_ops_addr =3D 0,=0D };=0D diff --git a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c b/Platform= /RISC-V/PlatformPkg/Universal/Sec/SecMain.c index 0af0b4bac8..e9f030f352 100644 --- a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c +++ b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c @@ -21,6 +21,7 @@ #include // Reference to header file in opensbi=0D #include // Reference to header file in opensbi=0D #include // Reference to header file in opensbi=0D +#include // Reference to header file in opensbi=0D =0D //=0D // Indicates the boot hart (PcdBootHartId) OpenSBI initialization is done.= =0D @@ -434,7 +435,7 @@ EFI_STATUS EFIAPI TemporaryRamDone ( STATIC int SbiEcallFirmwareHandler (=0D IN unsigned long ExtId,=0D IN unsigned long FuncId,=0D - IN unsigned long *Args,=0D + IN CONST struct sbi_trap_regs *TrapRegs,=0D OUT unsigned long *OutVal,=0D OUT struct sbi_trap_info *OutTrap=0D )=0D @@ -446,7 +447,7 @@ STATIC int SbiEcallFirmwareHandler ( *OutVal =3D (unsigned long) sbi_scratch_thishart_ptr();=0D break;=0D case SBI_EXT_FW_MSCRATCH_HARTID_FUNC:=0D - *OutVal =3D (unsigned long) sbi_hartid_to_scratch (Args[0]);=0D + *OutVal =3D (unsigned long) sbi_hartid_to_scratch (TrapRegs->a0);=0D break;=0D default:=0D Ret =3D SBI_ENOTSUPP;=0D diff --git a/Platform/RISC-V/PlatformPkg/Universal/Sec/Riscv64/SecEntry.S b= /Platform/RISC-V/PlatformPkg/Universal/Sec/Riscv64/SecEntry.S index d3d589aefc..692985cefb 100644 --- a/Platform/RISC-V/PlatformPkg/Universal/Sec/Riscv64/SecEntry.S +++ b/Platform/RISC-V/PlatformPkg/Universal/Sec/Riscv64/SecEntry.S @@ -21,6 +21,8 @@ .text=0D .align 3=0D =0D + .globl _start_warm=0D +=0D ASM_FUNC (_ModuleEntryPoint)=0D /*=0D * Jump to warm-boot if this is not the selected core booting,=0D --=20 2.31.1