From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mx0b-002e3701.pphosted.com (mx0b-002e3701.pphosted.com [148.163.143.35]) by mx.groups.io with SMTP id smtpd.web10.2669.1641618781490627917 for ; Fri, 07 Jan 2022 21:13:01 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@hpe.com header.s=pps0720 header.b=YkHOZ4Jj; spf=permerror, err=parse error for token &{10 18 %{ir}.%{v}.%{d}.spf.has.pphosted.com}: invalid domain name (domain: hpe.com, ip: 148.163.143.35, mailfrom: prvs=000704d8ca=abner.chang@hpe.com) Received: from pps.filterd (m0134425.ppops.net [127.0.0.1]) by mx0b-002e3701.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 2084nfMB022161 for ; Sat, 8 Jan 2022 05:13:00 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=hpe.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding; s=pps0720; bh=/DmjUYxrIGkOTo3qfHmx0m+PMKtzj4ALu7RVCQVMXGE=; b=YkHOZ4Jjcm4FcpWCDkT59VqYlIh9o3PiKatxawzFiRbnkZDy4TPYYuJMAnP+0t0bGmbc +2yWwxBCN8HPk4MJHfUAtnp1pcu74vl3jVeeZutH7aEYvbuNEabVV4TVAyLEzPDseuEM zd8TLDF3/oa0IIFkRyAC6gk/+TTmsCqVhtPMSIo0N8n+KxFtKvAYO7u3cdWbeW3+w3Mg P6wpsA55Cex7ZvuCWVIGIYubQB/0YTkysRtSPk+vcVbZU66AsWt/ZpM+8Wy4DzyEL44c nd5kcrX6FBayOJu3OjxEFddASiw4SAkwN5D/5B8hcQ2htgKINFxZmh13nym4+GaIPaaa qA== Received: from g2t2353.austin.hpe.com (g2t2353.austin.hpe.com [15.233.44.26]) by mx0b-002e3701.pphosted.com (PPS) with ESMTPS id 3df3wtg3cf-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Sat, 08 Jan 2022 05:13:00 +0000 Received: from g2t2360.austin.hpecorp.net (g2t2360.austin.hpecorp.net [16.196.225.135]) by g2t2353.austin.hpe.com (Postfix) with ESMTP id E635E84 for ; Sat, 8 Jan 2022 05:12:59 +0000 (UTC) Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.229]) by g2t2360.austin.hpecorp.net (Postfix) with ESMTP id 3B45D3D; Sat, 8 Jan 2022 05:12:59 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com Subject: [PATCH 38/79] Move OpenSbiPlatformLib to RISC-V/PlatformPkg Date: Sat, 8 Jan 2022 12:10:58 +0800 Message-Id: <20220108041121.16005-37-abner.chang@hpe.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20220108041121.16005-1-abner.chang@hpe.com> References: <20220108041121.16005-1-abner.chang@hpe.com> MIME-Version: 1.0 X-Proofpoint-GUID: zkL85FY-jfUPA9-FsaMykKrRZaJl8ulI X-Proofpoint-ORIG-GUID: zkL85FY-jfUPA9-FsaMykKrRZaJl8ulI X-HPE-SCL: -1 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.790,Hydra:6.0.425,FMLib:17.11.62.513 definitions=2022-01-08_01,2022-01-07_01,2021-12-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 phishscore=0 bulkscore=0 priorityscore=1501 suspectscore=0 lowpriorityscore=0 spamscore=0 impostorscore=0 mlxscore=0 malwarescore=0 clxscore=1015 mlxlogscore=999 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2110150000 definitions=main-2201080036 Content-Transfer-Encoding: quoted-printable (This is migrated from edk2-platforms) It's a generic platform file. Only the device tree decides what happens. Cc: Daniel Schaefer Cc: Abner Chang Cc: Sunil V L Reviewed-by: Abner Chang Signed-off-by: Daniel Schaefer --- .../OpensbiPlatformLib/OpensbiPlatformLib.inf | 56 +++++ .../OpensbiPlatformLib/PlatformOverride.h | 30 +++ .../Library/OpensbiPlatformLib/Platform.c | 224 ++++++++++++++++++ .../Library/OpensbiPlatformLib/SifiveFu540.c | 47 ++++ 4 files changed, 357 insertions(+) create mode 100644 Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/= OpensbiPlatformLib.inf create mode 100644 Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/= PlatformOverride.h create mode 100644 Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/= Platform.c create mode 100644 Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/= SifiveFu540.c diff --git a/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/Opensbi= PlatformLib.inf b/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/Op= ensbiPlatformLib.inf new file mode 100644 index 0000000000..f9f2073a5b --- /dev/null +++ b/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/OpensbiPlatfor= mLib.inf @@ -0,0 +1,56 @@ +## @file=0D +# RISC-V OpenSBI Platform Library=0D +# This is the the library which provides platform=0D +# level opensbi functions follow RISC-V OpenSBI implementation.=0D +#=0D +# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
=0D +#=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +##=0D +=0D +[Defines]=0D + INF_VERSION =3D 0x0001001b=0D + BASE_NAME =3D RiscVOpensbiPlatformLib=0D + FILE_GUID =3D 80C09428-44DD-437F-8252-F7AB64711AA5= =0D + MODULE_TYPE =3D SEC=0D + VERSION_STRING =3D 1.0=0D + LIBRARY_CLASS =3D RiscVOpensbiPlatformLib=0D +=0D +#=0D +# The following information is for reference only and not required by the = build tools.=0D +#=0D +# VALID_ARCHITECTURES =3D RISCV64=0D +#=0D +=0D +[Sources]=0D + Platform.c=0D + SifiveFu540.c=0D + PlatformOverride.h=0D +=0D +[Packages]=0D + EmbeddedPkg/EmbeddedPkg.dec=0D + MdeModulePkg/MdeModulePkg.dec=0D + MdePkg/MdePkg.dec=0D + Platform/SiFive/U5SeriesPkg/U5SeriesPkg.dec=0D + Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec=0D + Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec=0D +=0D +[LibraryClasses]=0D + BaseLib=0D + BaseMemoryLib=0D + DebugLib=0D + DebugAgentLib=0D + FdtLib=0D + PcdLib=0D + PrintLib=0D + RiscVCpuLib=0D +=0D +[FixedPcd]=0D + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootHartId=0D + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdHartCount=0D + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootableHartNumber=0D + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdOpenSbiStackSize=0D +=0D + gSiFiveU5SeriesPlatformsPkgTokenSpaceGuid.PcdU5UartBase=0D + gSiFiveU5SeriesPlatformsPkgTokenSpaceGuid.PcdU5PlatformSystemClock=0D diff --git a/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/Platfor= mOverride.h b/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/Platfo= rmOverride.h new file mode 100644 index 0000000000..2fbb8ca45d --- /dev/null +++ b/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/PlatformOverri= de.h @@ -0,0 +1,30 @@ +/*=0D + * SPDX-License-Identifier: BSD-2-Clause=0D + *=0D + * Copyright (c) 2020 Western Digital Corporation or its affiliates.=0D + *=0D + * Authors:=0D + * Anup Patel =0D + */=0D +=0D +#ifndef __PLATFORM_OVERRIDE_H__=0D +#define __PLATFORM_OVERRIDE_H__=0D +=0D +#include =0D +=0D +struct platform_override {=0D + const struct fdt_match *match_table;=0D + u64 (*features)(const struct fdt_match *match);=0D + u64 (*tlbr_flush_limit)(const struct fdt_match *match);=0D + int (*early_init)(bool cold_boot, const struct fdt_match *match);=0D + int (*final_init)(bool cold_boot, const struct fdt_match *match);=0D + void (*early_exit)(const struct fdt_match *match);=0D + void (*final_exit)(const struct fdt_match *match);=0D + int (*system_reset_check)(u32 reset_type, u32 reset_reason,=0D + const struct fdt_match *match);=0D + void (*system_reset)(u32 reset_type, u32 reset_reason,=0D + const struct fdt_match *match);=0D + int (*fdt_fixup)(void *fdt, const struct fdt_match *match);=0D +};=0D +=0D +#endif=0D diff --git a/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/Platfor= m.c b/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/Platform.c new file mode 100644 index 0000000000..79a78b834e --- /dev/null +++ b/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/Platform.c @@ -0,0 +1,224 @@ +/*=0D + * SPDX-License-Identifier: BSD-2-Clause=0D + *=0D + * Copyright (c) 2020 Western Digital Corporation or its affiliates.=0D + *=0D + * Authors:=0D + * Anup Patel =0D + */=0D +=0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +=0D +extern const struct platform_override sifive_fu540;=0D +=0D +static const struct platform_override *special_platforms[] =3D {=0D + &sifive_fu540,=0D +};=0D +=0D +static const struct platform_override *generic_plat =3D NULL;=0D +static const struct fdt_match *generic_plat_match =3D NULL;=0D +=0D +static void fw_platform_lookup_special(void *fdt, int root_offset)=0D +{=0D + int pos, noff;=0D + const struct platform_override *plat;=0D + const struct fdt_match *match;=0D +=0D + for (pos =3D 0; pos < array_size(special_platforms); pos++) {=0D + plat =3D special_platforms[pos];=0D + if (!plat->match_table)=0D + continue;=0D +=0D + noff =3D fdt_find_match(fdt, -1, plat->match_table, &match);=0D + if (noff < 0)=0D + continue;=0D +=0D + generic_plat =3D plat;=0D + generic_plat_match =3D match;=0D + break;=0D + }=0D +}=0D +=0D +extern struct sbi_platform platform;=0D +static u32 generic_hart_index2id[SBI_HARTMASK_MAX_BITS] =3D { 0 };=0D +=0D +/*=0D + * The fw_platform_init() function is called very early on the boot HART=0D + * OpenSBI reference firmwares so that platform specific code get chance=0D + * to update "platform" instance before it is used.=0D + *=0D + * The arguments passed to fw_platform_init() function are boot time state= =0D + * of A0 to A4 register. The "arg0" will be boot HART id and "arg1" will=0D + * be address of FDT passed by previous booting stage.=0D + *=0D + * The return value of fw_platform_init() function is the FDT location. If= =0D + * FDT is unchanged (or FDT is modified in-place) then fw_platform_init()= =0D + * can always return the original FDT location (i.e. 'arg1') unmodified.=0D + */=0D +unsigned long fw_platform_init(unsigned long arg0, unsigned long arg1,=0D + unsigned long arg2, unsigned long arg3,=0D + unsigned long arg4)=0D +{=0D + const char *model;=0D + void *fdt =3D (void *)arg1;=0D + u32 hartid, hart_count =3D 0;=0D + int rc, root_offset, cpus_offset, cpu_offset, len;=0D +=0D + root_offset =3D fdt_path_offset(fdt, "/");=0D + if (root_offset < 0)=0D + goto fail;=0D +=0D + fw_platform_lookup_special(fdt, root_offset);=0D +=0D + model =3D fdt_getprop(fdt, root_offset, "model", &len);=0D + if (model)=0D + sbi_strncpy(platform.name, model, sizeof(platform.name));=0D +=0D + if (generic_plat && generic_plat->features)=0D + platform.features =3D generic_plat->features(generic_plat_match);=0D +=0D + cpus_offset =3D fdt_path_offset(fdt, "/cpus");=0D + if (cpus_offset < 0)=0D + goto fail;=0D +=0D + fdt_for_each_subnode(cpu_offset, fdt, cpus_offset) {=0D + rc =3D fdt_parse_hart_id(fdt, cpu_offset, &hartid);=0D + if (rc)=0D + continue;=0D +=0D + if (SBI_HARTMASK_MAX_BITS <=3D hartid)=0D + continue;=0D +=0D + generic_hart_index2id[hart_count++] =3D hartid;=0D + }=0D +=0D + platform.hart_count =3D hart_count;=0D +=0D + /* Return original FDT pointer */=0D + return arg1;=0D +=0D +fail:=0D + while (1)=0D + wfi();=0D +}=0D +=0D +static int generic_early_init(bool cold_boot)=0D +{=0D + int rc;=0D +=0D + if (generic_plat && generic_plat->early_init) {=0D + rc =3D generic_plat->early_init(cold_boot, generic_plat_match);=0D + if (rc)=0D + return rc;=0D + }=0D +=0D + if (!cold_boot)=0D + return 0;=0D +=0D + return fdt_reset_init();=0D +}=0D +=0D +static int generic_final_init(bool cold_boot)=0D +{=0D + void *fdt;=0D + int rc;=0D +=0D + if (generic_plat && generic_plat->final_init) {=0D + rc =3D generic_plat->final_init(cold_boot, generic_plat_match);=0D + if (rc)=0D + return rc;=0D + }=0D +=0D + if (!cold_boot)=0D + return 0;=0D +=0D + fdt =3D sbi_scratch_thishart_arg1_ptr();=0D +=0D + fdt_cpu_fixup(fdt);=0D + fdt_fixups(fdt);=0D + fdt_domain_fixup(fdt);=0D +=0D + if (generic_plat && generic_plat->fdt_fixup) {=0D + rc =3D generic_plat->fdt_fixup(fdt, generic_plat_match);=0D + if (rc)=0D + return rc;=0D + }=0D +=0D + return 0;=0D +}=0D +=0D +static void generic_early_exit(void)=0D +{=0D + if (generic_plat && generic_plat->early_exit)=0D + generic_plat->early_exit(generic_plat_match);=0D +}=0D +=0D +static void generic_final_exit(void)=0D +{=0D + if (generic_plat && generic_plat->final_exit)=0D + generic_plat->final_exit(generic_plat_match);=0D +}=0D +=0D +static int generic_domains_init(void)=0D +{=0D + return fdt_domains_populate(sbi_scratch_thishart_arg1_ptr());=0D +}=0D +=0D +static u64 generic_tlbr_flush_limit(void)=0D +{=0D + if (generic_plat && generic_plat->tlbr_flush_limit)=0D + return generic_plat->tlbr_flush_limit(generic_plat_match);=0D + return SBI_PLATFORM_TLB_RANGE_FLUSH_LIMIT_DEFAULT;=0D +}=0D +=0D +const struct sbi_platform_operations platform_ops =3D {=0D + .early_init =3D generic_early_init,=0D + .final_init =3D generic_final_init,=0D + .early_exit =3D generic_early_exit,=0D + .final_exit =3D generic_final_exit,=0D + .domains_init =3D generic_domains_init,=0D + .console_init =3D fdt_serial_init,=0D + .irqchip_init =3D fdt_irqchip_init,=0D + .irqchip_exit =3D fdt_irqchip_exit,=0D + .ipi_init =3D fdt_ipi_init,=0D + .ipi_exit =3D fdt_ipi_exit,=0D + .get_tlbr_flush_limit =3D generic_tlbr_flush_limit,=0D + .timer_init =3D fdt_timer_init,=0D + .timer_exit =3D fdt_timer_exit,=0D +};=0D +=0D +#if FixedPcdGet32(PcdBootableHartNumber) =3D=3D 4=0D +#define U540_BOOTABLE_HART_COUNT FixedPcdGet32(PcdBootableHartNumber)=0D +static u32 U540_hart_index2id[U540_BOOTABLE_HART_COUNT] =3D {1, 2, 3, 4};= =0D +#endif=0D +=0D +struct sbi_platform platform =3D {=0D + .opensbi_version =3D OPENSBI_VERSION,=0D + .platform_version =3D SBI_PLATFORM_VERSION(0x0, 0x01),=0D + .name =3D "Generic",=0D + .features =3D SBI_PLATFORM_DEFAULT_FEATURES,=0D + .hart_count =3D SBI_HARTMASK_MAX_BITS,=0D +// TODO: Workaround for U540. Not sure why we need this. OpenSBI doesn't n= eed it.=0D +#if FixedPcdGet32(PcdBootableHartNumber) =3D=3D 4=0D + .hart_index2id =3D U540_hart_index2id,=0D +#else=0D + .hart_index2id =3D generic_hart_index2id,=0D +#endif=0D + // TODO: Any reason why it shouldn't just be SBI_PLATFORM_DEFAULT_HART_S= TACK_SIZE?=0D + .hart_stack_size =3D FixedPcdGet32(PcdOpenSbiStackSize),=0D + .platform_ops_addr =3D (unsigned long)&platform_ops=0D +};=0D diff --git a/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/SifiveF= u540.c b/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/SifiveFu540= .c new file mode 100644 index 0000000000..748b058840 --- /dev/null +++ b/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/SifiveFu540.c @@ -0,0 +1,47 @@ +/*=0D + * SPDX-License-Identifier: BSD-2-Clause=0D + *=0D + * Copyright (c) 2020 Western Digital Corporation or its affiliates.=0D + *=0D + * Authors:=0D + * Anup Patel =0D + */=0D +=0D +#include =0D +#include =0D +#include =0D +=0D +static u64 sifive_fu540_tlbr_flush_limit(const struct fdt_match *match)=0D +{=0D + /*=0D + * The sfence.vma by virtual address does not work on=0D + * SiFive FU540 so we return remote TLB flush limit as zero.=0D + */=0D + return 0;=0D +}=0D +=0D +static int sifive_fu540_fdt_fixup(void *fdt, const struct fdt_match *match= )=0D +{=0D + /*=0D + * SiFive Freedom U540 has an erratum that prevents S-mode software=0D + * to access a PMP protected region using 1GB page table mapping, so=0D + * always add the no-map attribute on this platform.=0D + */=0D + fdt_reserved_memory_nomap_fixup(fdt);=0D +=0D + return 0;=0D +}=0D +=0D +static const struct fdt_match sifive_fu540_match[] =3D {=0D + { .compatible =3D "sifive,fu540" },=0D + { .compatible =3D "sifive,fu540g" },=0D + { .compatible =3D "sifive,fu540-c000" },=0D + { .compatible =3D "sifive,hifive-unleashed-a00" },=0D + { },=0D +};=0D +=0D +const struct platform_override sifive_fu540 =3D {=0D + .match_table =3D sifive_fu540_match,=0D + .tlbr_flush_limit =3D sifive_fu540_tlbr_flush_limit,=0D + .fdt_fixup =3D sifive_fu540_fdt_fixup,=0D +};=0D --=20 2.31.1