From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mx0b-002e3701.pphosted.com (mx0b-002e3701.pphosted.com [148.163.143.35]) by mx.groups.io with SMTP id smtpd.web10.2659.1641618747876609399 for ; Fri, 07 Jan 2022 21:12:28 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@hpe.com header.s=pps0720 header.b=GuBjjVIG; spf=permerror, err=parse error for token &{10 18 %{ir}.%{v}.%{d}.spf.has.pphosted.com}: invalid domain name (domain: hpe.com, ip: 148.163.143.35, mailfrom: prvs=000704d8ca=abner.chang@hpe.com) Received: from pps.filterd (m0134423.ppops.net [127.0.0.1]) by mx0b-002e3701.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 2081WN1L003470 for ; Sat, 8 Jan 2022 05:12:27 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=hpe.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding; s=pps0720; bh=vvsKOO9lI3RzaxpijQuURgzBZYvt2eq5nGi04t82MOA=; b=GuBjjVIGfi5R+D9fDGsjwoTc0ePAwVgbEOBCULQGwOtXeOs5tbat4OInD/b68u+hLUhp PZrb7DTkkDacS3frmyMIuPz/MRLwgTAFN17uxNHFsRLpnjNPIQ6Qg4IUhZOUpSd6QvnH TSqv24/3p8cDLtmajOD3fERMuwWmJ8kNRCoP070UwOzzN4vHrCLOjkYkEKQbLBduXzfs AMIuUHVdy2T4ynjY314uhAw4QYyPgrbIhKU39jhU1evVWbTNcSeosun3AM4Nqyefq1Wg s2S1z43rZZuW7vtkOQgU4Ayorj+uCbqE8Pup3qZv8dxlbdONzU3G0a8zWzafgAVj0O8u CQ== Received: from g2t2353.austin.hpe.com (g2t2353.austin.hpe.com [15.233.44.26]) by mx0b-002e3701.pphosted.com (PPS) with ESMTPS id 3df04bh2hp-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Sat, 08 Jan 2022 05:12:26 +0000 Received: from g2t2360.austin.hpecorp.net (g2t2360.austin.hpecorp.net [16.196.225.135]) by g2t2353.austin.hpe.com (Postfix) with ESMTP id 5ACE677 for ; Sat, 8 Jan 2022 05:12:26 +0000 (UTC) Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.229]) by g2t2360.austin.hpecorp.net (Postfix) with ESMTP id A2C1C46; Sat, 8 Jan 2022 05:12:25 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com Subject: [PATCH 06/79] ProcessorPkg/Library: Add RiscVOpensbiLib Date: Sat, 8 Jan 2022 12:10:26 +0800 Message-Id: <20220108041121.16005-5-abner.chang@hpe.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20220108041121.16005-1-abner.chang@hpe.com> References: <20220108041121.16005-1-abner.chang@hpe.com> MIME-Version: 1.0 X-Proofpoint-GUID: quGgE2-r889OC_i07aSuWmTr3DAXNmTM X-Proofpoint-ORIG-GUID: quGgE2-r889OC_i07aSuWmTr3DAXNmTM X-HPE-SCL: -1 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.790,Hydra:6.0.425,FMLib:17.11.62.513 definitions=2022-01-08_01,2022-01-07_01,2021-12-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 mlxlogscore=999 spamscore=0 lowpriorityscore=0 bulkscore=0 malwarescore=0 adultscore=0 impostorscore=0 suspectscore=0 priorityscore=1501 mlxscore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2110150000 definitions=main-2201080036 Content-Transfer-Encoding: quoted-printable (This is migrated from edk2-platforms:Silicon/RISC-V) EDK2 RISC-V OpenSBI library which pull in external source files under RISC-V/ProcessorPkg/Library/RiscVOpensbiLib/opensbi to the build process. Signed-off-by: Abner Chang Co-authored-by: Daniel Schaefer Co-authored-by: Gilbert Chen Reviewed-by: Leif Lindholm Cc: Leif Lindholm Cc: Gilbert Chen Cc: Daniel Schaefer --- .../RiscVOpensbiLib/RiscVOpensbiLib.inf | 82 +++++++++++++++++++ .../Include/IndustryStandard/RiscVOpensbi.h | 59 +++++++++++++ .../ProcessorPkg/Include/OpensbiTypes.h | 80 ++++++++++++++++++ 3 files changed, 221 insertions(+) create mode 100644 Silicon/RISC-V/ProcessorPkg/Library/RiscVOpensbiLib/Ris= cVOpensbiLib.inf create mode 100644 Silicon/RISC-V/ProcessorPkg/Include/IndustryStandard/Ri= scVOpensbi.h create mode 100644 Silicon/RISC-V/ProcessorPkg/Include/OpensbiTypes.h diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVOpensbiLib/RiscVOpens= biLib.inf b/Silicon/RISC-V/ProcessorPkg/Library/RiscVOpensbiLib/RiscVOpensb= iLib.inf new file mode 100644 index 0000000000..71cc76444e --- /dev/null +++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVOpensbiLib/RiscVOpensbiLib.i= nf @@ -0,0 +1,82 @@ +## @file=0D +# RISC-V Opensbi Library Instance.=0D +#=0D +# Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
=0D +#=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +##=0D +=0D +[Defines]=0D + INF_VERSION =3D 0x0001001b=0D + BASE_NAME =3D RiscVOpensbiLib=0D + FILE_GUID =3D 6EF0C812-66F6-11E9-93CE-3F5D5F0DF0A7=0D + MODULE_TYPE =3D BASE=0D + VERSION_STRING =3D 1.0=0D + LIBRARY_CLASS =3D RiscVOpensbiLib=0D +=0D +[Sources]=0D + opensbi/lib/sbi/riscv_asm.c=0D + opensbi/lib/sbi/riscv_atomic.c=0D + opensbi/lib/sbi/riscv_hardfp.S=0D + opensbi/lib/sbi/riscv_locks.c=0D + opensbi/lib/sbi/sbi_bitmap.c=0D + opensbi/lib/sbi/sbi_bitops.c=0D + opensbi/lib/sbi/sbi_console.c=0D + opensbi/lib/sbi/sbi_ecall.c=0D + opensbi/lib/sbi/sbi_ecall_base.c=0D + opensbi/lib/sbi/sbi_ecall_hsm.c=0D + opensbi/lib/sbi/sbi_ecall_legacy.c=0D + opensbi/lib/sbi/sbi_ecall_replace.c=0D + opensbi/lib/sbi/sbi_ecall_vendor.c=0D + opensbi/lib/sbi/sbi_emulate_csr.c=0D + opensbi/lib/sbi/sbi_fifo.c=0D + opensbi/lib/sbi/sbi_hart.c=0D + opensbi/lib/sbi/sbi_math.c=0D + opensbi/lib/sbi/sbi_hfence.S=0D + opensbi/lib/sbi/sbi_hsm.c=0D + opensbi/lib/sbi/sbi_illegal_insn.c=0D + opensbi/lib/sbi/sbi_init.c=0D + opensbi/lib/sbi/sbi_ipi.c=0D + opensbi/lib/sbi/sbi_misaligned_ldst.c=0D + opensbi/lib/sbi/sbi_platform.c=0D + opensbi/lib/sbi/sbi_scratch.c=0D + opensbi/lib/sbi/sbi_string.c=0D + opensbi/lib/sbi/sbi_system.c=0D + opensbi/lib/sbi/sbi_timer.c=0D + opensbi/lib/sbi/sbi_tlb.c=0D + opensbi/lib/sbi/sbi_trap.c=0D + opensbi/lib/sbi/sbi_unpriv.c=0D + opensbi/lib/sbi/sbi_expected_trap.S=0D +=0D + opensbi/lib/utils/fdt/fdt_helper.c=0D + opensbi/lib/utils/fdt/fdt_fixup.c=0D + opensbi/lib/utils/ipi/fdt_ipi.c=0D + opensbi/lib/utils/ipi/fdt_ipi_clint.c=0D + opensbi/lib/utils/irqchip/fdt_irqchip.c=0D + opensbi/lib/utils/irqchip/fdt_irqchip_plic.c=0D + opensbi/lib/utils/irqchip/plic.c=0D + opensbi/lib/utils/reset/fdt_reset.c=0D + opensbi/lib/utils/reset/fdt_reset_htif.c=0D + opensbi/lib/utils/reset/fdt_reset_sifive.c=0D + opensbi/lib/utils/serial/fdt_serial.c=0D + opensbi/lib/utils/serial/fdt_serial_htif.c=0D + opensbi/lib/utils/serial/fdt_serial_shakti.c=0D + opensbi/lib/utils/serial/fdt_serial_sifive.c=0D + opensbi/lib/utils/serial/fdt_serial_uart8250.c=0D + opensbi/lib/utils/serial/shakti-uart.c=0D + opensbi/lib/utils/serial/sifive-uart.c=0D + opensbi/lib/utils/serial/uart8250.c=0D + opensbi/lib/utils/sys/clint.c=0D + opensbi/lib/utils/sys/htif.c=0D + opensbi/lib/utils/sys/sifive_test.c=0D + opensbi/lib/utils/timer/fdt_timer.c=0D + opensbi/lib/utils/timer/fdt_timer_clint.c=0D +=0D +[Packages]=0D + EmbeddedPkg/EmbeddedPkg.dec # For libfdt.=0D + MdePkg/MdePkg.dec=0D + Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec=0D +=0D +[BuildOptions]=0D + GCC:*_*_*_PP_FLAGS =3D -D__ASSEMBLY__=0D diff --git a/Silicon/RISC-V/ProcessorPkg/Include/IndustryStandard/RiscVOpen= sbi.h b/Silicon/RISC-V/ProcessorPkg/Include/IndustryStandard/RiscVOpensbi.h new file mode 100644 index 0000000000..2dab696af8 --- /dev/null +++ b/Silicon/RISC-V/ProcessorPkg/Include/IndustryStandard/RiscVOpensbi.h @@ -0,0 +1,59 @@ +/** @file=0D + SBI inline function calls.=0D +=0D + Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All right= s reserved.
=0D +=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +=0D +#ifndef EDK2_SBI_H_=0D +#define EDK2_SBI_H_=0D +=0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +=0D +#define RISC_V_MAX_HART_SUPPORTED SBI_HARTMASK_MAX_BITS=0D +=0D +typedef=0D +VOID=0D +(EFIAPI *RISCV_HART_SWITCH_MODE)(=0D + IN UINTN FuncArg0,=0D + IN UINTN FuncArg1,=0D + IN UINTN NextAddr,=0D + IN UINTN NextMode,=0D + IN BOOLEAN NextVirt=0D + );=0D +=0D +//=0D +// Keep the structure member in 64-bit alignment.=0D +//=0D +typedef struct {=0D + UINT64 IsaExtensionSupported; // The ISA extension th= is core supported.=0D + RISCV_UINT128 MachineVendorId; // Machine vendor ID=0D + RISCV_UINT128 MachineArchId; // Machine Architecture= ID=0D + RISCV_UINT128 MachineImplId; // Machine Implementati= on ID=0D + RISCV_HART_SWITCH_MODE HartSwitchMode; // OpenSBI's function t= o switch the mode of a hart=0D +} EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC;=0D +#define FIRMWARE_CONTEXT_HART_SPECIFIC_SIZE (64 * 8) // This is the size = of EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC=0D + // structure. Referr= ed by both C code and assembly code.=0D +=0D +typedef struct {=0D + VOID *PeiServiceTable; // PEI Service table=0D + EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC *HartSpecific[RISC_V_MAX_HART_= SUPPORTED];=0D +} EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT;=0D +=0D +//=0D +// Typedefs of OpenSBI type to make them conform to EDK2 coding guidelines= =0D +//=0D +typedef struct sbi_scratch SBI_SCRATCH;=0D +typedef struct sbi_platform SBI_PLATFORM;=0D +=0D +#endif=0D diff --git a/Silicon/RISC-V/ProcessorPkg/Include/OpensbiTypes.h b/Silicon/R= ISC-V/ProcessorPkg/Include/OpensbiTypes.h new file mode 100644 index 0000000000..37e407908a --- /dev/null +++ b/Silicon/RISC-V/ProcessorPkg/Include/OpensbiTypes.h @@ -0,0 +1,80 @@ +/** @file=0D + RISC-V OpesbSBI header file reference.=0D +=0D + Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All right= s reserved.
=0D +=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +#ifndef EDK2_SBI_TYPES_H_=0D +#define EDK2_SBI_TYPES_H_=0D +=0D +#include =0D +=0D +typedef INT8 s8;=0D +typedef UINT8 u8;=0D +typedef UINT8 uint8_t;=0D +=0D +typedef INT16 s16;=0D +typedef UINT16 u16;=0D +typedef INT16 int16_t;=0D +typedef UINT16 uint16_t;=0D +=0D +typedef INT32 s32;=0D +typedef UINT32 u32;=0D +typedef INT32 int32_t;=0D +typedef UINT32 uint32_t;=0D +=0D +typedef INT64 s64;=0D +typedef UINT64 u64;=0D +typedef INT64 int64_t;=0D +typedef UINT64 uint64_t;=0D +=0D +// PRILX is not used in EDK2 but we need to define it here because when=0D +// defining our own types, this constant is not defined but used by OpenSB= I.=0D +#define PRILX "016lx"=0D +=0D +typedef BOOLEAN bool;=0D +typedef unsigned long ulong;=0D +typedef UINT64 uintptr_t;=0D +typedef UINT64 size_t;=0D +typedef INT64 ssize_t;=0D +typedef UINT64 virtual_addr_t;=0D +typedef UINT64 virtual_size_t;=0D +typedef UINT64 physical_addr_t;=0D +typedef UINT64 physical_size_t;=0D +=0D +#define true TRUE=0D +#define false FALSE=0D +=0D +#define __packed __attribute__((packed))=0D +#define __noreturn __attribute__((noreturn))=0D +=0D +#if defined(__GNUC__) || defined(__clang__)=0D + #define likely(x) __builtin_expect((x), 1)=0D + #define unlikely(x) __builtin_expect((x), 0)=0D +#else=0D + #define likely(x) (x)=0D + #define unlikely(x) (x)=0D +#endif=0D +=0D +#undef offsetof=0D +#ifdef __compiler_offsetof=0D +#define offsetof(TYPE, MEMBER) __compiler_offsetof(TYPE,MEMBER)=0D +#else=0D +#define offsetof(TYPE, MEMBER) ((size_t) &((TYPE *)0)->MEMBER)=0D +#endif=0D +=0D +#define container_of(ptr, type, member) ({ \=0D + const typeof(((type *)0)->member) * __mptr =3D (ptr); \=0D + (type *)((char *)__mptr - offsetof(type, member)); })=0D +=0D +#define array_size(x) (sizeof(x) / sizeof((x)[0]))=0D +=0D +#define CLAMP(a, lo, hi) MIN(MAX(a, lo), hi)=0D +#define ROUNDUP(a, b) ((((a)-1) / (b) + 1) * (b))=0D +#define ROUNDDOWN(a, b) ((a) / (b) * (b))=0D +=0D +/* clang-format on */=0D +=0D +#endif=0D --=20 2.31.1