From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mx0b-002e3701.pphosted.com (mx0b-002e3701.pphosted.com [148.163.143.35]) by mx.groups.io with SMTP id smtpd.web12.2692.1641618751817218818 for ; Fri, 07 Jan 2022 21:12:32 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@hpe.com header.s=pps0720 header.b=aRvQpOeV; spf=permerror, err=parse error for token &{10 18 %{ir}.%{v}.%{d}.spf.has.pphosted.com}: invalid domain name (domain: hpe.com, ip: 148.163.143.35, mailfrom: prvs=000704d8ca=abner.chang@hpe.com) Received: from pps.filterd (m0134424.ppops.net [127.0.0.1]) by mx0b-002e3701.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 2082AmIk021546 for ; Sat, 8 Jan 2022 05:12:30 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=hpe.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding; s=pps0720; bh=4Wkgkb3FCnxKHY1qM3+kIxDJ316QHu2XMGoksqd+igE=; b=aRvQpOeVC76lFxzJweobY99iFpvoJKXvifMceu3W4G4vO9FdpwB7XWJC0YXoKdy/Qunj 7ZrUv2jLr9glOWgLJ6zAYUpsjwgtmOX+TdyDlrFTDWpPdcnx+minKoLX0ZdVCpjsMEv9 PjUMIf98GuNaOTT7uiGF0YTO+g4qh043u46AL2ah0OglL1bnPOjy859r7JsbphGLY2XK 2St9uT9HMaXtgPVJ+Jp0qnmppbPN/i3YM2ig65TD9EVjErmN7aGfFHZGfvu5HKvdgpL8 CHiMD10W1XDu+tZIwlU74QV2oAgbY3RtDREhMGgxGCbmHcU687Xscwj2Hb2Nc2B7Pxjw gw== Received: from g2t2352.austin.hpe.com (g2t2352.austin.hpe.com [15.233.44.25]) by mx0b-002e3701.pphosted.com (PPS) with ESMTPS id 3df1kq0mhy-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Sat, 08 Jan 2022 05:12:30 +0000 Received: from g2t2360.austin.hpecorp.net (g2t2360.austin.hpecorp.net [16.196.225.135]) by g2t2352.austin.hpe.com (Postfix) with ESMTP id A659662 for ; Sat, 8 Jan 2022 05:12:29 +0000 (UTC) Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.229]) by g2t2360.austin.hpecorp.net (Postfix) with ESMTP id EF05F36; Sat, 8 Jan 2022 05:12:28 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com Subject: [PATCH 09/79] ProcessorPkg/CpuDxe: Add RISC-V CPU DXE driver. Date: Sat, 8 Jan 2022 12:10:29 +0800 Message-Id: <20220108041121.16005-8-abner.chang@hpe.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20220108041121.16005-1-abner.chang@hpe.com> References: <20220108041121.16005-1-abner.chang@hpe.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: dGNdadZxc6DNgi_E4FloR7xhpNnFNaF8 X-Proofpoint-GUID: dGNdadZxc6DNgi_E4FloR7xhpNnFNaF8 X-HPE-SCL: -1 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.790,Hydra:6.0.425,FMLib:17.11.62.513 definitions=2022-01-08_01,2022-01-07_01,2021-12-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 mlxlogscore=999 clxscore=1015 bulkscore=0 malwarescore=0 suspectscore=0 phishscore=0 mlxscore=0 impostorscore=0 spamscore=0 adultscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2110150000 definitions=main-2201080036 Content-Transfer-Encoding: quoted-printable (This is migrated from edk2-platforms:Silicon/RISC-V) The driver produces RISC-V EFI_CPU_ARCH_PROTOCOL and use RISC-V platform level timer library. Due to RISC-V timer Control Status Register (CSR) is platform implementation specific, RISC-V CPU DXE driver invokes platform level timer library to access to timer CSRs. Signed-off-by: Abner Chang Co-authored-by: Gilbert Chen Reviewed-by: Leif Lindholm Cc: Leif Lindholm Cc: Gilbert Chen --- .../ProcessorPkg/Universal/CpuDxe/CpuDxe.inf | 48 +++ .../ProcessorPkg/Universal/CpuDxe/CpuDxe.h | 199 +++++++++++ .../ProcessorPkg/Universal/CpuDxe/CpuDxe.c | 316 ++++++++++++++++++ .../ProcessorPkg/Universal/CpuDxe/CpuDxe.uni | 13 + .../Universal/CpuDxe/CpuDxeExtra.uni | 14 + 5 files changed, 590 insertions(+) create mode 100644 Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxe.inf create mode 100644 Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxe.h create mode 100644 Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxe.c create mode 100644 Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxe.uni create mode 100644 Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxeExtr= a.uni diff --git a/Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxe.inf b/Sili= con/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxe.inf new file mode 100644 index 0000000000..29cc4413bd --- /dev/null +++ b/Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxe.inf @@ -0,0 +1,48 @@ +## @file=0D +# RISC-V CPU DXE module.=0D +#=0D +# Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. A= ll rights reserved.
=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +##=0D +=0D +[Defines]=0D + INF_VERSION =3D 0x0001001b=0D + BASE_NAME =3D CpuDxe=0D + MODULE_UNI_FILE =3D CpuDxe.uni=0D + FILE_GUID =3D 2AEB1f3E-5B6B-441B-92C1-4A9E6FC85E92= =0D + MODULE_TYPE =3D DXE_DRIVER=0D + VERSION_STRING =3D 1.0=0D +=0D + ENTRY_POINT =3D InitializeCpu=0D +=0D +[Packages]=0D + MdeModulePkg/MdeModulePkg.dec=0D + MdePkg/MdePkg.dec=0D + Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec=0D +=0D +[LibraryClasses]=0D + BaseLib=0D + CpuLib=0D + CpuExceptionHandlerLib=0D + DebugLib=0D + RiscVCpuLib=0D + TimerLib=0D + UefiBootServicesTableLib=0D + UefiDriverEntryPoint=0D +=0D +[Sources]=0D + CpuDxe.c=0D + CpuDxe.h=0D +=0D +[Protocols]=0D + gEfiCpuArchProtocolGuid ## PRODUCES=0D +=0D +[Pcd]=0D + gUefiRiscVPkgTokenSpaceGuid.PcdRiscVMachineTimerFrequencyInHerz=0D +=0D +[Depex]=0D + TRUE=0D +=0D +[UserExtensions.TianoCore."ExtraFiles"]=0D + CpuDxeExtra.uni=0D diff --git a/Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxe.h b/Silico= n/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxe.h new file mode 100644 index 0000000000..c2c2739434 --- /dev/null +++ b/Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxe.h @@ -0,0 +1,199 @@ +/** @file=0D + RISC-V CPU DXE module header file.=0D +=0D + Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. Al= l rights reserved.
=0D +=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +=0D +#ifndef CPU_DXE_H_=0D +#define CPU_DXE_H_=0D +=0D +#include =0D +=0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +=0D +/**=0D + Flush CPU data cache. If the instruction cache is fully coherent=0D + with all DMA operations then function can just return EFI_SUCCESS.=0D +=0D + @param This Protocol instance structure=0D + @param Start Physical address to start flushing from.=0D + @param Length Number of bytes to flush. Round up to chipset= =0D + granularity.=0D + @param FlushType Specifies the type of flush operation to perfo= rm.=0D +=0D + @retval EFI_SUCCESS If cache was flushed=0D + @retval EFI_UNSUPPORTED If flush type is not supported.=0D + @retval EFI_DEVICE_ERROR If requested range could not be flushed.=0D +=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +CpuFlushCpuDataCache (=0D + IN EFI_CPU_ARCH_PROTOCOL *This,=0D + IN EFI_PHYSICAL_ADDRESS Start,=0D + IN UINT64 Length,=0D + IN EFI_CPU_FLUSH_TYPE FlushType=0D + );=0D +=0D +/**=0D + Enables CPU interrupts.=0D +=0D + @param This Protocol instance structure=0D +=0D + @retval EFI_SUCCESS If interrupts were enabled in the CPU=0D + @retval EFI_DEVICE_ERROR If interrupts could not be enabled on the CPU.= =0D +=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +CpuEnableInterrupt (=0D + IN EFI_CPU_ARCH_PROTOCOL *This=0D + );=0D +=0D +/**=0D + Disables CPU interrupts.=0D +=0D + @param This Protocol instance structure=0D +=0D + @retval EFI_SUCCESS If interrupts were disabled in the CPU.=0D + @retval EFI_DEVICE_ERROR If interrupts could not be disabled on the CPU= .=0D +=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +CpuDisableInterrupt (=0D + IN EFI_CPU_ARCH_PROTOCOL *This=0D + );=0D +=0D +/**=0D + Return the state of interrupts.=0D +=0D + @param This Protocol instance structure=0D + @param State Pointer to the CPU's current interrupt st= ate=0D +=0D + @retval EFI_SUCCESS If interrupts were disabled in the CPU.=0D + @retval EFI_INVALID_PARAMETER State is NULL.=0D +=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +CpuGetInterruptState (=0D + IN EFI_CPU_ARCH_PROTOCOL *This,=0D + OUT BOOLEAN *State=0D + );=0D +=0D +/**=0D + Generates an INIT to the CPU.=0D +=0D + @param This Protocol instance structure=0D + @param InitType Type of CPU INIT to perform=0D +=0D + @retval EFI_SUCCESS If CPU INIT occurred. This value should never = be=0D + seen.=0D + @retval EFI_DEVICE_ERROR If CPU INIT failed.=0D + @retval EFI_UNSUPPORTED Requested type of CPU INIT not supported.=0D +=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +CpuInit (=0D + IN EFI_CPU_ARCH_PROTOCOL *This,=0D + IN EFI_CPU_INIT_TYPE InitType=0D + );=0D +=0D +/**=0D + Registers a function to be called from the CPU interrupt handler.=0D +=0D + @param This Protocol instance structure=0D + @param InterruptType Defines which interrupt to hook. IA-32=0D + valid range is 0x00 through 0xFF=0D + @param InterruptHandler A pointer to a function of type=0D + EFI_CPU_INTERRUPT_HANDLER that is called= =0D + when a processor interrupt occurs. A nul= l=0D + pointer is an error condition.=0D +=0D + @retval EFI_SUCCESS If handler installed or uninstalled.=0D + @retval EFI_ALREADY_STARTED InterruptHandler is not NULL, and a handl= er=0D + for InterruptType was previously installe= d.=0D + @retval EFI_INVALID_PARAMETER InterruptHandler is NULL, and a handler f= or=0D + InterruptType was not previously installe= d.=0D + @retval EFI_UNSUPPORTED The interrupt specified by InterruptType= =0D + is not supported.=0D +=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +CpuRegisterInterruptHandler (=0D + IN EFI_CPU_ARCH_PROTOCOL *This,=0D + IN EFI_EXCEPTION_TYPE InterruptType,=0D + IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler=0D + );=0D +=0D +/**=0D + Returns a timer value from one of the CPU's internal timers. There is no= =0D + inherent time interval between ticks but is a function of the CPU freque= ncy.=0D +=0D + @param This - Protocol instance structure.=0D + @param TimerIndex - Specifies which CPU timer is requested.=0D + @param TimerValue - Pointer to the returned timer value.=0D + @param TimerPeriod - A pointer to the amount of time that passe= s=0D + in femtoseconds (10-15) for each increment= =0D + of TimerValue. If TimerValue does not=0D + increment at a predictable rate, then 0 is= =0D + returned. The amount of time that has=0D + passed between two calls to GetTimerValue(= )=0D + can be calculated with the formula=0D + (TimerValue2 - TimerValue1) * TimerPeriod.= =0D + This parameter is optional and may be NULL= .=0D +=0D + @retval EFI_SUCCESS - If the CPU timer count was returned.=0D + @retval EFI_UNSUPPORTED - If the CPU does not have any readable ti= mers.=0D + @retval EFI_DEVICE_ERROR - If an error occurred while reading the t= imer.=0D + @retval EFI_INVALID_PARAMETER - TimerIndex is not valid or TimerValue is= NULL.=0D +=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +CpuGetTimerValue (=0D + IN EFI_CPU_ARCH_PROTOCOL *This,=0D + IN UINT32 TimerIndex,=0D + OUT UINT64 *TimerValue,=0D + OUT UINT64 *TimerPeriod OPTIONAL=0D + );=0D +=0D +/**=0D + Set memory cacheability attributes for given range of memeory.=0D +=0D + @param This Protocol instance structure=0D + @param BaseAddress Specifies the start address of the=0D + memory range=0D + @param Length Specifies the length of the memory range= =0D + @param Attributes The memory cacheability for the memory ra= nge=0D +=0D + @retval EFI_SUCCESS If the cacheability of that memory range = is=0D + set successfully=0D + @retval EFI_UNSUPPORTED If the desired operation cannot be done=0D + @retval EFI_INVALID_PARAMETER The input parameter is not correct,=0D + such as Length =3D 0=0D +=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +CpuSetMemoryAttributes (=0D + IN EFI_CPU_ARCH_PROTOCOL *This,=0D + IN EFI_PHYSICAL_ADDRESS BaseAddress,=0D + IN UINT64 Length,=0D + IN UINT64 Attributes=0D + );=0D +=0D +#endif=0D +=0D diff --git a/Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxe.c b/Silico= n/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxe.c new file mode 100644 index 0000000000..27a07b1561 --- /dev/null +++ b/Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxe.c @@ -0,0 +1,316 @@ +/** @file=0D + RISC-V CPU DXE driver.=0D +=0D + Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. Al= l rights reserved.
=0D +=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +=0D +#include "CpuDxe.h"=0D +=0D +//=0D +// Global Variables=0D +//=0D +STATIC BOOLEAN mInterruptState =3D FALSE;=0D +STATIC EFI_HANDLE mCpuHandle =3D NULL;=0D +=0D +EFI_CPU_ARCH_PROTOCOL gCpu =3D {=0D + CpuFlushCpuDataCache,=0D + CpuEnableInterrupt,=0D + CpuDisableInterrupt,=0D + CpuGetInterruptState,=0D + CpuInit,=0D + CpuRegisterInterruptHandler,=0D + CpuGetTimerValue,=0D + CpuSetMemoryAttributes,=0D + 1, // NumberOfTimers=0D + 4 // DmaBufferAlignment=0D +};=0D +=0D +//=0D +// CPU Arch Protocol Functions=0D +//=0D +=0D +/**=0D + Flush CPU data cache. If the instruction cache is fully coherent=0D + with all DMA operations then function can just return EFI_SUCCESS.=0D +=0D + @param This Protocol instance structure=0D + @param Start Physical address to start flushing from.=0D + @param Length Number of bytes to flush. Round up to chipset= =0D + granularity.=0D + @param FlushType Specifies the type of flush operation to perfo= rm.=0D +=0D + @retval EFI_SUCCESS If cache was flushed=0D + @retval EFI_UNSUPPORTED If flush type is not supported.=0D + @retval EFI_DEVICE_ERROR If requested range could not be flushed.=0D +=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +CpuFlushCpuDataCache (=0D + IN EFI_CPU_ARCH_PROTOCOL *This,=0D + IN EFI_PHYSICAL_ADDRESS Start,=0D + IN UINT64 Length,=0D + IN EFI_CPU_FLUSH_TYPE FlushType=0D + )=0D +{=0D + return EFI_SUCCESS;=0D +}=0D +=0D +=0D +/**=0D + Enables CPU interrupts.=0D +=0D + @param This Protocol instance structure=0D +=0D + @retval EFI_SUCCESS If interrupts were enabled in the CPU=0D + @retval EFI_DEVICE_ERROR If interrupts could not be enabled on the CPU.= =0D +=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +CpuEnableInterrupt (=0D + IN EFI_CPU_ARCH_PROTOCOL *This=0D + )=0D +{=0D + EnableInterrupts ();=0D + mInterruptState =3D TRUE;=0D + return EFI_SUCCESS;=0D +}=0D +=0D +=0D +/**=0D + Disables CPU interrupts.=0D +=0D + @param This Protocol instance structure=0D +=0D + @retval EFI_SUCCESS If interrupts were disabled in the CPU.=0D + @retval EFI_DEVICE_ERROR If interrupts could not be disabled on the CPU= .=0D +=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +CpuDisableInterrupt (=0D + IN EFI_CPU_ARCH_PROTOCOL *This=0D + )=0D +{=0D + DisableInterrupts ();=0D + mInterruptState =3D FALSE;=0D + return EFI_SUCCESS;=0D +}=0D +=0D +=0D +/**=0D + Return the state of interrupts.=0D +=0D + @param This Protocol instance structure=0D + @param State Pointer to the CPU's current interrupt st= ate=0D +=0D + @retval EFI_SUCCESS If interrupts were disabled in the CPU.=0D + @retval EFI_INVALID_PARAMETER State is NULL.=0D +=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +CpuGetInterruptState (=0D + IN EFI_CPU_ARCH_PROTOCOL *This,=0D + OUT BOOLEAN *State=0D + )=0D +{=0D + if (State =3D=3D NULL) {=0D + return EFI_INVALID_PARAMETER;=0D + }=0D +=0D + *State =3D mInterruptState;=0D + return EFI_SUCCESS;=0D +}=0D +=0D +=0D +/**=0D + Generates an INIT to the CPU.=0D +=0D + @param This Protocol instance structure=0D + @param InitType Type of CPU INIT to perform=0D +=0D + @retval EFI_SUCCESS If CPU INIT occurred. This value should never = be=0D + seen.=0D + @retval EFI_DEVICE_ERROR If CPU INIT failed.=0D + @retval EFI_UNSUPPORTED Requested type of CPU INIT not supported.=0D +=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +CpuInit (=0D + IN EFI_CPU_ARCH_PROTOCOL *This,=0D + IN EFI_CPU_INIT_TYPE InitType=0D + )=0D +{=0D + return EFI_UNSUPPORTED;=0D +}=0D +=0D +=0D +/**=0D + Registers a function to be called from the CPU interrupt handler.=0D +=0D + @param This Protocol instance structure=0D + @param InterruptType Defines which interrupt to hook. IA-32=0D + valid range is 0x00 through 0xFF=0D + @param InterruptHandler A pointer to a function of type=0D + EFI_CPU_INTERRUPT_HANDLER that is called= =0D + when a processor interrupt occurs. A nul= l=0D + pointer is an error condition.=0D +=0D + @retval EFI_SUCCESS If handler installed or uninstalled.=0D + @retval EFI_ALREADY_STARTED InterruptHandler is not NULL, and a handl= er=0D + for InterruptType was previously installe= d.=0D + @retval EFI_INVALID_PARAMETER InterruptHandler is NULL, and a handler f= or=0D + InterruptType was not previously installe= d.=0D + @retval EFI_UNSUPPORTED The interrupt specified by InterruptType= =0D + is not supported.=0D +=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +CpuRegisterInterruptHandler (=0D + IN EFI_CPU_ARCH_PROTOCOL *This,=0D + IN EFI_EXCEPTION_TYPE InterruptType,=0D + IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler=0D + )=0D +{=0D + return RegisterCpuInterruptHandler (InterruptType, InterruptHandler);=0D +}=0D +=0D +=0D +/**=0D + Returns a timer value from one of the CPU's internal timers. There is no= =0D + inherent time interval between ticks but is a function of the CPU freque= ncy.=0D +=0D + @param This - Protocol instance structure.=0D + @param TimerIndex - Specifies which CPU timer is requested.=0D + @param TimerValue - Pointer to the returned timer value.=0D + @param TimerPeriod - A pointer to the amount of time that passe= s=0D + in femtoseconds (10-15) for each increment= =0D + of TimerValue. If TimerValue does not=0D + increment at a predictable rate, then 0 is= =0D + returned. The amount of time that has=0D + passed between two calls to GetTimerValue(= )=0D + can be calculated with the formula=0D + (TimerValue2 - TimerValue1) * TimerPeriod.= =0D + This parameter is optional and may be NULL= .=0D +=0D + @retval EFI_SUCCESS - If the CPU timer count was returned.=0D + @retval EFI_UNSUPPORTED - If the CPU does not have any readable ti= mers.=0D + @retval EFI_DEVICE_ERROR - If an error occurred while reading the t= imer.=0D + @retval EFI_INVALID_PARAMETER - TimerIndex is not valid or TimerValue is= NULL.=0D +=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +CpuGetTimerValue (=0D + IN EFI_CPU_ARCH_PROTOCOL *This,=0D + IN UINT32 TimerIndex,=0D + OUT UINT64 *TimerValue,=0D + OUT UINT64 *TimerPeriod OPTIONAL=0D + )=0D +{=0D + if (TimerValue =3D=3D NULL) {=0D + return EFI_INVALID_PARAMETER;=0D + }=0D +=0D + if (TimerIndex !=3D 0) {=0D + return EFI_INVALID_PARAMETER;=0D + }=0D +=0D + *TimerValue =3D (UINT64)RiscVReadMachineTimer ();=0D + if (TimerPeriod !=3D NULL) {=0D + *TimerPeriod =3D DivU64x32 (=0D + 1000000000000000u,=0D + PcdGet64 (PcdRiscVMachineTimerFrequencyInHerz)=0D + );=0D + }=0D + return EFI_SUCCESS;=0D +}=0D +=0D +=0D +/**=0D + Implementation of SetMemoryAttributes() service of CPU Architecture Prot= ocol.=0D +=0D + This function modifies the attributes for the memory region specified by= BaseAddress and=0D + Length from their current attributes to the attributes specified by Attr= ibutes.=0D +=0D + @param This The EFI_CPU_ARCH_PROTOCOL instance.=0D + @param BaseAddress The physical address that is the start address = of a memory region.=0D + @param Length The size in bytes of the memory region.=0D + @param Attributes The bit mask of attributes to set for the memor= y region.=0D +=0D + @retval EFI_SUCCESS The attributes were set for the memory reg= ion.=0D + @retval EFI_ACCESS_DENIED The attributes for the memory resource ran= ge specified by=0D + BaseAddress and Length cannot be modified.= =0D + @retval EFI_INVALID_PARAMETER Length is zero.=0D + Attributes specified an illegal combinatio= n of attributes that=0D + cannot be set together.=0D + @retval EFI_OUT_OF_RESOURCES There are not enough system resources to m= odify the attributes of=0D + the memory resource range.=0D + @retval EFI_UNSUPPORTED The processor does not support one or more= bytes of the memory=0D + resource range specified by BaseAddress an= d Length.=0D + The bit mask of attributes is not support = for the memory resource=0D + range specified by BaseAddress and Length.= =0D +=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +CpuSetMemoryAttributes (=0D + IN EFI_CPU_ARCH_PROTOCOL *This,=0D + IN EFI_PHYSICAL_ADDRESS BaseAddress,=0D + IN UINT64 Length,=0D + IN UINT64 Attributes=0D + )=0D +{=0D + DEBUG ((DEBUG_INFO, "%a: Set memory attributes not supported yet\n", __F= UNCTION__));=0D + return EFI_UNSUPPORTED;=0D +}=0D +=0D +/**=0D + Initialize the state information for the CPU Architectural Protocol.=0D +=0D + @param ImageHandle Image handle this driver.=0D + @param SystemTable Pointer to the System Table.=0D +=0D + @retval EFI_SUCCESS Thread can be successfully created=0D + @retval EFI_OUT_OF_RESOURCES Cannot allocate protocol data structure=0D + @retval EFI_DEVICE_ERROR Cannot create the thread=0D +=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +InitializeCpu (=0D + IN EFI_HANDLE ImageHandle,=0D + IN EFI_SYSTEM_TABLE *SystemTable=0D + )=0D +{=0D + EFI_STATUS Status;=0D +=0D + //=0D + // Machine mode handler is initiated in CpuExceptionHandlerLibConstructo= r in=0D + // CpuExecptionHandlerLib.=0D + //=0D +=0D + //=0D + // Make sure interrupts are disabled=0D + //=0D + DisableInterrupts ();=0D +=0D + //=0D + // Install CPU Architectural Protocol=0D + //=0D + Status =3D gBS->InstallMultipleProtocolInterfaces (=0D + &mCpuHandle,=0D + &gEfiCpuArchProtocolGuid, &gCpu,=0D + NULL=0D + );=0D + ASSERT_EFI_ERROR (Status);=0D + return Status;=0D +}=0D +=0D diff --git a/Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxe.uni b/Sili= con/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxe.uni new file mode 100644 index 0000000000..460141a1aa --- /dev/null +++ b/Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxe.uni @@ -0,0 +1,13 @@ +// /** @file=0D +//=0D +// Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. A= ll rights reserved.
=0D +//=0D +// SPDX-License-Identifier: BSD-2-Clause-Patent=0D +//=0D +// **/=0D +=0D +=0D +#string STR_MODULE_ABSTRACT #language en-US "Installs RISC-V C= PU Architecture Protocol"=0D +=0D +#string STR_MODULE_DESCRIPTION #language en-US "RISC-V CPU driver= installs CPU Architecture Protocol."=0D +=0D diff --git a/Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxeExtra.uni b= /Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxeExtra.uni new file mode 100644 index 0000000000..6f819f068e --- /dev/null +++ b/Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxeExtra.uni @@ -0,0 +1,14 @@ +// /** @file=0D +// CpuDxe Localized Strings and Content=0D +//=0D +// Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. A= ll rights reserved.
=0D +//=0D +// SPDX-License-Identifier: BSD-2-Clause-Patent=0D +//=0D +// **/=0D +=0D +#string STR_PROPERTIES_MODULE_NAME=0D +#language en-US=0D +"RISC-V Architectural DXE Driver"=0D +=0D +=0D --=20 2.31.1