[PATCH 10/79] ProcessorPkg/SmbiosDxe: Generic SMBIOS DXE driver for RISC-V platforms.

["Abner Chang" <abner.chang@hpe.com>]

(This is migrated from edk2-platforms:Silicon/RISC-V)
RISC-V generic SMBIOS DXE driver for building up SMBIOS type 4, type 7
and type 44 records.

Signed-off-by: Abner Chang <abner.chang@hpe.com>
Co-authored-by: Gilbert Chen <gilbert.chen@hpe.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>
---
 .../Universal/SmbiosDxe/RiscVSmbiosDxe.inf    |  55 +++
 .../Include/ProcessorSpecificHobData.h        |  96 +++++
 .../Include/SmbiosProcessorSpecificData.h     |  57 +++
 .../Universal/SmbiosDxe/RiscVSmbiosDxe.h      |  23 ++
 .../Universal/SmbiosDxe/RiscVSmbiosDxe.c      | 327 ++++++++++++++++++
 .../Universal/SmbiosDxe/RiscVSmbiosDxe.uni    |  12 +
 .../SmbiosDxe/RiscVSmbiosDxeExtra.uni         |  13 +
 7 files changed, 583 insertions(+)
 create mode 100644 Silicon/RISC-V/ProcessorPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.inf
 create mode 100644 Silicon/RISC-V/ProcessorPkg/Include/ProcessorSpecificHobData.h
 create mode 100644 Silicon/RISC-V/ProcessorPkg/Include/SmbiosProcessorSpecificData.h
 create mode 100644 Silicon/RISC-V/ProcessorPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.h
 create mode 100644 Silicon/RISC-V/ProcessorPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.c
 create mode 100644 Silicon/RISC-V/ProcessorPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.uni
 create mode 100644 Silicon/RISC-V/ProcessorPkg/Universal/SmbiosDxe/RiscVSmbiosDxeExtra.uni

diff --git a/Silicon/RISC-V/ProcessorPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.inf b/Silicon/RISC-V/ProcessorPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.inf
new file mode 100644
index 0000000000..0fcfe1d3ad
--- /dev/null
+++ b/Silicon/RISC-V/ProcessorPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.inf
@@ -0,0 +1,55 @@
+## @file
+#  RISC-V SMBIOS DXE module.
+#
+#  Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+  INF_VERSION                    = 0x0001001b
+  BASE_NAME                      = RiscVSmbiosDxe
+  MODULE_UNI_FILE                = RiscVSmbiosDxe.uni
+  FILE_GUID                      = 5FC01647-AADD-42E1-AD99-DF4CB89F5A92
+  MODULE_TYPE                    = DXE_DRIVER
+  VERSION_STRING                 = 1.0
+  ENTRY_POINT                    = RiscVSmbiosBuilderEntry
+
+[Packages]
+  MdeModulePkg/MdeModulePkg.dec
+  MdePkg/MdePkg.dec
+  Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec
+
+[LibraryClasses]
+  BaseLib
+  BaseMemoryLib
+  DebugLib
+  HobLib
+  MemoryAllocationLib
+  UefiBootServicesTableLib
+  UefiDriverEntryPoint
+
+[Sources]
+  RiscVSmbiosDxe.c
+  RiscVSmbiosDxe.h
+
+[Protocols]
+  gEfiSmbiosProtocolGuid        # Consumed
+
+[Guids]
+
+
+[Pcd]
+
+[FixedPcd]
+  gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSmbiosGuidHobGuid
+  gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSmbiosType4GuidHobGuid
+  gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSmbiosType7GuidHobGuid
+  gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSpecificDataGuidHobGuid
+
+[Depex]
+  gEfiSmbiosProtocolGuid
+
+[UserExtensions.TianoCore."ExtraFiles"]
+  RiscVSmbiosDxeExtra.uni
diff --git a/Silicon/RISC-V/ProcessorPkg/Include/ProcessorSpecificHobData.h b/Silicon/RISC-V/ProcessorPkg/Include/ProcessorSpecificHobData.h
new file mode 100644
index 0000000000..2f5847e53e
--- /dev/null
+++ b/Silicon/RISC-V/ProcessorPkg/Include/ProcessorSpecificHobData.h
@@ -0,0 +1,96 @@
+/** @file
+  Definition of Processor Specific Data HOB.
+
+  Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+#ifndef RISC_V_PROCESSOR_SPECIFIC_HOB_DATA_H_
+#define RISC_V_PROCESSOR_SPECIFIC_HOB_DATA_H_
+
+#include <Uefi.h>
+#include <IndustryStandard/SmBios.h>
+#include <SmbiosProcessorSpecificData.h>
+
+#define TO_BE_FILLED 0
+#define TO_BE_FILLED_BY_VENDOR 0
+#define TO_BE_FILLED_BY_RISC_V_SMBIOS_DXE_DRIVER 0
+#define TO_BE_FILLED_BY_CODE 0
+
+#pragma pack(1)
+
+///
+/// RISC-V processor specific data HOB
+///
+typedef struct {
+  EFI_GUID ParentPrcessorGuid;
+  UINTN    ParentProcessorUid;
+  EFI_GUID CoreGuid;
+  VOID     *Context;        // The additional information of this core which
+                            // built in PEI phase and carried to DXE phase.
+                            // The content is pocessor or platform specific.
+  SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA ProcessorSpecificData;
+} RISC_V_PROCESSOR_SPECIFIC_HOB_DATA;
+
+///
+/// RISC-V SMBIOS type 4 (Processor) GUID data HOB
+///
+typedef struct {
+  EFI_GUID           PrcessorGuid;
+  UINTN              ProcessorUid;
+  SMBIOS_TABLE_TYPE4 SmbiosType4Processor;
+  UINT16             EndingZero;
+} RISC_V_PROCESSOR_TYPE4_HOB_DATA;
+
+#define RISC_V_CACHE_INFO_NOT_PROVIDED 0xFFFF
+
+#define RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_MASK 0x7
+   #define RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_1 0x01
+   #define RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_2 0x02
+   #define RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_3 0x03
+
+#define RISC_V_CACHE_CONFIGURATION_SOCKET_BIT_POSITION 3
+#define RISC_V_CACHE_CONFIGURATION_SOCKET_MASK (0x1 << RISC_V_CACHE_CONFIGURATION_SOCKET_BIT_POSITION)
+  #define RISC_V_CACHE_CONFIGURATION_SOCKET_SOCKETED (0x1 << RISC_V_CACHE_CONFIGURATION_SOCKET_BIT_POSITION)
+
+#define RISC_V_CACHE_CONFIGURATION_LOCATION_BIT_POSITION 5
+#define RISC_V_CACHE_CONFIGURATION_LOCATION_MASK (0x3 << RISC_V_CACHE_CONFIGURATION_LOCATION_BIT_POSITION)
+  #define RISC_V_CACHE_CONFIGURATION_LOCATION_INTERNAL (0x0 << RISC_V_CACHE_CONFIGURATION_LOCATION_BIT_POSITION)
+  #define RISC_V_CACHE_CONFIGURATION_LOCATION_EXTERNAL (0x1 << RISC_V_CACHE_CONFIGURATION_LOCATION_BIT_POSITION)
+  #define RISC_V_CACHE_CONFIGURATION_LOCATION_RESERVED (0x2 << RISC_V_CACHE_CONFIGURATION_LOCATION_BIT_POSITION)
+  #define RISC_V_CACHE_CONFIGURATION_LOCATION_UNKNOWN  (0x3 << RISC_V_CACHE_CONFIGURATION_LOCATION_BIT_POSITION)
+
+#define RISC_V_CACHE_CONFIGURATION_ENABLE_BIT_POSITION 7
+#define RISC_V_CACHE_CONFIGURATION_ENABLE_MASK       (0x1 << RISC_V_CACHE_CONFIGURATION_ENABLE_BIT_POSITION)
+  #define RISC_V_CACHE_CONFIGURATION_ENABLED           (0x1 << RISC_V_CACHE_CONFIGURATION_ENABLE_BIT_POSITION)
+
+#define RISC_V_CACHE_CONFIGURATION_MODE_BIT_POSITION 8
+#define RISC_V_CACHE_CONFIGURATION_MODE_MASK       (0x3 << RISC_V_CACHE_CONFIGURATION_MODE_BIT_POSITION)
+  #define RISC_V_CACHE_CONFIGURATION_MODE_WT       (0x0 << RISC_V_CACHE_CONFIGURATION_MODE_BIT_POSITION)
+  #define RISC_V_CACHE_CONFIGURATION_MODE_WB       (0x1 << RISC_V_CACHE_CONFIGURATION_MODE_BIT_POSITION)
+  #define RISC_V_CACHE_CONFIGURATION_MODE_VARIES   (0x2 << RISC_V_CACHE_CONFIGURATION_MODE_BIT_POSITION)
+  #define RISC_V_CACHE_CONFIGURATION_MODE_UNKNOWN  (0x3 << RISC_V_CACHE_CONFIGURATION_MODE_BIT_POSITION)
+///
+/// RISC-V SMBIOS type 7 (Cache) GUID data HOB
+///
+typedef struct {
+  EFI_GUID           PrcessorGuid;
+  UINTN              ProcessorUid;
+  SMBIOS_TABLE_TYPE7 SmbiosType7Cache;
+  UINT16             EndingZero;
+} RISC_V_PROCESSOR_TYPE7_HOB_DATA;
+
+///
+/// RISC-V SMBIOS type 7 (Cache) GUID data HOB
+///
+typedef struct {
+  RISC_V_PROCESSOR_TYPE4_HOB_DATA *Processor;
+  RISC_V_PROCESSOR_TYPE7_HOB_DATA *L1Cache;
+  RISC_V_PROCESSOR_TYPE7_HOB_DATA *L2Cache;
+  RISC_V_PROCESSOR_TYPE7_HOB_DATA *L3Cache;
+} RISC_V_PROCESSOR_SMBIOS_HOB_DATA;
+
+#pragma pack()
+
+#endif
diff --git a/Silicon/RISC-V/ProcessorPkg/Include/SmbiosProcessorSpecificData.h b/Silicon/RISC-V/ProcessorPkg/Include/SmbiosProcessorSpecificData.h
new file mode 100644
index 0000000000..81e48cd068
--- /dev/null
+++ b/Silicon/RISC-V/ProcessorPkg/Include/SmbiosProcessorSpecificData.h
@@ -0,0 +1,57 @@
+/** @file
+  Industry Standard Definitions of RISC-V Processor Specific data defined in
+  below link for complaiant with SMBIOS Table Specification v3.3.0.
+  https://github.com/riscv/riscv-smbios
+
+  Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+#ifndef SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA_H_
+#define SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA_H_
+
+#include <IndustryStandard/SmBios.h>
+#include <RiscVImpl.h>
+
+#pragma pack(1)
+
+typedef enum{
+  RegisterUnsupported = 0x00,
+  RegisterLen32       = 0x01,
+  RegisterLen64       = 0x02,
+  RegisterLen128      = 0x03
+} RISC_V_REGISTER_LENGTH;
+
+#define SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA_REVISION 0x100
+
+#define SMBIOS_RISC_V_PSD_MACHINE_MODE_SUPPORTED    (0x01 << 0)
+#define SMBIOS_RISC_V_PSD_SUPERVISOR_MODE_SUPPORTED (0x01 << 2)
+#define SMBIOS_RISC_V_PSD_USER_MODE_SUPPORTED       (0x01 << 3)
+#define SMBIOS_RISC_V_PSD_DEBUG_MODE_SUPPORTED      (0x01 << 7)
+
+///
+/// RISC-V processor specific data for SMBIOS type 44
+///
+typedef struct {
+  UINT16            Revision;
+  UINT8             Length;
+  RISCV_UINT128     HartId;
+  UINT8             BootHartId;
+  RISCV_UINT128     MachineVendorId;
+  RISCV_UINT128     MachineArchId;
+  RISCV_UINT128     MachineImplId;
+  UINT32            InstSetSupported;
+  UINT8             PrivilegeModeSupported;
+  RISCV_UINT128     MModeExcepDelegation;
+  RISCV_UINT128     MModeInterruptDelegation;
+  UINT8             HartXlen;
+  UINT8             MachineModeXlen;
+  UINT8             Reserved;
+  UINT8             SupervisorModeXlen;
+  UINT8             UserModeXlen;
+} SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA;
+
+#pragma pack()
+#endif
+
diff --git a/Silicon/RISC-V/ProcessorPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.h b/Silicon/RISC-V/ProcessorPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.h
new file mode 100644
index 0000000000..1072877ad8
--- /dev/null
+++ b/Silicon/RISC-V/ProcessorPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.h
@@ -0,0 +1,23 @@
+/** @file
+  RISC-V SMBIOS Builder DXE module header file.
+
+  Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef RISC_V_SMBIOS_DXE_H_
+#define RISC_V_SMBIOS_DXE_H_
+
+#include <PiDxe.h>
+#include <Protocol/Smbios.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/HobLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <ProcessorSpecificHobData.h>
+#include <SmbiosProcessorSpecificData.h>
+#endif
+
diff --git a/Silicon/RISC-V/ProcessorPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.c b/Silicon/RISC-V/ProcessorPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.c
new file mode 100644
index 0000000000..6079513a55
--- /dev/null
+++ b/Silicon/RISC-V/ProcessorPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.c
@@ -0,0 +1,327 @@
+/** @file
+  RISC-V generic SMBIOS DXE driver to build up SMBIOS type 4, type 7 and type 44 records.
+
+  Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "RiscVSmbiosDxe.h"
+
+STATIC EFI_SMBIOS_PROTOCOL   *mSmbios;
+
+/**
+  This function builds SMBIOS type 7 record according to
+  the given  RISC_V_PROCESSOR_TYPE7_HOB_DATA.
+
+  @param Type4HobData       Pointer to RISC_V_PROCESSOR_TYPE4_HOB_DATA
+  @param Type7DataHob       Pointer to RISC_V_PROCESSOR_TYPE7_HOB_DATA
+  @param SmbiosHandle       Pointer to SMBIOS_HANDLE
+
+  @retval EFI_STATUS
+
+**/
+STATIC
+EFI_STATUS
+BuildSmbiosType7 (
+ IN RISC_V_PROCESSOR_TYPE4_HOB_DATA *Type4HobData,
+ IN RISC_V_PROCESSOR_TYPE7_HOB_DATA *Type7DataHob,
+ OUT SMBIOS_HANDLE *SmbiosHandle
+)
+{
+  EFI_STATUS Status;
+  SMBIOS_HANDLE Handle;
+
+  if (!CompareGuid (&Type4HobData->PrcessorGuid, &Type7DataHob->PrcessorGuid) ||
+    Type4HobData->ProcessorUid != Type7DataHob->ProcessorUid) {
+    return EFI_INVALID_PARAMETER;
+  }
+  Handle = SMBIOS_HANDLE_PI_RESERVED;
+  Type7DataHob->SmbiosType7Cache.Hdr.Type = SMBIOS_TYPE_CACHE_INFORMATION;
+  Type7DataHob->SmbiosType7Cache.Hdr.Length = sizeof(SMBIOS_TABLE_TYPE7);
+  Type7DataHob->SmbiosType7Cache.Hdr.Handle = 0;
+  Type7DataHob->EndingZero = 0;
+  Status = mSmbios->Add (mSmbios, NULL, &Handle, &Type7DataHob->SmbiosType7Cache.Hdr);
+  if (EFI_ERROR(Status)) {
+    DEBUG ((DEBUG_ERROR, "%a: Fail to add SMBIOS Type 7\n", __FUNCTION__));
+    return Status;
+  }
+  DEBUG ((DEBUG_INFO, "SMBIOS Type 7 was added. SMBIOS Handle: 0x%x\n", Handle));
+  DEBUG ((DEBUG_VERBOSE, "     Cache belone to processor GUID: %g\n", &Type7DataHob->PrcessorGuid));
+  DEBUG ((DEBUG_VERBOSE, "     Cache belone processor  UID: %d\n", Type7DataHob->ProcessorUid));
+  DEBUG ((DEBUG_VERBOSE, "     ==============================\n"));
+  DEBUG ((DEBUG_VERBOSE, "     Socket Designation: %d\n", Type7DataHob->SmbiosType7Cache.SocketDesignation));
+  DEBUG ((DEBUG_VERBOSE, "     Cache Configuration: 0x%x\n", Type7DataHob->SmbiosType7Cache.CacheConfiguration));
+  DEBUG ((DEBUG_VERBOSE, "     Maximum Cache Size: 0x%x\n", Type7DataHob->SmbiosType7Cache.MaximumCacheSize));
+  DEBUG ((DEBUG_VERBOSE, "     Installed Size: 0x%x\n", Type7DataHob->SmbiosType7Cache.InstalledSize));
+  DEBUG ((DEBUG_VERBOSE, "     Supported SRAM Type: 0x%x\n", Type7DataHob->SmbiosType7Cache.SupportedSRAMType));
+  DEBUG ((DEBUG_VERBOSE, "     Current SRAMT ype: 0x%x\n", Type7DataHob->SmbiosType7Cache.CurrentSRAMType));
+  DEBUG ((DEBUG_VERBOSE, "     Cache Speed: 0x%x\n", Type7DataHob->SmbiosType7Cache.CacheSpeed));
+  DEBUG ((DEBUG_VERBOSE, "     Error Correction Type: 0x%x\n", Type7DataHob->SmbiosType7Cache.ErrorCorrectionType));
+  DEBUG ((DEBUG_VERBOSE, "     System Cache Type: 0x%x\n", Type7DataHob->SmbiosType7Cache.SystemCacheType));
+  DEBUG ((DEBUG_VERBOSE, "     Associativity: 0x%x\n", Type7DataHob->SmbiosType7Cache.Associativity));
+
+  *SmbiosHandle = Handle;
+  return EFI_SUCCESS;
+}
+
+/**
+  This function builds SMBIOS type 4 record according to
+  the given  RISC_V_PROCESSOR_TYPE4_HOB_DATA.
+
+  @param Type4HobData       Pointer to RISC_V_PROCESSOR_TYPE4_HOB_DATA
+  @param SmbiosHandle       Pointer to SMBIOS_HANDLE
+
+  @retval EFI_STATUS
+
+**/
+STATIC
+EFI_STATUS
+BuildSmbiosType4 (
+  IN RISC_V_PROCESSOR_TYPE4_HOB_DATA *Type4HobData,
+  OUT SMBIOS_HANDLE *SmbiosHandle
+  )
+{
+  EFI_HOB_GUID_TYPE *GuidHob;
+  RISC_V_PROCESSOR_TYPE7_HOB_DATA *Type7HobData;
+  SMBIOS_HANDLE Cache;
+  SMBIOS_HANDLE Processor;
+  EFI_STATUS Status;
+
+  DEBUG ((DEBUG_INFO, "Building Type 4.\n"));
+  DEBUG ((DEBUG_INFO, "    Processor GUID: %g\n", &Type4HobData->PrcessorGuid));
+  DEBUG ((DEBUG_INFO, "    Processor UUID: %d\n", Type4HobData->ProcessorUid));
+
+  Type4HobData->SmbiosType4Processor.L1CacheHandle = RISC_V_CACHE_INFO_NOT_PROVIDED;
+  Type4HobData->SmbiosType4Processor.L2CacheHandle = RISC_V_CACHE_INFO_NOT_PROVIDED;
+  Type4HobData->SmbiosType4Processor.L3CacheHandle = RISC_V_CACHE_INFO_NOT_PROVIDED;
+  GuidHob = (EFI_HOB_GUID_TYPE *)GetFirstGuidHob ((EFI_GUID *)PcdGetPtr(PcdProcessorSmbiosType7GuidHobGuid));
+  if (GuidHob == NULL) {
+    DEBUG ((DEBUG_ERROR, "No RISC-V SMBIOS Type7 data HOB found.\n"));
+    return EFI_NOT_FOUND;
+  }
+  //
+  // Go through each RISC_V_PROCESSOR_TYPE4_HOB_DATA for multiple processors.
+  //
+  do {
+    Type7HobData = (RISC_V_PROCESSOR_TYPE7_HOB_DATA *)GET_GUID_HOB_DATA (GuidHob);
+    Status = BuildSmbiosType7 (Type4HobData, Type7HobData, &Cache);
+    if (EFI_ERROR (Status)) {
+      return Status;
+    }
+    if ((Type7HobData->SmbiosType7Cache.SystemCacheType & RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_MASK) ==
+        RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_1) {
+      Type4HobData->SmbiosType4Processor.L1CacheHandle = Cache;
+    } else if ((Type7HobData->SmbiosType7Cache.SystemCacheType & RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_MASK) ==
+        RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_2) {
+      Type4HobData->SmbiosType4Processor.L2CacheHandle = Cache;
+    } else if ((Type7HobData->SmbiosType7Cache.SystemCacheType & RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_MASK) ==
+        RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_3) {
+      Type4HobData->SmbiosType4Processor.L3CacheHandle = Cache;
+    } else {
+      DEBUG ((DEBUG_ERROR, "Improper cache level of SMBIOS handle %d\n", Cache));
+    }
+    GuidHob = GetNextGuidHob((EFI_GUID *)PcdGetPtr(PcdProcessorSmbiosType7GuidHobGuid), GET_NEXT_HOB(GuidHob));
+  } while (GuidHob != NULL);
+
+  //
+  // Build SMBIOS Type 4 record
+  //
+  Processor = SMBIOS_HANDLE_PI_RESERVED;
+  Type4HobData->SmbiosType4Processor.Hdr.Type = SMBIOS_TYPE_PROCESSOR_INFORMATION;
+  Type4HobData->SmbiosType4Processor.Hdr.Length = sizeof(SMBIOS_TABLE_TYPE4);
+  Type4HobData->SmbiosType4Processor.Hdr.Handle = 0;
+  Type4HobData->EndingZero = 0;
+  Status = mSmbios->Add (mSmbios, NULL, &Processor, &Type4HobData->SmbiosType4Processor.Hdr);
+  if (EFI_ERROR(Status)) {
+    DEBUG ((DEBUG_ERROR, "Fail to add SMBIOS Type 4\n"));
+    return Status;
+  }
+  DEBUG ((DEBUG_INFO, "SMBIOS Type 4 was added. SMBIOS Handle: 0x%x\n", Processor));
+  DEBUG ((DEBUG_VERBOSE, "     Socket StringID: %d\n", Type4HobData->SmbiosType4Processor.Socket));
+  DEBUG ((DEBUG_VERBOSE, "     Processor Type: 0x%x\n", Type4HobData->SmbiosType4Processor.ProcessorType));
+  DEBUG ((DEBUG_VERBOSE, "     Processor Family: 0x%x\n", Type4HobData->SmbiosType4Processor.ProcessorFamily));
+  DEBUG ((DEBUG_VERBOSE, "     Processor Manufacture StringID: %d\n", Type4HobData->SmbiosType4Processor.ProcessorManufacture));
+  DEBUG ((DEBUG_VERBOSE, "     Processor Id: 0x%x:0x%x\n", \
+          Type4HobData->SmbiosType4Processor.ProcessorId.Signature, Type4HobData->SmbiosType4Processor.ProcessorId.FeatureFlags));
+  DEBUG ((DEBUG_VERBOSE, "     Processor Version StringID: %d\n", Type4HobData->SmbiosType4Processor.ProcessorVersion));
+  DEBUG ((DEBUG_VERBOSE, "     Voltage: 0x%x\n", Type4HobData->SmbiosType4Processor.Voltage));
+  DEBUG ((DEBUG_VERBOSE, "     External Clock: 0x%x\n", Type4HobData->SmbiosType4Processor.ExternalClock));
+  DEBUG ((DEBUG_VERBOSE, "     Max Speed: 0x%x\n", Type4HobData->SmbiosType4Processor.MaxSpeed));
+  DEBUG ((DEBUG_VERBOSE, "     Current Speed: 0x%x\n", Type4HobData->SmbiosType4Processor.CurrentSpeed));
+  DEBUG ((DEBUG_VERBOSE, "     Status: 0x%x\n", Type4HobData->SmbiosType4Processor.Status));
+  DEBUG ((DEBUG_VERBOSE, "     ProcessorUpgrade: 0x%x\n", Type4HobData->SmbiosType4Processor.ProcessorUpgrade));
+  DEBUG ((DEBUG_VERBOSE, "     L1 Cache Handle: 0x%x\n", Type4HobData->SmbiosType4Processor.L1CacheHandle));
+  DEBUG ((DEBUG_VERBOSE, "     L2 Cache Handle: 0x%x\n",Type4HobData->SmbiosType4Processor.L2CacheHandle));
+  DEBUG ((DEBUG_VERBOSE, "     L3 Cache Handle: 0x%x\n", Type4HobData->SmbiosType4Processor.L3CacheHandle));
+  DEBUG ((DEBUG_VERBOSE, "     Serial Number StringID: %d\n", Type4HobData->SmbiosType4Processor.SerialNumber));
+  DEBUG ((DEBUG_VERBOSE, "     Asset Tag StringID: %d\n", Type4HobData->SmbiosType4Processor.AssetTag));
+  DEBUG ((DEBUG_VERBOSE, "     Part Number StringID: %d\n", Type4HobData->SmbiosType4Processor.PartNumber));
+  DEBUG ((DEBUG_VERBOSE, "     Core Count: %d\n", Type4HobData->SmbiosType4Processor.CoreCount));
+  DEBUG ((DEBUG_VERBOSE, "     Enabled CoreCount: %d\n", Type4HobData->SmbiosType4Processor.EnabledCoreCount));
+  DEBUG ((DEBUG_VERBOSE, "     Thread Count: %d\n", Type4HobData->SmbiosType4Processor.ThreadCount));
+  DEBUG ((DEBUG_VERBOSE, "     Processor Characteristics: 0x%x\n", Type4HobData->SmbiosType4Processor.ProcessorCharacteristics));
+  DEBUG ((DEBUG_VERBOSE, "     Processor Family2: 0x%x\n", Type4HobData->SmbiosType4Processor.ProcessorFamily2));
+  DEBUG ((DEBUG_VERBOSE, "     Core Count 2: %d\n", Type4HobData->SmbiosType4Processor.CoreCount2));
+  DEBUG ((DEBUG_VERBOSE, "     Enabled CoreCount : %d\n", Type4HobData->SmbiosType4Processor.EnabledCoreCount2));
+  DEBUG ((DEBUG_VERBOSE, "     Thread Count 2: %d\n", Type4HobData->SmbiosType4Processor.ThreadCount2));
+
+  *SmbiosHandle = Processor;
+  return EFI_SUCCESS;
+}
+
+/**
+  This function builds SMBIOS type 44 record according..
+
+  @param Type4HobData      Pointer to RISC_V_PROCESSOR_TYPE4_HOB_DATA
+  @param Type4Handle       SMBIOS handle of type 4
+
+  @retval EFI_STATUS
+
+**/
+EFI_STATUS
+BuildSmbiosType44 (
+  IN RISC_V_PROCESSOR_TYPE4_HOB_DATA *Type4HobData,
+  IN SMBIOS_HANDLE Type4Handle
+  )
+{
+  EFI_HOB_GUID_TYPE *GuidHob;
+  RISC_V_PROCESSOR_SPECIFIC_HOB_DATA *ProcessorSpecificData;
+  SMBIOS_HANDLE RiscVType44;
+  SMBIOS_TABLE_TYPE44 *Type44Ptr;
+  EFI_STATUS Status;
+
+  DEBUG ((DEBUG_INFO, "Building Type 44 for...\n"));
+  DEBUG ((DEBUG_VERBOSE, "     Processor GUID: %g\n", &Type4HobData->PrcessorGuid));
+  DEBUG ((DEBUG_VERBOSE, "     Processor UUID: %d\n", Type4HobData->ProcessorUid));
+
+  GuidHob = (EFI_HOB_GUID_TYPE *)GetFirstGuidHob ((EFI_GUID *)PcdGetPtr(PcdProcessorSpecificDataGuidHobGuid));
+  if (GuidHob == NULL) {
+    DEBUG ((DEBUG_ERROR, "No RISC_V_PROCESSOR_SPECIFIC_HOB_DATA found.\n"));
+    return EFI_NOT_FOUND;
+  }
+  //
+  // Go through each RISC_V_PROCESSOR_SPECIFIC_HOB_DATA for multiple cores.
+  //
+  do {
+    ProcessorSpecificData = (RISC_V_PROCESSOR_SPECIFIC_HOB_DATA *)GET_GUID_HOB_DATA (GuidHob);
+    if (!CompareGuid (&ProcessorSpecificData->ParentPrcessorGuid, &Type4HobData->PrcessorGuid) ||
+      ProcessorSpecificData->ParentProcessorUid != Type4HobData->ProcessorUid) {
+      GuidHob = GetNextGuidHob((EFI_GUID *)PcdGetPtr(PcdProcessorSpecificDataGuidHobGuid), GET_NEXT_HOB(GuidHob));
+      if (GuidHob == NULL) {
+        break;
+      }
+      continue;
+    }
+
+    DEBUG ((DEBUG_VERBOSE, "================================\n"));
+    DEBUG ((DEBUG_VERBOSE, "Core GUID: %g\n", &ProcessorSpecificData->CoreGuid));
+
+    Type44Ptr = AllocateZeroPool(sizeof(SMBIOS_TABLE_TYPE44) + sizeof(SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA) + 2); // Two ending zero.
+    if (Type44Ptr == NULL) {
+      return EFI_NOT_FOUND;
+    }
+    Type44Ptr->Hdr.Type = SMBIOS_TYPE_PROCESSOR_ADDITIONAL_INFORMATION;
+    Type44Ptr->Hdr.Handle = 0;
+    Type44Ptr->Hdr.Length = sizeof(SMBIOS_TABLE_TYPE44) + sizeof(SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA);
+    Type44Ptr->RefHandle = Type4Handle;
+    Type44Ptr->ProcessorSpecificBlock.Length = sizeof(SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA);
+    Type44Ptr->ProcessorSpecificBlock.ProcessorArchType = Type4HobData->SmbiosType4Processor.ProcessorFamily2 -
+                                                          ProcessorFamilyRiscvRV32 + \
+                                                          ProcessorSpecificBlockArchTypeRiscVRV32;
+    CopyMem ((VOID *)(Type44Ptr + 1), (VOID *)&ProcessorSpecificData->ProcessorSpecificData, sizeof (SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA));
+
+    DEBUG ((DEBUG_VERBOSE, "Core type: %d\n", Type44Ptr->ProcessorSpecificBlock.ProcessorArchType));
+    DEBUG ((DEBUG_VERBOSE, "     HartId = 0x%x\n", ((SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA *)(Type44Ptr + 1))->HartId.Value64_L));
+    DEBUG ((DEBUG_VERBOSE, "     Is Boot Hart? = 0x%x\n", ((SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA *)(Type44Ptr + 1))->BootHartId));
+    DEBUG ((DEBUG_VERBOSE, "     PrivilegeModeSupported = 0x%x\n", ((SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA *)(Type44Ptr + 1))->PrivilegeModeSupported));
+    DEBUG ((DEBUG_VERBOSE, "     MModeExcepDelegation = 0x%x\n", ((SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA *)(Type44Ptr + 1))->MModeExcepDelegation.Value64_L));
+    DEBUG ((DEBUG_VERBOSE, "     MModeInterruptDelegation = 0x%x\n", ((SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA *)(Type44Ptr + 1))->MModeInterruptDelegation.Value64_L));
+    DEBUG ((DEBUG_VERBOSE, "     HartXlen = 0x%x\n", ((SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA *)(Type44Ptr + 1))->HartXlen));
+    DEBUG ((DEBUG_VERBOSE, "     MachineModeXlen = 0x%x\n", ((SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA *)(Type44Ptr + 1))->MachineModeXlen));
+    DEBUG ((DEBUG_VERBOSE, "     SupervisorModeXlen = 0x%x\n", ((SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA *)(Type44Ptr + 1))->SupervisorModeXlen));
+    DEBUG ((DEBUG_VERBOSE, "     UserModeXlen = 0x%x\n", ((SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA *)(Type44Ptr + 1))->UserModeXlen));
+    DEBUG ((DEBUG_VERBOSE, "     InstSetSupported = 0x%x\n", ((SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA *)(Type44Ptr + 1))->InstSetSupported));
+    DEBUG ((DEBUG_VERBOSE, "     MachineVendorId = 0x%x\n", ((SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA *)(Type44Ptr + 1))->MachineVendorId.Value64_L));
+    DEBUG ((DEBUG_VERBOSE, "     MachineArchId = 0x%x\n", ((SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA *)(Type44Ptr + 1))->MachineArchId.Value64_L));
+    DEBUG ((DEBUG_VERBOSE, "     MachineImplId = 0x%x\n", ((SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA *)(Type44Ptr + 1))->MachineImplId.Value64_L));
+
+    //
+    // Add to SMBIOS table.
+    //
+    RiscVType44 = SMBIOS_HANDLE_PI_RESERVED;
+    Status = mSmbios->Add (mSmbios, NULL, &RiscVType44, &Type44Ptr->Hdr);
+    if (EFI_ERROR(Status)) {
+      DEBUG ((DEBUG_ERROR, "Fail to add SMBIOS Type 44\n"));
+      return Status;
+    }
+    DEBUG ((DEBUG_INFO, "SMBIOS Type 44 was added. SMBIOS Handle: 0x%x\n", RiscVType44));
+
+    GuidHob = GetNextGuidHob((EFI_GUID *)PcdGetPtr(PcdProcessorSpecificDataGuidHobGuid), GET_NEXT_HOB(GuidHob));
+  } while (GuidHob != NULL);
+  return EFI_SUCCESS;
+}
+
+/**
+  Entry point of RISC-V SMBIOS builder.
+
+  @param ImageHandle     Image handle this driver.
+  @param SystemTable     Pointer to the System Table.
+
+  @retval EFI_SUCCESS           Thread can be successfully created
+  @retval EFI_OUT_OF_RESOURCES  Cannot allocate protocol data structure
+  @retval EFI_DEVICE_ERROR      Cannot create the thread
+
+**/
+EFI_STATUS
+EFIAPI
+RiscVSmbiosBuilderEntry (
+  IN EFI_HANDLE                            ImageHandle,
+  IN EFI_SYSTEM_TABLE                      *SystemTable
+  )
+{
+  EFI_STATUS Status;
+  EFI_HOB_GUID_TYPE *GuidHob;
+  RISC_V_PROCESSOR_TYPE4_HOB_DATA *Type4HobData;
+  SMBIOS_HANDLE Processor;
+
+  DEBUG ((DEBUG_INFO, "%a: entry\n", __FUNCTION__));
+
+  Status = gBS->LocateProtocol (
+                  &gEfiSmbiosProtocolGuid,
+                  NULL,
+                  (VOID **)&mSmbios
+                  );
+  if (EFI_ERROR (Status)) {
+    DEBUG ((DEBUG_ERROR, "Locate SMBIOS Protocol fail\n"));
+    return Status;
+  }
+  GuidHob = (EFI_HOB_GUID_TYPE *)GetFirstGuidHob ((EFI_GUID *)PcdGetPtr(PcdProcessorSmbiosType4GuidHobGuid));
+  if (GuidHob == NULL) {
+    DEBUG ((DEBUG_ERROR, "No RISC-V SMBIOS information found.\n"));
+    return EFI_NOT_FOUND;
+  }
+  Type4HobData = (RISC_V_PROCESSOR_TYPE4_HOB_DATA *)GET_GUID_HOB_DATA (GuidHob);
+  Status = EFI_NOT_FOUND;
+  //
+  // Go through each RISC_V_PROCESSOR_TYPE4_HOB_DATA for multiple processors.
+  //
+  do {
+    Status = BuildSmbiosType4 (Type4HobData, &Processor);
+    if (EFI_ERROR (Status)) {
+      DEBUG ((DEBUG_ERROR, "No RISC-V SMBIOS type 4 created.\n"));
+      ASSERT (FALSE);
+    }
+    Status = BuildSmbiosType44 (Type4HobData, Processor);
+    if (EFI_ERROR (Status)) {
+      DEBUG ((DEBUG_ERROR, "No RISC-V SMBIOS type 44 found.\n"));
+      ASSERT (FALSE);
+    }
+
+    GuidHob = GetNextGuidHob((EFI_GUID *)PcdGetPtr(PcdProcessorSmbiosType4GuidHobGuid), GET_NEXT_HOB(GuidHob));
+  } while (GuidHob != NULL);
+  DEBUG ((DEBUG_INFO, "%a: exit\n", __FUNCTION__));
+  return Status;
+}
+
diff --git a/Silicon/RISC-V/ProcessorPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.uni b/Silicon/RISC-V/ProcessorPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.uni
new file mode 100644
index 0000000000..1bffe09fe7
--- /dev/null
+++ b/Silicon/RISC-V/ProcessorPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.uni
@@ -0,0 +1,12 @@
+// /** @file
+//
+// Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+//
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+// **/
+
+#string STR_MODULE_ABSTRACT             #language en-US "RISC-V Processor SMBIOS Builder"
+
+#string STR_MODULE_DESCRIPTION          #language en-US "Build RISC-V Processor SMBIOS Type 4, 7, 44 records."
+
diff --git a/Silicon/RISC-V/ProcessorPkg/Universal/SmbiosDxe/RiscVSmbiosDxeExtra.uni b/Silicon/RISC-V/ProcessorPkg/Universal/SmbiosDxe/RiscVSmbiosDxeExtra.uni
new file mode 100644
index 0000000000..4b37ca2bbb
--- /dev/null
+++ b/Silicon/RISC-V/ProcessorPkg/Universal/SmbiosDxe/RiscVSmbiosDxeExtra.uni
@@ -0,0 +1,13 @@
+// /** @file
+// RISC-V SMBIOS Builder Localized Strings and Content
+//
+// Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+//
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+// **/
+
+#string STR_PROPERTIES_MODULE_NAME
+#language en-US
+"RISC-V SMBIOS Record Builder DXE Driver"
+
-- 
2.31.1