From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mx0b-002e3701.pphosted.com (mx0b-002e3701.pphosted.com [148.163.143.35]) by mx.groups.io with SMTP id smtpd.web08.2746.1641618752347509274 for ; Fri, 07 Jan 2022 21:12:32 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@hpe.com header.s=pps0720 header.b=gXnw3HMm; spf=permerror, err=parse error for token &{10 18 %{ir}.%{v}.%{d}.spf.has.pphosted.com}: invalid domain name (domain: hpe.com, ip: 148.163.143.35, mailfrom: prvs=000704d8ca=abner.chang@hpe.com) Received: from pps.filterd (m0150244.ppops.net [127.0.0.1]) by mx0b-002e3701.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 208455SC007180 for ; Sat, 8 Jan 2022 05:12:31 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=hpe.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : content-transfer-encoding : mime-version; s=pps0720; bh=pQNmfa29GVl4T4rK0jN/Vff/6emVGaMvPmzkfqvZ9x4=; b=gXnw3HMmdaUpgkc5MzEjy12u15yqnayal/vJMasTqfMOW2gER/AyK+SnRK6NfqHUz795 3TixsbjmNcuAnGAweIEJdubRGHmKnXhlz0k0T4TohwV2BkH4OW4YsyslF91ONGJKAMbj 8E5EiNo4zH6BaiarIZHrpR1WmzOU2Gwxra/WX8pLqxn49r9x1SJR3aWdulVrzWfnoH/b NbB6ib6cwF0QdXFbShzBS8Bor7ykUQFB42xUIJSi2qYMsQO+yRUrUmC+u93F0HeKInKf MANPdEHgjdb1+/4wUHS/21OlBPhPW0yad7A/z1CUrN5S8aJoXFjvbDAtpVbCjPdVTB11 qw== Received: from g2t2354.austin.hpe.com (g2t2354.austin.hpe.com [15.233.44.27]) by mx0b-002e3701.pphosted.com (PPS) with ESMTPS id 3df395r7r2-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Sat, 08 Jan 2022 05:12:31 +0000 Received: from g2t2360.austin.hpecorp.net (g2t2360.austin.hpecorp.net [16.196.225.135]) by g2t2354.austin.hpe.com (Postfix) with ESMTP id B421EA0 for ; Sat, 8 Jan 2022 05:12:30 +0000 (UTC) Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.229]) by g2t2360.austin.hpecorp.net (Postfix) with ESMTP id 045EE36; Sat, 8 Jan 2022 05:12:29 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com Subject: [PATCH 10/79] ProcessorPkg/SmbiosDxe: Generic SMBIOS DXE driver for RISC-V platforms. Date: Sat, 8 Jan 2022 12:10:30 +0800 Message-Id: <20220108041121.16005-9-abner.chang@hpe.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20220108041121.16005-1-abner.chang@hpe.com> References: <20220108041121.16005-1-abner.chang@hpe.com> X-Proofpoint-ORIG-GUID: 3K_xtP7XSw3JqIIlR7o-hYVRJ_yUwUG2 X-Proofpoint-GUID: 3K_xtP7XSw3JqIIlR7o-hYVRJ_yUwUG2 X-Proofpoint-UnRewURL: 0 URL was un-rewritten MIME-Version: 1.0 X-HPE-SCL: -1 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.790,Hydra:6.0.425,FMLib:17.11.62.513 definitions=2022-01-08_01,2022-01-07_01,2021-12-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 phishscore=0 mlxlogscore=999 adultscore=0 lowpriorityscore=0 suspectscore=0 mlxscore=0 bulkscore=0 priorityscore=1501 clxscore=1015 impostorscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2110150000 definitions=main-2201080036 Content-Transfer-Encoding: quoted-printable (This is migrated from edk2-platforms:Silicon/RISC-V) RISC-V generic SMBIOS DXE driver for building up SMBIOS type 4, type 7 and type 44 records. Signed-off-by: Abner Chang Co-authored-by: Gilbert Chen Reviewed-by: Leif Lindholm Cc: Leif Lindholm Cc: Gilbert Chen --- .../Universal/SmbiosDxe/RiscVSmbiosDxe.inf | 55 +++ .../Include/ProcessorSpecificHobData.h | 96 +++++ .../Include/SmbiosProcessorSpecificData.h | 57 +++ .../Universal/SmbiosDxe/RiscVSmbiosDxe.h | 23 ++ .../Universal/SmbiosDxe/RiscVSmbiosDxe.c | 327 ++++++++++++++++++ .../Universal/SmbiosDxe/RiscVSmbiosDxe.uni | 12 + .../SmbiosDxe/RiscVSmbiosDxeExtra.uni | 13 + 7 files changed, 583 insertions(+) create mode 100644 Silicon/RISC-V/ProcessorPkg/Universal/SmbiosDxe/RiscVSm= biosDxe.inf create mode 100644 Silicon/RISC-V/ProcessorPkg/Include/ProcessorSpecificHo= bData.h create mode 100644 Silicon/RISC-V/ProcessorPkg/Include/SmbiosProcessorSpec= ificData.h create mode 100644 Silicon/RISC-V/ProcessorPkg/Universal/SmbiosDxe/RiscVSm= biosDxe.h create mode 100644 Silicon/RISC-V/ProcessorPkg/Universal/SmbiosDxe/RiscVSm= biosDxe.c create mode 100644 Silicon/RISC-V/ProcessorPkg/Universal/SmbiosDxe/RiscVSm= biosDxe.uni create mode 100644 Silicon/RISC-V/ProcessorPkg/Universal/SmbiosDxe/RiscVSm= biosDxeExtra.uni diff --git a/Silicon/RISC-V/ProcessorPkg/Universal/SmbiosDxe/RiscVSmbiosDxe= .inf b/Silicon/RISC-V/ProcessorPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.inf new file mode 100644 index 0000000000..0fcfe1d3ad --- /dev/null +++ b/Silicon/RISC-V/ProcessorPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.inf @@ -0,0 +1,55 @@ +## @file=0D +# RISC-V SMBIOS DXE module.=0D +#=0D +# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
=0D +#=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +##=0D +=0D +[Defines]=0D + INF_VERSION =3D 0x0001001b=0D + BASE_NAME =3D RiscVSmbiosDxe=0D + MODULE_UNI_FILE =3D RiscVSmbiosDxe.uni=0D + FILE_GUID =3D 5FC01647-AADD-42E1-AD99-DF4CB89F5A92= =0D + MODULE_TYPE =3D DXE_DRIVER=0D + VERSION_STRING =3D 1.0=0D + ENTRY_POINT =3D RiscVSmbiosBuilderEntry=0D +=0D +[Packages]=0D + MdeModulePkg/MdeModulePkg.dec=0D + MdePkg/MdePkg.dec=0D + Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec=0D +=0D +[LibraryClasses]=0D + BaseLib=0D + BaseMemoryLib=0D + DebugLib=0D + HobLib=0D + MemoryAllocationLib=0D + UefiBootServicesTableLib=0D + UefiDriverEntryPoint=0D +=0D +[Sources]=0D + RiscVSmbiosDxe.c=0D + RiscVSmbiosDxe.h=0D +=0D +[Protocols]=0D + gEfiSmbiosProtocolGuid # Consumed=0D +=0D +[Guids]=0D +=0D +=0D +[Pcd]=0D +=0D +[FixedPcd]=0D + gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSmbiosGuidHobGuid=0D + gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSmbiosType4GuidHobGuid=0D + gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSmbiosType7GuidHobGuid=0D + gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSpecificDataGuidHobGuid=0D +=0D +[Depex]=0D + gEfiSmbiosProtocolGuid=0D +=0D +[UserExtensions.TianoCore."ExtraFiles"]=0D + RiscVSmbiosDxeExtra.uni=0D diff --git a/Silicon/RISC-V/ProcessorPkg/Include/ProcessorSpecificHobData.h= b/Silicon/RISC-V/ProcessorPkg/Include/ProcessorSpecificHobData.h new file mode 100644 index 0000000000..2f5847e53e --- /dev/null +++ b/Silicon/RISC-V/ProcessorPkg/Include/ProcessorSpecificHobData.h @@ -0,0 +1,96 @@ +/** @file=0D + Definition of Processor Specific Data HOB.=0D +=0D + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All right= s reserved.
=0D +=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +#ifndef RISC_V_PROCESSOR_SPECIFIC_HOB_DATA_H_=0D +#define RISC_V_PROCESSOR_SPECIFIC_HOB_DATA_H_=0D +=0D +#include =0D +#include =0D +#include =0D +=0D +#define TO_BE_FILLED 0=0D +#define TO_BE_FILLED_BY_VENDOR 0=0D +#define TO_BE_FILLED_BY_RISC_V_SMBIOS_DXE_DRIVER 0=0D +#define TO_BE_FILLED_BY_CODE 0=0D +=0D +#pragma pack(1)=0D +=0D +///=0D +/// RISC-V processor specific data HOB=0D +///=0D +typedef struct {=0D + EFI_GUID ParentPrcessorGuid;=0D + UINTN ParentProcessorUid;=0D + EFI_GUID CoreGuid;=0D + VOID *Context; // The additional information of this core whi= ch=0D + // built in PEI phase and carried to DXE phase= .=0D + // The content is pocessor or platform specifi= c.=0D + SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA ProcessorSpecificData;=0D +} RISC_V_PROCESSOR_SPECIFIC_HOB_DATA;=0D +=0D +///=0D +/// RISC-V SMBIOS type 4 (Processor) GUID data HOB=0D +///=0D +typedef struct {=0D + EFI_GUID PrcessorGuid;=0D + UINTN ProcessorUid;=0D + SMBIOS_TABLE_TYPE4 SmbiosType4Processor;=0D + UINT16 EndingZero;=0D +} RISC_V_PROCESSOR_TYPE4_HOB_DATA;=0D +=0D +#define RISC_V_CACHE_INFO_NOT_PROVIDED 0xFFFF=0D +=0D +#define RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_MASK 0x7=0D + #define RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_1 0x01=0D + #define RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_2 0x02=0D + #define RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_3 0x03=0D +=0D +#define RISC_V_CACHE_CONFIGURATION_SOCKET_BIT_POSITION 3=0D +#define RISC_V_CACHE_CONFIGURATION_SOCKET_MASK (0x1 << RISC_V_CACHE_CONFIG= URATION_SOCKET_BIT_POSITION)=0D + #define RISC_V_CACHE_CONFIGURATION_SOCKET_SOCKETED (0x1 << RISC_V_CACHE_= CONFIGURATION_SOCKET_BIT_POSITION)=0D +=0D +#define RISC_V_CACHE_CONFIGURATION_LOCATION_BIT_POSITION 5=0D +#define RISC_V_CACHE_CONFIGURATION_LOCATION_MASK (0x3 << RISC_V_CACHE_CONF= IGURATION_LOCATION_BIT_POSITION)=0D + #define RISC_V_CACHE_CONFIGURATION_LOCATION_INTERNAL (0x0 << RISC_V_CACH= E_CONFIGURATION_LOCATION_BIT_POSITION)=0D + #define RISC_V_CACHE_CONFIGURATION_LOCATION_EXTERNAL (0x1 << RISC_V_CACH= E_CONFIGURATION_LOCATION_BIT_POSITION)=0D + #define RISC_V_CACHE_CONFIGURATION_LOCATION_RESERVED (0x2 << RISC_V_CACH= E_CONFIGURATION_LOCATION_BIT_POSITION)=0D + #define RISC_V_CACHE_CONFIGURATION_LOCATION_UNKNOWN (0x3 << RISC_V_CACH= E_CONFIGURATION_LOCATION_BIT_POSITION)=0D +=0D +#define RISC_V_CACHE_CONFIGURATION_ENABLE_BIT_POSITION 7=0D +#define RISC_V_CACHE_CONFIGURATION_ENABLE_MASK (0x1 << RISC_V_CACHE_= CONFIGURATION_ENABLE_BIT_POSITION)=0D + #define RISC_V_CACHE_CONFIGURATION_ENABLED (0x1 << RISC_V_CACH= E_CONFIGURATION_ENABLE_BIT_POSITION)=0D +=0D +#define RISC_V_CACHE_CONFIGURATION_MODE_BIT_POSITION 8=0D +#define RISC_V_CACHE_CONFIGURATION_MODE_MASK (0x3 << RISC_V_CACHE_CO= NFIGURATION_MODE_BIT_POSITION)=0D + #define RISC_V_CACHE_CONFIGURATION_MODE_WT (0x0 << RISC_V_CACHE_CO= NFIGURATION_MODE_BIT_POSITION)=0D + #define RISC_V_CACHE_CONFIGURATION_MODE_WB (0x1 << RISC_V_CACHE_CO= NFIGURATION_MODE_BIT_POSITION)=0D + #define RISC_V_CACHE_CONFIGURATION_MODE_VARIES (0x2 << RISC_V_CACHE_CO= NFIGURATION_MODE_BIT_POSITION)=0D + #define RISC_V_CACHE_CONFIGURATION_MODE_UNKNOWN (0x3 << RISC_V_CACHE_CO= NFIGURATION_MODE_BIT_POSITION)=0D +///=0D +/// RISC-V SMBIOS type 7 (Cache) GUID data HOB=0D +///=0D +typedef struct {=0D + EFI_GUID PrcessorGuid;=0D + UINTN ProcessorUid;=0D + SMBIOS_TABLE_TYPE7 SmbiosType7Cache;=0D + UINT16 EndingZero;=0D +} RISC_V_PROCESSOR_TYPE7_HOB_DATA;=0D +=0D +///=0D +/// RISC-V SMBIOS type 7 (Cache) GUID data HOB=0D +///=0D +typedef struct {=0D + RISC_V_PROCESSOR_TYPE4_HOB_DATA *Processor;=0D + RISC_V_PROCESSOR_TYPE7_HOB_DATA *L1Cache;=0D + RISC_V_PROCESSOR_TYPE7_HOB_DATA *L2Cache;=0D + RISC_V_PROCESSOR_TYPE7_HOB_DATA *L3Cache;=0D +} RISC_V_PROCESSOR_SMBIOS_HOB_DATA;=0D +=0D +#pragma pack()=0D +=0D +#endif=0D diff --git a/Silicon/RISC-V/ProcessorPkg/Include/SmbiosProcessorSpecificDat= a.h b/Silicon/RISC-V/ProcessorPkg/Include/SmbiosProcessorSpecificData.h new file mode 100644 index 0000000000..81e48cd068 --- /dev/null +++ b/Silicon/RISC-V/ProcessorPkg/Include/SmbiosProcessorSpecificData.h @@ -0,0 +1,57 @@ +/** @file=0D + Industry Standard Definitions of RISC-V Processor Specific data defined = in=0D + below link for complaiant with SMBIOS Table Specification v3.3.0.=0D + https://github.com/riscv/riscv-smbios=0D +=0D + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All right= s reserved.
=0D +=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +#ifndef SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA_H_=0D +#define SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA_H_=0D +=0D +#include =0D +#include =0D +=0D +#pragma pack(1)=0D +=0D +typedef enum{=0D + RegisterUnsupported =3D 0x00,=0D + RegisterLen32 =3D 0x01,=0D + RegisterLen64 =3D 0x02,=0D + RegisterLen128 =3D 0x03=0D +} RISC_V_REGISTER_LENGTH;=0D +=0D +#define SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA_REVISION 0x100=0D +=0D +#define SMBIOS_RISC_V_PSD_MACHINE_MODE_SUPPORTED (0x01 << 0)=0D +#define SMBIOS_RISC_V_PSD_SUPERVISOR_MODE_SUPPORTED (0x01 << 2)=0D +#define SMBIOS_RISC_V_PSD_USER_MODE_SUPPORTED (0x01 << 3)=0D +#define SMBIOS_RISC_V_PSD_DEBUG_MODE_SUPPORTED (0x01 << 7)=0D +=0D +///=0D +/// RISC-V processor specific data for SMBIOS type 44=0D +///=0D +typedef struct {=0D + UINT16 Revision;=0D + UINT8 Length;=0D + RISCV_UINT128 HartId;=0D + UINT8 BootHartId;=0D + RISCV_UINT128 MachineVendorId;=0D + RISCV_UINT128 MachineArchId;=0D + RISCV_UINT128 MachineImplId;=0D + UINT32 InstSetSupported;=0D + UINT8 PrivilegeModeSupported;=0D + RISCV_UINT128 MModeExcepDelegation;=0D + RISCV_UINT128 MModeInterruptDelegation;=0D + UINT8 HartXlen;=0D + UINT8 MachineModeXlen;=0D + UINT8 Reserved;=0D + UINT8 SupervisorModeXlen;=0D + UINT8 UserModeXlen;=0D +} SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA;=0D +=0D +#pragma pack()=0D +#endif=0D +=0D diff --git a/Silicon/RISC-V/ProcessorPkg/Universal/SmbiosDxe/RiscVSmbiosDxe= .h b/Silicon/RISC-V/ProcessorPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.h new file mode 100644 index 0000000000..1072877ad8 --- /dev/null +++ b/Silicon/RISC-V/ProcessorPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.h @@ -0,0 +1,23 @@ +/** @file=0D + RISC-V SMBIOS Builder DXE module header file.=0D +=0D + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All right= s reserved.
=0D +=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +=0D +#ifndef RISC_V_SMBIOS_DXE_H_=0D +#define RISC_V_SMBIOS_DXE_H_=0D +=0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#endif=0D +=0D diff --git a/Silicon/RISC-V/ProcessorPkg/Universal/SmbiosDxe/RiscVSmbiosDxe= .c b/Silicon/RISC-V/ProcessorPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.c new file mode 100644 index 0000000000..6079513a55 --- /dev/null +++ b/Silicon/RISC-V/ProcessorPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.c @@ -0,0 +1,327 @@ +/** @file=0D + RISC-V generic SMBIOS DXE driver to build up SMBIOS type 4, type 7 and t= ype 44 records.=0D +=0D + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All right= s reserved.
=0D +=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +=0D +#include "RiscVSmbiosDxe.h"=0D +=0D +STATIC EFI_SMBIOS_PROTOCOL *mSmbios;=0D +=0D +/**=0D + This function builds SMBIOS type 7 record according to=0D + the given RISC_V_PROCESSOR_TYPE7_HOB_DATA.=0D +=0D + @param Type4HobData Pointer to RISC_V_PROCESSOR_TYPE4_HOB_DATA=0D + @param Type7DataHob Pointer to RISC_V_PROCESSOR_TYPE7_HOB_DATA=0D + @param SmbiosHandle Pointer to SMBIOS_HANDLE=0D +=0D + @retval EFI_STATUS=0D +=0D +**/=0D +STATIC=0D +EFI_STATUS=0D +BuildSmbiosType7 (=0D + IN RISC_V_PROCESSOR_TYPE4_HOB_DATA *Type4HobData,=0D + IN RISC_V_PROCESSOR_TYPE7_HOB_DATA *Type7DataHob,=0D + OUT SMBIOS_HANDLE *SmbiosHandle=0D +)=0D +{=0D + EFI_STATUS Status;=0D + SMBIOS_HANDLE Handle;=0D +=0D + if (!CompareGuid (&Type4HobData->PrcessorGuid, &Type7DataHob->PrcessorGu= id) ||=0D + Type4HobData->ProcessorUid !=3D Type7DataHob->ProcessorUid) {=0D + return EFI_INVALID_PARAMETER;=0D + }=0D + Handle =3D SMBIOS_HANDLE_PI_RESERVED;=0D + Type7DataHob->SmbiosType7Cache.Hdr.Type =3D SMBIOS_TYPE_CACHE_INFORMATIO= N;=0D + Type7DataHob->SmbiosType7Cache.Hdr.Length =3D sizeof(SMBIOS_TABLE_TYPE7)= ;=0D + Type7DataHob->SmbiosType7Cache.Hdr.Handle =3D 0;=0D + Type7DataHob->EndingZero =3D 0;=0D + Status =3D mSmbios->Add (mSmbios, NULL, &Handle, &Type7DataHob->SmbiosTy= pe7Cache.Hdr);=0D + if (EFI_ERROR(Status)) {=0D + DEBUG ((DEBUG_ERROR, "%a: Fail to add SMBIOS Type 7\n", __FUNCTION__))= ;=0D + return Status;=0D + }=0D + DEBUG ((DEBUG_INFO, "SMBIOS Type 7 was added. SMBIOS Handle: 0x%x\n", Ha= ndle));=0D + DEBUG ((DEBUG_VERBOSE, " Cache belone to processor GUID: %g\n", &Typ= e7DataHob->PrcessorGuid));=0D + DEBUG ((DEBUG_VERBOSE, " Cache belone processor UID: %d\n", Type7Da= taHob->ProcessorUid));=0D + DEBUG ((DEBUG_VERBOSE, " =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D\n"));=0D + DEBUG ((DEBUG_VERBOSE, " Socket Designation: %d\n", Type7DataHob->Sm= biosType7Cache.SocketDesignation));=0D + DEBUG ((DEBUG_VERBOSE, " Cache Configuration: 0x%x\n", Type7DataHob-= >SmbiosType7Cache.CacheConfiguration));=0D + DEBUG ((DEBUG_VERBOSE, " Maximum Cache Size: 0x%x\n", Type7DataHob->= SmbiosType7Cache.MaximumCacheSize));=0D + DEBUG ((DEBUG_VERBOSE, " Installed Size: 0x%x\n", Type7DataHob->Smbi= osType7Cache.InstalledSize));=0D + DEBUG ((DEBUG_VERBOSE, " Supported SRAM Type: 0x%x\n", Type7DataHob-= >SmbiosType7Cache.SupportedSRAMType));=0D + DEBUG ((DEBUG_VERBOSE, " Current SRAMT ype: 0x%x\n", Type7DataHob->S= mbiosType7Cache.CurrentSRAMType));=0D + DEBUG ((DEBUG_VERBOSE, " Cache Speed: 0x%x\n", Type7DataHob->SmbiosT= ype7Cache.CacheSpeed));=0D + DEBUG ((DEBUG_VERBOSE, " Error Correction Type: 0x%x\n", Type7DataHo= b->SmbiosType7Cache.ErrorCorrectionType));=0D + DEBUG ((DEBUG_VERBOSE, " System Cache Type: 0x%x\n", Type7DataHob->S= mbiosType7Cache.SystemCacheType));=0D + DEBUG ((DEBUG_VERBOSE, " Associativity: 0x%x\n", Type7DataHob->Smbio= sType7Cache.Associativity));=0D +=0D + *SmbiosHandle =3D Handle;=0D + return EFI_SUCCESS;=0D +}=0D +=0D +/**=0D + This function builds SMBIOS type 4 record according to=0D + the given RISC_V_PROCESSOR_TYPE4_HOB_DATA.=0D +=0D + @param Type4HobData Pointer to RISC_V_PROCESSOR_TYPE4_HOB_DATA=0D + @param SmbiosHandle Pointer to SMBIOS_HANDLE=0D +=0D + @retval EFI_STATUS=0D +=0D +**/=0D +STATIC=0D +EFI_STATUS=0D +BuildSmbiosType4 (=0D + IN RISC_V_PROCESSOR_TYPE4_HOB_DATA *Type4HobData,=0D + OUT SMBIOS_HANDLE *SmbiosHandle=0D + )=0D +{=0D + EFI_HOB_GUID_TYPE *GuidHob;=0D + RISC_V_PROCESSOR_TYPE7_HOB_DATA *Type7HobData;=0D + SMBIOS_HANDLE Cache;=0D + SMBIOS_HANDLE Processor;=0D + EFI_STATUS Status;=0D +=0D + DEBUG ((DEBUG_INFO, "Building Type 4.\n"));=0D + DEBUG ((DEBUG_INFO, " Processor GUID: %g\n", &Type4HobData->PrcessorG= uid));=0D + DEBUG ((DEBUG_INFO, " Processor UUID: %d\n", Type4HobData->ProcessorU= id));=0D +=0D + Type4HobData->SmbiosType4Processor.L1CacheHandle =3D RISC_V_CACHE_INFO_N= OT_PROVIDED;=0D + Type4HobData->SmbiosType4Processor.L2CacheHandle =3D RISC_V_CACHE_INFO_N= OT_PROVIDED;=0D + Type4HobData->SmbiosType4Processor.L3CacheHandle =3D RISC_V_CACHE_INFO_N= OT_PROVIDED;=0D + GuidHob =3D (EFI_HOB_GUID_TYPE *)GetFirstGuidHob ((EFI_GUID *)PcdGetPtr(= PcdProcessorSmbiosType7GuidHobGuid));=0D + if (GuidHob =3D=3D NULL) {=0D + DEBUG ((DEBUG_ERROR, "No RISC-V SMBIOS Type7 data HOB found.\n"));=0D + return EFI_NOT_FOUND;=0D + }=0D + //=0D + // Go through each RISC_V_PROCESSOR_TYPE4_HOB_DATA for multiple processo= rs.=0D + //=0D + do {=0D + Type7HobData =3D (RISC_V_PROCESSOR_TYPE7_HOB_DATA *)GET_GUID_HOB_DATA = (GuidHob);=0D + Status =3D BuildSmbiosType7 (Type4HobData, Type7HobData, &Cache);=0D + if (EFI_ERROR (Status)) {=0D + return Status;=0D + }=0D + if ((Type7HobData->SmbiosType7Cache.SystemCacheType & RISC_V_CACHE_CON= FIGURATION_CACHE_LEVEL_MASK) =3D=3D=0D + RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_1) {=0D + Type4HobData->SmbiosType4Processor.L1CacheHandle =3D Cache;=0D + } else if ((Type7HobData->SmbiosType7Cache.SystemCacheType & RISC_V_CA= CHE_CONFIGURATION_CACHE_LEVEL_MASK) =3D=3D=0D + RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_2) {=0D + Type4HobData->SmbiosType4Processor.L2CacheHandle =3D Cache;=0D + } else if ((Type7HobData->SmbiosType7Cache.SystemCacheType & RISC_V_CA= CHE_CONFIGURATION_CACHE_LEVEL_MASK) =3D=3D=0D + RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_3) {=0D + Type4HobData->SmbiosType4Processor.L3CacheHandle =3D Cache;=0D + } else {=0D + DEBUG ((DEBUG_ERROR, "Improper cache level of SMBIOS handle %d\n", C= ache));=0D + }=0D + GuidHob =3D GetNextGuidHob((EFI_GUID *)PcdGetPtr(PcdProcessorSmbiosTyp= e7GuidHobGuid), GET_NEXT_HOB(GuidHob));=0D + } while (GuidHob !=3D NULL);=0D +=0D + //=0D + // Build SMBIOS Type 4 record=0D + //=0D + Processor =3D SMBIOS_HANDLE_PI_RESERVED;=0D + Type4HobData->SmbiosType4Processor.Hdr.Type =3D SMBIOS_TYPE_PROCESSOR_IN= FORMATION;=0D + Type4HobData->SmbiosType4Processor.Hdr.Length =3D sizeof(SMBIOS_TABLE_TY= PE4);=0D + Type4HobData->SmbiosType4Processor.Hdr.Handle =3D 0;=0D + Type4HobData->EndingZero =3D 0;=0D + Status =3D mSmbios->Add (mSmbios, NULL, &Processor, &Type4HobData->Smbio= sType4Processor.Hdr);=0D + if (EFI_ERROR(Status)) {=0D + DEBUG ((DEBUG_ERROR, "Fail to add SMBIOS Type 4\n"));=0D + return Status;=0D + }=0D + DEBUG ((DEBUG_INFO, "SMBIOS Type 4 was added. SMBIOS Handle: 0x%x\n", Pr= ocessor));=0D + DEBUG ((DEBUG_VERBOSE, " Socket StringID: %d\n", Type4HobData->Smbio= sType4Processor.Socket));=0D + DEBUG ((DEBUG_VERBOSE, " Processor Type: 0x%x\n", Type4HobData->Smbi= osType4Processor.ProcessorType));=0D + DEBUG ((DEBUG_VERBOSE, " Processor Family: 0x%x\n", Type4HobData->Sm= biosType4Processor.ProcessorFamily));=0D + DEBUG ((DEBUG_VERBOSE, " Processor Manufacture StringID: %d\n", Type= 4HobData->SmbiosType4Processor.ProcessorManufacture));=0D + DEBUG ((DEBUG_VERBOSE, " Processor Id: 0x%x:0x%x\n", \=0D + Type4HobData->SmbiosType4Processor.ProcessorId.Signature, Type4H= obData->SmbiosType4Processor.ProcessorId.FeatureFlags));=0D + DEBUG ((DEBUG_VERBOSE, " Processor Version StringID: %d\n", Type4Hob= Data->SmbiosType4Processor.ProcessorVersion));=0D + DEBUG ((DEBUG_VERBOSE, " Voltage: 0x%x\n", Type4HobData->SmbiosType4= Processor.Voltage));=0D + DEBUG ((DEBUG_VERBOSE, " External Clock: 0x%x\n", Type4HobData->Smbi= osType4Processor.ExternalClock));=0D + DEBUG ((DEBUG_VERBOSE, " Max Speed: 0x%x\n", Type4HobData->SmbiosTyp= e4Processor.MaxSpeed));=0D + DEBUG ((DEBUG_VERBOSE, " Current Speed: 0x%x\n", Type4HobData->Smbio= sType4Processor.CurrentSpeed));=0D + DEBUG ((DEBUG_VERBOSE, " Status: 0x%x\n", Type4HobData->SmbiosType4P= rocessor.Status));=0D + DEBUG ((DEBUG_VERBOSE, " ProcessorUpgrade: 0x%x\n", Type4HobData->Sm= biosType4Processor.ProcessorUpgrade));=0D + DEBUG ((DEBUG_VERBOSE, " L1 Cache Handle: 0x%x\n", Type4HobData->Smb= iosType4Processor.L1CacheHandle));=0D + DEBUG ((DEBUG_VERBOSE, " L2 Cache Handle: 0x%x\n",Type4HobData->Smbi= osType4Processor.L2CacheHandle));=0D + DEBUG ((DEBUG_VERBOSE, " L3 Cache Handle: 0x%x\n", Type4HobData->Smb= iosType4Processor.L3CacheHandle));=0D + DEBUG ((DEBUG_VERBOSE, " Serial Number StringID: %d\n", Type4HobData= ->SmbiosType4Processor.SerialNumber));=0D + DEBUG ((DEBUG_VERBOSE, " Asset Tag StringID: %d\n", Type4HobData->Sm= biosType4Processor.AssetTag));=0D + DEBUG ((DEBUG_VERBOSE, " Part Number StringID: %d\n", Type4HobData->= SmbiosType4Processor.PartNumber));=0D + DEBUG ((DEBUG_VERBOSE, " Core Count: %d\n", Type4HobData->SmbiosType= 4Processor.CoreCount));=0D + DEBUG ((DEBUG_VERBOSE, " Enabled CoreCount: %d\n", Type4HobData->Smb= iosType4Processor.EnabledCoreCount));=0D + DEBUG ((DEBUG_VERBOSE, " Thread Count: %d\n", Type4HobData->SmbiosTy= pe4Processor.ThreadCount));=0D + DEBUG ((DEBUG_VERBOSE, " Processor Characteristics: 0x%x\n", Type4Ho= bData->SmbiosType4Processor.ProcessorCharacteristics));=0D + DEBUG ((DEBUG_VERBOSE, " Processor Family2: 0x%x\n", Type4HobData->S= mbiosType4Processor.ProcessorFamily2));=0D + DEBUG ((DEBUG_VERBOSE, " Core Count 2: %d\n", Type4HobData->SmbiosTy= pe4Processor.CoreCount2));=0D + DEBUG ((DEBUG_VERBOSE, " Enabled CoreCount : %d\n", Type4HobData->Sm= biosType4Processor.EnabledCoreCount2));=0D + DEBUG ((DEBUG_VERBOSE, " Thread Count 2: %d\n", Type4HobData->Smbios= Type4Processor.ThreadCount2));=0D +=0D + *SmbiosHandle =3D Processor;=0D + return EFI_SUCCESS;=0D +}=0D +=0D +/**=0D + This function builds SMBIOS type 44 record according..=0D +=0D + @param Type4HobData Pointer to RISC_V_PROCESSOR_TYPE4_HOB_DATA=0D + @param Type4Handle SMBIOS handle of type 4=0D +=0D + @retval EFI_STATUS=0D +=0D +**/=0D +EFI_STATUS=0D +BuildSmbiosType44 (=0D + IN RISC_V_PROCESSOR_TYPE4_HOB_DATA *Type4HobData,=0D + IN SMBIOS_HANDLE Type4Handle=0D + )=0D +{=0D + EFI_HOB_GUID_TYPE *GuidHob;=0D + RISC_V_PROCESSOR_SPECIFIC_HOB_DATA *ProcessorSpecificData;=0D + SMBIOS_HANDLE RiscVType44;=0D + SMBIOS_TABLE_TYPE44 *Type44Ptr;=0D + EFI_STATUS Status;=0D +=0D + DEBUG ((DEBUG_INFO, "Building Type 44 for...\n"));=0D + DEBUG ((DEBUG_VERBOSE, " Processor GUID: %g\n", &Type4HobData->Prces= sorGuid));=0D + DEBUG ((DEBUG_VERBOSE, " Processor UUID: %d\n", Type4HobData->Proces= sorUid));=0D +=0D + GuidHob =3D (EFI_HOB_GUID_TYPE *)GetFirstGuidHob ((EFI_GUID *)PcdGetPtr(= PcdProcessorSpecificDataGuidHobGuid));=0D + if (GuidHob =3D=3D NULL) {=0D + DEBUG ((DEBUG_ERROR, "No RISC_V_PROCESSOR_SPECIFIC_HOB_DATA found.\n")= );=0D + return EFI_NOT_FOUND;=0D + }=0D + //=0D + // Go through each RISC_V_PROCESSOR_SPECIFIC_HOB_DATA for multiple cores= .=0D + //=0D + do {=0D + ProcessorSpecificData =3D (RISC_V_PROCESSOR_SPECIFIC_HOB_DATA *)GET_GU= ID_HOB_DATA (GuidHob);=0D + if (!CompareGuid (&ProcessorSpecificData->ParentPrcessorGuid, &Type4Ho= bData->PrcessorGuid) ||=0D + ProcessorSpecificData->ParentProcessorUid !=3D Type4HobData->Process= orUid) {=0D + GuidHob =3D GetNextGuidHob((EFI_GUID *)PcdGetPtr(PcdProcessorSpecifi= cDataGuidHobGuid), GET_NEXT_HOB(GuidHob));=0D + if (GuidHob =3D=3D NULL) {=0D + break;=0D + }=0D + continue;=0D + }=0D +=0D + DEBUG ((DEBUG_VERBOSE, "=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D\n"));=0D + DEBUG ((DEBUG_VERBOSE, "Core GUID: %g\n", &ProcessorSpecificData->Core= Guid));=0D +=0D + Type44Ptr =3D AllocateZeroPool(sizeof(SMBIOS_TABLE_TYPE44) + sizeof(SM= BIOS_RISC_V_PROCESSOR_SPECIFIC_DATA) + 2); // Two ending zero.=0D + if (Type44Ptr =3D=3D NULL) {=0D + return EFI_NOT_FOUND;=0D + }=0D + Type44Ptr->Hdr.Type =3D SMBIOS_TYPE_PROCESSOR_ADDITIONAL_INFORMATION;= =0D + Type44Ptr->Hdr.Handle =3D 0;=0D + Type44Ptr->Hdr.Length =3D sizeof(SMBIOS_TABLE_TYPE44) + sizeof(SMBIOS_= RISC_V_PROCESSOR_SPECIFIC_DATA);=0D + Type44Ptr->RefHandle =3D Type4Handle;=0D + Type44Ptr->ProcessorSpecificBlock.Length =3D sizeof(SMBIOS_RISC_V_PROC= ESSOR_SPECIFIC_DATA);=0D + Type44Ptr->ProcessorSpecificBlock.ProcessorArchType =3D Type4HobData->= SmbiosType4Processor.ProcessorFamily2 -=0D + ProcessorFamilyR= iscvRV32 + \=0D + ProcessorSpecifi= cBlockArchTypeRiscVRV32;=0D + CopyMem ((VOID *)(Type44Ptr + 1), (VOID *)&ProcessorSpecificData->Proc= essorSpecificData, sizeof (SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA));=0D +=0D + DEBUG ((DEBUG_VERBOSE, "Core type: %d\n", Type44Ptr->ProcessorSpecific= Block.ProcessorArchType));=0D + DEBUG ((DEBUG_VERBOSE, " HartId =3D 0x%x\n", ((SMBIOS_RISC_V_PROCE= SSOR_SPECIFIC_DATA *)(Type44Ptr + 1))->HartId.Value64_L));=0D + DEBUG ((DEBUG_VERBOSE, " Is Boot Hart? =3D 0x%x\n", ((SMBIOS_RISC_= V_PROCESSOR_SPECIFIC_DATA *)(Type44Ptr + 1))->BootHartId));=0D + DEBUG ((DEBUG_VERBOSE, " PrivilegeModeSupported =3D 0x%x\n", ((SMB= IOS_RISC_V_PROCESSOR_SPECIFIC_DATA *)(Type44Ptr + 1))->PrivilegeModeSupport= ed));=0D + DEBUG ((DEBUG_VERBOSE, " MModeExcepDelegation =3D 0x%x\n", ((SMBIO= S_RISC_V_PROCESSOR_SPECIFIC_DATA *)(Type44Ptr + 1))->MModeExcepDelegation.V= alue64_L));=0D + DEBUG ((DEBUG_VERBOSE, " MModeInterruptDelegation =3D 0x%x\n", ((S= MBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA *)(Type44Ptr + 1))->MModeInterruptDele= gation.Value64_L));=0D + DEBUG ((DEBUG_VERBOSE, " HartXlen =3D 0x%x\n", ((SMBIOS_RISC_V_PRO= CESSOR_SPECIFIC_DATA *)(Type44Ptr + 1))->HartXlen));=0D + DEBUG ((DEBUG_VERBOSE, " MachineModeXlen =3D 0x%x\n", ((SMBIOS_RIS= C_V_PROCESSOR_SPECIFIC_DATA *)(Type44Ptr + 1))->MachineModeXlen));=0D + DEBUG ((DEBUG_VERBOSE, " SupervisorModeXlen =3D 0x%x\n", ((SMBIOS_= RISC_V_PROCESSOR_SPECIFIC_DATA *)(Type44Ptr + 1))->SupervisorModeXlen));=0D + DEBUG ((DEBUG_VERBOSE, " UserModeXlen =3D 0x%x\n", ((SMBIOS_RISC_V= _PROCESSOR_SPECIFIC_DATA *)(Type44Ptr + 1))->UserModeXlen));=0D + DEBUG ((DEBUG_VERBOSE, " InstSetSupported =3D 0x%x\n", ((SMBIOS_RI= SC_V_PROCESSOR_SPECIFIC_DATA *)(Type44Ptr + 1))->InstSetSupported));=0D + DEBUG ((DEBUG_VERBOSE, " MachineVendorId =3D 0x%x\n", ((SMBIOS_RIS= C_V_PROCESSOR_SPECIFIC_DATA *)(Type44Ptr + 1))->MachineVendorId.Value64_L))= ;=0D + DEBUG ((DEBUG_VERBOSE, " MachineArchId =3D 0x%x\n", ((SMBIOS_RISC_= V_PROCESSOR_SPECIFIC_DATA *)(Type44Ptr + 1))->MachineArchId.Value64_L));=0D + DEBUG ((DEBUG_VERBOSE, " MachineImplId =3D 0x%x\n", ((SMBIOS_RISC_= V_PROCESSOR_SPECIFIC_DATA *)(Type44Ptr + 1))->MachineImplId.Value64_L));=0D +=0D + //=0D + // Add to SMBIOS table.=0D + //=0D + RiscVType44 =3D SMBIOS_HANDLE_PI_RESERVED;=0D + Status =3D mSmbios->Add (mSmbios, NULL, &RiscVType44, &Type44Ptr->Hdr)= ;=0D + if (EFI_ERROR(Status)) {=0D + DEBUG ((DEBUG_ERROR, "Fail to add SMBIOS Type 44\n"));=0D + return Status;=0D + }=0D + DEBUG ((DEBUG_INFO, "SMBIOS Type 44 was added. SMBIOS Handle: 0x%x\n",= RiscVType44));=0D +=0D + GuidHob =3D GetNextGuidHob((EFI_GUID *)PcdGetPtr(PcdProcessorSpecificD= ataGuidHobGuid), GET_NEXT_HOB(GuidHob));=0D + } while (GuidHob !=3D NULL);=0D + return EFI_SUCCESS;=0D +}=0D +=0D +/**=0D + Entry point of RISC-V SMBIOS builder.=0D +=0D + @param ImageHandle Image handle this driver.=0D + @param SystemTable Pointer to the System Table.=0D +=0D + @retval EFI_SUCCESS Thread can be successfully created=0D + @retval EFI_OUT_OF_RESOURCES Cannot allocate protocol data structure=0D + @retval EFI_DEVICE_ERROR Cannot create the thread=0D +=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +RiscVSmbiosBuilderEntry (=0D + IN EFI_HANDLE ImageHandle,=0D + IN EFI_SYSTEM_TABLE *SystemTable=0D + )=0D +{=0D + EFI_STATUS Status;=0D + EFI_HOB_GUID_TYPE *GuidHob;=0D + RISC_V_PROCESSOR_TYPE4_HOB_DATA *Type4HobData;=0D + SMBIOS_HANDLE Processor;=0D +=0D + DEBUG ((DEBUG_INFO, "%a: entry\n", __FUNCTION__));=0D +=0D + Status =3D gBS->LocateProtocol (=0D + &gEfiSmbiosProtocolGuid,=0D + NULL,=0D + (VOID **)&mSmbios=0D + );=0D + if (EFI_ERROR (Status)) {=0D + DEBUG ((DEBUG_ERROR, "Locate SMBIOS Protocol fail\n"));=0D + return Status;=0D + }=0D + GuidHob =3D (EFI_HOB_GUID_TYPE *)GetFirstGuidHob ((EFI_GUID *)PcdGetPtr(= PcdProcessorSmbiosType4GuidHobGuid));=0D + if (GuidHob =3D=3D NULL) {=0D + DEBUG ((DEBUG_ERROR, "No RISC-V SMBIOS information found.\n"));=0D + return EFI_NOT_FOUND;=0D + }=0D + Type4HobData =3D (RISC_V_PROCESSOR_TYPE4_HOB_DATA *)GET_GUID_HOB_DATA (G= uidHob);=0D + Status =3D EFI_NOT_FOUND;=0D + //=0D + // Go through each RISC_V_PROCESSOR_TYPE4_HOB_DATA for multiple processo= rs.=0D + //=0D + do {=0D + Status =3D BuildSmbiosType4 (Type4HobData, &Processor);=0D + if (EFI_ERROR (Status)) {=0D + DEBUG ((DEBUG_ERROR, "No RISC-V SMBIOS type 4 created.\n"));=0D + ASSERT (FALSE);=0D + }=0D + Status =3D BuildSmbiosType44 (Type4HobData, Processor);=0D + if (EFI_ERROR (Status)) {=0D + DEBUG ((DEBUG_ERROR, "No RISC-V SMBIOS type 44 found.\n"));=0D + ASSERT (FALSE);=0D + }=0D +=0D + GuidHob =3D GetNextGuidHob((EFI_GUID *)PcdGetPtr(PcdProcessorSmbiosTyp= e4GuidHobGuid), GET_NEXT_HOB(GuidHob));=0D + } while (GuidHob !=3D NULL);=0D + DEBUG ((DEBUG_INFO, "%a: exit\n", __FUNCTION__));=0D + return Status;=0D +}=0D +=0D diff --git a/Silicon/RISC-V/ProcessorPkg/Universal/SmbiosDxe/RiscVSmbiosDxe= .uni b/Silicon/RISC-V/ProcessorPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.uni new file mode 100644 index 0000000000..1bffe09fe7 --- /dev/null +++ b/Silicon/RISC-V/ProcessorPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.uni @@ -0,0 +1,12 @@ +// /** @file=0D +//=0D +// Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
=0D +//=0D +// SPDX-License-Identifier: BSD-2-Clause-Patent=0D +//=0D +// **/=0D +=0D +#string STR_MODULE_ABSTRACT #language en-US "RISC-V Processor = SMBIOS Builder"=0D +=0D +#string STR_MODULE_DESCRIPTION #language en-US "Build RISC-V Proc= essor SMBIOS Type 4, 7, 44 records."=0D +=0D diff --git a/Silicon/RISC-V/ProcessorPkg/Universal/SmbiosDxe/RiscVSmbiosDxe= Extra.uni b/Silicon/RISC-V/ProcessorPkg/Universal/SmbiosDxe/RiscVSmbiosDxeE= xtra.uni new file mode 100644 index 0000000000..4b37ca2bbb --- /dev/null +++ b/Silicon/RISC-V/ProcessorPkg/Universal/SmbiosDxe/RiscVSmbiosDxeExtra.u= ni @@ -0,0 +1,13 @@ +// /** @file=0D +// RISC-V SMBIOS Builder Localized Strings and Content=0D +//=0D +// Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
=0D +//=0D +// SPDX-License-Identifier: BSD-2-Clause-Patent=0D +//=0D +// **/=0D +=0D +#string STR_PROPERTIES_MODULE_NAME=0D +#language en-US=0D +"RISC-V SMBIOS Record Builder DXE Driver"=0D +=0D --=20 2.31.1