From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mx0a-002e3701.pphosted.com (mx0a-002e3701.pphosted.com [148.163.147.86]) by mx.groups.io with SMTP id smtpd.web08.3764.1641630285764028814 for ; Sat, 08 Jan 2022 00:24:46 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@hpe.com header.s=pps0720 header.b=OvO7Fwfb; spf=permerror, err=parse error for token &{10 18 %{ir}.%{v}.%{d}.spf.has.pphosted.com}: invalid domain name (domain: hpe.com, ip: 148.163.147.86, mailfrom: prvs=000704d8ca=abner.chang@hpe.com) Received: from pps.filterd (m0134421.ppops.net [127.0.0.1]) by mx0b-002e3701.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 208282B8029570 for ; Sat, 8 Jan 2022 08:24:45 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=hpe.com; h=from : to : cc : subject : date : message-id : mime-version : content-transfer-encoding; s=pps0720; bh=8cm88NVGfZPJsNUUblBRbxf86mQPwiDhB3RKYY+OuDU=; b=OvO7Fwfb9PeJ+AjIAkuS7zI0t71cWXtP5jAvs0n2uljgNjE7oH+0Y2E/FjetZjAYfeFP tFYEg9OXoW7JtLGrZxcOzLmCTqQ96ByRWKrH8NjXZ3G66lNBQEv3OFhnhGUrJVUM1LEd 6U6/8rRqE+KC1/e1+t0K5MO9nM2MRr857CLtEt5w1xoxJnNCcozvmfRtK8DFSCie7DBv Z1RRbkFnt4pMF2C/tpXrKBmCfyr07xUgGtiHRD7sJZNAJSVuWXBhFiNC8D4xfu6Y0uzv 4h9I3H3rRcJ7QSHYIqupzB9Riplj3s7bIW7OfvQI1HeiclG9IMTpIgWyGNZCvoPPLqcL Pg== Received: from g4t3426.houston.hpe.com (g4t3426.houston.hpe.com [15.241.140.75]) by mx0b-002e3701.pphosted.com (PPS) with ESMTPS id 3df0tcsek7-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Sat, 08 Jan 2022 08:24:44 +0000 Received: from g4t3433.houston.hpecorp.net (g4t3433.houston.hpecorp.net [16.208.49.245]) by g4t3426.houston.hpe.com (Postfix) with ESMTP id 1F16B5C for ; Sat, 8 Jan 2022 08:24:44 +0000 (UTC) Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.229]) by g4t3433.houston.hpecorp.net (Postfix) with ESMTP id 5A1A446; Sat, 8 Jan 2022 08:24:43 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com Subject: [PATCH 41/79] RISC-V: Create opensbi firmware domains Date: Sat, 8 Jan 2022 15:23:43 +0800 Message-Id: <20220108072343.17829-1-abner.chang@hpe.com> X-Mailer: git-send-email 2.31.1 MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: ewzKy4C2F6gbB2JKVUbtwhGBfpE1x72n X-Proofpoint-GUID: ewzKy4C2F6gbB2JKVUbtwhGBfpE1x72n X-HPE-SCL: -1 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.790,Hydra:6.0.425,FMLib:17.11.62.513 definitions=2022-01-08_03,2022-01-07_01,2021-12-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 mlxlogscore=999 clxscore=1015 adultscore=0 bulkscore=0 spamscore=0 malwarescore=0 mlxscore=0 lowpriorityscore=0 phishscore=0 priorityscore=1501 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2110150000 definitions=main-2201080063 Content-Transfer-Encoding: quoted-printable (This is migrated from edk2-platforms) Incorporate with opensbi to create three firmware domains, - Boot firmware domain, which built with opensbi library as M-mode access only region. - Firmware domain which includes PEI and DXE regions, the PMP attribute is readable, wriable and executable. - EFI Variable region which is readable and writable. Cc: Sunil V L Cc: Daniel Schaefer Signed-off-by: Abner Chang Reviewed-by: Daniel Schaefer Reviewed-by: Sunil V L --- .../RISC-V/PlatformPkg/RiscVPlatformPkg.dec | 40 ++++----- .../OpensbiPlatformLib/OpensbiPlatformLib.inf | 9 +- .../PlatformPkg/Universal/Sec/SecMain.inf | 6 +- .../Library/OpensbiPlatformLib/Platform.c | 84 ++++++++++++++++--- .../PlatformPkg/Universal/Sec/SecMain.c | 53 +++++------- .../Universal/Sec/Riscv64/SecEntry.S | 7 +- 6 files changed, 124 insertions(+), 75 deletions(-) diff --git a/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec b/Platform/RI= SC-V/PlatformPkg/RiscVPlatformPkg.dec index ad15a155fe..7e41e7bdb2 100644 --- a/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec +++ b/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec @@ -1,7 +1,7 @@ ## @file RiscVPlatformPkg.dec=0D # This Package provides UEFI RISC-V platform modules and libraries.=0D #=0D -# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All right= s reserved.
=0D +# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All right= s reserved.
=0D #=0D # SPDX-License-Identifier: BSD-2-Clause-Patent=0D #=0D @@ -31,33 +31,33 @@ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVPeiFvSize|0x0|UINT32|0x00001= 003=0D gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVDxeFvBase|0x0|UINT32|0x00001= 004=0D gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVDxeFvSize|0x0|UINT32|0x00001= 005=0D - gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVDtbFvBase|0x0|UINT32|0x00001= 016=0D - gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVDtbFvSize|0x0|UINT32|0x00001= 017=0D -=0D + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVDtbFvBase|0x0|UINT32|0x00001= 006=0D + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVDtbFvSize|0x0|UINT32|0x00001= 007=0D + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRootFirmwareDomainBaseAddress|0x0= |UINT32|0x00001008=0D + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRootFirmwareDomainSize|0x0|UINT32= |0x00001009=0D + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFirmwareDomainBaseAddress|0x0|UIN= T32|0x0000100a=0D + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFirmwareDomainSize|0x0|UINT32|0x0= 000100b=0D + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFirmwareRegionBaseAddress= |0x0|UINT32|0x0000100c=0D + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFirmwareRegionSize|0x0|UI= NT32|0x0000100d=0D #=0D # Definition of EFI Variable region=0D #=0D - gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFdBaseAddress|0|UINT32|0x= 00001010=0D - gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFdSize|0|UINT32|0x0000101= 1=0D - gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFdBlockSize|0|UINT32|0x00= 001012=0D - gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPlatformFlashNvStorageVariableBas= e|0|UINT32|0x00001013=0D - gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPlatformFlashNvStorageFtwWorkingB= ase|0|UINT32|0x00001014=0D - gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPlatformFlashNvStorageFtwSpareBas= e|0|UINT32|0x00001015=0D -#=0D -# Firmware region which is protected by PMP.=0D -#=0D - gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFwBlockSize|0|UINT32|0x00001020=0D - gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFwStartAddress|0|UINT32|0x0000102= 1=0D - gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFwEndAddress|0|UINT32|0x00001022= =0D + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFdBaseAddress|0|UINT32|0x= 00001040=0D + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFdSize|0|UINT32|0x0000104= 1=0D + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFdBlockSize|0|UINT32|0x00= 001042=0D + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPlatformFlashNvStorageVariableBas= e|0|UINT32|0x00001043=0D + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPlatformFlashNvStorageFtwWorkingB= ase|0|UINT32|0x00001044=0D + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPlatformFlashNvStorageFtwSpareBas= e|0|UINT32|0x00001045=0D +=0D #=0D # Definition of RISC-V Hart=0D #=0D - gUefiRiscVPlatformPkgTokenSpaceGuid.PcdHartCount|0|UINT32|0x00001023=0D - gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootHartId|0|UINT32|0x00001024=0D + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdHartCount|0|UINT32|0x00001083=0D + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootHartId|0|UINT32|0x00001084=0D #=0D # The bootable hart core number, which is incorporate with OpenSBI platfor= m hart_index2id value.=0D #=0D - gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootableHartNumber|0|UINT32|0x000= 01025=0D + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootableHartNumber|0|UINT32|0x000= 01085=0D #=0D # Definitions for OpenSbi=0D #=0D @@ -73,7 +73,7 @@ [PcdsPatchableInModule]=0D =0D [PcdsFeatureFlag]=0D - gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootlogoOnlyEnable|FALSE|BOOLEAN|= 0x00001006=0D + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootlogoOnlyEnable|FALSE|BOOLEAN|= 0x00001200=0D =0D [PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx]=0D =0D diff --git a/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/Opensbi= PlatformLib.inf b/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/Op= ensbiPlatformLib.inf index f9f2073a5b..a408737961 100644 --- a/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/OpensbiPlatfor= mLib.inf +++ b/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/OpensbiPlatfor= mLib.inf @@ -3,7 +3,7 @@ # This is the the library which provides platform=0D # level opensbi functions follow RISC-V OpenSBI implementation.=0D #=0D -# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
=0D +# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
=0D #=0D # SPDX-License-Identifier: BSD-2-Clause-Patent=0D #=0D @@ -54,3 +54,10 @@ =0D gSiFiveU5SeriesPlatformsPkgTokenSpaceGuid.PcdU5UartBase=0D gSiFiveU5SeriesPlatformsPkgTokenSpaceGuid.PcdU5PlatformSystemClock=0D +=0D + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRootFirmwareDomainBaseAddress=0D + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRootFirmwareDomainSize=0D + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFirmwareDomainBaseAddress=0D + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFirmwareDomainSize=0D + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFirmwareRegionBaseAddress= =0D + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFirmwareRegionSize=0D diff --git a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf b/Platfo= rm/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf index 78bd75e3ac..bcb8b9f908 100644 --- a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf +++ b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf @@ -1,7 +1,7 @@ ## @file=0D # RISC-V SEC module.=0D #=0D -# Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
=0D +# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
=0D #=0D # SPDX-License-Identifier: BSD-2-Clause-Patent=0D #=0D @@ -64,8 +64,8 @@ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootHartId=0D gUefiRiscVPlatformPkgTokenSpaceGuid.PcdHartCount=0D gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootableHartNumber=0D - gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFwStartAddress=0D - gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFwEndAddress=0D + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRootFirmwareDomainBaseAddress=0D + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRootFirmwareDomainSize=0D gUefiRiscVPlatformPkgTokenSpaceGuid.PcdOpenSbiStackSize=0D gUefiRiscVPlatformPkgTokenSpaceGuid.PcdScratchRamBase=0D gUefiRiscVPlatformPkgTokenSpaceGuid.PcdScratchRamSize=0D diff --git a/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/Platfor= m.c b/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/Platform.c index 79a78b834e..9926911297 100644 --- a/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/Platform.c +++ b/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/Platform.c @@ -1,7 +1,7 @@ /*=0D * SPDX-License-Identifier: BSD-2-Clause=0D *=0D - * Copyright (c) 2020 Western Digital Corporation or its affiliates.=0D + * Copyright (c) 2021 Western Digital Corporation or its affiliates.=0D *=0D * Authors:=0D * Anup Patel =0D @@ -10,6 +10,7 @@ #include =0D #include =0D #include =0D +#include =0D #include =0D #include =0D #include =0D @@ -185,20 +186,77 @@ static u64 generic_tlbr_flush_limit(void) return SBI_PLATFORM_TLB_RANGE_FLUSH_LIMIT_DEFAULT;=0D }=0D =0D +static int generic_system_reset_check(u32 reset_type, u32 reset_reason)=0D +{=0D + if (generic_plat && generic_plat->system_reset_check)=0D + return generic_plat->system_reset_check(reset_type,=0D + reset_reason,=0D + generic_plat_match);=0D + return fdt_system_reset_check(reset_type, reset_reason);=0D +}=0D +=0D +static void generic_system_reset(u32 reset_type, u32 reset_reason)=0D +{=0D + if (generic_plat && generic_plat->system_reset) {=0D + generic_plat->system_reset(reset_type, reset_reason,=0D + generic_plat_match);=0D + return;=0D + }=0D +=0D + fdt_system_reset(reset_type, reset_reason);=0D +}=0D +=0D +#define EDK2_ROOT_FW_REGION 0=0D +#define EDK2_FW_REGION 1=0D +#define EDK2_VARIABLE_REGION 2=0D +#define EDK2_ALL_REGION 3=0D +#define EDK2_END_REGION 4=0D +static struct sbi_domain_memregion root_memregs[EDK2_END_REGION + 1] =3D {= 0 };=0D +=0D +struct sbi_domain_memregion *get_mem_regions(void) {=0D + /* EDK2 root firmware domain memory region */=0D + root_memregs[EDK2_ROOT_FW_REGION].order =3D log2roundup(FixedPcdGet32(Pc= dRootFirmwareDomainSize));=0D + root_memregs[EDK2_ROOT_FW_REGION].base =3D FixedPcdGet32(PcdRootFirmware= DomainBaseAddress);=0D + root_memregs[EDK2_ROOT_FW_REGION].flags =3D 0;=0D +=0D + /*EDK2 firmware domain memory region */=0D + root_memregs[EDK2_FW_REGION].order =3D log2roundup(FixedPcdGet32(PcdFirm= wareDomainSize));=0D + root_memregs[EDK2_FW_REGION].base =3D FixedPcdGet32(PcdFirmwareDomainBas= eAddress);=0D + root_memregs[EDK2_FW_REGION].flags =3D SBI_DOMAIN_MEMREGION_EXECUTABLE |= SBI_DOMAIN_MEMREGION_READABLE;=0D +=0D + /*EDK2 firmware domain memory region */=0D + root_memregs[EDK2_VARIABLE_REGION].order =3D log2roundup(FixedPcdGet32(P= cdVariableFirmwareRegionSize));=0D + root_memregs[EDK2_VARIABLE_REGION].base =3D FixedPcdGet32(PcdVariableFir= mwareRegionBaseAddress);=0D + root_memregs[EDK2_VARIABLE_REGION].flags =3D SBI_DOMAIN_MEMREGION_READAB= LE | SBI_DOMAIN_MEMREGION_WRITEABLE;=0D +=0D + /* EDK2 domain allow everything memory region */=0D + root_memregs[EDK2_ALL_REGION].order =3D __riscv_xlen;=0D + root_memregs[EDK2_ALL_REGION].base =3D 0;=0D + root_memregs[EDK2_ALL_REGION].flags =3D (SBI_DOMAIN_MEMREGION_READABLE |= =0D + SBI_DOMAIN_MEMREGION_WRITEABLE |=0D + SBI_DOMAIN_MEMREGION_EXECUTABLE);=0D +=0D + /* EDK2 domain memory region end */=0D + root_memregs[EDK2_END_REGION].order =3D 0;=0D +=0D + return root_memregs;=0D +}=0D +=0D const struct sbi_platform_operations platform_ops =3D {=0D - .early_init =3D generic_early_init,=0D - .final_init =3D generic_final_init,=0D - .early_exit =3D generic_early_exit,=0D - .final_exit =3D generic_final_exit,=0D - .domains_init =3D generic_domains_init,=0D - .console_init =3D fdt_serial_init,=0D - .irqchip_init =3D fdt_irqchip_init,=0D - .irqchip_exit =3D fdt_irqchip_exit,=0D - .ipi_init =3D fdt_ipi_init,=0D - .ipi_exit =3D fdt_ipi_exit,=0D + .early_init =3D generic_early_init,=0D + .final_init =3D generic_final_init,=0D + .early_exit =3D generic_early_exit,=0D + .final_exit =3D generic_final_exit,=0D + .domains_root_regions =3D get_mem_regions,=0D + .domains_init =3D generic_domains_init,=0D + .console_init =3D fdt_serial_init,=0D + .irqchip_init =3D fdt_irqchip_init,=0D + .irqchip_exit =3D fdt_irqchip_exit,=0D + .ipi_init =3D fdt_ipi_init,=0D + .ipi_exit =3D fdt_ipi_exit,=0D .get_tlbr_flush_limit =3D generic_tlbr_flush_limit,=0D - .timer_init =3D fdt_timer_init,=0D - .timer_exit =3D fdt_timer_exit,=0D + .timer_init =3D fdt_timer_init,=0D + .timer_exit =3D fdt_timer_exit,=0D };=0D =0D #if FixedPcdGet32(PcdBootableHartNumber) =3D=3D 4=0D diff --git a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c b/Platform= /RISC-V/PlatformPkg/Universal/Sec/SecMain.c index e9f030f352..e88a7b8e80 100644 --- a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c +++ b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c @@ -1,7 +1,7 @@ /** @file=0D RISC-V SEC phase module.=0D =0D - Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All right= s reserved.
=0D + Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All right= s reserved.
=0D =0D SPDX-License-Identifier: BSD-2-Clause-Patent=0D =0D @@ -336,7 +336,7 @@ FindAndReportEntryPoints ( =0D **/=0D VOID=0D -DebutPrintFirmwareContext (=0D +DebugPrintFirmwareContext (=0D EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *FirmwareContext=0D )=0D {=0D @@ -398,7 +398,7 @@ TemporaryRamMigration ( //=0D FirmwareContext->PeiServiceTable +=3D (unsigned long)((UINTN)NewStack - = (UINTN)OldStack);=0D DEBUG ((DEBUG_INFO, "%a: OpenSBI Firmware Context is relocated to 0x%x\n= ", __FUNCTION__, FirmwareContext));=0D - DebutPrintFirmwareContext ((EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *)Firmwar= eContext);=0D + DebugPrintFirmwareContext ((EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *)Firmwar= eContext);=0D =0D register uintptr_t a0 asm ("a0") =3D (uintptr_t)((UINTN)NewStack - (UINT= N)OldStack);=0D asm volatile ("add sp, sp, a0"::"r"(a0):);=0D @@ -496,12 +496,12 @@ RegisterFirmwareSbiExtension ( This function transits to S-mode PEI phase from M-mode SEC phase.=0D =0D @param[in] BootHartId Hardware thread ID of boot hart.=0D - @param[in] FuncArg1 Arg1 delivered from previous phase.=0D + @param[in] Scratch Pointer to sbi_scratch structure.=0D =0D **/=0D VOID EFIAPI PeiCore (=0D - IN UINTN BootHartId,=0D - IN UINTN FuncArg1=0D + IN UINTN BootHartId,=0D + IN struct sbi_scratch *Scratch=0D )=0D {=0D EFI_SEC_PEI_HAND_OFF SecCoreData;=0D @@ -529,7 +529,7 @@ VOID EFIAPI PeiCore ( //=0D DEBUG ((DEBUG_INFO, "%a: OpenSBI scratch address for each hart:\n", __FU= NCTION__));=0D for (HartId =3D 0; HartId < SBI_HARTMASK_MAX_BITS; HartId ++) {=0D - SbiGetMscratchHartid (HartId, &ScratchSpace);=0D + ScratchSpace =3D sbi_hartid_to_scratch (HartId);=0D if(ScratchSpace !=3D NULL) {=0D DEBUG((DEBUG_INFO, " Hart %d: 0x%x\n", HartId, ScratchSpace= ));=0D }=0D @@ -540,9 +540,8 @@ VOID EFIAPI PeiCore ( // Firmware context residents in stack and will be switched to memory wh= en=0D // temporary RAM migration.=0D //=0D - SbiGetMscratchHartid (BootHartId, &ScratchSpace);=0D ZeroMem ((VOID *)&FirmwareContext, sizeof (EFI_RISCV_OPENSBI_FIRMWARE_CO= NTEXT));=0D - ThisSbiPlatform =3D (struct sbi_platform *)sbi_platform_ptr(ScratchSpace= );=0D + ThisSbiPlatform =3D (struct sbi_platform *)sbi_platform_ptr(Scratch);=0D if (ThisSbiPlatform->opensbi_version > OPENSBI_VERSION) {=0D DEBUG ((DEBUG_ERROR, "%a: OpenSBI platform table version 0x%x is new= er than OpenSBI version 0x%x.\n"=0D "There maybe be some backward compatable issues= .\n",=0D @@ -562,13 +561,13 @@ VOID EFIAPI PeiCore ( //=0D // Save Flattened Device tree in firmware context=0D //=0D - FirmwareContext.FlattenedDeviceTree =3D FuncArg1;=0D + FirmwareContext.FlattenedDeviceTree =3D Scratch->next_arg1;=0D =0D //=0D // Set firmware context Hart-specific pointer=0D //=0D for (HartId =3D 0; HartId < SBI_HARTMASK_MAX_BITS; HartId ++) {=0D - SbiGetMscratchHartid (HartId, &ScratchSpace);=0D + ScratchSpace =3D sbi_hartid_to_scratch (HartId);=0D if (ScratchSpace !=3D NULL) {=0D FirmwareContext.HartSpecific[HartId] =3D=0D (EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC *)((UINT8 *)ScratchSpace= - FIRMWARE_CONTEXT_HART_SPECIFIC_SIZE);=0D @@ -588,6 +587,10 @@ VOID EFIAPI PeiCore ( //=0D // Transfer the control to the PEI core=0D //=0D + Scratch->next_addr =3D (UINTN)(*PeiCoreEntryPoint);=0D + Scratch->next_mode =3D PRV_S;=0D + DEBUG ((DEBUG_INFO, "%a: Initializing OpenSBI library for booting hart %= d\n", __FUNCTION__, BootHartId));=0D + sbi_init(Scratch);=0D (*PeiCoreEntryPoint) (&SecCoreData, (EFI_PEI_PPI_DESCRIPTOR *)&mPrivateD= ispatchTable);=0D }=0D =0D @@ -598,34 +601,19 @@ VOID EFIAPI PeiCore ( To register the SBI extension we stay in M-Mode and then transition here= ,=0D rather than before in sbi_init.=0D =0D - @param[in] ThisHartId Hardware thread ID.=0D - @param[in] FuncArg1 Arg1 delivered from previous phase.=0D + @param[in] ThisHartId Hardware thread ID.=0D + @param[in] Scratch Pointer to sbi_scratch structure.=0D =0D **/=0D VOID=0D EFIAPI=0D LaunchPeiCore (=0D IN UINTN ThisHartId,=0D - IN UINTN FuncArg1=0D + IN struct sbi_scratch *Scratch=0D )=0D {=0D - UINT32 PeiCoreMode;=0D -=0D - DEBUG ((DEBUG_INFO, "%a: Set boot hart done.\n", __FUNCTION__));=0D - atomic_write (&BootHartDone, (UINT64)TRUE);=0D RegisterFirmwareSbiExtension ();=0D -=0D - PeiCoreMode =3D FixedPcdGet32 (PcdPeiCorePrivilegeMode);=0D - if (PeiCoreMode =3D=3D PRV_S) {=0D - DEBUG ((DEBUG_INFO, "%a: Switch to S-Mode for PeiCore.\n", __FUNCTION_= _));=0D - sbi_hart_switch_mode (ThisHartId, FuncArg1, (UINTN)PeiCore, PRV_S, FAL= SE);=0D - } else if (PeiCoreMode =3D=3D PRV_M) {=0D - DEBUG ((DEBUG_INFO, "%a: Switch to M-Mode for PeiCore.\n", __FUNCTION_= _));=0D - PeiCore (ThisHartId, FuncArg1);=0D - } else {=0D - DEBUG ((DEBUG_INFO, "%a: The privilege mode specified in PcdPeiCorePri= vilegeMode is not supported.\n", __FUNCTION__));=0D - while (TRUE);=0D - }=0D + PeiCore (ThisHartId, Scratch);=0D }=0D =0D /**=0D @@ -750,10 +738,7 @@ VOID EFIAPI SecCoreStartUpWithStack( HartFirmwareContext->HartSwitchMode =3D RiscVOpenSbiHartSwitchMode;=0D =0D if (HartId =3D=3D FixedPcdGet32(PcdBootHartId)) {=0D - Scratch->next_addr =3D (UINTN)LaunchPeiCore;=0D - Scratch->next_mode =3D PRV_M;=0D - DEBUG ((DEBUG_INFO, "%a: Initializing OpenSBI library for booting hart= %d\n", __FUNCTION__, HartId));=0D - sbi_init(Scratch);=0D + LaunchPeiCore (HartId, Scratch);=0D }=0D =0D //=0D diff --git a/Platform/RISC-V/PlatformPkg/Universal/Sec/Riscv64/SecEntry.S b= /Platform/RISC-V/PlatformPkg/Universal/Sec/Riscv64/SecEntry.S index 692985cefb..b3eccf92eb 100644 --- a/Platform/RISC-V/PlatformPkg/Universal/Sec/Riscv64/SecEntry.S +++ b/Platform/RISC-V/PlatformPkg/Universal/Sec/Riscv64/SecEntry.S @@ -1,5 +1,5 @@ /*=0D - * Copyright (c) 2020 , Hewlett Packard Enterprise Development LP. All rig= hts reserved.=0D + * Copyright (c) 2021 , Hewlett Packard Enterprise Development LP. All rig= hts reserved.=0D *=0D * SPDX-License-Identifier: BSD-2-Clause=0D *=0D @@ -71,9 +71,8 @@ _scratch_init: /* Initialize scratch space */=0D =0D /* Firmware range and size */=0D - li a4, FixedPcdGet32 (PcdFwStartAddress)=0D - li a5, FixedPcdGet32 (PcdFwEndAddress)=0D - sub a5, a5, a4=0D + li a4, FixedPcdGet32 (PcdRootFirmwareDomainBaseAddress)=0D + li a5, FixedPcdGet32 (PcdRootFirmwareDomainSize)=0D sd a4, SBI_SCRATCH_FW_START_OFFSET(tp)=0D sd a5, SBI_SCRATCH_FW_SIZE_OFFSET(tp)=0D =0D --=20 2.31.1