From: "Abner Chang" <abner.chang@hpe.com>
To: devel@edk2.groups.io
Cc: abner.chang@hpe.com
Subject: [PATCH 54/79] RiscV/ProcessorPkg: Create read mtime CSR library instances
Date: Sat, 8 Jan 2022 15:24:37 +0800 [thread overview]
Message-ID: <20220108072444.17879-13-abner.chang@hpe.com> (raw)
In-Reply-To: <20220108072444.17879-1-abner.chang@hpe.com>
(This is migrated from edk2-platforms:Silicon)
Create library instances of reading Machine mode timer.
- MacineModeTimerLib is used to read mtime CSR through
platfrom library.
- EmulatedMacineModeTimerLib is used to read mtime CSR
through shadow CSR.
Cc: Sunil V L <sunilvl@ventanamicro.com>
Cc: Daniel Schaefer <daniel.schaefer@hpe.com>
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Reviewed-by: Daniel Schaefer <daniel.schaefer@hpe.com>
Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
---
.../RISC-V/ProcessorPkg/RiscVProcessorPkg.dsc | 2 +
.../EmulatedMachineModeTimerLib.inf | 34 +++++++++++++++++
.../MachineModeTimerLib.inf | 38 +++++++++++++++++++
.../Include/IndustryStandard/RiscV.h | 5 +++
.../Include/Library/RiscVCpuLib.h | 3 ++
.../EmulatedMachineModeTimerLib.S | 24 ++++++++++++
.../MachineModeTimerLib/MachineModeTimerLib.S | 25 ++++++++++++
7 files changed, 131 insertions(+)
create mode 100644 Silicon/RISC-V/ProcessorPkg/Library/RiscVReadMachineModeTimer/EmulatedMachineModeTimerLib/EmulatedMachineModeTimerLib.inf
create mode 100644 Silicon/RISC-V/ProcessorPkg/Library/RiscVReadMachineModeTimer/MachineModeTimerLib/MachineModeTimerLib.inf
create mode 100644 Silicon/RISC-V/ProcessorPkg/Library/RiscVReadMachineModeTimer/EmulatedMachineModeTimerLib/EmulatedMachineModeTimerLib.S
create mode 100644 Silicon/RISC-V/ProcessorPkg/Library/RiscVReadMachineModeTimer/MachineModeTimerLib/MachineModeTimerLib.S
diff --git a/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dsc b/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dsc
index 531319322c..3b5738957d 100644
--- a/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dsc
+++ b/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dsc
@@ -44,6 +44,8 @@
RiscVEdk2SbiLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVEdk2SbiLib/RiscVEdk2SbiLib.inf
RiscVOpensbiLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVOpensbiLib/RiscVOpensbiLib.inf
TimerLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVTimerLib/BaseRiscVTimerLib.inf
+ MachineModeTimerLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVReadMachineModeTimer/MachineModeTimerLib/MachineModeTimerLib.inf
+ #MachineModeTimerLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVReadMachineModeTimer/EmulatedMachineModeTimerLib/EmulatedMachineModeTimerLib.inf
BaseLib|MdePkg/Library/BaseLib/BaseLib.inf
BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
DebugAgentLib|MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLibNull.inf
diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVReadMachineModeTimer/EmulatedMachineModeTimerLib/EmulatedMachineModeTimerLib.inf b/Silicon/RISC-V/ProcessorPkg/Library/RiscVReadMachineModeTimer/EmulatedMachineModeTimerLib/EmulatedMachineModeTimerLib.inf
new file mode 100644
index 0000000000..369028a9a6
--- /dev/null
+++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVReadMachineModeTimer/EmulatedMachineModeTimerLib/EmulatedMachineModeTimerLib.inf
@@ -0,0 +1,34 @@
+## @file
+# Library to read Machine Mode Timer.
+#
+# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001b
+ BASE_NAME = EmulatedMachineModeTimerLib
+ FILE_GUID = 81B82615-D85C-4377-8BFF-7442322E2835
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = MachineModeTimerLib
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = RISCV64
+#
+
+[Sources]
+
+[Sources.RISCV64]
+ EmulatedMachineModeTimerLib.S
+
+[Packages]
+ MdePkg/MdePkg.dec
+ Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec
+
+
+
diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVReadMachineModeTimer/MachineModeTimerLib/MachineModeTimerLib.inf b/Silicon/RISC-V/ProcessorPkg/Library/RiscVReadMachineModeTimer/MachineModeTimerLib/MachineModeTimerLib.inf
new file mode 100644
index 0000000000..71d4315445
--- /dev/null
+++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVReadMachineModeTimer/MachineModeTimerLib/MachineModeTimerLib.inf
@@ -0,0 +1,38 @@
+## @file
+# Library to read Machine Mode Timer.
+#
+# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001b
+ BASE_NAME = MachineModeTimerLib
+ FILE_GUID = 6390D8AA-E0E6-4625-A515-9BB2DC7BBCAB
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = MachineModeTimerLib
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = RISCV64
+#
+
+[Sources]
+
+[Sources.RISCV64]
+ MachineModeTimerLib.S
+
+[Packages]
+ MdePkg/MdePkg.dec
+ Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec
+
+[LibraryClasses]
+ RiscVCpuLib
+ RiscVPlatformTimerLib
+
+
+
diff --git a/Silicon/RISC-V/ProcessorPkg/Include/IndustryStandard/RiscV.h b/Silicon/RISC-V/ProcessorPkg/Include/IndustryStandard/RiscV.h
index f6726bda24..c9715a2ee2 100644
--- a/Silicon/RISC-V/ProcessorPkg/Include/IndustryStandard/RiscV.h
+++ b/Silicon/RISC-V/ProcessorPkg/Include/IndustryStandard/RiscV.h
@@ -154,4 +154,9 @@
#define RISCV_CSR_MTOHOST 0x780
#define RISCV_CSR_MFROMHOST 0x781
+//
+// User mode CSR
+//
+#define RISCV_CSR_CYCLE 0xc00
+#define RISCV_CSR_TIME 0xc01
#endif
diff --git a/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVCpuLib.h b/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVCpuLib.h
index f70723567e..8d51152fa9 100644
--- a/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVCpuLib.h
+++ b/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVCpuLib.h
@@ -32,6 +32,9 @@ RiscVGetMachineTrapCause (VOID);
UINT64
RiscVReadMachineTimer (VOID);
+UINT64
+RiscVReadMachineTimerInterface (VOID);
+
VOID
RiscVSetMachineTimerCmp (UINT64);
diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVReadMachineModeTimer/EmulatedMachineModeTimerLib/EmulatedMachineModeTimerLib.S b/Silicon/RISC-V/ProcessorPkg/Library/RiscVReadMachineModeTimer/EmulatedMachineModeTimerLib/EmulatedMachineModeTimerLib.S
new file mode 100644
index 0000000000..1acd0ab062
--- /dev/null
+++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVReadMachineModeTimer/EmulatedMachineModeTimerLib/EmulatedMachineModeTimerLib.S
@@ -0,0 +1,24 @@
+//------------------------------------------------------------------------------
+//
+// Read Machine mode timer using shadow CSR.
+//
+// Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+//
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+//------------------------------------------------------------------------------
+#include <IndustryStandard/RiscV.h>
+
+.data
+
+.text
+.align 3
+
+.global ASM_PFX(RiscVReadMachineTimerInterface)
+//
+// Read machine mode timer CSR through shadow CSR.
+// @retval a0 : 64-bit machine timer.
+//
+ASM_PFX (RiscVReadMachineTimerInterface):
+ csrr a0, RISCV_CSR_TIME
+ ret
diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVReadMachineModeTimer/MachineModeTimerLib/MachineModeTimerLib.S b/Silicon/RISC-V/ProcessorPkg/Library/RiscVReadMachineModeTimer/MachineModeTimerLib/MachineModeTimerLib.S
new file mode 100644
index 0000000000..16f8bdd70a
--- /dev/null
+++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVReadMachineModeTimer/MachineModeTimerLib/MachineModeTimerLib.S
@@ -0,0 +1,25 @@
+//------------------------------------------------------------------------------
+//
+// Read mtimer through platform library.
+//
+// Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+//
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+//------------------------------------------------------------------------------
+#include <RiscVImpl.h>
+
+.data
+
+.text
+.align 3
+
+.global ASM_PFX(RiscVReadMachineTimerInterface)
+//
+// Read machine mode timer CSR.
+// @retval a0 : 64-bit machine timer.
+//
+ASM_PFX (RiscVReadMachineTimerInterface):
+ call RiscVReadMachineTimer
+ ret
+
--
2.31.1
next prev parent reply other threads:[~2022-01-08 8:25 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-01-08 7:24 [PATCH 42/79] RISC-V: Use RISC-V PeiCoreEntryPoint library Abner Chang
2022-01-08 7:24 ` [PATCH 43/79] Platform/RISC-V: Add library to get PPI descriptor Abner Chang
2022-01-08 7:24 ` [PATCH 44/79] Platform/RISC-V: Use PlatformSecPpiLib Abner Chang
2022-01-08 7:24 ` [PATCH 45/79] Platform/RISC-V: Add NULL library instance of RiscVSpecialPlatformLib Abner Chang
2022-01-08 7:24 ` [PATCH 46/79] Platform/RISC-V: Remove platform dependency from common platform lib Abner Chang
2022-01-08 7:24 ` [PATCH 47/79] Platform/RISC-V: Remove Null instance of OpensbiPlatformLibNull Abner Chang
2022-01-08 7:24 ` [PATCH 48/79] RiscVPlatformPkg/Sec: Initial hart_index2Id array Abner Chang
2022-01-08 7:24 ` [PATCH 49/79] RiscVPlatformPkg/OpensbiPlatformLib: Remove platform code Abner Chang
2022-01-08 7:24 ` [PATCH 50/79] RiscVPlatformPkg/RiscVSpecialPlatformLib: Rename module name Abner Chang
2022-01-08 7:24 ` [PATCH 51/79] RiscVPkg: Update opensbi library Abner Chang
2022-01-08 7:24 ` [PATCH 52/79] RiscVPlatformPkg/Sec: Check Cold/Warm hart Abner Chang
2022-01-08 7:24 ` [PATCH 53/79] RiscVPlatformPkg/Sec: Add more comments to Secmain.c Abner Chang
2022-01-08 7:24 ` Abner Chang [this message]
2022-01-08 7:24 ` [PATCH 55/79] RiscV/ProcessorPkg: Use mtime CSR library Abner Chang
2022-01-08 7:24 ` [PATCH 56/79] RISC-V/PlatformPkg: Updates for the latest OpenSBI Abner Chang
2022-01-08 7:24 ` [PATCH 57/79] PlatformPkg/Sec: Separate EDK2 Opensbi platform hook Abner Chang
2022-01-08 7:24 ` [PATCH 58/79] RISC-V/PlatformPkg: Determine hart number from DTB Abner Chang
2022-01-08 7:24 ` [PATCH 59/79] Silicon/RISC-V: Add PciCpuIoDxe driver Abner Chang
2022-01-08 7:24 ` [PATCH 60/79] Platform/RISC-V: Add debug message to SecMain.c Abner Chang
2022-01-08 7:24 ` [PATCH 61/79] Platform/RISC-V: Initialize variable to zero Abner Chang
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