* [PATCH 56/79] RISC-V/PlatformPkg: Updates for the latest OpenSBI
[not found] <20220108044518.16375-1-abner.chang@hpe.com>
@ 2022-01-08 4:45 ` Abner Chang
0 siblings, 0 replies; 21+ messages in thread
From: Abner Chang @ 2022-01-08 4:45 UTC (permalink / raw)
To: devel; +Cc: abner.chang
(This is migrated from edk2-platforms:Platform)
Code changes to incorporate with OpenSBI commit ID:
a731c7e36988c3308e1978ecde491f2f6182d490
Cc: Sunil V L <sunilvl@ventanamicro.com>
Cc: Daniel Schaefer <daniel.schaefer@hpe.com>
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Reviewed-by: Daniel Schaefer <daniel.schaefer@hpe.com>
Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
---
.../OpensbiPlatformLib/OpensbiPlatformLib.inf | 10 +-
.../PlatformPkg/Universal/Sec/SecMain.inf | 4 +
.../Library/OpensbiPlatformLib/Platform.c | 57 ----
.../Universal/Sec/Edk2OpenSbiPlatform.c | 149 ---------
.../PlatformPkg/Universal/Sec/SecMain.c | 48 ++-
.../Universal/Sec/Riscv64/SecEntry.S | 300 ++++++++++--------
6 files changed, 212 insertions(+), 356 deletions(-)
diff --git a/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/OpensbiPlatformLib.inf b/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/OpensbiPlatformLib.inf
index 909fbffa8d..2e1227733a 100644
--- a/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/OpensbiPlatformLib.inf
+++ b/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/OpensbiPlatformLib.inf
@@ -51,12 +51,4 @@
gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootableHartNumber
gUefiRiscVPlatformPkgTokenSpaceGuid.PcdOpenSbiStackSize
- gSiFiveU5SeriesPlatformsPkgTokenSpaceGuid.PcdU5UartBase
- gSiFiveU5SeriesPlatformsPkgTokenSpaceGuid.PcdU5PlatformSystemClock
-
- gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRootFirmwareDomainBaseAddress
- gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRootFirmwareDomainSize
- gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFirmwareDomainBaseAddress
- gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFirmwareDomainSize
- gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFirmwareRegionBaseAddress
- gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFirmwareRegionSize
+
diff --git a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf
index 1cfbef961f..dd5f01ab4d 100644
--- a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf
+++ b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf
@@ -66,6 +66,10 @@
gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootableHartIndexToId
gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRootFirmwareDomainBaseAddress
gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRootFirmwareDomainSize
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFirmwareDomainBaseAddress
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFirmwareDomainSize
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFirmwareRegionBaseAddress
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFirmwareRegionSize
gUefiRiscVPlatformPkgTokenSpaceGuid.PcdOpenSbiStackSize
gUefiRiscVPlatformPkgTokenSpaceGuid.PcdScratchRamBase
gUefiRiscVPlatformPkgTokenSpaceGuid.PcdScratchRamSize
diff --git a/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/Platform.c b/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/Platform.c
index b477b81d74..c62d235333 100644
--- a/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/Platform.c
+++ b/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/Platform.c
@@ -197,68 +197,11 @@ static u64 generic_tlbr_flush_limit(void)
return SBI_PLATFORM_TLB_RANGE_FLUSH_LIMIT_DEFAULT;
}
-static int generic_system_reset_check(u32 reset_type, u32 reset_reason)
-{
- if (generic_plat && generic_plat->system_reset_check)
- return generic_plat->system_reset_check(reset_type,
- reset_reason,
- generic_plat_match);
- return fdt_system_reset_check(reset_type, reset_reason);
-}
-
-static void generic_system_reset(u32 reset_type, u32 reset_reason)
-{
- if (generic_plat && generic_plat->system_reset) {
- generic_plat->system_reset(reset_type, reset_reason,
- generic_plat_match);
- return;
- }
-
- fdt_system_reset(reset_type, reset_reason);
-}
-
-#define EDK2_ROOT_FW_REGION 0
-#define EDK2_FW_REGION 1
-#define EDK2_VARIABLE_REGION 2
-#define EDK2_ALL_REGION 3
-#define EDK2_END_REGION 4
-static struct sbi_domain_memregion root_memregs[EDK2_END_REGION + 1] = { 0 };
-
-struct sbi_domain_memregion *get_mem_regions(void) {
- /* EDK2 root firmware domain memory region */
- root_memregs[EDK2_ROOT_FW_REGION].order = log2roundup(FixedPcdGet32(PcdRootFirmwareDomainSize));
- root_memregs[EDK2_ROOT_FW_REGION].base = FixedPcdGet32(PcdRootFirmwareDomainBaseAddress);
- root_memregs[EDK2_ROOT_FW_REGION].flags = 0;
-
- /*EDK2 firmware domain memory region */
- root_memregs[EDK2_FW_REGION].order = log2roundup(FixedPcdGet32(PcdFirmwareDomainSize));
- root_memregs[EDK2_FW_REGION].base = FixedPcdGet32(PcdFirmwareDomainBaseAddress);
- root_memregs[EDK2_FW_REGION].flags = SBI_DOMAIN_MEMREGION_EXECUTABLE | SBI_DOMAIN_MEMREGION_READABLE;
-
- /*EDK2 firmware domain memory region */
- root_memregs[EDK2_VARIABLE_REGION].order = log2roundup(FixedPcdGet32(PcdVariableFirmwareRegionSize));
- root_memregs[EDK2_VARIABLE_REGION].base = FixedPcdGet32(PcdVariableFirmwareRegionBaseAddress);
- root_memregs[EDK2_VARIABLE_REGION].flags = SBI_DOMAIN_MEMREGION_READABLE | SBI_DOMAIN_MEMREGION_WRITEABLE;
-
- /* EDK2 domain allow everything memory region */
- root_memregs[EDK2_ALL_REGION].order = __riscv_xlen;
- root_memregs[EDK2_ALL_REGION].base = 0;
- root_memregs[EDK2_ALL_REGION].flags = (SBI_DOMAIN_MEMREGION_READABLE |
- SBI_DOMAIN_MEMREGION_WRITEABLE |
- SBI_DOMAIN_MEMREGION_EXECUTABLE);
-
- /* EDK2 domain memory region end */
- root_memregs[EDK2_END_REGION].order = 0;
-
- return root_memregs;
-}
-
const struct sbi_platform_operations platform_ops = {
.early_init = generic_early_init,
.final_init = generic_final_init,
.early_exit = generic_early_exit,
.final_exit = generic_final_exit,
- .domains_root_regions = get_mem_regions,
.domains_init = generic_domains_init,
.console_init = fdt_serial_init,
.irqchip_init = fdt_irqchip_init,
diff --git a/Platform/RISC-V/PlatformPkg/Universal/Sec/Edk2OpenSbiPlatform.c b/Platform/RISC-V/PlatformPkg/Universal/Sec/Edk2OpenSbiPlatform.c
index 79b2f33675..779705489c 100644
--- a/Platform/RISC-V/PlatformPkg/Universal/Sec/Edk2OpenSbiPlatform.c
+++ b/Platform/RISC-V/PlatformPkg/Universal/Sec/Edk2OpenSbiPlatform.c
@@ -117,18 +117,6 @@ int Edk2OpensbiPlatforMMISAGetXLEN (VOID)
return 0;
}
-/** Get platform specific root domain memory regions */
-struct sbi_domain_memregion *
-Edk2OpensbiPlatformGetMemRegions (VOID)
-{
- DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));
-
- if (platform_ops.domains_root_regions) {
- return platform_ops.domains_root_regions ();
- }
- return 0;
-}
-
/** Initialize (or populate) domains for the platform */
int Edk2OpensbiPlatformDomainsInit (VOID)
{
@@ -140,25 +128,6 @@ int Edk2OpensbiPlatformDomainsInit (VOID)
return 0;
}
-/** Write a character to the platform console output */
-VOID Edk2OpensbiPlatformSerialPutc (
- CHAR8 Ch
- )
-{
- if (platform_ops.console_putc) {
- return platform_ops.console_putc (Ch);
- }
-}
-
-/** Read a character from the platform console input */
-int Edk2OpensbiPlatformSerialGetc (VOID)
-{
- if (platform_ops.console_getc) {
- return platform_ops.console_getc ();
- }
- return 0;
-}
-
/** Initialize the platform console */
int Edk2OpensbiPlatformSerialInit (VOID)
{
@@ -193,30 +162,6 @@ VOID Edk2OpensbiPlatformIrqchipExit (VOID)
}
}
-/** Send IPI to a target HART */
-VOID Edk2OpensbiPlatformIpiSend (
- UINT32 TargetHart
- )
-{
- DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));
-
- if (platform_ops.ipi_send) {
- return platform_ops.ipi_send (TargetHart);
- }
-}
-
-/** Clear IPI for a target HART */
-VOID Edk2OpensbiPlatformIpiClear (
- UINT32 TargetHart
- )
-{
- DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));
-
- if (platform_ops.ipi_clear) {
- return platform_ops.ipi_clear (TargetHart);
- }
-}
-
/** Initialize IPI for current HART */
int Edk2OpensbiPlatformIpiInit (
BOOLEAN ColdBoot
@@ -251,33 +196,6 @@ UINT64 Edk2OpensbiPlatformTlbrFlushLimit (VOID)
return 0;
}
-/** Get platform timer value */
-UINT64 Edk2OpensbiPlatformTimerValue (VOID)
-{
- if (platform_ops.timer_value) {
- return platform_ops.timer_value ();
- }
- return 0;
-}
-
-/** Start platform timer event for current HART */
-VOID Edk2OpensbiPlatformTimerEventStart (
- UINT64 NextEvent
- )
-{
- if (platform_ops.timer_event_start) {
- return platform_ops.timer_event_start (NextEvent);
- }
-}
-
-/** Stop platform timer event for current HART */
-VOID Edk2OpensbiPlatformTimerEventStop (VOID)
-{
- if (platform_ops.timer_event_stop) {
- return platform_ops.timer_event_stop ();
- }
-}
-
/** Initialize platform timer for current HART */
int Edk2OpensbiPlatformTimerInit (
BOOLEAN ColdBoot
@@ -301,61 +219,6 @@ VOID Edk2OpensbiPlatformTimerExit (VOID)
}
}
-/** Bringup the given hart */
-int Edk2OpensbiPlatformHartStart (
- UINT32 HartId,
- ulong Saddr
- )
-{
- DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));
-
- if (platform_ops.hart_start) {
- return platform_ops.hart_start (HartId, Saddr);
- }
- return 0;
-}
-/**
- Stop the current hart from running. This call doesn't expect to
- return if success.
-**/
-int Edk2OpensbiPlatformHartStop (VOID)
-{
- DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));
-
- if (platform_ops.hart_stop) {
- return platform_ops.hart_stop ();
- }
- return 0;
-}
-
-/**
- Check whether reset type and reason supported by the platform*
-
-**/
-int Edk2OpensbiPlatformSystemResetCheck (
- UINT32 ResetType,
- UINT32 ResetReason
- )
-{
- if (platform_ops.system_reset_check) {
- return platform_ops.system_reset_check (ResetType, ResetReason);
- }
- return 0;
-}
-
-/** Reset the platform */
-VOID Edk2OpensbiPlatformSystemReset (
- UINT32 ResetType,
- UINT32 ResetReason
- )
-{
- DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));
-
- if (platform_ops.system_reset) {
- return platform_ops.system_reset (ResetType, ResetReason);
- }
-}
-
/** platform specific SBI extension implementation probe function */
int Edk2OpensbiPlatformVendorExtCheck (
long ExtId
@@ -400,27 +263,15 @@ const struct sbi_platform_operations Edk2OpensbiPlatformOps = {
.final_exit = Edk2OpensbiPlatformFinalExit,
.misa_check_extension = Edk2OpensbiPlatforMMISACheckExtension,
.misa_get_xlen = Edk2OpensbiPlatforMMISAGetXLEN,
- .domains_root_regions = Edk2OpensbiPlatformGetMemRegions,
.domains_init = Edk2OpensbiPlatformDomainsInit,
- .console_putc = Edk2OpensbiPlatformSerialPutc,
- .console_getc = Edk2OpensbiPlatformSerialGetc,
.console_init = Edk2OpensbiPlatformSerialInit,
.irqchip_init = Edk2OpensbiPlatformIrqchipInit,
.irqchip_exit = Edk2OpensbiPlatformIrqchipExit,
- .ipi_send = Edk2OpensbiPlatformIpiSend,
- .ipi_clear = Edk2OpensbiPlatformIpiClear,
.ipi_init = Edk2OpensbiPlatformIpiInit,
.ipi_exit = Edk2OpensbiPlatformIpiExit,
.get_tlbr_flush_limit = Edk2OpensbiPlatformTlbrFlushLimit,
- .timer_value = Edk2OpensbiPlatformTimerValue,
- .timer_event_stop = Edk2OpensbiPlatformTimerEventStop,
- .timer_event_start = Edk2OpensbiPlatformTimerEventStart,
.timer_init = Edk2OpensbiPlatformTimerInit,
.timer_exit = Edk2OpensbiPlatformTimerExit,
- .hart_start = Edk2OpensbiPlatformHartStart,
- .hart_stop = Edk2OpensbiPlatformHartStop,
- .system_reset_check = Edk2OpensbiPlatformSystemResetCheck,
- .system_reset = Edk2OpensbiPlatformSystemReset,
.vendor_ext_check = Edk2OpensbiPlatformVendorExtCheck,
.vendor_ext_provider = Edk2OpensbiPlatformVendorExtProvider,
};
diff --git a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c
index 93ff8a598d..3bc3690047 100644
--- a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c
+++ b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c
@@ -15,10 +15,12 @@
#include <sbi/riscv_asm.h>
#include <sbi/riscv_atomic.h>
#include <sbi/sbi_console.h> // Reference to header file in opensbi
+#include <sbi/sbi_domain.h>
#include <sbi/sbi_hart.h> // Reference to header file in opensbi
-#include <sbi/sbi_hartmask.h> // Reference to header file in opensbi
+#include <sbi/sbi_hartmask.h> // Reference to header file in opensbi
#include <sbi/sbi_scratch.h> // Reference to header file in opensbi
#include <sbi/sbi_platform.h> // Reference to header file in opensbi
+#include <sbi/sbi_math.h> // Reference to header file in opensbi
#include <sbi/sbi_init.h> // Reference to header file in opensbi
#include <sbi/sbi_ecall.h> // Reference to header file in opensbi
#include <sbi/sbi_trap.h> // Reference to header file in opensbi
@@ -31,8 +33,41 @@ extern struct sbi_platform_operations Edk2OpensbiPlatformOps;
atomic_t BootHartDone = ATOMIC_INITIALIZER(0);
atomic_t NonBootHartMessageLock = ATOMIC_INITIALIZER(0);
+int sbi_domain_root_add_memregion(const struct sbi_domain_memregion *reg);
+
typedef struct sbi_scratch *(*hartid2scratch)(ulong hartid, ulong hartindex);
+struct sbi_domain_memregion fw_memregs;
+
+int SecSetEdk2FwMemoryRegions (VOID) {
+ int Ret;
+
+ Ret = 0;
+
+ //
+ // EDK2 PEI domain memory region
+ //
+ fw_memregs.order = log2roundup(FixedPcdGet32(PcdFirmwareDomainSize));
+ fw_memregs.base = FixedPcdGet32(PcdFirmwareDomainBaseAddress);
+ fw_memregs.flags = SBI_DOMAIN_MEMREGION_EXECUTABLE | SBI_DOMAIN_MEMREGION_READABLE;
+ Ret = sbi_domain_root_add_memregion ((const struct sbi_domain_memregion *)&fw_memregs);
+ if (Ret != 0) {
+ DEBUG ((DEBUG_ERROR, "%a: Add firmware regiosn of FW Domain fail\n", __FUNCTION__));
+ }
+
+ //
+ // EDK2 EFI Variable domain memory region
+ //
+ fw_memregs.order = log2roundup(FixedPcdGet32(PcdVariableFirmwareRegionSize));
+ fw_memregs.base = FixedPcdGet32(PcdVariableFirmwareRegionBaseAddress);
+ fw_memregs.flags = SBI_DOMAIN_MEMREGION_READABLE | SBI_DOMAIN_MEMREGION_WRITEABLE;
+ Ret = sbi_domain_root_add_memregion ((const struct sbi_domain_memregion *)&fw_memregs);
+ if (Ret != 0) {
+ DEBUG ((DEBUG_ERROR, "%a: Add firmware regiosn of variable FW Domain fail\n", __FUNCTION__));
+ }
+ return Ret;
+}
+
/**
Locates a section within a series of sections
with the specified section type.
@@ -405,6 +440,13 @@ SecPostOpenSbiPlatformEarlylInit(
DEBUG ((DEBUG_INFO, "%a: Non boot hart %d.\n", __FUNCTION__, HartId));
return 0;
}
+ //
+ // Setup firmware memory region.
+ //
+ if (SecSetEdk2FwMemoryRegions () != 0) {
+ ASSERT (FALSE);
+ }
+
//
// Boot HART is already in the process of OpenSBI initialization.
// We can let other HART to keep booting.
@@ -477,7 +519,7 @@ SecPostOpenSbiPlatformFinalInit (
}
}
- DEBUG((DEBUG_INFO, "%a: Jump to PEI Core with \n", __FUNCTION__));
+ DEBUG((DEBUG_INFO, "%a: Will jump to PEI Core in OpenSBI with \n", __FUNCTION__));
DEBUG((DEBUG_INFO, " sbi_scratch = %x\n", SbiScratch));
DEBUG((DEBUG_INFO, " sbi_platform = %x\n", SbiPlatform));
DEBUG((DEBUG_INFO, " FirmwareContext = %x\n", FirmwareContext));
@@ -793,7 +835,7 @@ VOID EFIAPI SecCoreStartUpWithStack(
sbi_init(Scratch);
}
-void OpensbiDebugPrint (char *debugstr, ...)
+VOID OpensbiDebugPrint (CHAR8 *debugstr, ...)
{
VA_LIST Marker;
diff --git a/Platform/RISC-V/PlatformPkg/Universal/Sec/Riscv64/SecEntry.S b/Platform/RISC-V/PlatformPkg/Universal/Sec/Riscv64/SecEntry.S
index f0c3dff0d9..96087738a3 100644
--- a/Platform/RISC-V/PlatformPkg/Universal/Sec/Riscv64/SecEntry.S
+++ b/Platform/RISC-V/PlatformPkg/Universal/Sec/Riscv64/SecEntry.S
@@ -18,6 +18,12 @@
#include <SecMain.h>
+.macro MOV_3R __d0, __s0, __d1, __s1, __d2, __s2
+ add \__d0, \__s0, zero
+ add \__d1, \__s1, zero
+ add \__d2, \__s2, zero
+.endm
+
.text
.align 3
@@ -90,7 +96,11 @@ _scratch_init:
la a4, _hartid_to_scratch
sd a4, SBI_SCRATCH_HARTID_TO_SCRATCH_OFFSET(tp) /* Save _hartid_to_scratch function in scratch buffer*/
sd zero, SBI_SCRATCH_TMP0_OFFSET(tp)
-
+ /* Store trap-exit function address in scratch space */
+ lla a4, _trap_exit
+ sd a4, SBI_SCRATCH_TRAP_EXIT_OFFSET(tp)
+ /* Clear tmp0 in scratch space */
+ sd zero, SBI_SCRATCH_TMP0_OFFSET(tp)
#ifdef FW_OPTIONS
li a4, FW_OPTIONS
sd a4, SBI_SCRATCH_OPTIONS_OFFSET(tp)
@@ -322,160 +332,174 @@ _uninitialized_hart_wait:
wfi
j _uninitialized_hart_wait
- .align 3
- .section .entry, "ax", %progbits
- .align 3
- .globl _trap_handler
-_trap_handler:
-
+.macro TRAP_SAVE_AND_SETUP_SP_T0
/* Swap TP and MSCRATCH */
- csrrw tp, CSR_MSCRATCH, tp
+ csrrw tp, CSR_MSCRATCH, tp
/* Save T0 in scratch space */
- REG_S t0, SBI_SCRATCH_TMP0_OFFSET(tp)
+ REG_S t0, SBI_SCRATCH_TMP0_OFFSET(tp)
- /* Check which mode we came from */
- csrr t0, CSR_MSTATUS
- srl t0, t0, MSTATUS_MPP_SHIFT
- and t0, t0, PRV_M
- xori t0, t0, PRV_M
- beq t0, zero, _trap_handler_m_mode
-
- /* We came from S-mode or U-mode */
-_trap_handler_s_mode:
- /* Set T0 to original SP */
- add t0, sp, zero
-
- /* Setup exception stack */
- add sp, tp, -(SBI_TRAP_REGS_SIZE)
-
- /* Jump to code common for all modes */
- j _trap_handler_all_mode
-
- /* We came from M-mode */
-_trap_handler_m_mode:
- /* Set T0 to original SP */
- add t0, sp, zero
-
- /* Re-use current SP as exception stack */
- add sp, sp, -(SBI_TRAP_REGS_SIZE)
-
-_trap_handler_all_mode:
- /* Save original SP (from T0) on stack */
- REG_S t0, SBI_TRAP_REGS_OFFSET(sp)(sp)
+ /*
+ * Set T0 to appropriate exception stack
+ *
+ * Came_From_M_Mode = ((MSTATUS.MPP < PRV_M) ? 1 : 0) - 1;
+ * Exception_Stack = TP ^ (Came_From_M_Mode & (SP ^ TP))
+ *
+ * Came_From_M_Mode = 0 ==> Exception_Stack = TP
+ * Came_From_M_Mode = -1 ==> Exception_Stack = SP
+ */
+ csrr t0, CSR_MSTATUS
+ srl t0, t0, MSTATUS_MPP_SHIFT
+ and t0, t0, PRV_M
+ slti t0, t0, PRV_M
+ add t0, t0, -1
+ xor sp, sp, tp
+ and t0, t0, sp
+ xor sp, sp, tp
+ xor t0, tp, t0
+
+ /* Save original SP on exception stack */
+ REG_S sp, (SBI_TRAP_REGS_OFFSET(sp) - SBI_TRAP_REGS_SIZE)(t0)
+
+ /* Set SP to exception stack and make room for trap registers */
+ add sp, t0, -(SBI_TRAP_REGS_SIZE)
/* Restore T0 from scratch space */
- REG_L t0, SBI_SCRATCH_TMP0_OFFSET(tp)
+ REG_L t0, SBI_SCRATCH_TMP0_OFFSET(tp)
/* Save T0 on stack */
- REG_S t0, SBI_TRAP_REGS_OFFSET(t0)(sp)
+ REG_S t0, SBI_TRAP_REGS_OFFSET(t0)(sp)
/* Swap TP and MSCRATCH */
- csrrw tp, CSR_MSCRATCH, tp
+ csrrw tp, CSR_MSCRATCH, tp
+.endm
+.macro TRAP_SAVE_MEPC_MSTATUS have_mstatush
/* Save MEPC and MSTATUS CSRs */
- csrr t0, CSR_MEPC
- REG_S t0, SBI_TRAP_REGS_OFFSET(mepc)(sp)
- csrr t0, CSR_MSTATUS
- REG_S t0, SBI_TRAP_REGS_OFFSET(mstatus)(sp)
- REG_S zero, SBI_TRAP_REGS_OFFSET(mstatusH)(sp)
-#if __riscv_xlen == 32
- csrr t0, CSR_MISA
- srli t0, t0, ('H' - 'A')
- andi t0, t0, 0x1
- beq t0, zero, _skip_mstatush_save
- csrr t0, CSR_MSTATUSH
- REG_S t0, SBI_TRAP_REGS_OFFSET(mstatusH)(sp)
-_skip_mstatush_save:
-#endif
+ csrr t0, CSR_MEPC
+ REG_S t0, SBI_TRAP_REGS_OFFSET(mepc)(sp)
+ csrr t0, CSR_MSTATUS
+ REG_S t0, SBI_TRAP_REGS_OFFSET(mstatus)(sp)
+.if \have_mstatush
+ csrr t0, CSR_MSTATUSH
+ REG_S t0, SBI_TRAP_REGS_OFFSET(mstatusH)(sp)
+.else
+ REG_S zero, SBI_TRAP_REGS_OFFSET(mstatusH)(sp)
+.endif
+.endm
+
+.macro TRAP_SAVE_GENERAL_REGS_EXCEPT_SP_T0
+ /* Save all general regisers except SP and T0 */
+ REG_S zero, SBI_TRAP_REGS_OFFSET(zero)(sp)
+ REG_S ra, SBI_TRAP_REGS_OFFSET(ra)(sp)
+ REG_S gp, SBI_TRAP_REGS_OFFSET(gp)(sp)
+ REG_S tp, SBI_TRAP_REGS_OFFSET(tp)(sp)
+ REG_S t1, SBI_TRAP_REGS_OFFSET(t1)(sp)
+ REG_S t2, SBI_TRAP_REGS_OFFSET(t2)(sp)
+ REG_S s0, SBI_TRAP_REGS_OFFSET(s0)(sp)
+ REG_S s1, SBI_TRAP_REGS_OFFSET(s1)(sp)
+ REG_S a0, SBI_TRAP_REGS_OFFSET(a0)(sp)
+ REG_S a1, SBI_TRAP_REGS_OFFSET(a1)(sp)
+ REG_S a2, SBI_TRAP_REGS_OFFSET(a2)(sp)
+ REG_S a3, SBI_TRAP_REGS_OFFSET(a3)(sp)
+ REG_S a4, SBI_TRAP_REGS_OFFSET(a4)(sp)
+ REG_S a5, SBI_TRAP_REGS_OFFSET(a5)(sp)
+ REG_S a6, SBI_TRAP_REGS_OFFSET(a6)(sp)
+ REG_S a7, SBI_TRAP_REGS_OFFSET(a7)(sp)
+ REG_S s2, SBI_TRAP_REGS_OFFSET(s2)(sp)
+ REG_S s3, SBI_TRAP_REGS_OFFSET(s3)(sp)
+ REG_S s4, SBI_TRAP_REGS_OFFSET(s4)(sp)
+ REG_S s5, SBI_TRAP_REGS_OFFSET(s5)(sp)
+ REG_S s6, SBI_TRAP_REGS_OFFSET(s6)(sp)
+ REG_S s7, SBI_TRAP_REGS_OFFSET(s7)(sp)
+ REG_S s8, SBI_TRAP_REGS_OFFSET(s8)(sp)
+ REG_S s9, SBI_TRAP_REGS_OFFSET(s9)(sp)
+ REG_S s10, SBI_TRAP_REGS_OFFSET(s10)(sp)
+ REG_S s11, SBI_TRAP_REGS_OFFSET(s11)(sp)
+ REG_S t3, SBI_TRAP_REGS_OFFSET(t3)(sp)
+ REG_S t4, SBI_TRAP_REGS_OFFSET(t4)(sp)
+ REG_S t5, SBI_TRAP_REGS_OFFSET(t5)(sp)
+ REG_S t6, SBI_TRAP_REGS_OFFSET(t6)(sp)
+.endm
+
+.macro TRAP_CALL_C_ROUTINE
+ /* Call C routine */
+ add a0, sp, zero
+ call sbi_trap_handler
+.endm
+
+.macro TRAP_RESTORE_GENERAL_REGS_EXCEPT_A0_T0
+ /* Restore all general regisers except A0 and T0 */
+ REG_L ra, SBI_TRAP_REGS_OFFSET(ra)(a0)
+ REG_L sp, SBI_TRAP_REGS_OFFSET(sp)(a0)
+ REG_L gp, SBI_TRAP_REGS_OFFSET(gp)(a0)
+ REG_L tp, SBI_TRAP_REGS_OFFSET(tp)(a0)
+ REG_L t1, SBI_TRAP_REGS_OFFSET(t1)(a0)
+ REG_L t2, SBI_TRAP_REGS_OFFSET(t2)(a0)
+ REG_L s0, SBI_TRAP_REGS_OFFSET(s0)(a0)
+ REG_L s1, SBI_TRAP_REGS_OFFSET(s1)(a0)
+ REG_L a1, SBI_TRAP_REGS_OFFSET(a1)(a0)
+ REG_L a2, SBI_TRAP_REGS_OFFSET(a2)(a0)
+ REG_L a3, SBI_TRAP_REGS_OFFSET(a3)(a0)
+ REG_L a4, SBI_TRAP_REGS_OFFSET(a4)(a0)
+ REG_L a5, SBI_TRAP_REGS_OFFSET(a5)(a0)
+ REG_L a6, SBI_TRAP_REGS_OFFSET(a6)(a0)
+ REG_L a7, SBI_TRAP_REGS_OFFSET(a7)(a0)
+ REG_L s2, SBI_TRAP_REGS_OFFSET(s2)(a0)
+ REG_L s3, SBI_TRAP_REGS_OFFSET(s3)(a0)
+ REG_L s4, SBI_TRAP_REGS_OFFSET(s4)(a0)
+ REG_L s5, SBI_TRAP_REGS_OFFSET(s5)(a0)
+ REG_L s6, SBI_TRAP_REGS_OFFSET(s6)(a0)
+ REG_L s7, SBI_TRAP_REGS_OFFSET(s7)(a0)
+ REG_L s8, SBI_TRAP_REGS_OFFSET(s8)(a0)
+ REG_L s9, SBI_TRAP_REGS_OFFSET(s9)(a0)
+ REG_L s10, SBI_TRAP_REGS_OFFSET(s10)(a0)
+ REG_L s11, SBI_TRAP_REGS_OFFSET(s11)(a0)
+ REG_L t3, SBI_TRAP_REGS_OFFSET(t3)(a0)
+ REG_L t4, SBI_TRAP_REGS_OFFSET(t4)(a0)
+ REG_L t5, SBI_TRAP_REGS_OFFSET(t5)(a0)
+ REG_L t6, SBI_TRAP_REGS_OFFSET(t6)(a0)
+.endm
+
+.macro TRAP_RESTORE_MEPC_MSTATUS have_mstatush
+ /* Restore MEPC and MSTATUS CSRs */
+ REG_L t0, SBI_TRAP_REGS_OFFSET(mepc)(a0)
+ csrw CSR_MEPC, t0
+ REG_L t0, SBI_TRAP_REGS_OFFSET(mstatus)(a0)
+ csrw CSR_MSTATUS, t0
+.if \have_mstatush
+ REG_L t0, SBI_TRAP_REGS_OFFSET(mstatusH)(a0)
+ csrw CSR_MSTATUSH, t0
+.endif
+.endm
+
+.macro TRAP_RESTORE_A0_T0
+ /* Restore T0 */
+ REG_L t0, SBI_TRAP_REGS_OFFSET(t0)(a0)
- /* Save all general registers except SP and T0 */
- REG_S zero, SBI_TRAP_REGS_OFFSET(zero)(sp)
- REG_S ra, SBI_TRAP_REGS_OFFSET(ra)(sp)
- REG_S gp, SBI_TRAP_REGS_OFFSET(gp)(sp)
- REG_S tp, SBI_TRAP_REGS_OFFSET(tp)(sp)
- REG_S t1, SBI_TRAP_REGS_OFFSET(t1)(sp)
- REG_S t2, SBI_TRAP_REGS_OFFSET(t2)(sp)
- REG_S s0, SBI_TRAP_REGS_OFFSET(s0)(sp)
- REG_S s1, SBI_TRAP_REGS_OFFSET(s1)(sp)
- REG_S a0, SBI_TRAP_REGS_OFFSET(a0)(sp)
- REG_S a1, SBI_TRAP_REGS_OFFSET(a1)(sp)
- REG_S a2, SBI_TRAP_REGS_OFFSET(a2)(sp)
- REG_S a3, SBI_TRAP_REGS_OFFSET(a3)(sp)
- REG_S a4, SBI_TRAP_REGS_OFFSET(a4)(sp)
- REG_S a5, SBI_TRAP_REGS_OFFSET(a5)(sp)
- REG_S a6, SBI_TRAP_REGS_OFFSET(a6)(sp)
- REG_S a7, SBI_TRAP_REGS_OFFSET(a7)(sp)
- REG_S s2, SBI_TRAP_REGS_OFFSET(s2)(sp)
- REG_S s3, SBI_TRAP_REGS_OFFSET(s3)(sp)
- REG_S s4, SBI_TRAP_REGS_OFFSET(s4)(sp)
- REG_S s5, SBI_TRAP_REGS_OFFSET(s5)(sp)
- REG_S s6, SBI_TRAP_REGS_OFFSET(s6)(sp)
- REG_S s7, SBI_TRAP_REGS_OFFSET(s7)(sp)
- REG_S s8, SBI_TRAP_REGS_OFFSET(s8)(sp)
- REG_S s9, SBI_TRAP_REGS_OFFSET(s9)(sp)
- REG_S s10, SBI_TRAP_REGS_OFFSET(s10)(sp)
- REG_S s11, SBI_TRAP_REGS_OFFSET(s11)(sp)
- REG_S t3, SBI_TRAP_REGS_OFFSET(t3)(sp)
- REG_S t4, SBI_TRAP_REGS_OFFSET(t4)(sp)
- REG_S t5, SBI_TRAP_REGS_OFFSET(t5)(sp)
- REG_S t6, SBI_TRAP_REGS_OFFSET(t6)(sp)
+ /* Restore A0 */
+ REG_L a0, SBI_TRAP_REGS_OFFSET(a0)(a0)
+.endm
- /* Call C routine */
- add a0, sp, zero
- call sbi_trap_handler
-
- /* Restore all general registers except SP and T0 */
- REG_L ra, SBI_TRAP_REGS_OFFSET(ra)(sp)
- REG_L gp, SBI_TRAP_REGS_OFFSET(gp)(sp)
- REG_L tp, SBI_TRAP_REGS_OFFSET(tp)(sp)
- REG_L t1, SBI_TRAP_REGS_OFFSET(t1)(sp)
- REG_L t2, SBI_TRAP_REGS_OFFSET(t2)(sp)
- REG_L s0, SBI_TRAP_REGS_OFFSET(s0)(sp)
- REG_L s1, SBI_TRAP_REGS_OFFSET(s1)(sp)
- REG_L a0, SBI_TRAP_REGS_OFFSET(a0)(sp)
- REG_L a1, SBI_TRAP_REGS_OFFSET(a1)(sp)
- REG_L a2, SBI_TRAP_REGS_OFFSET(a2)(sp)
- REG_L a3, SBI_TRAP_REGS_OFFSET(a3)(sp)
- REG_L a4, SBI_TRAP_REGS_OFFSET(a4)(sp)
- REG_L a5, SBI_TRAP_REGS_OFFSET(a5)(sp)
- REG_L a6, SBI_TRAP_REGS_OFFSET(a6)(sp)
- REG_L a7, SBI_TRAP_REGS_OFFSET(a7)(sp)
- REG_L s2, SBI_TRAP_REGS_OFFSET(s2)(sp)
- REG_L s3, SBI_TRAP_REGS_OFFSET(s3)(sp)
- REG_L s4, SBI_TRAP_REGS_OFFSET(s4)(sp)
- REG_L s5, SBI_TRAP_REGS_OFFSET(s5)(sp)
- REG_L s6, SBI_TRAP_REGS_OFFSET(s6)(sp)
- REG_L s7, SBI_TRAP_REGS_OFFSET(s7)(sp)
- REG_L s8, SBI_TRAP_REGS_OFFSET(s8)(sp)
- REG_L s9, SBI_TRAP_REGS_OFFSET(s9)(sp)
- REG_L s10, SBI_TRAP_REGS_OFFSET(s10)(sp)
- REG_L s11, SBI_TRAP_REGS_OFFSET(s11)(sp)
- REG_L t3, SBI_TRAP_REGS_OFFSET(t3)(sp)
- REG_L t4, SBI_TRAP_REGS_OFFSET(t4)(sp)
- REG_L t5, SBI_TRAP_REGS_OFFSET(t5)(sp)
- REG_L t6, SBI_TRAP_REGS_OFFSET(t6)(sp)
+ .section .entry, "ax", %progbits
+ .align 3
+ .globl _trap_handler
+ .globl _trap_exit
+_trap_handler:
+ TRAP_SAVE_AND_SETUP_SP_T0
- /* Restore MEPC and MSTATUS CSRs */
- REG_L t0, SBI_TRAP_REGS_OFFSET(mepc)(sp)
- csrw CSR_MEPC, t0
- REG_L t0, SBI_TRAP_REGS_OFFSET(mstatus)(sp)
- csrw CSR_MSTATUS, t0
-#if __riscv_xlen == 32
- csrr t0, CSR_MISA
- srli t0, t0, ('H' - 'A')
- andi t0, t0, 0x1
- beq t0, zero, _skip_mstatush_restore
- REG_L t0, SBI_TRAP_REGS_OFFSET(mstatusH)(sp)
- csrw CSR_MSTATUSH, t0
-_skip_mstatush_restore:
-#endif
+ TRAP_SAVE_MEPC_MSTATUS 0
- /* Restore T0 */
- REG_L t0, SBI_TRAP_REGS_OFFSET(t0)(sp)
+ TRAP_SAVE_GENERAL_REGS_EXCEPT_SP_T0
+
+ TRAP_CALL_C_ROUTINE
+
+_trap_exit:
+ TRAP_RESTORE_GENERAL_REGS_EXCEPT_A0_T0
+
+ TRAP_RESTORE_MEPC_MSTATUS 0
- /* Restore SP */
- REG_L sp, SBI_TRAP_REGS_OFFSET(sp)(sp)
+ TRAP_RESTORE_A0_T0
mret
--
2.31.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH 42/79] RISC-V: Use RISC-V PeiCoreEntryPoint library
@ 2022-01-08 7:24 Abner Chang
2022-01-08 7:24 ` [PATCH 43/79] Platform/RISC-V: Add library to get PPI descriptor Abner Chang
` (18 more replies)
0 siblings, 19 replies; 21+ messages in thread
From: Abner Chang @ 2022-01-08 7:24 UTC (permalink / raw)
To: devel; +Cc: abner.chang
(This is migrated from edk2-platforms)
1. Use RISC-V PeiCoreEntryPoint library instance for opensbi
to switch to the next phase with arg0 as HART Id and arg1
as the SEC to PEI handoff data.
2. Introduce EDK2 opensbi platform operation functions.
With this, OEM can has its won platform initialization code
before and/or after opensbi vendor platform functions.
Cc: Sunil V L <sunilvl@ventanamicro.com>
Cc: Daniel Schaefer <daniel.schaefer@hpe.com>
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Reviewed-by: Daniel Schaefer <daniel.schaefer@hpe.com>
Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
---
.../PlatformPkg/Universal/Sec/SecMain.inf | 2 +
.../PlatformPkg/Universal/Sec/SecMain.h | 10 +
.../Include/IndustryStandard/RiscVOpensbi.h | 8 +-
.../Universal/Sec/Edk2OpenSbiPlatform.c | 426 ++++++++++++++++++
.../PlatformPkg/Universal/Sec/SecMain.c | 152 +++++--
5 files changed, 545 insertions(+), 53 deletions(-)
create mode 100644 Platform/RISC-V/PlatformPkg/Universal/Sec/Edk2OpenSbiPlatform.c
diff --git a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf
index bcb8b9f908..4207c83413 100644
--- a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf
+++ b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf
@@ -23,11 +23,13 @@
[Sources]
SecMain.c
+ Edk2OpenSbiPlatform.c
[Sources.RISCV64]
Riscv64/SecEntry.S
[Packages]
+ EmbeddedPkg/EmbeddedPkg.dec
MdeModulePkg/MdeModulePkg.dec
MdePkg/MdePkg.dec
Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec
diff --git a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.h b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.h
index 94ea46263c..c04ddbad7f 100644
--- a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.h
+++ b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.h
@@ -28,6 +28,16 @@
#include <Ppi/TemporaryRamDone.h>
#include <Ppi/TemporaryRamSupport.h>
+int
+SecPostOpenSbiPlatformEarlylInit(
+ IN BOOLEAN ColdBoot
+ );
+
+int
+SecPostOpenSbiPlatformFinalInit (
+ IN BOOLEAN ColdBoot
+ );
+
VOID
SecMachineModeTrapHandler (
IN VOID
diff --git a/Silicon/RISC-V/ProcessorPkg/Include/IndustryStandard/RiscVOpensbi.h b/Silicon/RISC-V/ProcessorPkg/Include/IndustryStandard/RiscVOpensbi.h
index e7ac6d26ee..d639429306 100644
--- a/Silicon/RISC-V/ProcessorPkg/Include/IndustryStandard/RiscVOpensbi.h
+++ b/Silicon/RISC-V/ProcessorPkg/Include/IndustryStandard/RiscVOpensbi.h
@@ -1,7 +1,7 @@
/** @file
SBI inline function calls.
- Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+ Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -46,8 +46,10 @@ typedef struct {
// structure. Referred by both C code and assembly code.
typedef struct {
- VOID *PeiServiceTable; // PEI Service table
- UINT64 FlattenedDeviceTree; // Pointer to Flattened Device tree
+ UINT64 BootHartId;
+ VOID *PeiServiceTable; // PEI Service table
+ UINT64 FlattenedDeviceTree; // Pointer to Flattened Device tree
+ UINT64 SecPeiHandOffData; // This is EFI_SEC_PEI_HAND_OFF passed to PEI Core.
EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC *HartSpecific[RISC_V_MAX_HART_SUPPORTED];
} EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT;
diff --git a/Platform/RISC-V/PlatformPkg/Universal/Sec/Edk2OpenSbiPlatform.c b/Platform/RISC-V/PlatformPkg/Universal/Sec/Edk2OpenSbiPlatform.c
new file mode 100644
index 0000000000..79b2f33675
--- /dev/null
+++ b/Platform/RISC-V/PlatformPkg/Universal/Sec/Edk2OpenSbiPlatform.c
@@ -0,0 +1,426 @@
+/*
+ Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ */
+
+#include <Library/DebugAgentLib.h>
+#include <Library/DebugLib.h>
+
+#include <libfdt.h>
+#include <sbi/riscv_asm.h>
+#include <sbi/sbi_domain.h>
+#include <sbi/sbi_hartmask.h>
+#include <sbi/sbi_platform.h>
+#include <sbi/sbi_string.h>
+#include <sbi/sbi_math.h>
+#include <sbi_utils/fdt/fdt_domain.h>
+#include <sbi_utils/fdt/fdt_fixup.h>
+#include <sbi_utils/fdt/fdt_helper.h>
+#include <sbi_utils/irqchip/fdt_irqchip.h>
+#include <sbi_utils/serial/fdt_serial.h>
+#include <sbi_utils/timer/fdt_timer.h>
+#include <sbi_utils/ipi/fdt_ipi.h>
+#include <sbi_utils/reset/fdt_reset.h>
+
+#include "SecMain.h"
+
+extern struct sbi_platform_operations platform_ops;
+
+int Edk2OpensbiPlatformEarlyInit (
+ BOOLEAN ColdBoot
+ )
+{
+ int ReturnCode;
+
+ DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));
+
+ if (platform_ops.early_init) {
+ ReturnCode = platform_ops.early_init (ColdBoot);
+ if (ReturnCode) {
+ return ReturnCode;
+ }
+ }
+ if (ColdBoot == TRUE) {
+ return SecPostOpenSbiPlatformEarlylInit(ColdBoot);
+ }
+ return 0;
+}
+
+int Edk2OpensbiPlatformFinalInit (
+ BOOLEAN ColdBoot
+ )
+{
+ int ReturnCode;
+
+ DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));
+
+ if (platform_ops.final_init) {
+ ReturnCode = platform_ops.final_init (ColdBoot);
+ if (ReturnCode) {
+ return ReturnCode;
+ }
+ }
+ if (ColdBoot == TRUE) {
+ return SecPostOpenSbiPlatformFinalInit(ColdBoot);
+ }
+ return 0;
+}
+
+VOID Edk2OpensbiPlatformEarlyExit (
+ VOID
+ )
+{
+ DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));
+
+ if (platform_ops.early_exit) {
+ return platform_ops.early_exit ();
+ }
+}
+
+/** Platform final exit */
+VOID Edk2OpensbiPlatformFinalExit (
+ VOID
+ )
+{
+ DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));
+
+ if (platform_ops.early_exit) {
+ return platform_ops.early_exit ();
+ }
+}
+
+/**
+ For platforms that do not implement misa, non-standard
+ methods are needed to determine cpu extension.
+**/
+int Edk2OpensbiPlatforMMISACheckExtension (
+ CHAR8 Extension
+ )
+{
+ if (platform_ops.misa_check_extension) {
+ return platform_ops.misa_check_extension (Extension);
+ }
+ return 0;
+}
+
+/**
+ For platforms that do not implement misa, non-standard
+ methods are needed to get MXL field of misa.
+**/
+int Edk2OpensbiPlatforMMISAGetXLEN (VOID)
+{
+ if (platform_ops.misa_get_xlen) {
+ return platform_ops.misa_get_xlen ();
+ }
+ return 0;
+}
+
+/** Get platform specific root domain memory regions */
+struct sbi_domain_memregion *
+Edk2OpensbiPlatformGetMemRegions (VOID)
+{
+ DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));
+
+ if (platform_ops.domains_root_regions) {
+ return platform_ops.domains_root_regions ();
+ }
+ return 0;
+}
+
+/** Initialize (or populate) domains for the platform */
+int Edk2OpensbiPlatformDomainsInit (VOID)
+{
+ DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));
+
+ if (platform_ops.domains_init) {
+ return platform_ops.domains_init ();
+ }
+ return 0;
+}
+
+/** Write a character to the platform console output */
+VOID Edk2OpensbiPlatformSerialPutc (
+ CHAR8 Ch
+ )
+{
+ if (platform_ops.console_putc) {
+ return platform_ops.console_putc (Ch);
+ }
+}
+
+/** Read a character from the platform console input */
+int Edk2OpensbiPlatformSerialGetc (VOID)
+{
+ if (platform_ops.console_getc) {
+ return platform_ops.console_getc ();
+ }
+ return 0;
+}
+
+/** Initialize the platform console */
+int Edk2OpensbiPlatformSerialInit (VOID)
+{
+ DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));
+
+ if (platform_ops.console_init) {
+ return platform_ops.console_init ();
+ }
+ return 0;
+}
+
+/** Initialize the platform interrupt controller for current HART */
+int Edk2OpensbiPlatformIrqchipInit (
+ BOOLEAN ColdBoot
+ )
+{
+ DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));
+
+ if (platform_ops.irqchip_init) {
+ return platform_ops.irqchip_init (ColdBoot);
+ }
+ return 0;
+}
+
+/** Exit the platform interrupt controller for current HART */
+VOID Edk2OpensbiPlatformIrqchipExit (VOID)
+{
+ DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));
+
+ if (platform_ops.irqchip_exit) {
+ return platform_ops.irqchip_exit ();
+ }
+}
+
+/** Send IPI to a target HART */
+VOID Edk2OpensbiPlatformIpiSend (
+ UINT32 TargetHart
+ )
+{
+ DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));
+
+ if (platform_ops.ipi_send) {
+ return platform_ops.ipi_send (TargetHart);
+ }
+}
+
+/** Clear IPI for a target HART */
+VOID Edk2OpensbiPlatformIpiClear (
+ UINT32 TargetHart
+ )
+{
+ DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));
+
+ if (platform_ops.ipi_clear) {
+ return platform_ops.ipi_clear (TargetHart);
+ }
+}
+
+/** Initialize IPI for current HART */
+int Edk2OpensbiPlatformIpiInit (
+ BOOLEAN ColdBoot
+ )
+{
+ DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));
+
+ if (platform_ops.ipi_init) {
+ return platform_ops.ipi_init (ColdBoot);
+ }
+ return 0;
+}
+
+/** Exit IPI for current HART */
+VOID Edk2OpensbiPlatformIpiExit (VOID)
+{
+ DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));
+
+ if (platform_ops.ipi_exit) {
+ return platform_ops.ipi_exit ();
+ }
+}
+
+/** Get tlb flush limit value **/
+UINT64 Edk2OpensbiPlatformTlbrFlushLimit (VOID)
+{
+ DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));
+
+ if (platform_ops.get_tlbr_flush_limit) {
+ return platform_ops.get_tlbr_flush_limit ();
+ }
+ return 0;
+}
+
+/** Get platform timer value */
+UINT64 Edk2OpensbiPlatformTimerValue (VOID)
+{
+ if (platform_ops.timer_value) {
+ return platform_ops.timer_value ();
+ }
+ return 0;
+}
+
+/** Start platform timer event for current HART */
+VOID Edk2OpensbiPlatformTimerEventStart (
+ UINT64 NextEvent
+ )
+{
+ if (platform_ops.timer_event_start) {
+ return platform_ops.timer_event_start (NextEvent);
+ }
+}
+
+/** Stop platform timer event for current HART */
+VOID Edk2OpensbiPlatformTimerEventStop (VOID)
+{
+ if (platform_ops.timer_event_stop) {
+ return platform_ops.timer_event_stop ();
+ }
+}
+
+/** Initialize platform timer for current HART */
+int Edk2OpensbiPlatformTimerInit (
+ BOOLEAN ColdBoot
+ )
+{
+ DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));
+
+ if (platform_ops.timer_init) {
+ return platform_ops.timer_init (ColdBoot);
+ }
+ return 0;
+}
+
+/** Exit platform timer for current HART */
+VOID Edk2OpensbiPlatformTimerExit (VOID)
+{
+ DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));
+
+ if (platform_ops.timer_exit) {
+ return platform_ops.timer_exit ();
+ }
+}
+
+/** Bringup the given hart */
+int Edk2OpensbiPlatformHartStart (
+ UINT32 HartId,
+ ulong Saddr
+ )
+{
+ DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));
+
+ if (platform_ops.hart_start) {
+ return platform_ops.hart_start (HartId, Saddr);
+ }
+ return 0;
+}
+/**
+ Stop the current hart from running. This call doesn't expect to
+ return if success.
+**/
+int Edk2OpensbiPlatformHartStop (VOID)
+{
+ DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));
+
+ if (platform_ops.hart_stop) {
+ return platform_ops.hart_stop ();
+ }
+ return 0;
+}
+
+/**
+ Check whether reset type and reason supported by the platform*
+
+**/
+int Edk2OpensbiPlatformSystemResetCheck (
+ UINT32 ResetType,
+ UINT32 ResetReason
+ )
+{
+ if (platform_ops.system_reset_check) {
+ return platform_ops.system_reset_check (ResetType, ResetReason);
+ }
+ return 0;
+}
+
+/** Reset the platform */
+VOID Edk2OpensbiPlatformSystemReset (
+ UINT32 ResetType,
+ UINT32 ResetReason
+ )
+{
+ DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));
+
+ if (platform_ops.system_reset) {
+ return platform_ops.system_reset (ResetType, ResetReason);
+ }
+}
+
+/** platform specific SBI extension implementation probe function */
+int Edk2OpensbiPlatformVendorExtCheck (
+ long ExtId
+ )
+{
+ DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));
+
+ if (platform_ops.vendor_ext_check) {
+ return platform_ops.vendor_ext_check (ExtId);
+ }
+ return 0;
+}
+
+
+/** platform specific SBI extension implementation provider */
+int Edk2OpensbiPlatformVendorExtProvider (
+ long ExtId,
+ long FuncId,
+ const struct sbi_trap_regs *Regs,
+ unsigned long *OutValue,
+ struct sbi_trap_info *OutTrap
+ )
+{
+ DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));
+
+ if (platform_ops.vendor_ext_provider) {
+ return platform_ops.vendor_ext_provider (
+ ExtId,
+ FuncId,
+ Regs,
+ OutValue,
+ OutTrap
+ );
+ }
+ return 0;
+}
+
+const struct sbi_platform_operations Edk2OpensbiPlatformOps = {
+ .early_init = Edk2OpensbiPlatformEarlyInit,
+ .final_init = Edk2OpensbiPlatformFinalInit,
+ .early_exit = Edk2OpensbiPlatformEarlyExit,
+ .final_exit = Edk2OpensbiPlatformFinalExit,
+ .misa_check_extension = Edk2OpensbiPlatforMMISACheckExtension,
+ .misa_get_xlen = Edk2OpensbiPlatforMMISAGetXLEN,
+ .domains_root_regions = Edk2OpensbiPlatformGetMemRegions,
+ .domains_init = Edk2OpensbiPlatformDomainsInit,
+ .console_putc = Edk2OpensbiPlatformSerialPutc,
+ .console_getc = Edk2OpensbiPlatformSerialGetc,
+ .console_init = Edk2OpensbiPlatformSerialInit,
+ .irqchip_init = Edk2OpensbiPlatformIrqchipInit,
+ .irqchip_exit = Edk2OpensbiPlatformIrqchipExit,
+ .ipi_send = Edk2OpensbiPlatformIpiSend,
+ .ipi_clear = Edk2OpensbiPlatformIpiClear,
+ .ipi_init = Edk2OpensbiPlatformIpiInit,
+ .ipi_exit = Edk2OpensbiPlatformIpiExit,
+ .get_tlbr_flush_limit = Edk2OpensbiPlatformTlbrFlushLimit,
+ .timer_value = Edk2OpensbiPlatformTimerValue,
+ .timer_event_stop = Edk2OpensbiPlatformTimerEventStop,
+ .timer_event_start = Edk2OpensbiPlatformTimerEventStart,
+ .timer_init = Edk2OpensbiPlatformTimerInit,
+ .timer_exit = Edk2OpensbiPlatformTimerExit,
+ .hart_start = Edk2OpensbiPlatformHartStart,
+ .hart_stop = Edk2OpensbiPlatformHartStop,
+ .system_reset_check = Edk2OpensbiPlatformSystemResetCheck,
+ .system_reset = Edk2OpensbiPlatformSystemReset,
+ .vendor_ext_check = Edk2OpensbiPlatformVendorExtCheck,
+ .vendor_ext_provider = Edk2OpensbiPlatformVendorExtProvider,
+};
diff --git a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c
index e88a7b8e80..44984b0078 100644
--- a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c
+++ b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c
@@ -23,6 +23,8 @@
#include <sbi/sbi_ecall.h> // Reference to header file in opensbi
#include <sbi/sbi_trap.h> // Reference to header file in opensbi
+extern struct sbi_platform_operations Edk2OpensbiPlatformOps;
+
//
// Indicates the boot hart (PcdBootHartId) OpenSBI initialization is done.
//
@@ -31,27 +33,6 @@ atomic_t NonBootHartMessageLock = ATOMIC_INITIALIZER(0);
typedef struct sbi_scratch *(*hartid2scratch)(ulong hartid, ulong hartindex);
-STATIC EFI_PEI_TEMPORARY_RAM_SUPPORT_PPI mTemporaryRamSupportPpi = {
- TemporaryRamMigration
-};
-
-STATIC EFI_PEI_TEMPORARY_RAM_DONE_PPI mTemporaryRamDonePpi = {
- TemporaryRamDone
-};
-
-STATIC EFI_PEI_PPI_DESCRIPTOR mPrivateDispatchTable[] = {
- {
- EFI_PEI_PPI_DESCRIPTOR_PPI,
- &gEfiTemporaryRamSupportPpiGuid,
- &mTemporaryRamSupportPpi
- },
- {
- (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
- &gEfiTemporaryRamDonePpiGuid,
- &mTemporaryRamDonePpi
- },
-};
-
/**
Locates a section within a series of sections
with the specified section type.
@@ -491,6 +472,91 @@ RegisterFirmwareSbiExtension (
return EFI_SUCCESS;
}
+
+/**
+ OpenSBI platform early init hook.
+
+**/
+int
+SecPostOpenSbiPlatformEarlylInit(
+ IN BOOLEAN ColdBoot
+ )
+{
+ //
+ // Boot HART is already in the process of OpenSBI initialization.
+ // We can let other HART to keep booting.
+ //
+ DEBUG ((DEBUG_INFO, "%a: Set boot hart done.\n", __FUNCTION__));
+ atomic_write (&BootHartDone, (UINT64)TRUE);
+ return 0;
+}
+
+/**
+ OpenSBI platform final init hook.
+ We restore the next_arg1 to the pointer of EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT.
+
+**/
+int
+SecPostOpenSbiPlatformFinalInit (
+ IN BOOLEAN ColdBoot
+ )
+{
+ UINT32 HartId;
+ struct sbi_scratch *SbiScratch;
+ struct sbi_scratch *ScratchSpace;
+ struct sbi_platform *SbiPlatform;
+ EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *FirmwareContext;
+
+ DEBUG((DEBUG_INFO, "%a: Entry, preparing to jump to PEI Core\n\n", __FUNCTION__));
+
+ SbiScratch = sbi_scratch_thishart_ptr();
+ SbiPlatform = (struct sbi_platform *)sbi_platform_ptr(SbiScratch);
+ FirmwareContext = (EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *)SbiPlatform->firmware_context;
+
+ //
+ // Print out scratch address of each hart
+ //
+ DEBUG ((DEBUG_INFO, "%a: OpenSBI scratch address for each hart:\n", __FUNCTION__));
+ for (HartId = 0; HartId < SBI_HARTMASK_MAX_BITS; HartId ++) {
+ if (sbi_platform_hart_invalid(SbiPlatform, HartId)) {
+ continue;
+ }
+ ScratchSpace = sbi_hartid_to_scratch (HartId);
+ if(ScratchSpace != NULL) {
+ DEBUG((DEBUG_INFO, " Hart %d: 0x%x\n", HartId, ScratchSpace));
+ } else {
+ DEBUG((DEBUG_INFO, " Hart %d not initialized yet\n", HartId));
+ }
+ }
+
+ //
+ // Set firmware context Hart-specific pointer
+ //
+ for (HartId = 0; HartId < SBI_HARTMASK_MAX_BITS; HartId ++) {
+ if (sbi_platform_hart_invalid(SbiPlatform, HartId)) {
+ continue;
+ }
+ ScratchSpace = sbi_hartid_to_scratch (HartId);
+ if (ScratchSpace != NULL) {
+ FirmwareContext->HartSpecific[HartId] =
+ (EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC *)((UINT8 *)ScratchSpace - FIRMWARE_CONTEXT_HART_SPECIFIC_SIZE);
+ DEBUG ((DEBUG_INFO, "%a: OpenSBI Hart %d Firmware Context Hart-specific at address: 0x%x\n",
+ __FUNCTION__,
+ HartId,
+ FirmwareContext->HartSpecific [HartId]
+ ));
+ }
+ }
+
+ DEBUG((DEBUG_INFO, "%a: Jump to PEI Core with \n", __FUNCTION__));
+ DEBUG((DEBUG_INFO, " sbi_scratch = %x\n", SbiScratch));
+ DEBUG((DEBUG_INFO, " sbi_platform = %x\n", SbiPlatform));
+ DEBUG((DEBUG_INFO, " FirmwareContext = %x\n", FirmwareContext));
+ SbiScratch->next_arg1 = (unsigned long)FirmwareContext;
+
+ return 0;
+}
+
/** Transion from SEC phase to PEI phase.
This function transits to S-mode PEI phase from M-mode SEC phase.
@@ -508,9 +574,7 @@ VOID EFIAPI PeiCore (
EFI_PEI_CORE_ENTRY_POINT PeiCoreEntryPoint;
EFI_FIRMWARE_VOLUME_HEADER *BootFv = (EFI_FIRMWARE_VOLUME_HEADER *)FixedPcdGet32(PcdRiscVPeiFvBase);
EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT FirmwareContext;
- struct sbi_scratch *ScratchSpace;
struct sbi_platform *ThisSbiPlatform;
- UINT32 HartId;
FindAndReportEntryPoints (&BootFv, &PeiCoreEntryPoint);
@@ -524,17 +588,6 @@ VOID EFIAPI PeiCore (
SecCoreData.StackBase = (UINT8 *)SecCoreData.TemporaryRamBase + (SecCoreData.TemporaryRamSize >> 1);
SecCoreData.StackSize = SecCoreData.TemporaryRamSize >> 1;
- //
- // Print out scratch address of each hart
- //
- DEBUG ((DEBUG_INFO, "%a: OpenSBI scratch address for each hart:\n", __FUNCTION__));
- for (HartId = 0; HartId < SBI_HARTMASK_MAX_BITS; HartId ++) {
- ScratchSpace = sbi_hartid_to_scratch (HartId);
- if(ScratchSpace != NULL) {
- DEBUG((DEBUG_INFO, " Hart %d: 0x%x\n", HartId, ScratchSpace));
- }
- }
-
//
// Set up OpepSBI firmware context pointer on boot hart OpenSbi scratch.
// Firmware context residents in stack and will be switched to memory when
@@ -564,20 +617,10 @@ VOID EFIAPI PeiCore (
FirmwareContext.FlattenedDeviceTree = Scratch->next_arg1;
//
- // Set firmware context Hart-specific pointer
+ // Transfer the control to the PEI core
//
- for (HartId = 0; HartId < SBI_HARTMASK_MAX_BITS; HartId ++) {
- ScratchSpace = sbi_hartid_to_scratch (HartId);
- if (ScratchSpace != NULL) {
- FirmwareContext.HartSpecific[HartId] =
- (EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC *)((UINT8 *)ScratchSpace - FIRMWARE_CONTEXT_HART_SPECIFIC_SIZE);
- DEBUG ((DEBUG_INFO, "%a: OpenSBI Hart %d Firmware Context Hart-specific at address: 0x%x\n",
- __FUNCTION__,
- HartId,
- FirmwareContext.HartSpecific [HartId]
- ));
- }
- }
+ FirmwareContext.SecPeiHandOffData = (UINT64)&SecCoreData;
+
//
// Set supervisor translation mode to Bare mode
//
@@ -585,13 +628,12 @@ VOID EFIAPI PeiCore (
RiscVSetSupervisorAddressTranslationRegister ((UINT64)RISCV_SATP_MODE_OFF << RISCV_SATP_MODE_BIT_POSITION);
//
- // Transfer the control to the PEI core
+ // Scratch->next_arg1 is the device tree.
//
- Scratch->next_addr = (UINTN)(*PeiCoreEntryPoint);
+ Scratch->next_addr = (UINTN)(PeiCoreEntryPoint);
Scratch->next_mode = PRV_S;
DEBUG ((DEBUG_INFO, "%a: Initializing OpenSBI library for booting hart %d\n", __FUNCTION__, BootHartId));
sbi_init(Scratch);
- (*PeiCoreEntryPoint) (&SecCoreData, (EFI_PEI_PPI_DESCRIPTOR *)&mPrivateDispatchTable);
}
/**
@@ -715,6 +757,7 @@ VOID EFIAPI SecCoreStartUpWithStack(
{
UINT64 BootHartDoneSbiInit;
UINT64 NonBootHartMessageLockValue;
+ struct sbi_platform *ThisSbiPlatform;
EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC *HartFirmwareContext;
Scratch->next_arg1 = (unsigned long)GetDeviceTreeAddress ();
@@ -737,6 +780,14 @@ VOID EFIAPI SecCoreStartUpWithStack(
HartFirmwareContext->MachineImplId.Value64_H = 0;
HartFirmwareContext->HartSwitchMode = RiscVOpenSbiHartSwitchMode;
+ //
+ // Hook platorm_ops with EDK2 one. Thus we can have interface
+ // call out to OEM EDK2 platform code in M-mode before switching
+ // to S-mode in opensbo init.
+ //
+ ThisSbiPlatform = (struct sbi_platform *)sbi_platform_ptr(Scratch);
+ ThisSbiPlatform->platform_ops_addr = (unsigned long)&Edk2OpensbiPlatformOps;
+
if (HartId == FixedPcdGet32(PcdBootHartId)) {
LaunchPeiCore (HartId, Scratch);
}
@@ -768,6 +819,7 @@ VOID EFIAPI SecCoreStartUpWithStack(
// Non boot hart wiil be halted waiting for SBI_HART_STARTING.
// Use HSM ecall to start non boot hart (SBI_EXT_HSM_HART_START) later on,
//
+ Scratch->next_mode = PRV_S;
sbi_init(Scratch);
}
--
2.31.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH 43/79] Platform/RISC-V: Add library to get PPI descriptor
2022-01-08 7:24 [PATCH 42/79] RISC-V: Use RISC-V PeiCoreEntryPoint library Abner Chang
@ 2022-01-08 7:24 ` Abner Chang
2022-01-08 7:24 ` [PATCH 44/79] Platform/RISC-V: Use PlatformSecPpiLib Abner Chang
` (17 subsequent siblings)
18 siblings, 0 replies; 21+ messages in thread
From: Abner Chang @ 2022-01-08 7:24 UTC (permalink / raw)
To: devel; +Cc: abner.chang
(This is migrated from edk2-platforms:Platform)
The library to provide the platform PPI descriptors in
PEI core entry before executing PEI core.
Cc: Sunil V L <sunilvl@ventanamicro.com>
Cc: Daniel Schaefer <daniel.schaefer@hpe.com>
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Reviewed-by: Daniel Schaefer <daniel.schaefer@hpe.com>
Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
---
.../RISC-V/PlatformPkg/RiscVPlatformPkg.dsc | 2 ++
.../PlatformSecPpiLibNull.inf | 36 +++++++++++++++++++
.../Include/Library/PlatformSecPpiLib.h | 24 +++++++++++++
.../PlatformSecPpiLibNull/PlatformSecPpiLib.c | 28 +++++++++++++++
4 files changed, 90 insertions(+)
create mode 100644 Platform/RISC-V/PlatformPkg/Library/PlatformSecPpiLibNull/PlatformSecPpiLibNull.inf
create mode 100644 Platform/RISC-V/PlatformPkg/Include/Library/PlatformSecPpiLib.h
create mode 100644 Platform/RISC-V/PlatformPkg/Library/PlatformSecPpiLibNull/PlatformSecPpiLib.c
diff --git a/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dsc b/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dsc
index 8eec09549f..b96324e961 100644
--- a/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dsc
+++ b/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dsc
@@ -61,6 +61,7 @@
[LibraryClasses.common.PEI_CORE]
# RISC-V platform PEI core entry point.
PeiCoreEntryPoint|Platform/RISC-V/PlatformPkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.inf
+ PlatformSecPpiLib|Platform/RISC-V/PlatformPkg/Library/PlatformSecPpiLibNull/PlatformSecPpiLibNull.inf
[LibraryClasses.common.PEIM]
FirmwareContextProcessorSpecificLib|Platform/RISC-V/PlatformPkg/Library/FirmwareContextProcessorSpecificLib/FirmwareContextProcessorSpecificLib.inf
@@ -82,6 +83,7 @@
Platform/RISC-V/PlatformPkg/Library/FirmwareContextProcessorSpecificLib/FirmwareContextProcessorSpecificLib.inf
Platform/RISC-V/PlatformPkg/Library/RiscVPlatformTempMemoryInitLibNull/RiscVPlatformTempMemoryInitLibNull.inf
Platform/RISC-V/PlatformPkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.inf
+ Platform/RISC-V/PlatformPkg/Library/PlatformSecPpiLibNull/PlatformSecPpiLibNull.inf
[Components.common.SEC]
Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf
diff --git a/Platform/RISC-V/PlatformPkg/Library/PlatformSecPpiLibNull/PlatformSecPpiLibNull.inf b/Platform/RISC-V/PlatformPkg/Library/PlatformSecPpiLibNull/PlatformSecPpiLibNull.inf
new file mode 100644
index 0000000000..22f5751655
--- /dev/null
+++ b/Platform/RISC-V/PlatformPkg/Library/PlatformSecPpiLibNull/PlatformSecPpiLibNull.inf
@@ -0,0 +1,36 @@
+## @file
+# Library instance to to provide PPI before PEI Core
+#
+# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001b
+ BASE_NAME = PlatformSecPpiLib
+ FILE_GUID = A2CDDADC-CB65-4EED-9CAE-192B0BDD6C84
+ MODULE_TYPE = PEIM
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = PlatformSecPpiLib|PEI_CORE
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = RISCV64
+#
+
+[Sources]
+ PlatformSecPpiLib.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec
+ #Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec
+
+[LibraryClasses]
+ #BaseLib
+ #PrintLib
+
diff --git a/Platform/RISC-V/PlatformPkg/Include/Library/PlatformSecPpiLib.h b/Platform/RISC-V/PlatformPkg/Include/Library/PlatformSecPpiLib.h
new file mode 100644
index 0000000000..88468e660b
--- /dev/null
+++ b/Platform/RISC-V/PlatformPkg/Include/Library/PlatformSecPpiLib.h
@@ -0,0 +1,24 @@
+/** @file
+ RISC-V platform SEC PPI before PEI Core.
+
+ Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef RISCV_PLATFORM_SEC_PPI_H_
+#define RISCV_PLATFORM_SEC_PPI_H_
+
+#include <PiPei.h>
+
+/** Return platform SEC PPI before PEI Core
+
+ @param[in,out] ThisPpiList Pointer to retrieve EFI_PEI_PPI_DESCRIPTOR.
+
+**/
+EFI_STATUS
+GetPlatformPrePeiCorePpiDescriptor (
+ IN OUT EFI_PEI_PPI_DESCRIPTOR **ThisPpiList
+);
+
+#endif
diff --git a/Platform/RISC-V/PlatformPkg/Library/PlatformSecPpiLibNull/PlatformSecPpiLib.c b/Platform/RISC-V/PlatformPkg/Library/PlatformSecPpiLibNull/PlatformSecPpiLib.c
new file mode 100644
index 0000000000..d5c089b02d
--- /dev/null
+++ b/Platform/RISC-V/PlatformPkg/Library/PlatformSecPpiLibNull/PlatformSecPpiLib.c
@@ -0,0 +1,28 @@
+/**@file
+ NULL library instance of PlatformSecPpiLib
+
+ Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+//
+// The package level header files this module uses
+//
+#include <PiPei.h>
+
+/** Return platform SEC PPI before PEI Core
+
+ @param[in,out] ThisPpiList Pointer to retrieve EFI_PEI_PPI_DESCRIPTOR.
+
+**/
+EFI_STATUS
+GetPlatformPrePeiCorePpiDescriptor (
+ IN OUT EFI_PEI_PPI_DESCRIPTOR **ThisPpiList
+)
+{
+ *ThisPpiList = NULL;
+ return EFI_NOT_FOUND;
+}
+
--
2.31.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH 44/79] Platform/RISC-V: Use PlatformSecPpiLib
2022-01-08 7:24 [PATCH 42/79] RISC-V: Use RISC-V PeiCoreEntryPoint library Abner Chang
2022-01-08 7:24 ` [PATCH 43/79] Platform/RISC-V: Add library to get PPI descriptor Abner Chang
@ 2022-01-08 7:24 ` Abner Chang
2022-01-08 7:24 ` [PATCH 45/79] Platform/RISC-V: Add NULL library instance of RiscVSpecialPlatformLib Abner Chang
` (16 subsequent siblings)
18 siblings, 0 replies; 21+ messages in thread
From: Abner Chang @ 2022-01-08 7:24 UTC (permalink / raw)
To: devel; +Cc: abner.chang
(This is migrated from edk2-platforms:Platform)
Use PlatformSecPpiLib to get PPI descriptor and
remove PPI descriptor related code from SEC.
Cc: Sunil V L <sunilvl@ventanamicro.com>
Cc: Daniel Schaefer <daniel.schaefer@hpe.com>
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Reviewed-by: Daniel Schaefer <daniel.schaefer@hpe.com>
Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
---
.../PeiCoreEntryPoint/PeiCoreEntryPoint.inf | 1 +
.../PlatformPkg/Universal/Sec/SecMain.inf | 4 -
.../PlatformPkg/Universal/Sec/SecMain.h | 17 ----
.../PeiCoreEntryPoint/PeiCoreEntryPoint.c | 15 +++-
.../PlatformPkg/Universal/Sec/SecMain.c | 84 -------------------
5 files changed, 14 insertions(+), 107 deletions(-)
diff --git a/Platform/RISC-V/PlatformPkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.inf b/Platform/RISC-V/PlatformPkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.inf
index e16a974636..4f3af27bcf 100644
--- a/Platform/RISC-V/PlatformPkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.inf
+++ b/Platform/RISC-V/PlatformPkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.inf
@@ -32,5 +32,6 @@
[LibraryClasses]
BaseLib
DebugLib
+ PlatformSecPpiLib
RiscVFirmwareContextLib
diff --git a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf
index 4207c83413..9736277fa1 100644
--- a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf
+++ b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf
@@ -52,10 +52,6 @@
RiscVOpensbiPlatformLib
RiscVEdk2SbiLib
-[Ppis]
- gEfiTemporaryRamSupportPpiGuid # PPI ALWAYS_PRODUCED
- gEfiTemporaryRamDonePpiGuid # PPI ALWAYS_PRODUCED
-
[FixedPcd]
gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVPeiFvBase
gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVPeiFvSize
diff --git a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.h b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.h
index c04ddbad7f..496799efc0 100644
--- a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.h
+++ b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.h
@@ -25,8 +25,6 @@
#include <Library/PeCoffLib.h>
#include <Library/PeiServicesLib.h>
#include <Library/RiscVCpuLib.h>
-#include <Ppi/TemporaryRamDone.h>
-#include <Ppi/TemporaryRamSupport.h>
int
SecPostOpenSbiPlatformEarlylInit(
@@ -49,19 +47,4 @@ SecStartupPhase2 (
IN VOID *Context
);
-EFI_STATUS
-EFIAPI
-TemporaryRamMigration (
- IN CONST EFI_PEI_SERVICES **PeiServices,
- IN EFI_PHYSICAL_ADDRESS TemporaryMemoryBase,
- IN EFI_PHYSICAL_ADDRESS PermanentMemoryBase,
- IN UINTN CopySize
- );
-
-EFI_STATUS
-EFIAPI
-TemporaryRamDone (
- VOID
- );
-
#endif // _SECMAIN_H_
diff --git a/Platform/RISC-V/PlatformPkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.c b/Platform/RISC-V/PlatformPkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.c
index 2fd0f2315b..16488b7bc9 100644
--- a/Platform/RISC-V/PlatformPkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.c
+++ b/Platform/RISC-V/PlatformPkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.c
@@ -17,6 +17,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#include <Library/BaseLib.h>
#include <Library/DebugLib.h>
#include <Library/PeiCoreEntryPoint.h>
+#include <Library/PlatformSecPpiLib.h>
#include <Library/RiscVFirmwareContextLib.h>
/**
@@ -49,15 +50,25 @@ _ModuleEntryPoint(
IN CONST EFI_PEI_PPI_DESCRIPTOR *PpiList
)
{
+ EFI_STATUS Status;
EFI_SEC_PEI_HAND_OFF *ThisSecCoreData;
EFI_PEI_PPI_DESCRIPTOR *ThisPpiList;
EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *FirmwareContext;
FirmwareContext = (EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *)PpiList;
SetFirmwareContextPointer (FirmwareContext);
+ FirmwareContext->BootHartId = (UINT64)SecCoreData;
+
ThisSecCoreData = (EFI_SEC_PEI_HAND_OFF *)FirmwareContext->SecPeiHandOffData;
- ThisPpiList = (EFI_PEI_PPI_DESCRIPTOR *)FirmwareContext->SecPeiHandoffPpi;
- ProcessModuleEntryPointList (ThisSecCoreData, ThisPpiList, NULL);
+ Status = GetPlatformPrePeiCorePpiDescriptor (&ThisPpiList);
+ if (EFI_ERROR (Status)) {
+ ThisPpiList = NULL;
+ }
+
+ //
+ // Invoke PEI Core entry point.
+ //
+ ProcessModuleEntryPointList(ThisSecCoreData, ThisPpiList, NULL);
//
// Should never return
diff --git a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c
index 44984b0078..fb0adbca54 100644
--- a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c
+++ b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c
@@ -312,90 +312,6 @@ FindAndReportEntryPoints (
return;
}
-/*
- Print out the content of firmware context.
-
-**/
-VOID
-DebugPrintFirmwareContext (
- EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *FirmwareContext
- )
-{
- DEBUG ((DEBUG_INFO, "%a: OpenSBI Firmware Context at 0x%x\n", __FUNCTION__, FirmwareContext));
- DEBUG ((DEBUG_INFO, "%a: PEI Service at 0x%x\n\n", __FUNCTION__, FirmwareContext->PeiServiceTable));
-}
-/** Temporary RAM migration function.
-
- This function migrates the data from temporary RAM to permanent
- memory.
-
- @param[in] PeiServices PEI service
- @param[in] TemporaryMemoryBase Temporary memory base address
- @param[in] PermanentMemoryBase Permanent memory base address
- @param[in] CopySize Size to copy
-
-**/
-EFI_STATUS
-EFIAPI
-TemporaryRamMigration (
- IN CONST EFI_PEI_SERVICES **PeiServices,
- IN EFI_PHYSICAL_ADDRESS TemporaryMemoryBase,
- IN EFI_PHYSICAL_ADDRESS PermanentMemoryBase,
- IN UINTN CopySize
- )
-{
- VOID *OldHeap;
- VOID *NewHeap;
- VOID *OldStack;
- VOID *NewStack;
- EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *FirmwareContext;
-
- DEBUG ((DEBUG_INFO,
- "%a: Temp Mem Base:0x%Lx, Permanent Mem Base:0x%Lx, CopySize:0x%Lx\n",
- __FUNCTION__,
- TemporaryMemoryBase,
- PermanentMemoryBase,
- (UINT64)CopySize
- ));
-
- OldHeap = (VOID*)(UINTN)TemporaryMemoryBase;
- NewHeap = (VOID*)((UINTN)PermanentMemoryBase + (CopySize >> 1));
-
- OldStack = (VOID*)((UINTN)TemporaryMemoryBase + (CopySize >> 1));
- NewStack = (VOID*)(UINTN)PermanentMemoryBase;
-
- CopyMem (NewHeap, OldHeap, CopySize >> 1); // Migrate Heap
- CopyMem (NewStack, OldStack, CopySize >> 1); // Migrate Stack
-
- //
- // Reset firmware context pointer
- //
- SbiGetFirmwareContext (&FirmwareContext);
- FirmwareContext = (VOID *)FirmwareContext + (unsigned long)((UINTN)NewStack - (UINTN)OldStack);
- SbiSetFirmwareContext (FirmwareContext);
-
- //
- // Relocate PEI Service **
- //
- FirmwareContext->PeiServiceTable += (unsigned long)((UINTN)NewStack - (UINTN)OldStack);
- DEBUG ((DEBUG_INFO, "%a: OpenSBI Firmware Context is relocated to 0x%x\n", __FUNCTION__, FirmwareContext));
- DebugPrintFirmwareContext ((EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *)FirmwareContext);
-
- register uintptr_t a0 asm ("a0") = (uintptr_t)((UINTN)NewStack - (UINTN)OldStack);
- asm volatile ("add sp, sp, a0"::"r"(a0):);
- return EFI_SUCCESS;
-}
-
-/** Temprary RAM done function.
-
-**/
-EFI_STATUS EFIAPI TemporaryRamDone (
- VOID
- )
-{
- DEBUG ((DEBUG_INFO, "%a: 2nd time PEI core, temporary ram done.\n", __FUNCTION__));
- return EFI_SUCCESS;
-}
/**
Handles SBI calls of EDK2's SBI FW extension.
--
2.31.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH 45/79] Platform/RISC-V: Add NULL library instance of RiscVSpecialPlatformLib
2022-01-08 7:24 [PATCH 42/79] RISC-V: Use RISC-V PeiCoreEntryPoint library Abner Chang
2022-01-08 7:24 ` [PATCH 43/79] Platform/RISC-V: Add library to get PPI descriptor Abner Chang
2022-01-08 7:24 ` [PATCH 44/79] Platform/RISC-V: Use PlatformSecPpiLib Abner Chang
@ 2022-01-08 7:24 ` Abner Chang
2022-01-08 7:24 ` [PATCH 46/79] Platform/RISC-V: Remove platform dependency from common platform lib Abner Chang
` (15 subsequent siblings)
18 siblings, 0 replies; 21+ messages in thread
From: Abner Chang @ 2022-01-08 7:24 UTC (permalink / raw)
To: devel; +Cc: abner.chang
(This is migrated from edk2-platforms)
This is the library instance to provide platform_override for the
special RISC-V platform. This module incorporates with
OpensbiPlatformLib and RISC-V Opensbi library.
Cc: Sunil V L <sunilvl@ventanamicro.com>
Cc: Daniel Schaefer <daniel.schaefer@hpe.com>
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Reviewed-by: Daniel Schaefer <daniel.schaefer@hpe.com>
Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
---
.../RISC-V/ProcessorPkg/RiscVProcessorPkg.dec | 1 +
.../RISC-V/PlatformPkg/RiscVPlatformPkg.dsc | 2 ++
.../RiscVSpecialPlatformLib.inf | 36 +++++++++++++++++++
.../Include/Library/RiscVSpecialPlatformLib.h | 20 +++++++++++
.../RiscVSpecialPlatformLib.c | 19 ++++++++++
5 files changed, 78 insertions(+)
create mode 100644 Platform/RISC-V/PlatformPkg/Library/RiscVSpecialPlatformLib/RiscVSpecialPlatformLib.inf
create mode 100644 Platform/RISC-V/PlatformPkg/Include/Library/RiscVSpecialPlatformLib.h
create mode 100644 Platform/RISC-V/PlatformPkg/Library/RiscVSpecialPlatformLib/RiscVSpecialPlatformLib.c
diff --git a/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec b/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec
index 08279a97b1..9c8b57cce3 100644
--- a/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec
+++ b/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec
@@ -19,6 +19,7 @@
Include/Library
Library/RiscVOpensbiLib/opensbi # OpenSBI header file reference ("include/sbi/...")
Library/RiscVOpensbiLib/opensbi/include # Header file reference from opensbi files, ("sbi/...")
+ Library/RiscVOpensbiLib/opensbi/platform/generic/include # Header file reference from opensbi files, ("sbi/...")
[LibraryClasses]
RiscVPlatformDxeIplLib|Include/Library/RiscVPlatformDxeIpl.h
diff --git a/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dsc b/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dsc
index b96324e961..ec8875be14 100644
--- a/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dsc
+++ b/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dsc
@@ -71,6 +71,7 @@
[LibraryClasses.common.SEC]
ExtractGuidedSectionLib|MdePkg/Library/BaseExtractGuidedSectionLib/BaseExtractGuidedSectionLib.inf
+ RiscVSpecialPlatformLib|Platform/RISC-V/PlatformPkg/Library/RiscVSpecialPlatformLib/RiscVSpecialPlatformLib.inf
[LibraryClasses.common.DXE_DRIVER]
PlatformBootManagerLib|Platform/RISC-V/PlatformPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
@@ -84,6 +85,7 @@
Platform/RISC-V/PlatformPkg/Library/RiscVPlatformTempMemoryInitLibNull/RiscVPlatformTempMemoryInitLibNull.inf
Platform/RISC-V/PlatformPkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.inf
Platform/RISC-V/PlatformPkg/Library/PlatformSecPpiLibNull/PlatformSecPpiLibNull.inf
+ Platform/RISC-V/PlatformPkg/Library/RiscVSpecialPlatformLib/RiscVSpecialPlatformLib.inf
[Components.common.SEC]
Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf
diff --git a/Platform/RISC-V/PlatformPkg/Library/RiscVSpecialPlatformLib/RiscVSpecialPlatformLib.inf b/Platform/RISC-V/PlatformPkg/Library/RiscVSpecialPlatformLib/RiscVSpecialPlatformLib.inf
new file mode 100644
index 0000000000..567eeee56d
--- /dev/null
+++ b/Platform/RISC-V/PlatformPkg/Library/RiscVSpecialPlatformLib/RiscVSpecialPlatformLib.inf
@@ -0,0 +1,36 @@
+## @file
+# Null library instance to provide platform_override for the
+# special RISC-V platform. This module incorporates with
+# OpensbiPlatformLib and RISC-V Opensbi library.
+#
+# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001b
+ BASE_NAME = RiscVSpecialPlatformLib
+ FILE_GUID = 79361802-18B6-458A-8C79-DA6256DEF776
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = RiscVSpecialPlatformLib|SEC
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = RISCV64
+#
+
+[Sources]
+ RiscVSpecialPlatformLib.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec
+ Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec
+
+[LibraryClasses]
+ BaseLib
diff --git a/Platform/RISC-V/PlatformPkg/Include/Library/RiscVSpecialPlatformLib.h b/Platform/RISC-V/PlatformPkg/Include/Library/RiscVSpecialPlatformLib.h
new file mode 100644
index 0000000000..644bb08ebf
--- /dev/null
+++ b/Platform/RISC-V/PlatformPkg/Include/Library/RiscVSpecialPlatformLib.h
@@ -0,0 +1,20 @@
+/** @file
+ library definition to provide platform_override of special platforms.
+ This library incorporates with OpensbiPlatformLib and RISC-V Opensbi library
+
+ Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef RISCV_SPECIAL_PLATFORM_LIB_
+#define RISCV_SPECIAL_PLATFORM_LIB_
+
+#include <PiPei.h>
+
+//
+// This is declared under Silicon/RISC-V/ProcessorPkg/Library/RiscVOpensbiLib/opensbi/platform/generic/include/
+//
+#include <platform_override.h>
+
+#endif
diff --git a/Platform/RISC-V/PlatformPkg/Library/RiscVSpecialPlatformLib/RiscVSpecialPlatformLib.c b/Platform/RISC-V/PlatformPkg/Library/RiscVSpecialPlatformLib/RiscVSpecialPlatformLib.c
new file mode 100644
index 0000000000..3a77ff6b17
--- /dev/null
+++ b/Platform/RISC-V/PlatformPkg/Library/RiscVSpecialPlatformLib/RiscVSpecialPlatformLib.c
@@ -0,0 +1,19 @@
+/**@file
+ Library to provide platform_override for the special
+ RISC-V platform. This module incorporates with
+ OpensbiPlatformLib and RISC-V Opensbi library.
+
+ Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+//
+// The package level header files this module uses
+//
+#include <Library/RiscVSpecialPlatformLib.h>
+
+const struct platform_override *SpecialPlatformArray = NULL;
+INTN NumberOfPlaformsInArray;
+
--
2.31.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH 46/79] Platform/RISC-V: Remove platform dependency from common platform lib
2022-01-08 7:24 [PATCH 42/79] RISC-V: Use RISC-V PeiCoreEntryPoint library Abner Chang
` (2 preceding siblings ...)
2022-01-08 7:24 ` [PATCH 45/79] Platform/RISC-V: Add NULL library instance of RiscVSpecialPlatformLib Abner Chang
@ 2022-01-08 7:24 ` Abner Chang
2022-01-08 7:24 ` [PATCH 47/79] Platform/RISC-V: Remove Null instance of OpensbiPlatformLibNull Abner Chang
` (14 subsequent siblings)
18 siblings, 0 replies; 21+ messages in thread
From: Abner Chang @ 2022-01-08 7:24 UTC (permalink / raw)
To: devel; +Cc: abner.chang
(This is migrated from edk2-platforms:Platform)
This is the generic library for all RISC-V platforms. Remove
the dependencies of SiFive U540 platform.
Cc: Sunil V L <sunilvl@ventanamicro.com>
Cc: Daniel Schaefer <daniel.schaefer@hpe.com>
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Reviewed-by: Daniel Schaefer <daniel.schaefer@hpe.com>
Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
---
.../OpensbiPlatformLib/OpensbiPlatformLib.inf | 3 +-
.../OpensbiPlatformLib/PlatformOverride.h | 30 ------------
.../Library/OpensbiPlatformLib/Platform.c | 25 +++++++---
.../Library/OpensbiPlatformLib/SifiveFu540.c | 47 -------------------
4 files changed, 19 insertions(+), 86 deletions(-)
delete mode 100644 Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/PlatformOverride.h
delete mode 100644 Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/SifiveFu540.c
diff --git a/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/OpensbiPlatformLib.inf b/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/OpensbiPlatformLib.inf
index a408737961..909fbffa8d 100644
--- a/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/OpensbiPlatformLib.inf
+++ b/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/OpensbiPlatformLib.inf
@@ -25,8 +25,6 @@
[Sources]
Platform.c
- SifiveFu540.c
- PlatformOverride.h
[Packages]
EmbeddedPkg/EmbeddedPkg.dec
@@ -45,6 +43,7 @@
PcdLib
PrintLib
RiscVCpuLib
+ RiscVSpecialPlatformLib
[FixedPcd]
gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootHartId
diff --git a/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/PlatformOverride.h b/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/PlatformOverride.h
deleted file mode 100644
index 2fbb8ca45d..0000000000
--- a/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/PlatformOverride.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * SPDX-License-Identifier: BSD-2-Clause
- *
- * Copyright (c) 2020 Western Digital Corporation or its affiliates.
- *
- * Authors:
- * Anup Patel <anup.patel@wdc.com>
- */
-
-#ifndef __PLATFORM_OVERRIDE_H__
-#define __PLATFORM_OVERRIDE_H__
-
-#include <sbi/sbi_types.h>
-
-struct platform_override {
- const struct fdt_match *match_table;
- u64 (*features)(const struct fdt_match *match);
- u64 (*tlbr_flush_limit)(const struct fdt_match *match);
- int (*early_init)(bool cold_boot, const struct fdt_match *match);
- int (*final_init)(bool cold_boot, const struct fdt_match *match);
- void (*early_exit)(const struct fdt_match *match);
- void (*final_exit)(const struct fdt_match *match);
- int (*system_reset_check)(u32 reset_type, u32 reset_reason,
- const struct fdt_match *match);
- void (*system_reset)(u32 reset_type, u32 reset_reason,
- const struct fdt_match *match);
- int (*fdt_fixup)(void *fdt, const struct fdt_match *match);
-};
-
-#endif
diff --git a/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/Platform.c b/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/Platform.c
index 9926911297..bdd7a6d3ba 100644
--- a/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/Platform.c
+++ b/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/Platform.c
@@ -5,10 +5,16 @@
*
* Authors:
* Anup Patel <anup.patel@wdc.com>
+
+ Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
*/
#include <libfdt.h>
-#include <PlatformOverride.h>
+#include <Library/RiscVSpecialPlatformLib.h>
+
#include <sbi/riscv_asm.h>
#include <sbi/sbi_domain.h>
#include <sbi/sbi_hartmask.h>
@@ -24,11 +30,12 @@
#include <sbi_utils/ipi/fdt_ipi.h>
#include <sbi_utils/reset/fdt_reset.h>
-extern const struct platform_override sifive_fu540;
-
-static const struct platform_override *special_platforms[] = {
- &sifive_fu540,
-};
+//
+// SpecialPlatformArray and NumberOfSpecialPlatform are
+// provided by RiscVSpecialPlatformLib library.
+//
+extern const struct platform_override *special_platforms[];
+extern INTN NumberOfPlaformsInArray;
static const struct platform_override *generic_plat = NULL;
static const struct fdt_match *generic_plat_match = NULL;
@@ -39,7 +46,11 @@ static void fw_platform_lookup_special(void *fdt, int root_offset)
const struct platform_override *plat;
const struct fdt_match *match;
- for (pos = 0; pos < array_size(special_platforms); pos++) {
+ if (special_platforms == NULL || NumberOfPlaformsInArray == 0) {
+ return;
+ }
+
+ for (pos = 0; pos < (int)NumberOfPlaformsInArray; pos++) {
plat = special_platforms[pos];
if (!plat->match_table)
continue;
diff --git a/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/SifiveFu540.c b/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/SifiveFu540.c
deleted file mode 100644
index 748b058840..0000000000
--- a/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/SifiveFu540.c
+++ /dev/null
@@ -1,47 +0,0 @@
-/*
- * SPDX-License-Identifier: BSD-2-Clause
- *
- * Copyright (c) 2020 Western Digital Corporation or its affiliates.
- *
- * Authors:
- * Anup Patel <anup.patel@wdc.com>
- */
-
-#include <PlatformOverride.h>
-#include <sbi_utils/fdt/fdt_helper.h>
-#include <sbi_utils/fdt/fdt_fixup.h>
-
-static u64 sifive_fu540_tlbr_flush_limit(const struct fdt_match *match)
-{
- /*
- * The sfence.vma by virtual address does not work on
- * SiFive FU540 so we return remote TLB flush limit as zero.
- */
- return 0;
-}
-
-static int sifive_fu540_fdt_fixup(void *fdt, const struct fdt_match *match)
-{
- /*
- * SiFive Freedom U540 has an erratum that prevents S-mode software
- * to access a PMP protected region using 1GB page table mapping, so
- * always add the no-map attribute on this platform.
- */
- fdt_reserved_memory_nomap_fixup(fdt);
-
- return 0;
-}
-
-static const struct fdt_match sifive_fu540_match[] = {
- { .compatible = "sifive,fu540" },
- { .compatible = "sifive,fu540g" },
- { .compatible = "sifive,fu540-c000" },
- { .compatible = "sifive,hifive-unleashed-a00" },
- { },
-};
-
-const struct platform_override sifive_fu540 = {
- .match_table = sifive_fu540_match,
- .tlbr_flush_limit = sifive_fu540_tlbr_flush_limit,
- .fdt_fixup = sifive_fu540_fdt_fixup,
-};
--
2.31.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH 47/79] Platform/RISC-V: Remove Null instance of OpensbiPlatformLibNull
2022-01-08 7:24 [PATCH 42/79] RISC-V: Use RISC-V PeiCoreEntryPoint library Abner Chang
` (3 preceding siblings ...)
2022-01-08 7:24 ` [PATCH 46/79] Platform/RISC-V: Remove platform dependency from common platform lib Abner Chang
@ 2022-01-08 7:24 ` Abner Chang
2022-01-08 7:24 ` [PATCH 48/79] RiscVPlatformPkg/Sec: Initial hart_index2Id array Abner Chang
` (13 subsequent siblings)
18 siblings, 0 replies; 21+ messages in thread
From: Abner Chang @ 2022-01-08 7:24 UTC (permalink / raw)
To: devel; +Cc: abner.chang
(This is migrated from edk2-platforms:Platform)
Remove Null instance of OpensbiPlatformLibNull,
OpensbiPlatformLib is the generic one for RsicVPlatformPkg.
Cc: Sunil V L <sunilvl@ventanamicro.com>
Cc: Daniel Schaefer <daniel.schaefer@hpe.com>
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Reviewed-by: Daniel Schaefer <daniel.schaefer@hpe.com>
Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
---
.../RISC-V/PlatformPkg/RiscVPlatformPkg.dsc | 2 +-
.../OpensbiPlatformLibNull.inf | 38 --------------
.../Library/OpensbiPlatformLibNull/Platform.c | 51 -------------------
3 files changed, 1 insertion(+), 90 deletions(-)
delete mode 100644 Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLibNull/OpensbiPlatformLibNull.inf
delete mode 100644 Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLibNull/Platform.c
diff --git a/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dsc b/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dsc
index ec8875be14..93b3cd8de9 100644
--- a/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dsc
+++ b/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dsc
@@ -77,7 +77,7 @@
PlatformBootManagerLib|Platform/RISC-V/PlatformPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
[Components.common]
- Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLibNull/OpensbiPlatformLibNull.inf
+ Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/OpensbiPlatformLib.inf
Platform/RISC-V/PlatformPkg/Library/PlatformMemoryTestLibNull/PlatformMemoryTestLibNull.inf
Platform/RISC-V/PlatformPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
Platform/RISC-V/PlatformPkg/Library/PlatformUpdateProgressLibNull/PlatformUpdateProgressLibNull.inf
diff --git a/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLibNull/OpensbiPlatformLibNull.inf b/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLibNull/OpensbiPlatformLibNull.inf
deleted file mode 100644
index 125a1220bc..0000000000
--- a/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLibNull/OpensbiPlatformLibNull.inf
+++ /dev/null
@@ -1,38 +0,0 @@
-## @file
-# RISC-V OpenSbi Platform NULL Library
-#
-# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
-#
-# SPDX-License-Identifier: BSD-2-Clause-Patent
-#
-##
-
-[Defines]
- INF_VERSION = 0x0001001b
- BASE_NAME = RiscVOpensbiPlatformLibNull
- FILE_GUID = 9424ED54-EBDA-4FB5-8FF6-8291B07BB151
- MODULE_TYPE = SEC
- VERSION_STRING = 1.0
- LIBRARY_CLASS = RiscVOpensbiPlatformLib
-
-#
-# The following information is for reference only and not required by the build tools.
-#
-# VALID_ARCHITECTURES = RISCV64
-#
-
-[Sources]
- Platform.c
-
-[Packages]
- MdeModulePkg/MdeModulePkg.dec
- MdePkg/MdePkg.dec
- Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec
-
-[LibraryClasses]
- BaseLib
- BaseMemoryLib
- DebugLib
- DebugAgentLib
-
-
diff --git a/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLibNull/Platform.c b/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLibNull/Platform.c
deleted file mode 100644
index b7e39d19c1..0000000000
--- a/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLibNull/Platform.c
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- *
- * Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
- *
- * SPDX-License-Identifier: BSD-2-Clause
- *
- * Copyright (c) 2019 Western Digital Corporation or its affiliates.
- *
- * Authors:
- * Atish Patra <atish.patra@wdc.com>
- */
-
-#include <sbi/sbi_const.h>
-#include <sbi/sbi_platform.h>
-
-const struct sbi_platform_operations platform_ops = {
- .early_init = NULL,
- .final_init = NULL,
- .early_exit = NULL,
- .final_exit = NULL,
- .domains_root_regions = NULL,
- .domains_init = NULL,
- .console_putc = NULL,
- .console_getc = NULL,
- .console_init = NULL,
- .irqchip_init = NULL,
- .irqchip_exit = NULL,
- .ipi_send = NULL,
- .ipi_clear = NULL,
- .ipi_init = NULL,
- .ipi_exit = NULL,
- .get_tlbr_flush_limit = NULL,
- .timer_value = NULL,
- .timer_event_stop = NULL,
- .timer_event_start = NULL,
- .timer_init = NULL,
- .timer_exit = NULL,
- .system_reset_check = NULL,
- .system_reset = NULL,
-};
-
-struct sbi_platform platform = {
- .opensbi_version = OPENSBI_VERSION,
- .platform_version = SBI_PLATFORM_VERSION(0x0, 0x01),
- .name = "NULL Platform",
- .features = 0,
- .hart_count = 0,
- .hart_index2id = 0,
- .hart_stack_size = 0,
- .platform_ops_addr = 0,
-};
--
2.31.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH 48/79] RiscVPlatformPkg/Sec: Initial hart_index2Id array
2022-01-08 7:24 [PATCH 42/79] RISC-V: Use RISC-V PeiCoreEntryPoint library Abner Chang
` (4 preceding siblings ...)
2022-01-08 7:24 ` [PATCH 47/79] Platform/RISC-V: Remove Null instance of OpensbiPlatformLibNull Abner Chang
@ 2022-01-08 7:24 ` Abner Chang
2022-01-08 7:24 ` [PATCH 49/79] RiscVPlatformPkg/OpensbiPlatformLib: Remove platform code Abner Chang
` (12 subsequent siblings)
18 siblings, 0 replies; 21+ messages in thread
From: Abner Chang @ 2022-01-08 7:24 UTC (permalink / raw)
To: devel; +Cc: abner.chang
(This is migrated from edk2-platforms:Platform)
Initial hart index to Id array by invoking OpenSBI
fw_platform_init function.
Introduce PcdBootableHartIndexToId PCD which could be
used to overwrite the hart_index2Id arrary built
from Devie tree according to platform demand.
Cc: Sunil V L <sunilvl@ventanamicro.com>
Cc: Daniel Schaefer <daniel.schaefer@hpe.com>
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Reviewed-by: Daniel Schaefer <daniel.schaefer@hpe.com>
Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
---
.../RISC-V/PlatformPkg/RiscVPlatformPkg.dec | 13 +++-
.../RISC-V/PlatformPkg/RiscVPlatformPkg.dsc | 3 +-
.../PlatformPkg/Universal/Sec/SecMain.inf | 2 +
.../PlatformPkg/Universal/Sec/SecMain.c | 62 ++++++++++++++++---
.../Universal/Sec/Riscv64/SecEntry.S | 29 ++++++++-
5 files changed, 96 insertions(+), 13 deletions(-)
diff --git a/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec b/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec
index 7e41e7bdb2..947ae40e20 100644
--- a/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec
+++ b/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec
@@ -55,10 +55,21 @@
gUefiRiscVPlatformPkgTokenSpaceGuid.PcdHartCount|0|UINT32|0x00001083
gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootHartId|0|UINT32|0x00001084
#
-# The bootable hart core number, which is incorporate with OpenSBI platform hart_index2id value.
+# The bootable hart core number, which incorporates with OpenSBI platform hart_index2id value.
+# PcdBootableHartNumber = 0 means the number of bootable hart comes from Device Tree.
+# Otherwise the number assigned in PcdBootableHartNumber overwrite it.
#
gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootableHartNumber|0|UINT32|0x00001085
#
+# PcdBootableHartIndexToId is valid if PcdBootableHartNumber != 0.
+# If PcdBootableHartNumber != 0, then PcdBootableHartIndexToId is an array of
+# bootable hart ID.
+# For example,
+# if PcdBootableHartNumber == 3 then PcdBootableHartIndexToId could be defined
+# as {0x1, 0x2, 0x3}.
+#
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootableHartIndexToId|NULL|VOID*|0x00001086
+#
# Definitions for OpenSbi
#
gUefiRiscVPlatformPkgTokenSpaceGuid.PcdScratchRamBase|0|UINT32|0x00001100
diff --git a/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dsc b/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dsc
index 93b3cd8de9..97d5dd08a0 100644
--- a/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dsc
+++ b/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dsc
@@ -39,7 +39,8 @@
!include MdePkg/MdeLibs.dsc.inc
[LibraryClasses.common]
- RiscVOpensbiPlatformLib|Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLibNull/OpensbiPlatformLibNull.inf
+ FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib.inf
+ RiscVOpensbiPlatformLib|Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/OpensbiPlatformLib.inf
RiscVCpuLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVCpuLib/RiscVCpuLib.inf
RiscVEdk2SbiLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVEdk2SbiLib/RiscVEdk2SbiLib.inf
RiscVOpensbiLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVOpensbiLib/RiscVOpensbiLib.inf
diff --git a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf
index 9736277fa1..1cfbef961f 100644
--- a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf
+++ b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf
@@ -41,6 +41,7 @@
DebugAgentLib
DebugLib
ExtractGuidedSectionLib
+ FdtLib
IoLib
PcdLib
PeCoffLib
@@ -62,6 +63,7 @@
gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootHartId
gUefiRiscVPlatformPkgTokenSpaceGuid.PcdHartCount
gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootableHartNumber
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootableHartIndexToId
gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRootFirmwareDomainBaseAddress
gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRootFirmwareDomainSize
gUefiRiscVPlatformPkgTokenSpaceGuid.PcdOpenSbiStackSize
diff --git a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c
index fb0adbca54..51d9edfe75 100644
--- a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c
+++ b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c
@@ -615,16 +615,17 @@ GetDeviceTreeAddress (
EFI_COMMON_SECTION_HEADER *FoundSection;
if (FixedPcdGet32 (PcdDeviceTreeAddress)) {
+ DEBUG ((DEBUG_INFO, "Use fixed address of DBT from PcdDeviceTreeAddress.\n"));
return (VOID *)*((unsigned long *)FixedPcdGet32 (PcdDeviceTreeAddress));
} else if (FixedPcdGet32 (PcdRiscVDtbFvBase)) {
+ DEBUG ((DEBUG_INFO, "Use DBT FV\n"));
Status = FindFfsFileAndSection (
(EFI_FIRMWARE_VOLUME_HEADER *)FixedPcdGet32 (PcdRiscVDtbFvBase),
EFI_FV_FILETYPE_FREEFORM,
EFI_SECTION_RAW,
&FoundSection
- );
+ );
if (EFI_ERROR(Status)) {
- DEBUG ((DEBUG_ERROR, "Platform Device Tree is not found from FV.\n"));
return NULL;
}
FoundSection ++;
@@ -635,6 +636,35 @@ GetDeviceTreeAddress (
}
return NULL;
}
+/**
+ Overwrite hart_index2id array if platform would like to use the
+ bootable harts other than those declared in Device Tree
+
+ @param[in] SbiPlatform Pointer to SBI platform
+ @retval hart_index2id Index to ID value may be overwrote.
+ @retval hart_count Index to ID value may be overwrote.
+
+**/
+VOID
+Edk2PlatformHartIndex2Id (
+ IN struct sbi_platform *SbiPlatform
+ )
+{
+ UINT32 Index;
+ UINT32 *HartIndexToId;
+ UINT32 BootableHartCount;
+ UINT8 *PlatformHartIndex2IdArray;
+
+ BootableHartCount = FixedPcdGet32(PcdBootableHartNumber);
+ if (BootableHartCount != 0) {
+ HartIndexToId = (UINT32 *)SbiPlatform->hart_index2id;
+ PlatformHartIndex2IdArray = (UINT8 *)FixedPcdGetPtr (PcdBootableHartIndexToId);
+ for (Index = 0; Index < BootableHartCount; Index++) {
+ *(HartIndexToId + Index) = (UINT32)(*(PlatformHartIndex2IdArray + Index));
+ }
+ SbiPlatform->hart_count = BootableHartCount;
+ }
+}
/**
This function initilizes hart specific information and SBI.
@@ -671,17 +701,13 @@ VOID EFIAPI SecCoreStartUpWithStack(
IN struct sbi_scratch *Scratch
)
{
+ UINT32 HardIndex;
UINT64 BootHartDoneSbiInit;
UINT64 NonBootHartMessageLockValue;
struct sbi_platform *ThisSbiPlatform;
EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC *HartFirmwareContext;
- Scratch->next_arg1 = (unsigned long)GetDeviceTreeAddress ();
- if (Scratch->next_arg1 == (unsigned long)NULL) {
- DEBUG ((DEBUG_ERROR, "Platform Device Tree is not found\n"));
- ASSERT (FALSE);
- }
- DEBUG ((DEBUG_INFO, "DTB address: 0x%08x\n", Scratch->next_arg1));
+ DEBUG ((DEBUG_INFO, "HART ID: 0x%x enter SecCoreStartUpWithStack\n", HartId));
//
// Setup EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC for each hart.
@@ -705,6 +731,18 @@ VOID EFIAPI SecCoreStartUpWithStack(
ThisSbiPlatform->platform_ops_addr = (unsigned long)&Edk2OpensbiPlatformOps;
if (HartId == FixedPcdGet32(PcdBootHartId)) {
+
+ Scratch->next_arg1 = (unsigned long)GetDeviceTreeAddress ();
+ if (Scratch->next_arg1 == (unsigned long)NULL) {
+ DEBUG ((DEBUG_ERROR, "Platform Device Tree is not found\n"));
+ ASSERT (FALSE);
+ }
+
+ DEBUG ((DEBUG_INFO, "HART number: 0x%x\n", ThisSbiPlatform->hart_count));
+ DEBUG ((DEBUG_INFO, "HART index to HART ID:\n"));
+ for (HardIndex = 0; HardIndex < ThisSbiPlatform->hart_count; HardIndex ++) {
+ DEBUG ((DEBUG_INFO, " Index: %d -> Hard ID: %x\n", HardIndex, ThisSbiPlatform->hart_index2id [HardIndex]));
+ }
LaunchPeiCore (HartId, Scratch);
}
@@ -739,3 +777,11 @@ VOID EFIAPI SecCoreStartUpWithStack(
sbi_init(Scratch);
}
+void xxxx (char *debugstr, ...)
+{
+ VA_LIST Marker;
+
+ VA_START (Marker, debugstr);
+ DebugVPrint (DEBUG_INFO, debugstr, Marker);
+ VA_END (Marker);
+}
diff --git a/Platform/RISC-V/PlatformPkg/Universal/Sec/Riscv64/SecEntry.S b/Platform/RISC-V/PlatformPkg/Universal/Sec/Riscv64/SecEntry.S
index b3eccf92eb..f0c3dff0d9 100644
--- a/Platform/RISC-V/PlatformPkg/Universal/Sec/Riscv64/SecEntry.S
+++ b/Platform/RISC-V/PlatformPkg/Universal/Sec/Riscv64/SecEntry.S
@@ -101,16 +101,35 @@ _scratch_init:
/* Loop to next hart */
blt t1, s7, _scratch_init
- /* Fill-out temporary memory with 55aa*/
+ li a4, FixedPcdGet32 (PcdTemporaryRamBase)
+ li a5, FixedPcdGet32 (PcdTemporaryRamSize)
+
+ /* Use Temp memory as the stack for calling to C code */
+ add sp, a4, a5
+ /* Get the address of device tree and call generic fw_platform_init */
+ call GetDeviceTreeAddress /* a0 return the device tree address */
+ beqz a0, skip_fw_init
+ add a1, a0, 0 /* a1 is device tree */
+ csrr a0, CSR_MHARTID /* a0 is hart ID */
+ call fw_platform_init
+skip_fw_init:
+
+ /* Zero out temporary memory */
li a4, FixedPcdGet32 (PcdTemporaryRamBase)
li a5, FixedPcdGet32 (PcdTemporaryRamSize)
add a5, a4, a5
1:
- li a3, 0x5AA55AA55AA55AA5
+ li a3, 0x0
sd a3, (a4)
add a4, a4, __SIZEOF_POINTER__
blt a4, a5, 1b
+ /* Overwrite hart_index2id array of
+ platform would like to use the bootable hart
+ other than it defined in Device Tree */
+ la a0, platform
+ call Edk2PlatformHartIndex2Id
+
/* Update boot hart flag */
la a4, _boot_hart_done
li a5, 1
@@ -136,6 +155,10 @@ _start_warm:
csrw CSR_MIP, zero
li s7, FixedPcdGet32 (PcdBootableHartNumber)
+ bnez s7, 1f
+ la a4, platform
+ REG_L s7, SBI_PLATFORM_HART_COUNT_OFFSET(a4)
+1:
li s8, FixedPcdGet32 (PcdOpenSbiStackSize)
la a4, platform
@@ -205,7 +228,7 @@ _start_warm:
/* Setup stack */
add sp, tp, zero
- /* Setup stack for the Hart executing EFI to top of temporary ram*/
+ /* Setup stack for the boot hart executing EFI to top of temporary ram*/
csrr a6, CSR_MHARTID
li a5, FixedPcdGet32 (PcdBootHartId)
bne a6, a5, 1f
--
2.31.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH 49/79] RiscVPlatformPkg/OpensbiPlatformLib: Remove platform code
2022-01-08 7:24 [PATCH 42/79] RISC-V: Use RISC-V PeiCoreEntryPoint library Abner Chang
` (5 preceding siblings ...)
2022-01-08 7:24 ` [PATCH 48/79] RiscVPlatformPkg/Sec: Initial hart_index2Id array Abner Chang
@ 2022-01-08 7:24 ` Abner Chang
2022-01-08 7:24 ` [PATCH 50/79] RiscVPlatformPkg/RiscVSpecialPlatformLib: Rename module name Abner Chang
` (11 subsequent siblings)
18 siblings, 0 replies; 21+ messages in thread
From: Abner Chang @ 2022-01-08 7:24 UTC (permalink / raw)
To: devel; +Cc: abner.chang
(This is migrated from edk2-platforms:Platform)
Remove platform code from generic OpensbiPlatfomLib.
Cc: Sunil V L <sunilvl@ventanamicro.com>
Cc: Daniel Schaefer <daniel.schaefer@hpe.com>
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Reviewed-by: Daniel Schaefer <daniel.schaefer@hpe.com>
Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
---
.../Library/OpensbiPlatformLib/Platform.c | 25 ++++++-------------
1 file changed, 7 insertions(+), 18 deletions(-)
diff --git a/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/Platform.c b/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/Platform.c
index bdd7a6d3ba..b477b81d74 100644
--- a/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/Platform.c
+++ b/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/Platform.c
@@ -270,24 +270,13 @@ const struct sbi_platform_operations platform_ops = {
.timer_exit = fdt_timer_exit,
};
-#if FixedPcdGet32(PcdBootableHartNumber) == 4
-#define U540_BOOTABLE_HART_COUNT FixedPcdGet32(PcdBootableHartNumber)
-static u32 U540_hart_index2id[U540_BOOTABLE_HART_COUNT] = {1, 2, 3, 4};
-#endif
-
struct sbi_platform platform = {
- .opensbi_version = OPENSBI_VERSION,
- .platform_version = SBI_PLATFORM_VERSION(0x0, 0x01),
- .name = "Generic",
- .features = SBI_PLATFORM_DEFAULT_FEATURES,
- .hart_count = SBI_HARTMASK_MAX_BITS,
-// TODO: Workaround for U540. Not sure why we need this. OpenSBI doesn't need it.
-#if FixedPcdGet32(PcdBootableHartNumber) == 4
- .hart_index2id = U540_hart_index2id,
-#else
- .hart_index2id = generic_hart_index2id,
-#endif
- // TODO: Any reason why it shouldn't just be SBI_PLATFORM_DEFAULT_HART_STACK_SIZE?
- .hart_stack_size = FixedPcdGet32(PcdOpenSbiStackSize),
+ .opensbi_version = OPENSBI_VERSION,
+ .platform_version = SBI_PLATFORM_VERSION(0x0, 0x01),
+ .name = "Generic",
+ .features = SBI_PLATFORM_DEFAULT_FEATURES,
+ .hart_count = SBI_HARTMASK_MAX_BITS,
+ .hart_index2id = generic_hart_index2id,
+ .hart_stack_size = FixedPcdGet32(PcdOpenSbiStackSize), // The stack given by SEC for each hart
.platform_ops_addr = (unsigned long)&platform_ops
};
--
2.31.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH 50/79] RiscVPlatformPkg/RiscVSpecialPlatformLib: Rename module name
2022-01-08 7:24 [PATCH 42/79] RISC-V: Use RISC-V PeiCoreEntryPoint library Abner Chang
` (6 preceding siblings ...)
2022-01-08 7:24 ` [PATCH 49/79] RiscVPlatformPkg/OpensbiPlatformLib: Remove platform code Abner Chang
@ 2022-01-08 7:24 ` Abner Chang
2022-01-08 7:24 ` [PATCH 51/79] RiscVPkg: Update opensbi library Abner Chang
` (10 subsequent siblings)
18 siblings, 0 replies; 21+ messages in thread
From: Abner Chang @ 2022-01-08 7:24 UTC (permalink / raw)
To: devel; +Cc: abner.chang
(This is migrated from edk2-platforms:Platform)
Rename RiscVSpecialPlatformLib to RiscVSpecialPlatformLibNull
because this is the NULL instance for RiscVPlatformPkg.
Cc: Sunil V L <sunilvl@ventanamicro.com>
Cc: Daniel Schaefer <daniel.schaefer@hpe.com>
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Reviewed-by: Daniel Schaefer <daniel.schaefer@hpe.com>
Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
---
Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dsc | 4 ++--
.../RiscVSpecialPlatformLibNull.inf} | 0
.../RiscVSpecialPlatformLib.c | 3 ++-
3 files changed, 4 insertions(+), 3 deletions(-)
rename Platform/RISC-V/PlatformPkg/Library/{RiscVSpecialPlatformLib/RiscVSpecialPlatformLib.inf => RiscVSpecialPlatformLibNull/RiscVSpecialPlatformLibNull.inf} (100%)
rename Platform/RISC-V/PlatformPkg/Library/{RiscVSpecialPlatformLib => RiscVSpecialPlatformLibNull}/RiscVSpecialPlatformLib.c (76%)
diff --git a/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dsc b/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dsc
index 97d5dd08a0..bbb043f9ed 100644
--- a/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dsc
+++ b/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dsc
@@ -72,7 +72,7 @@
[LibraryClasses.common.SEC]
ExtractGuidedSectionLib|MdePkg/Library/BaseExtractGuidedSectionLib/BaseExtractGuidedSectionLib.inf
- RiscVSpecialPlatformLib|Platform/RISC-V/PlatformPkg/Library/RiscVSpecialPlatformLib/RiscVSpecialPlatformLib.inf
+ RiscVSpecialPlatformLib|Platform/RISC-V/PlatformPkg/Library/RiscVSpecialPlatformLibNull/RiscVSpecialPlatformLibNull.inf
[LibraryClasses.common.DXE_DRIVER]
PlatformBootManagerLib|Platform/RISC-V/PlatformPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
@@ -86,7 +86,7 @@
Platform/RISC-V/PlatformPkg/Library/RiscVPlatformTempMemoryInitLibNull/RiscVPlatformTempMemoryInitLibNull.inf
Platform/RISC-V/PlatformPkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.inf
Platform/RISC-V/PlatformPkg/Library/PlatformSecPpiLibNull/PlatformSecPpiLibNull.inf
- Platform/RISC-V/PlatformPkg/Library/RiscVSpecialPlatformLib/RiscVSpecialPlatformLib.inf
+ Platform/RISC-V/PlatformPkg/Library/RiscVSpecialPlatformLibNull/RiscVSpecialPlatformLibNull.inf
[Components.common.SEC]
Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf
diff --git a/Platform/RISC-V/PlatformPkg/Library/RiscVSpecialPlatformLib/RiscVSpecialPlatformLib.inf b/Platform/RISC-V/PlatformPkg/Library/RiscVSpecialPlatformLibNull/RiscVSpecialPlatformLibNull.inf
similarity index 100%
rename from Platform/RISC-V/PlatformPkg/Library/RiscVSpecialPlatformLib/RiscVSpecialPlatformLib.inf
rename to Platform/RISC-V/PlatformPkg/Library/RiscVSpecialPlatformLibNull/RiscVSpecialPlatformLibNull.inf
diff --git a/Platform/RISC-V/PlatformPkg/Library/RiscVSpecialPlatformLib/RiscVSpecialPlatformLib.c b/Platform/RISC-V/PlatformPkg/Library/RiscVSpecialPlatformLibNull/RiscVSpecialPlatformLib.c
similarity index 76%
rename from Platform/RISC-V/PlatformPkg/Library/RiscVSpecialPlatformLib/RiscVSpecialPlatformLib.c
rename to Platform/RISC-V/PlatformPkg/Library/RiscVSpecialPlatformLibNull/RiscVSpecialPlatformLib.c
index 3a77ff6b17..18c152001c 100644
--- a/Platform/RISC-V/PlatformPkg/Library/RiscVSpecialPlatformLib/RiscVSpecialPlatformLib.c
+++ b/Platform/RISC-V/PlatformPkg/Library/RiscVSpecialPlatformLibNull/RiscVSpecialPlatformLib.c
@@ -14,6 +14,7 @@
//
#include <Library/RiscVSpecialPlatformLib.h>
-const struct platform_override *SpecialPlatformArray = NULL;
+const struct platform_override *special_platforms = NULL;
+const struct platform_override *SpecialPlatformArray = NULL;
INTN NumberOfPlaformsInArray;
--
2.31.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH 51/79] RiscVPkg: Update opensbi library
2022-01-08 7:24 [PATCH 42/79] RISC-V: Use RISC-V PeiCoreEntryPoint library Abner Chang
` (7 preceding siblings ...)
2022-01-08 7:24 ` [PATCH 50/79] RiscVPlatformPkg/RiscVSpecialPlatformLib: Rename module name Abner Chang
@ 2022-01-08 7:24 ` Abner Chang
2022-01-08 7:24 ` [PATCH 52/79] RiscVPlatformPkg/Sec: Check Cold/Warm hart Abner Chang
` (9 subsequent siblings)
18 siblings, 0 replies; 21+ messages in thread
From: Abner Chang @ 2022-01-08 7:24 UTC (permalink / raw)
To: devel; +Cc: abner.chang
(This is migrated from edk2-platforms:Silicon)
Update opensbi library to a731c7e36988c3308e1978ecde491f2f6182d490,
which is based on v0.9.
Cc: Daniel Schaefer <daniel.schaefer@hpe.com>
Cc: Sunil V L <sunilvl@ventanamicro.com>
Signed-off-by: Daniel Schaefer <daniel.schaefer@hpe.com>
Reviewed-by: Daniel Schaefer <daniel.schaefer@hpe.com>
Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
---
Silicon/RISC-V/ProcessorPkg/Library/RiscVOpensbiLib/opensbi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVOpensbiLib/opensbi b/Silicon/RISC-V/ProcessorPkg/Library/RiscVOpensbiLib/opensbi
index ac5e821d50..a731c7e369 160000
--- a/Silicon/RISC-V/ProcessorPkg/Library/RiscVOpensbiLib/opensbi
+++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVOpensbiLib/opensbi
@@ -1 +1 @@
-Subproject commit ac5e821d50be631f26274765a59bc1b444ffd862
+Subproject commit a731c7e36988c3308e1978ecde491f2f6182d490
--
2.31.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH 52/79] RiscVPlatformPkg/Sec: Check Cold/Warm hart
2022-01-08 7:24 [PATCH 42/79] RISC-V: Use RISC-V PeiCoreEntryPoint library Abner Chang
` (8 preceding siblings ...)
2022-01-08 7:24 ` [PATCH 51/79] RiscVPkg: Update opensbi library Abner Chang
@ 2022-01-08 7:24 ` Abner Chang
2022-01-08 7:24 ` [PATCH 53/79] RiscVPlatformPkg/Sec: Add more comments to Secmain.c Abner Chang
` (8 subsequent siblings)
18 siblings, 0 replies; 21+ messages in thread
From: Abner Chang @ 2022-01-08 7:24 UTC (permalink / raw)
To: devel; +Cc: abner.chang
(This is migrated from edk2-platforms:Platform)
Check Coldboot or Warmboot hart in SEC OpenSBI platform function.
Cc: Sunil V L <sunilvl@ventanamicro.com>
Cc: Daniel Schaefer <daniel.schaefer@hpe.com>
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Reviewed-by: Daniel Schaefer <daniel.schaefer@hpe.com>
Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
---
.../RISC-V/PlatformPkg/Universal/Sec/SecMain.c | 15 ++++++++++++++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c
index 51d9edfe75..9b162fb3b6 100644
--- a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c
+++ b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c
@@ -398,6 +398,13 @@ SecPostOpenSbiPlatformEarlylInit(
IN BOOLEAN ColdBoot
)
{
+ UINT32 HartId;
+
+ if (!ColdBoot) {
+ HartId = current_hartid();
+ DEBUG ((DEBUG_INFO, "%a: Non boot hart %d.\n", __FUNCTION__, HartId));
+ return 0;
+ }
//
// Boot HART is already in the process of OpenSBI initialization.
// We can let other HART to keep booting.
@@ -423,6 +430,12 @@ SecPostOpenSbiPlatformFinalInit (
struct sbi_platform *SbiPlatform;
EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *FirmwareContext;
+ if (!ColdBoot) {
+ HartId = current_hartid();
+ DEBUG ((DEBUG_INFO, "%a: Non boot hart %d.\n", __FUNCTION__, HartId));
+ return 0;
+ }
+
DEBUG((DEBUG_INFO, "%a: Entry, preparing to jump to PEI Core\n\n", __FUNCTION__));
SbiScratch = sbi_scratch_thishart_ptr();
@@ -777,7 +790,7 @@ VOID EFIAPI SecCoreStartUpWithStack(
sbi_init(Scratch);
}
-void xxxx (char *debugstr, ...)
+void OpensbiDebugPrint (char *debugstr, ...)
{
VA_LIST Marker;
--
2.31.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH 53/79] RiscVPlatformPkg/Sec: Add more comments to Secmain.c
2022-01-08 7:24 [PATCH 42/79] RISC-V: Use RISC-V PeiCoreEntryPoint library Abner Chang
` (9 preceding siblings ...)
2022-01-08 7:24 ` [PATCH 52/79] RiscVPlatformPkg/Sec: Check Cold/Warm hart Abner Chang
@ 2022-01-08 7:24 ` Abner Chang
2022-01-08 7:24 ` [PATCH 54/79] RiscV/ProcessorPkg: Create read mtime CSR library instances Abner Chang
` (7 subsequent siblings)
18 siblings, 0 replies; 21+ messages in thread
From: Abner Chang @ 2022-01-08 7:24 UTC (permalink / raw)
To: devel; +Cc: abner.chang
(This is migrated from edk2-platforms:Platform)
Add more comments to SecMain.c
Cc: Sunil V L <sunilvl@ventanamicro.com>
Cc: Daniel Schaefer <daniel.schaefer@hpe.com>
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Reviewed-by: Daniel Schaefer <daniel.schaefer@hpe.com>
Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
---
Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c | 9 ++++++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c
index 9b162fb3b6..93ff8a598d 100644
--- a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c
+++ b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c
@@ -628,7 +628,10 @@ GetDeviceTreeAddress (
EFI_COMMON_SECTION_HEADER *FoundSection;
if (FixedPcdGet32 (PcdDeviceTreeAddress)) {
- DEBUG ((DEBUG_INFO, "Use fixed address of DBT from PcdDeviceTreeAddress.\n"));
+ DEBUG ((DEBUG_INFO, "Use fixed address of DBT from PcdDeviceTreeAddress 0x%x.\n", FixedPcdGet32 (PcdDeviceTreeAddress)));
+ //
+ // Device tree address is pointed by PcdDeviceTreeAddress.
+ //
return (VOID *)*((unsigned long *)FixedPcdGet32 (PcdDeviceTreeAddress));
} else if (FixedPcdGet32 (PcdRiscVDtbFvBase)) {
DEBUG ((DEBUG_INFO, "Use DBT FV\n"));
@@ -720,7 +723,7 @@ VOID EFIAPI SecCoreStartUpWithStack(
struct sbi_platform *ThisSbiPlatform;
EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC *HartFirmwareContext;
- DEBUG ((DEBUG_INFO, "HART ID: 0x%x enter SecCoreStartUpWithStack\n", HartId));
+ //DEBUG ((DEBUG_INFO, "HART ID: 0x%x enter SecCoreStartUpWithStack\n", HartId));
//
// Setup EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC for each hart.
@@ -750,7 +753,7 @@ VOID EFIAPI SecCoreStartUpWithStack(
DEBUG ((DEBUG_ERROR, "Platform Device Tree is not found\n"));
ASSERT (FALSE);
}
-
+ DEBUG ((DEBUG_INFO, "Device Tree at 0x%x\n", Scratch->next_arg1));
DEBUG ((DEBUG_INFO, "HART number: 0x%x\n", ThisSbiPlatform->hart_count));
DEBUG ((DEBUG_INFO, "HART index to HART ID:\n"));
for (HardIndex = 0; HardIndex < ThisSbiPlatform->hart_count; HardIndex ++) {
--
2.31.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH 54/79] RiscV/ProcessorPkg: Create read mtime CSR library instances
2022-01-08 7:24 [PATCH 42/79] RISC-V: Use RISC-V PeiCoreEntryPoint library Abner Chang
` (10 preceding siblings ...)
2022-01-08 7:24 ` [PATCH 53/79] RiscVPlatformPkg/Sec: Add more comments to Secmain.c Abner Chang
@ 2022-01-08 7:24 ` Abner Chang
2022-01-08 7:24 ` [PATCH 55/79] RiscV/ProcessorPkg: Use mtime CSR library Abner Chang
` (6 subsequent siblings)
18 siblings, 0 replies; 21+ messages in thread
From: Abner Chang @ 2022-01-08 7:24 UTC (permalink / raw)
To: devel; +Cc: abner.chang
(This is migrated from edk2-platforms:Silicon)
Create library instances of reading Machine mode timer.
- MacineModeTimerLib is used to read mtime CSR through
platfrom library.
- EmulatedMacineModeTimerLib is used to read mtime CSR
through shadow CSR.
Cc: Sunil V L <sunilvl@ventanamicro.com>
Cc: Daniel Schaefer <daniel.schaefer@hpe.com>
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Reviewed-by: Daniel Schaefer <daniel.schaefer@hpe.com>
Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
---
.../RISC-V/ProcessorPkg/RiscVProcessorPkg.dsc | 2 +
.../EmulatedMachineModeTimerLib.inf | 34 +++++++++++++++++
.../MachineModeTimerLib.inf | 38 +++++++++++++++++++
.../Include/IndustryStandard/RiscV.h | 5 +++
.../Include/Library/RiscVCpuLib.h | 3 ++
.../EmulatedMachineModeTimerLib.S | 24 ++++++++++++
.../MachineModeTimerLib/MachineModeTimerLib.S | 25 ++++++++++++
7 files changed, 131 insertions(+)
create mode 100644 Silicon/RISC-V/ProcessorPkg/Library/RiscVReadMachineModeTimer/EmulatedMachineModeTimerLib/EmulatedMachineModeTimerLib.inf
create mode 100644 Silicon/RISC-V/ProcessorPkg/Library/RiscVReadMachineModeTimer/MachineModeTimerLib/MachineModeTimerLib.inf
create mode 100644 Silicon/RISC-V/ProcessorPkg/Library/RiscVReadMachineModeTimer/EmulatedMachineModeTimerLib/EmulatedMachineModeTimerLib.S
create mode 100644 Silicon/RISC-V/ProcessorPkg/Library/RiscVReadMachineModeTimer/MachineModeTimerLib/MachineModeTimerLib.S
diff --git a/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dsc b/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dsc
index 531319322c..3b5738957d 100644
--- a/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dsc
+++ b/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dsc
@@ -44,6 +44,8 @@
RiscVEdk2SbiLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVEdk2SbiLib/RiscVEdk2SbiLib.inf
RiscVOpensbiLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVOpensbiLib/RiscVOpensbiLib.inf
TimerLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVTimerLib/BaseRiscVTimerLib.inf
+ MachineModeTimerLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVReadMachineModeTimer/MachineModeTimerLib/MachineModeTimerLib.inf
+ #MachineModeTimerLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVReadMachineModeTimer/EmulatedMachineModeTimerLib/EmulatedMachineModeTimerLib.inf
BaseLib|MdePkg/Library/BaseLib/BaseLib.inf
BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
DebugAgentLib|MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLibNull.inf
diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVReadMachineModeTimer/EmulatedMachineModeTimerLib/EmulatedMachineModeTimerLib.inf b/Silicon/RISC-V/ProcessorPkg/Library/RiscVReadMachineModeTimer/EmulatedMachineModeTimerLib/EmulatedMachineModeTimerLib.inf
new file mode 100644
index 0000000000..369028a9a6
--- /dev/null
+++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVReadMachineModeTimer/EmulatedMachineModeTimerLib/EmulatedMachineModeTimerLib.inf
@@ -0,0 +1,34 @@
+## @file
+# Library to read Machine Mode Timer.
+#
+# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001b
+ BASE_NAME = EmulatedMachineModeTimerLib
+ FILE_GUID = 81B82615-D85C-4377-8BFF-7442322E2835
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = MachineModeTimerLib
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = RISCV64
+#
+
+[Sources]
+
+[Sources.RISCV64]
+ EmulatedMachineModeTimerLib.S
+
+[Packages]
+ MdePkg/MdePkg.dec
+ Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec
+
+
+
diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVReadMachineModeTimer/MachineModeTimerLib/MachineModeTimerLib.inf b/Silicon/RISC-V/ProcessorPkg/Library/RiscVReadMachineModeTimer/MachineModeTimerLib/MachineModeTimerLib.inf
new file mode 100644
index 0000000000..71d4315445
--- /dev/null
+++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVReadMachineModeTimer/MachineModeTimerLib/MachineModeTimerLib.inf
@@ -0,0 +1,38 @@
+## @file
+# Library to read Machine Mode Timer.
+#
+# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001b
+ BASE_NAME = MachineModeTimerLib
+ FILE_GUID = 6390D8AA-E0E6-4625-A515-9BB2DC7BBCAB
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = MachineModeTimerLib
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = RISCV64
+#
+
+[Sources]
+
+[Sources.RISCV64]
+ MachineModeTimerLib.S
+
+[Packages]
+ MdePkg/MdePkg.dec
+ Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec
+
+[LibraryClasses]
+ RiscVCpuLib
+ RiscVPlatformTimerLib
+
+
+
diff --git a/Silicon/RISC-V/ProcessorPkg/Include/IndustryStandard/RiscV.h b/Silicon/RISC-V/ProcessorPkg/Include/IndustryStandard/RiscV.h
index f6726bda24..c9715a2ee2 100644
--- a/Silicon/RISC-V/ProcessorPkg/Include/IndustryStandard/RiscV.h
+++ b/Silicon/RISC-V/ProcessorPkg/Include/IndustryStandard/RiscV.h
@@ -154,4 +154,9 @@
#define RISCV_CSR_MTOHOST 0x780
#define RISCV_CSR_MFROMHOST 0x781
+//
+// User mode CSR
+//
+#define RISCV_CSR_CYCLE 0xc00
+#define RISCV_CSR_TIME 0xc01
#endif
diff --git a/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVCpuLib.h b/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVCpuLib.h
index f70723567e..8d51152fa9 100644
--- a/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVCpuLib.h
+++ b/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVCpuLib.h
@@ -32,6 +32,9 @@ RiscVGetMachineTrapCause (VOID);
UINT64
RiscVReadMachineTimer (VOID);
+UINT64
+RiscVReadMachineTimerInterface (VOID);
+
VOID
RiscVSetMachineTimerCmp (UINT64);
diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVReadMachineModeTimer/EmulatedMachineModeTimerLib/EmulatedMachineModeTimerLib.S b/Silicon/RISC-V/ProcessorPkg/Library/RiscVReadMachineModeTimer/EmulatedMachineModeTimerLib/EmulatedMachineModeTimerLib.S
new file mode 100644
index 0000000000..1acd0ab062
--- /dev/null
+++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVReadMachineModeTimer/EmulatedMachineModeTimerLib/EmulatedMachineModeTimerLib.S
@@ -0,0 +1,24 @@
+//------------------------------------------------------------------------------
+//
+// Read Machine mode timer using shadow CSR.
+//
+// Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+//
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+//------------------------------------------------------------------------------
+#include <IndustryStandard/RiscV.h>
+
+.data
+
+.text
+.align 3
+
+.global ASM_PFX(RiscVReadMachineTimerInterface)
+//
+// Read machine mode timer CSR through shadow CSR.
+// @retval a0 : 64-bit machine timer.
+//
+ASM_PFX (RiscVReadMachineTimerInterface):
+ csrr a0, RISCV_CSR_TIME
+ ret
diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVReadMachineModeTimer/MachineModeTimerLib/MachineModeTimerLib.S b/Silicon/RISC-V/ProcessorPkg/Library/RiscVReadMachineModeTimer/MachineModeTimerLib/MachineModeTimerLib.S
new file mode 100644
index 0000000000..16f8bdd70a
--- /dev/null
+++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVReadMachineModeTimer/MachineModeTimerLib/MachineModeTimerLib.S
@@ -0,0 +1,25 @@
+//------------------------------------------------------------------------------
+//
+// Read mtimer through platform library.
+//
+// Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+//
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+//------------------------------------------------------------------------------
+#include <RiscVImpl.h>
+
+.data
+
+.text
+.align 3
+
+.global ASM_PFX(RiscVReadMachineTimerInterface)
+//
+// Read machine mode timer CSR.
+// @retval a0 : 64-bit machine timer.
+//
+ASM_PFX (RiscVReadMachineTimerInterface):
+ call RiscVReadMachineTimer
+ ret
+
--
2.31.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH 55/79] RiscV/ProcessorPkg: Use mtime CSR library
2022-01-08 7:24 [PATCH 42/79] RISC-V: Use RISC-V PeiCoreEntryPoint library Abner Chang
` (11 preceding siblings ...)
2022-01-08 7:24 ` [PATCH 54/79] RiscV/ProcessorPkg: Create read mtime CSR library instances Abner Chang
@ 2022-01-08 7:24 ` Abner Chang
2022-01-08 7:24 ` [PATCH 56/79] RISC-V/PlatformPkg: Updates for the latest OpenSBI Abner Chang
` (5 subsequent siblings)
18 siblings, 0 replies; 21+ messages in thread
From: Abner Chang @ 2022-01-08 7:24 UTC (permalink / raw)
To: devel; +Cc: abner.chang
(This is migrated from edk2-platforms:Silicon)
Use mtime CSR library interface to access mtime
CSR.
Cc: Sunil V L <sunilvl@ventanamicro.com>
Cc: Daniel Schaefer <daniel.schaefer@hpe.com>
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Reviewed-by: Daniel Schaefer <daniel.schaefer@hpe.com>
Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
---
.../Library/RiscVTimerLib/BaseRiscVTimerLib.inf | 3 ++-
Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxe.inf | 1 +
.../ProcessorPkg/Library/RiscVTimerLib/RiscVTimerLib.c | 6 +++---
Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxe.c | 2 +-
4 files changed, 7 insertions(+), 5 deletions(-)
diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVTimerLib/BaseRiscVTimerLib.inf b/Silicon/RISC-V/ProcessorPkg/Library/RiscVTimerLib/BaseRiscVTimerLib.inf
index c914d3b4b6..3c61149da8 100644
--- a/Silicon/RISC-V/ProcessorPkg/Library/RiscVTimerLib/BaseRiscVTimerLib.inf
+++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVTimerLib/BaseRiscVTimerLib.inf
@@ -30,5 +30,6 @@
BaseLib
PcdLib
RiscVCpuLib
- RiscVPlatformTimerLib
+ MachineModeTimerLib
+
diff --git a/Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxe.inf b/Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxe.inf
index 29cc4413bd..a422c12e32 100644
--- a/Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxe.inf
+++ b/Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxe.inf
@@ -26,6 +26,7 @@
CpuLib
CpuExceptionHandlerLib
DebugLib
+ MachineModeTimerLib
RiscVCpuLib
TimerLib
UefiBootServicesTableLib
diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVTimerLib/RiscVTimerLib.c b/Silicon/RISC-V/ProcessorPkg/Library/RiscVTimerLib/RiscVTimerLib.c
index 97fe2aef4b..54ca99787e 100644
--- a/Silicon/RISC-V/ProcessorPkg/Library/RiscVTimerLib/RiscVTimerLib.c
+++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVTimerLib/RiscVTimerLib.c
@@ -36,9 +36,9 @@ InternalRiscVTimerDelay (
//
// The target timer count is calculated here
//
- Ticks = RiscVReadMachineTimer () + Delay;
+ Ticks = RiscVReadMachineTimerInterface () + Delay;
Delay = 1 << (RISCV_TIMER_COMPARE_BITS - 2);
- while (((Ticks - RiscVReadMachineTimer ()) & ( 1 << (RISCV_TIMER_COMPARE_BITS - 1))) == 0) {
+ while (((Ticks - RiscVReadMachineTimerInterface ()) & ( 1 << (RISCV_TIMER_COMPARE_BITS - 1))) == 0) {
CpuPause ();
}
} while (Times-- > 0);
@@ -118,7 +118,7 @@ GetPerformanceCounter (
VOID
)
{
- return (UINT64)RiscVReadMachineTimer ();
+ return (UINT64)RiscVReadMachineTimerInterface ();
}
/**return
diff --git a/Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxe.c b/Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxe.c
index b8b8e91a6c..3104c6d2de 100644
--- a/Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxe.c
+++ b/Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxe.c
@@ -223,7 +223,7 @@ CpuGetTimerValue (
return EFI_INVALID_PARAMETER;
}
- *TimerValue = (UINT64)RiscVReadMachineTimer ();
+ *TimerValue = (UINT64)RiscVReadMachineTimerInterface ();
if (TimerPeriod != NULL) {
*TimerPeriod = DivU64x32 (
1000000000000000u,
--
2.31.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH 56/79] RISC-V/PlatformPkg: Updates for the latest OpenSBI
2022-01-08 7:24 [PATCH 42/79] RISC-V: Use RISC-V PeiCoreEntryPoint library Abner Chang
` (12 preceding siblings ...)
2022-01-08 7:24 ` [PATCH 55/79] RiscV/ProcessorPkg: Use mtime CSR library Abner Chang
@ 2022-01-08 7:24 ` Abner Chang
2022-01-08 7:24 ` [PATCH 57/79] PlatformPkg/Sec: Separate EDK2 Opensbi platform hook Abner Chang
` (4 subsequent siblings)
18 siblings, 0 replies; 21+ messages in thread
From: Abner Chang @ 2022-01-08 7:24 UTC (permalink / raw)
To: devel; +Cc: abner.chang
(This is migrated from edk2-platforms:Platform)
Code changes to incorporate with OpenSBI commit ID:
a731c7e36988c3308e1978ecde491f2f6182d490
Cc: Sunil V L <sunilvl@ventanamicro.com>
Cc: Daniel Schaefer <daniel.schaefer@hpe.com>
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Reviewed-by: Daniel Schaefer <daniel.schaefer@hpe.com>
Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
---
.../OpensbiPlatformLib/OpensbiPlatformLib.inf | 10 +-
.../PlatformPkg/Universal/Sec/SecMain.inf | 4 +
.../Library/OpensbiPlatformLib/Platform.c | 57 ----
.../Universal/Sec/Edk2OpenSbiPlatform.c | 149 ---------
.../PlatformPkg/Universal/Sec/SecMain.c | 48 ++-
.../Universal/Sec/Riscv64/SecEntry.S | 300 ++++++++++--------
6 files changed, 212 insertions(+), 356 deletions(-)
diff --git a/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/OpensbiPlatformLib.inf b/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/OpensbiPlatformLib.inf
index 909fbffa8d..2e1227733a 100644
--- a/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/OpensbiPlatformLib.inf
+++ b/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/OpensbiPlatformLib.inf
@@ -51,12 +51,4 @@
gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootableHartNumber
gUefiRiscVPlatformPkgTokenSpaceGuid.PcdOpenSbiStackSize
- gSiFiveU5SeriesPlatformsPkgTokenSpaceGuid.PcdU5UartBase
- gSiFiveU5SeriesPlatformsPkgTokenSpaceGuid.PcdU5PlatformSystemClock
-
- gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRootFirmwareDomainBaseAddress
- gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRootFirmwareDomainSize
- gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFirmwareDomainBaseAddress
- gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFirmwareDomainSize
- gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFirmwareRegionBaseAddress
- gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFirmwareRegionSize
+
diff --git a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf
index 1cfbef961f..dd5f01ab4d 100644
--- a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf
+++ b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf
@@ -66,6 +66,10 @@
gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootableHartIndexToId
gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRootFirmwareDomainBaseAddress
gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRootFirmwareDomainSize
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFirmwareDomainBaseAddress
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFirmwareDomainSize
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFirmwareRegionBaseAddress
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFirmwareRegionSize
gUefiRiscVPlatformPkgTokenSpaceGuid.PcdOpenSbiStackSize
gUefiRiscVPlatformPkgTokenSpaceGuid.PcdScratchRamBase
gUefiRiscVPlatformPkgTokenSpaceGuid.PcdScratchRamSize
diff --git a/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/Platform.c b/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/Platform.c
index b477b81d74..c62d235333 100644
--- a/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/Platform.c
+++ b/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/Platform.c
@@ -197,68 +197,11 @@ static u64 generic_tlbr_flush_limit(void)
return SBI_PLATFORM_TLB_RANGE_FLUSH_LIMIT_DEFAULT;
}
-static int generic_system_reset_check(u32 reset_type, u32 reset_reason)
-{
- if (generic_plat && generic_plat->system_reset_check)
- return generic_plat->system_reset_check(reset_type,
- reset_reason,
- generic_plat_match);
- return fdt_system_reset_check(reset_type, reset_reason);
-}
-
-static void generic_system_reset(u32 reset_type, u32 reset_reason)
-{
- if (generic_plat && generic_plat->system_reset) {
- generic_plat->system_reset(reset_type, reset_reason,
- generic_plat_match);
- return;
- }
-
- fdt_system_reset(reset_type, reset_reason);
-}
-
-#define EDK2_ROOT_FW_REGION 0
-#define EDK2_FW_REGION 1
-#define EDK2_VARIABLE_REGION 2
-#define EDK2_ALL_REGION 3
-#define EDK2_END_REGION 4
-static struct sbi_domain_memregion root_memregs[EDK2_END_REGION + 1] = { 0 };
-
-struct sbi_domain_memregion *get_mem_regions(void) {
- /* EDK2 root firmware domain memory region */
- root_memregs[EDK2_ROOT_FW_REGION].order = log2roundup(FixedPcdGet32(PcdRootFirmwareDomainSize));
- root_memregs[EDK2_ROOT_FW_REGION].base = FixedPcdGet32(PcdRootFirmwareDomainBaseAddress);
- root_memregs[EDK2_ROOT_FW_REGION].flags = 0;
-
- /*EDK2 firmware domain memory region */
- root_memregs[EDK2_FW_REGION].order = log2roundup(FixedPcdGet32(PcdFirmwareDomainSize));
- root_memregs[EDK2_FW_REGION].base = FixedPcdGet32(PcdFirmwareDomainBaseAddress);
- root_memregs[EDK2_FW_REGION].flags = SBI_DOMAIN_MEMREGION_EXECUTABLE | SBI_DOMAIN_MEMREGION_READABLE;
-
- /*EDK2 firmware domain memory region */
- root_memregs[EDK2_VARIABLE_REGION].order = log2roundup(FixedPcdGet32(PcdVariableFirmwareRegionSize));
- root_memregs[EDK2_VARIABLE_REGION].base = FixedPcdGet32(PcdVariableFirmwareRegionBaseAddress);
- root_memregs[EDK2_VARIABLE_REGION].flags = SBI_DOMAIN_MEMREGION_READABLE | SBI_DOMAIN_MEMREGION_WRITEABLE;
-
- /* EDK2 domain allow everything memory region */
- root_memregs[EDK2_ALL_REGION].order = __riscv_xlen;
- root_memregs[EDK2_ALL_REGION].base = 0;
- root_memregs[EDK2_ALL_REGION].flags = (SBI_DOMAIN_MEMREGION_READABLE |
- SBI_DOMAIN_MEMREGION_WRITEABLE |
- SBI_DOMAIN_MEMREGION_EXECUTABLE);
-
- /* EDK2 domain memory region end */
- root_memregs[EDK2_END_REGION].order = 0;
-
- return root_memregs;
-}
-
const struct sbi_platform_operations platform_ops = {
.early_init = generic_early_init,
.final_init = generic_final_init,
.early_exit = generic_early_exit,
.final_exit = generic_final_exit,
- .domains_root_regions = get_mem_regions,
.domains_init = generic_domains_init,
.console_init = fdt_serial_init,
.irqchip_init = fdt_irqchip_init,
diff --git a/Platform/RISC-V/PlatformPkg/Universal/Sec/Edk2OpenSbiPlatform.c b/Platform/RISC-V/PlatformPkg/Universal/Sec/Edk2OpenSbiPlatform.c
index 79b2f33675..779705489c 100644
--- a/Platform/RISC-V/PlatformPkg/Universal/Sec/Edk2OpenSbiPlatform.c
+++ b/Platform/RISC-V/PlatformPkg/Universal/Sec/Edk2OpenSbiPlatform.c
@@ -117,18 +117,6 @@ int Edk2OpensbiPlatforMMISAGetXLEN (VOID)
return 0;
}
-/** Get platform specific root domain memory regions */
-struct sbi_domain_memregion *
-Edk2OpensbiPlatformGetMemRegions (VOID)
-{
- DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));
-
- if (platform_ops.domains_root_regions) {
- return platform_ops.domains_root_regions ();
- }
- return 0;
-}
-
/** Initialize (or populate) domains for the platform */
int Edk2OpensbiPlatformDomainsInit (VOID)
{
@@ -140,25 +128,6 @@ int Edk2OpensbiPlatformDomainsInit (VOID)
return 0;
}
-/** Write a character to the platform console output */
-VOID Edk2OpensbiPlatformSerialPutc (
- CHAR8 Ch
- )
-{
- if (platform_ops.console_putc) {
- return platform_ops.console_putc (Ch);
- }
-}
-
-/** Read a character from the platform console input */
-int Edk2OpensbiPlatformSerialGetc (VOID)
-{
- if (platform_ops.console_getc) {
- return platform_ops.console_getc ();
- }
- return 0;
-}
-
/** Initialize the platform console */
int Edk2OpensbiPlatformSerialInit (VOID)
{
@@ -193,30 +162,6 @@ VOID Edk2OpensbiPlatformIrqchipExit (VOID)
}
}
-/** Send IPI to a target HART */
-VOID Edk2OpensbiPlatformIpiSend (
- UINT32 TargetHart
- )
-{
- DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));
-
- if (platform_ops.ipi_send) {
- return platform_ops.ipi_send (TargetHart);
- }
-}
-
-/** Clear IPI for a target HART */
-VOID Edk2OpensbiPlatformIpiClear (
- UINT32 TargetHart
- )
-{
- DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));
-
- if (platform_ops.ipi_clear) {
- return platform_ops.ipi_clear (TargetHart);
- }
-}
-
/** Initialize IPI for current HART */
int Edk2OpensbiPlatformIpiInit (
BOOLEAN ColdBoot
@@ -251,33 +196,6 @@ UINT64 Edk2OpensbiPlatformTlbrFlushLimit (VOID)
return 0;
}
-/** Get platform timer value */
-UINT64 Edk2OpensbiPlatformTimerValue (VOID)
-{
- if (platform_ops.timer_value) {
- return platform_ops.timer_value ();
- }
- return 0;
-}
-
-/** Start platform timer event for current HART */
-VOID Edk2OpensbiPlatformTimerEventStart (
- UINT64 NextEvent
- )
-{
- if (platform_ops.timer_event_start) {
- return platform_ops.timer_event_start (NextEvent);
- }
-}
-
-/** Stop platform timer event for current HART */
-VOID Edk2OpensbiPlatformTimerEventStop (VOID)
-{
- if (platform_ops.timer_event_stop) {
- return platform_ops.timer_event_stop ();
- }
-}
-
/** Initialize platform timer for current HART */
int Edk2OpensbiPlatformTimerInit (
BOOLEAN ColdBoot
@@ -301,61 +219,6 @@ VOID Edk2OpensbiPlatformTimerExit (VOID)
}
}
-/** Bringup the given hart */
-int Edk2OpensbiPlatformHartStart (
- UINT32 HartId,
- ulong Saddr
- )
-{
- DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));
-
- if (platform_ops.hart_start) {
- return platform_ops.hart_start (HartId, Saddr);
- }
- return 0;
-}
-/**
- Stop the current hart from running. This call doesn't expect to
- return if success.
-**/
-int Edk2OpensbiPlatformHartStop (VOID)
-{
- DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));
-
- if (platform_ops.hart_stop) {
- return platform_ops.hart_stop ();
- }
- return 0;
-}
-
-/**
- Check whether reset type and reason supported by the platform*
-
-**/
-int Edk2OpensbiPlatformSystemResetCheck (
- UINT32 ResetType,
- UINT32 ResetReason
- )
-{
- if (platform_ops.system_reset_check) {
- return platform_ops.system_reset_check (ResetType, ResetReason);
- }
- return 0;
-}
-
-/** Reset the platform */
-VOID Edk2OpensbiPlatformSystemReset (
- UINT32 ResetType,
- UINT32 ResetReason
- )
-{
- DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));
-
- if (platform_ops.system_reset) {
- return platform_ops.system_reset (ResetType, ResetReason);
- }
-}
-
/** platform specific SBI extension implementation probe function */
int Edk2OpensbiPlatformVendorExtCheck (
long ExtId
@@ -400,27 +263,15 @@ const struct sbi_platform_operations Edk2OpensbiPlatformOps = {
.final_exit = Edk2OpensbiPlatformFinalExit,
.misa_check_extension = Edk2OpensbiPlatforMMISACheckExtension,
.misa_get_xlen = Edk2OpensbiPlatforMMISAGetXLEN,
- .domains_root_regions = Edk2OpensbiPlatformGetMemRegions,
.domains_init = Edk2OpensbiPlatformDomainsInit,
- .console_putc = Edk2OpensbiPlatformSerialPutc,
- .console_getc = Edk2OpensbiPlatformSerialGetc,
.console_init = Edk2OpensbiPlatformSerialInit,
.irqchip_init = Edk2OpensbiPlatformIrqchipInit,
.irqchip_exit = Edk2OpensbiPlatformIrqchipExit,
- .ipi_send = Edk2OpensbiPlatformIpiSend,
- .ipi_clear = Edk2OpensbiPlatformIpiClear,
.ipi_init = Edk2OpensbiPlatformIpiInit,
.ipi_exit = Edk2OpensbiPlatformIpiExit,
.get_tlbr_flush_limit = Edk2OpensbiPlatformTlbrFlushLimit,
- .timer_value = Edk2OpensbiPlatformTimerValue,
- .timer_event_stop = Edk2OpensbiPlatformTimerEventStop,
- .timer_event_start = Edk2OpensbiPlatformTimerEventStart,
.timer_init = Edk2OpensbiPlatformTimerInit,
.timer_exit = Edk2OpensbiPlatformTimerExit,
- .hart_start = Edk2OpensbiPlatformHartStart,
- .hart_stop = Edk2OpensbiPlatformHartStop,
- .system_reset_check = Edk2OpensbiPlatformSystemResetCheck,
- .system_reset = Edk2OpensbiPlatformSystemReset,
.vendor_ext_check = Edk2OpensbiPlatformVendorExtCheck,
.vendor_ext_provider = Edk2OpensbiPlatformVendorExtProvider,
};
diff --git a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c
index 93ff8a598d..3bc3690047 100644
--- a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c
+++ b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c
@@ -15,10 +15,12 @@
#include <sbi/riscv_asm.h>
#include <sbi/riscv_atomic.h>
#include <sbi/sbi_console.h> // Reference to header file in opensbi
+#include <sbi/sbi_domain.h>
#include <sbi/sbi_hart.h> // Reference to header file in opensbi
-#include <sbi/sbi_hartmask.h> // Reference to header file in opensbi
+#include <sbi/sbi_hartmask.h> // Reference to header file in opensbi
#include <sbi/sbi_scratch.h> // Reference to header file in opensbi
#include <sbi/sbi_platform.h> // Reference to header file in opensbi
+#include <sbi/sbi_math.h> // Reference to header file in opensbi
#include <sbi/sbi_init.h> // Reference to header file in opensbi
#include <sbi/sbi_ecall.h> // Reference to header file in opensbi
#include <sbi/sbi_trap.h> // Reference to header file in opensbi
@@ -31,8 +33,41 @@ extern struct sbi_platform_operations Edk2OpensbiPlatformOps;
atomic_t BootHartDone = ATOMIC_INITIALIZER(0);
atomic_t NonBootHartMessageLock = ATOMIC_INITIALIZER(0);
+int sbi_domain_root_add_memregion(const struct sbi_domain_memregion *reg);
+
typedef struct sbi_scratch *(*hartid2scratch)(ulong hartid, ulong hartindex);
+struct sbi_domain_memregion fw_memregs;
+
+int SecSetEdk2FwMemoryRegions (VOID) {
+ int Ret;
+
+ Ret = 0;
+
+ //
+ // EDK2 PEI domain memory region
+ //
+ fw_memregs.order = log2roundup(FixedPcdGet32(PcdFirmwareDomainSize));
+ fw_memregs.base = FixedPcdGet32(PcdFirmwareDomainBaseAddress);
+ fw_memregs.flags = SBI_DOMAIN_MEMREGION_EXECUTABLE | SBI_DOMAIN_MEMREGION_READABLE;
+ Ret = sbi_domain_root_add_memregion ((const struct sbi_domain_memregion *)&fw_memregs);
+ if (Ret != 0) {
+ DEBUG ((DEBUG_ERROR, "%a: Add firmware regiosn of FW Domain fail\n", __FUNCTION__));
+ }
+
+ //
+ // EDK2 EFI Variable domain memory region
+ //
+ fw_memregs.order = log2roundup(FixedPcdGet32(PcdVariableFirmwareRegionSize));
+ fw_memregs.base = FixedPcdGet32(PcdVariableFirmwareRegionBaseAddress);
+ fw_memregs.flags = SBI_DOMAIN_MEMREGION_READABLE | SBI_DOMAIN_MEMREGION_WRITEABLE;
+ Ret = sbi_domain_root_add_memregion ((const struct sbi_domain_memregion *)&fw_memregs);
+ if (Ret != 0) {
+ DEBUG ((DEBUG_ERROR, "%a: Add firmware regiosn of variable FW Domain fail\n", __FUNCTION__));
+ }
+ return Ret;
+}
+
/**
Locates a section within a series of sections
with the specified section type.
@@ -405,6 +440,13 @@ SecPostOpenSbiPlatformEarlylInit(
DEBUG ((DEBUG_INFO, "%a: Non boot hart %d.\n", __FUNCTION__, HartId));
return 0;
}
+ //
+ // Setup firmware memory region.
+ //
+ if (SecSetEdk2FwMemoryRegions () != 0) {
+ ASSERT (FALSE);
+ }
+
//
// Boot HART is already in the process of OpenSBI initialization.
// We can let other HART to keep booting.
@@ -477,7 +519,7 @@ SecPostOpenSbiPlatformFinalInit (
}
}
- DEBUG((DEBUG_INFO, "%a: Jump to PEI Core with \n", __FUNCTION__));
+ DEBUG((DEBUG_INFO, "%a: Will jump to PEI Core in OpenSBI with \n", __FUNCTION__));
DEBUG((DEBUG_INFO, " sbi_scratch = %x\n", SbiScratch));
DEBUG((DEBUG_INFO, " sbi_platform = %x\n", SbiPlatform));
DEBUG((DEBUG_INFO, " FirmwareContext = %x\n", FirmwareContext));
@@ -793,7 +835,7 @@ VOID EFIAPI SecCoreStartUpWithStack(
sbi_init(Scratch);
}
-void OpensbiDebugPrint (char *debugstr, ...)
+VOID OpensbiDebugPrint (CHAR8 *debugstr, ...)
{
VA_LIST Marker;
diff --git a/Platform/RISC-V/PlatformPkg/Universal/Sec/Riscv64/SecEntry.S b/Platform/RISC-V/PlatformPkg/Universal/Sec/Riscv64/SecEntry.S
index f0c3dff0d9..96087738a3 100644
--- a/Platform/RISC-V/PlatformPkg/Universal/Sec/Riscv64/SecEntry.S
+++ b/Platform/RISC-V/PlatformPkg/Universal/Sec/Riscv64/SecEntry.S
@@ -18,6 +18,12 @@
#include <SecMain.h>
+.macro MOV_3R __d0, __s0, __d1, __s1, __d2, __s2
+ add \__d0, \__s0, zero
+ add \__d1, \__s1, zero
+ add \__d2, \__s2, zero
+.endm
+
.text
.align 3
@@ -90,7 +96,11 @@ _scratch_init:
la a4, _hartid_to_scratch
sd a4, SBI_SCRATCH_HARTID_TO_SCRATCH_OFFSET(tp) /* Save _hartid_to_scratch function in scratch buffer*/
sd zero, SBI_SCRATCH_TMP0_OFFSET(tp)
-
+ /* Store trap-exit function address in scratch space */
+ lla a4, _trap_exit
+ sd a4, SBI_SCRATCH_TRAP_EXIT_OFFSET(tp)
+ /* Clear tmp0 in scratch space */
+ sd zero, SBI_SCRATCH_TMP0_OFFSET(tp)
#ifdef FW_OPTIONS
li a4, FW_OPTIONS
sd a4, SBI_SCRATCH_OPTIONS_OFFSET(tp)
@@ -322,160 +332,174 @@ _uninitialized_hart_wait:
wfi
j _uninitialized_hart_wait
- .align 3
- .section .entry, "ax", %progbits
- .align 3
- .globl _trap_handler
-_trap_handler:
-
+.macro TRAP_SAVE_AND_SETUP_SP_T0
/* Swap TP and MSCRATCH */
- csrrw tp, CSR_MSCRATCH, tp
+ csrrw tp, CSR_MSCRATCH, tp
/* Save T0 in scratch space */
- REG_S t0, SBI_SCRATCH_TMP0_OFFSET(tp)
+ REG_S t0, SBI_SCRATCH_TMP0_OFFSET(tp)
- /* Check which mode we came from */
- csrr t0, CSR_MSTATUS
- srl t0, t0, MSTATUS_MPP_SHIFT
- and t0, t0, PRV_M
- xori t0, t0, PRV_M
- beq t0, zero, _trap_handler_m_mode
-
- /* We came from S-mode or U-mode */
-_trap_handler_s_mode:
- /* Set T0 to original SP */
- add t0, sp, zero
-
- /* Setup exception stack */
- add sp, tp, -(SBI_TRAP_REGS_SIZE)
-
- /* Jump to code common for all modes */
- j _trap_handler_all_mode
-
- /* We came from M-mode */
-_trap_handler_m_mode:
- /* Set T0 to original SP */
- add t0, sp, zero
-
- /* Re-use current SP as exception stack */
- add sp, sp, -(SBI_TRAP_REGS_SIZE)
-
-_trap_handler_all_mode:
- /* Save original SP (from T0) on stack */
- REG_S t0, SBI_TRAP_REGS_OFFSET(sp)(sp)
+ /*
+ * Set T0 to appropriate exception stack
+ *
+ * Came_From_M_Mode = ((MSTATUS.MPP < PRV_M) ? 1 : 0) - 1;
+ * Exception_Stack = TP ^ (Came_From_M_Mode & (SP ^ TP))
+ *
+ * Came_From_M_Mode = 0 ==> Exception_Stack = TP
+ * Came_From_M_Mode = -1 ==> Exception_Stack = SP
+ */
+ csrr t0, CSR_MSTATUS
+ srl t0, t0, MSTATUS_MPP_SHIFT
+ and t0, t0, PRV_M
+ slti t0, t0, PRV_M
+ add t0, t0, -1
+ xor sp, sp, tp
+ and t0, t0, sp
+ xor sp, sp, tp
+ xor t0, tp, t0
+
+ /* Save original SP on exception stack */
+ REG_S sp, (SBI_TRAP_REGS_OFFSET(sp) - SBI_TRAP_REGS_SIZE)(t0)
+
+ /* Set SP to exception stack and make room for trap registers */
+ add sp, t0, -(SBI_TRAP_REGS_SIZE)
/* Restore T0 from scratch space */
- REG_L t0, SBI_SCRATCH_TMP0_OFFSET(tp)
+ REG_L t0, SBI_SCRATCH_TMP0_OFFSET(tp)
/* Save T0 on stack */
- REG_S t0, SBI_TRAP_REGS_OFFSET(t0)(sp)
+ REG_S t0, SBI_TRAP_REGS_OFFSET(t0)(sp)
/* Swap TP and MSCRATCH */
- csrrw tp, CSR_MSCRATCH, tp
+ csrrw tp, CSR_MSCRATCH, tp
+.endm
+.macro TRAP_SAVE_MEPC_MSTATUS have_mstatush
/* Save MEPC and MSTATUS CSRs */
- csrr t0, CSR_MEPC
- REG_S t0, SBI_TRAP_REGS_OFFSET(mepc)(sp)
- csrr t0, CSR_MSTATUS
- REG_S t0, SBI_TRAP_REGS_OFFSET(mstatus)(sp)
- REG_S zero, SBI_TRAP_REGS_OFFSET(mstatusH)(sp)
-#if __riscv_xlen == 32
- csrr t0, CSR_MISA
- srli t0, t0, ('H' - 'A')
- andi t0, t0, 0x1
- beq t0, zero, _skip_mstatush_save
- csrr t0, CSR_MSTATUSH
- REG_S t0, SBI_TRAP_REGS_OFFSET(mstatusH)(sp)
-_skip_mstatush_save:
-#endif
+ csrr t0, CSR_MEPC
+ REG_S t0, SBI_TRAP_REGS_OFFSET(mepc)(sp)
+ csrr t0, CSR_MSTATUS
+ REG_S t0, SBI_TRAP_REGS_OFFSET(mstatus)(sp)
+.if \have_mstatush
+ csrr t0, CSR_MSTATUSH
+ REG_S t0, SBI_TRAP_REGS_OFFSET(mstatusH)(sp)
+.else
+ REG_S zero, SBI_TRAP_REGS_OFFSET(mstatusH)(sp)
+.endif
+.endm
+
+.macro TRAP_SAVE_GENERAL_REGS_EXCEPT_SP_T0
+ /* Save all general regisers except SP and T0 */
+ REG_S zero, SBI_TRAP_REGS_OFFSET(zero)(sp)
+ REG_S ra, SBI_TRAP_REGS_OFFSET(ra)(sp)
+ REG_S gp, SBI_TRAP_REGS_OFFSET(gp)(sp)
+ REG_S tp, SBI_TRAP_REGS_OFFSET(tp)(sp)
+ REG_S t1, SBI_TRAP_REGS_OFFSET(t1)(sp)
+ REG_S t2, SBI_TRAP_REGS_OFFSET(t2)(sp)
+ REG_S s0, SBI_TRAP_REGS_OFFSET(s0)(sp)
+ REG_S s1, SBI_TRAP_REGS_OFFSET(s1)(sp)
+ REG_S a0, SBI_TRAP_REGS_OFFSET(a0)(sp)
+ REG_S a1, SBI_TRAP_REGS_OFFSET(a1)(sp)
+ REG_S a2, SBI_TRAP_REGS_OFFSET(a2)(sp)
+ REG_S a3, SBI_TRAP_REGS_OFFSET(a3)(sp)
+ REG_S a4, SBI_TRAP_REGS_OFFSET(a4)(sp)
+ REG_S a5, SBI_TRAP_REGS_OFFSET(a5)(sp)
+ REG_S a6, SBI_TRAP_REGS_OFFSET(a6)(sp)
+ REG_S a7, SBI_TRAP_REGS_OFFSET(a7)(sp)
+ REG_S s2, SBI_TRAP_REGS_OFFSET(s2)(sp)
+ REG_S s3, SBI_TRAP_REGS_OFFSET(s3)(sp)
+ REG_S s4, SBI_TRAP_REGS_OFFSET(s4)(sp)
+ REG_S s5, SBI_TRAP_REGS_OFFSET(s5)(sp)
+ REG_S s6, SBI_TRAP_REGS_OFFSET(s6)(sp)
+ REG_S s7, SBI_TRAP_REGS_OFFSET(s7)(sp)
+ REG_S s8, SBI_TRAP_REGS_OFFSET(s8)(sp)
+ REG_S s9, SBI_TRAP_REGS_OFFSET(s9)(sp)
+ REG_S s10, SBI_TRAP_REGS_OFFSET(s10)(sp)
+ REG_S s11, SBI_TRAP_REGS_OFFSET(s11)(sp)
+ REG_S t3, SBI_TRAP_REGS_OFFSET(t3)(sp)
+ REG_S t4, SBI_TRAP_REGS_OFFSET(t4)(sp)
+ REG_S t5, SBI_TRAP_REGS_OFFSET(t5)(sp)
+ REG_S t6, SBI_TRAP_REGS_OFFSET(t6)(sp)
+.endm
+
+.macro TRAP_CALL_C_ROUTINE
+ /* Call C routine */
+ add a0, sp, zero
+ call sbi_trap_handler
+.endm
+
+.macro TRAP_RESTORE_GENERAL_REGS_EXCEPT_A0_T0
+ /* Restore all general regisers except A0 and T0 */
+ REG_L ra, SBI_TRAP_REGS_OFFSET(ra)(a0)
+ REG_L sp, SBI_TRAP_REGS_OFFSET(sp)(a0)
+ REG_L gp, SBI_TRAP_REGS_OFFSET(gp)(a0)
+ REG_L tp, SBI_TRAP_REGS_OFFSET(tp)(a0)
+ REG_L t1, SBI_TRAP_REGS_OFFSET(t1)(a0)
+ REG_L t2, SBI_TRAP_REGS_OFFSET(t2)(a0)
+ REG_L s0, SBI_TRAP_REGS_OFFSET(s0)(a0)
+ REG_L s1, SBI_TRAP_REGS_OFFSET(s1)(a0)
+ REG_L a1, SBI_TRAP_REGS_OFFSET(a1)(a0)
+ REG_L a2, SBI_TRAP_REGS_OFFSET(a2)(a0)
+ REG_L a3, SBI_TRAP_REGS_OFFSET(a3)(a0)
+ REG_L a4, SBI_TRAP_REGS_OFFSET(a4)(a0)
+ REG_L a5, SBI_TRAP_REGS_OFFSET(a5)(a0)
+ REG_L a6, SBI_TRAP_REGS_OFFSET(a6)(a0)
+ REG_L a7, SBI_TRAP_REGS_OFFSET(a7)(a0)
+ REG_L s2, SBI_TRAP_REGS_OFFSET(s2)(a0)
+ REG_L s3, SBI_TRAP_REGS_OFFSET(s3)(a0)
+ REG_L s4, SBI_TRAP_REGS_OFFSET(s4)(a0)
+ REG_L s5, SBI_TRAP_REGS_OFFSET(s5)(a0)
+ REG_L s6, SBI_TRAP_REGS_OFFSET(s6)(a0)
+ REG_L s7, SBI_TRAP_REGS_OFFSET(s7)(a0)
+ REG_L s8, SBI_TRAP_REGS_OFFSET(s8)(a0)
+ REG_L s9, SBI_TRAP_REGS_OFFSET(s9)(a0)
+ REG_L s10, SBI_TRAP_REGS_OFFSET(s10)(a0)
+ REG_L s11, SBI_TRAP_REGS_OFFSET(s11)(a0)
+ REG_L t3, SBI_TRAP_REGS_OFFSET(t3)(a0)
+ REG_L t4, SBI_TRAP_REGS_OFFSET(t4)(a0)
+ REG_L t5, SBI_TRAP_REGS_OFFSET(t5)(a0)
+ REG_L t6, SBI_TRAP_REGS_OFFSET(t6)(a0)
+.endm
+
+.macro TRAP_RESTORE_MEPC_MSTATUS have_mstatush
+ /* Restore MEPC and MSTATUS CSRs */
+ REG_L t0, SBI_TRAP_REGS_OFFSET(mepc)(a0)
+ csrw CSR_MEPC, t0
+ REG_L t0, SBI_TRAP_REGS_OFFSET(mstatus)(a0)
+ csrw CSR_MSTATUS, t0
+.if \have_mstatush
+ REG_L t0, SBI_TRAP_REGS_OFFSET(mstatusH)(a0)
+ csrw CSR_MSTATUSH, t0
+.endif
+.endm
+
+.macro TRAP_RESTORE_A0_T0
+ /* Restore T0 */
+ REG_L t0, SBI_TRAP_REGS_OFFSET(t0)(a0)
- /* Save all general registers except SP and T0 */
- REG_S zero, SBI_TRAP_REGS_OFFSET(zero)(sp)
- REG_S ra, SBI_TRAP_REGS_OFFSET(ra)(sp)
- REG_S gp, SBI_TRAP_REGS_OFFSET(gp)(sp)
- REG_S tp, SBI_TRAP_REGS_OFFSET(tp)(sp)
- REG_S t1, SBI_TRAP_REGS_OFFSET(t1)(sp)
- REG_S t2, SBI_TRAP_REGS_OFFSET(t2)(sp)
- REG_S s0, SBI_TRAP_REGS_OFFSET(s0)(sp)
- REG_S s1, SBI_TRAP_REGS_OFFSET(s1)(sp)
- REG_S a0, SBI_TRAP_REGS_OFFSET(a0)(sp)
- REG_S a1, SBI_TRAP_REGS_OFFSET(a1)(sp)
- REG_S a2, SBI_TRAP_REGS_OFFSET(a2)(sp)
- REG_S a3, SBI_TRAP_REGS_OFFSET(a3)(sp)
- REG_S a4, SBI_TRAP_REGS_OFFSET(a4)(sp)
- REG_S a5, SBI_TRAP_REGS_OFFSET(a5)(sp)
- REG_S a6, SBI_TRAP_REGS_OFFSET(a6)(sp)
- REG_S a7, SBI_TRAP_REGS_OFFSET(a7)(sp)
- REG_S s2, SBI_TRAP_REGS_OFFSET(s2)(sp)
- REG_S s3, SBI_TRAP_REGS_OFFSET(s3)(sp)
- REG_S s4, SBI_TRAP_REGS_OFFSET(s4)(sp)
- REG_S s5, SBI_TRAP_REGS_OFFSET(s5)(sp)
- REG_S s6, SBI_TRAP_REGS_OFFSET(s6)(sp)
- REG_S s7, SBI_TRAP_REGS_OFFSET(s7)(sp)
- REG_S s8, SBI_TRAP_REGS_OFFSET(s8)(sp)
- REG_S s9, SBI_TRAP_REGS_OFFSET(s9)(sp)
- REG_S s10, SBI_TRAP_REGS_OFFSET(s10)(sp)
- REG_S s11, SBI_TRAP_REGS_OFFSET(s11)(sp)
- REG_S t3, SBI_TRAP_REGS_OFFSET(t3)(sp)
- REG_S t4, SBI_TRAP_REGS_OFFSET(t4)(sp)
- REG_S t5, SBI_TRAP_REGS_OFFSET(t5)(sp)
- REG_S t6, SBI_TRAP_REGS_OFFSET(t6)(sp)
+ /* Restore A0 */
+ REG_L a0, SBI_TRAP_REGS_OFFSET(a0)(a0)
+.endm
- /* Call C routine */
- add a0, sp, zero
- call sbi_trap_handler
-
- /* Restore all general registers except SP and T0 */
- REG_L ra, SBI_TRAP_REGS_OFFSET(ra)(sp)
- REG_L gp, SBI_TRAP_REGS_OFFSET(gp)(sp)
- REG_L tp, SBI_TRAP_REGS_OFFSET(tp)(sp)
- REG_L t1, SBI_TRAP_REGS_OFFSET(t1)(sp)
- REG_L t2, SBI_TRAP_REGS_OFFSET(t2)(sp)
- REG_L s0, SBI_TRAP_REGS_OFFSET(s0)(sp)
- REG_L s1, SBI_TRAP_REGS_OFFSET(s1)(sp)
- REG_L a0, SBI_TRAP_REGS_OFFSET(a0)(sp)
- REG_L a1, SBI_TRAP_REGS_OFFSET(a1)(sp)
- REG_L a2, SBI_TRAP_REGS_OFFSET(a2)(sp)
- REG_L a3, SBI_TRAP_REGS_OFFSET(a3)(sp)
- REG_L a4, SBI_TRAP_REGS_OFFSET(a4)(sp)
- REG_L a5, SBI_TRAP_REGS_OFFSET(a5)(sp)
- REG_L a6, SBI_TRAP_REGS_OFFSET(a6)(sp)
- REG_L a7, SBI_TRAP_REGS_OFFSET(a7)(sp)
- REG_L s2, SBI_TRAP_REGS_OFFSET(s2)(sp)
- REG_L s3, SBI_TRAP_REGS_OFFSET(s3)(sp)
- REG_L s4, SBI_TRAP_REGS_OFFSET(s4)(sp)
- REG_L s5, SBI_TRAP_REGS_OFFSET(s5)(sp)
- REG_L s6, SBI_TRAP_REGS_OFFSET(s6)(sp)
- REG_L s7, SBI_TRAP_REGS_OFFSET(s7)(sp)
- REG_L s8, SBI_TRAP_REGS_OFFSET(s8)(sp)
- REG_L s9, SBI_TRAP_REGS_OFFSET(s9)(sp)
- REG_L s10, SBI_TRAP_REGS_OFFSET(s10)(sp)
- REG_L s11, SBI_TRAP_REGS_OFFSET(s11)(sp)
- REG_L t3, SBI_TRAP_REGS_OFFSET(t3)(sp)
- REG_L t4, SBI_TRAP_REGS_OFFSET(t4)(sp)
- REG_L t5, SBI_TRAP_REGS_OFFSET(t5)(sp)
- REG_L t6, SBI_TRAP_REGS_OFFSET(t6)(sp)
+ .section .entry, "ax", %progbits
+ .align 3
+ .globl _trap_handler
+ .globl _trap_exit
+_trap_handler:
+ TRAP_SAVE_AND_SETUP_SP_T0
- /* Restore MEPC and MSTATUS CSRs */
- REG_L t0, SBI_TRAP_REGS_OFFSET(mepc)(sp)
- csrw CSR_MEPC, t0
- REG_L t0, SBI_TRAP_REGS_OFFSET(mstatus)(sp)
- csrw CSR_MSTATUS, t0
-#if __riscv_xlen == 32
- csrr t0, CSR_MISA
- srli t0, t0, ('H' - 'A')
- andi t0, t0, 0x1
- beq t0, zero, _skip_mstatush_restore
- REG_L t0, SBI_TRAP_REGS_OFFSET(mstatusH)(sp)
- csrw CSR_MSTATUSH, t0
-_skip_mstatush_restore:
-#endif
+ TRAP_SAVE_MEPC_MSTATUS 0
- /* Restore T0 */
- REG_L t0, SBI_TRAP_REGS_OFFSET(t0)(sp)
+ TRAP_SAVE_GENERAL_REGS_EXCEPT_SP_T0
+
+ TRAP_CALL_C_ROUTINE
+
+_trap_exit:
+ TRAP_RESTORE_GENERAL_REGS_EXCEPT_A0_T0
+
+ TRAP_RESTORE_MEPC_MSTATUS 0
- /* Restore SP */
- REG_L sp, SBI_TRAP_REGS_OFFSET(sp)(sp)
+ TRAP_RESTORE_A0_T0
mret
--
2.31.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH 57/79] PlatformPkg/Sec: Separate EDK2 Opensbi platform hook.
2022-01-08 7:24 [PATCH 42/79] RISC-V: Use RISC-V PeiCoreEntryPoint library Abner Chang
` (13 preceding siblings ...)
2022-01-08 7:24 ` [PATCH 56/79] RISC-V/PlatformPkg: Updates for the latest OpenSBI Abner Chang
@ 2022-01-08 7:24 ` Abner Chang
2022-01-08 7:24 ` [PATCH 58/79] RISC-V/PlatformPkg: Determine hart number from DTB Abner Chang
` (3 subsequent siblings)
18 siblings, 0 replies; 21+ messages in thread
From: Abner Chang @ 2022-01-08 7:24 UTC (permalink / raw)
To: devel; +Cc: abner.chang
(This is migrated from edk2-platforms:Platform)
Separate EDK2 Opensbi platform operations hooks from
Secmain as an individual library which can be override
by OEM platform.
Cc: Sunil V L <sunilvl@ventanamicro.com>
Cc: Daniel Schaefer <daniel.schaefer@hpe.com>
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Reviewed-by: Daniel Schaefer <daniel.schaefer@hpe.com>
Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
---
.../RISC-V/PlatformPkg/RiscVPlatformPkg.dec | 1 +
.../RISC-V/PlatformPkg/RiscVPlatformPkg.dsc | 4 +-
.../Edk2OpensbiPlatformWrapperLib.inf | 44 ++
.../PlatformPkg/Universal/Sec/SecMain.inf | 10 +-
.../Library/Edk2OpensbiPlatformWrapperLib.h | 16 +
.../PlatformPkg/Universal/Sec/SecMain.h | 1 +
.../Edk2OpensbiPlatformWrapperLib.c | 530 ++++++++++++++++++
.../Universal/Sec/Edk2OpenSbiPlatform.c | 277 ---------
.../PlatformPkg/Universal/Sec/SecMain.c | 141 -----
9 files changed, 598 insertions(+), 426 deletions(-)
create mode 100644 Platform/RISC-V/PlatformPkg/Library/Edk2OpensbiPlatformWrapperLib/Edk2OpensbiPlatformWrapperLib.inf
create mode 100644 Platform/RISC-V/PlatformPkg/Include/Library/Edk2OpensbiPlatformWrapperLib.h
create mode 100644 Platform/RISC-V/PlatformPkg/Library/Edk2OpensbiPlatformWrapperLib/Edk2OpensbiPlatformWrapperLib.c
delete mode 100644 Platform/RISC-V/PlatformPkg/Universal/Sec/Edk2OpenSbiPlatform.c
diff --git a/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec b/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec
index 947ae40e20..19206556ce 100644
--- a/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec
+++ b/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec
@@ -20,6 +20,7 @@
[LibraryClasses]
FirmwareContextProcessorSpecificLib|Include/Library/FirmwareContextProcessorSpecificLib.h
RiscVPlatformTempMemoryInitLib|Include/Library/RiscVPlatformTempMemoryInitLib.h
+ Edk2OpensbiPlatformiLib|Include/Library/Edk2OpensbiPlatformiWrapperLib.h
[Guids]
gUefiRiscVPlatformPkgTokenSpaceGuid = {0x6A67AF99, 0x4592, 0x40F8, { 0xB6, 0xBE, 0x62, 0xBC, 0xA1, 0x0D, 0xA1, 0xEC}}
diff --git a/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dsc b/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dsc
index bbb043f9ed..47a0fc4494 100644
--- a/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dsc
+++ b/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dsc
@@ -43,7 +43,6 @@
RiscVOpensbiPlatformLib|Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/OpensbiPlatformLib.inf
RiscVCpuLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVCpuLib/RiscVCpuLib.inf
RiscVEdk2SbiLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVEdk2SbiLib/RiscVEdk2SbiLib.inf
- RiscVOpensbiLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVOpensbiLib/RiscVOpensbiLib.inf
BaseLib|MdePkg/Library/BaseLib/BaseLib.inf
BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
DebugAgentLib|MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLibNull.inf
@@ -72,6 +71,8 @@
[LibraryClasses.common.SEC]
ExtractGuidedSectionLib|MdePkg/Library/BaseExtractGuidedSectionLib/BaseExtractGuidedSectionLib.inf
+ RiscVOpensbiLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVOpensbiLib/RiscVOpensbiLib.inf
+ Edk2OpensbiPlatformWrapperLib|Platform/RISC-V/PlatformPkg/Library/Edk2OpensbiPlatformWrapperLib/Edk2OpensbiPlatformWrapperLib.inf
RiscVSpecialPlatformLib|Platform/RISC-V/PlatformPkg/Library/RiscVSpecialPlatformLibNull/RiscVSpecialPlatformLibNull.inf
[LibraryClasses.common.DXE_DRIVER]
@@ -87,6 +88,7 @@
Platform/RISC-V/PlatformPkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.inf
Platform/RISC-V/PlatformPkg/Library/PlatformSecPpiLibNull/PlatformSecPpiLibNull.inf
Platform/RISC-V/PlatformPkg/Library/RiscVSpecialPlatformLibNull/RiscVSpecialPlatformLibNull.inf
+ Platform/RISC-V/PlatformPkg/Library/Edk2OpensbiPlatformWrapperLib/Edk2OpensbiPlatformWrapperLib.inf
[Components.common.SEC]
Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf
diff --git a/Platform/RISC-V/PlatformPkg/Library/Edk2OpensbiPlatformWrapperLib/Edk2OpensbiPlatformWrapperLib.inf b/Platform/RISC-V/PlatformPkg/Library/Edk2OpensbiPlatformWrapperLib/Edk2OpensbiPlatformWrapperLib.inf
new file mode 100644
index 0000000000..8c268c556d
--- /dev/null
+++ b/Platform/RISC-V/PlatformPkg/Library/Edk2OpensbiPlatformWrapperLib/Edk2OpensbiPlatformWrapperLib.inf
@@ -0,0 +1,44 @@
+## @file
+# EDK2 OpenSBI generic platform wrapper library
+#
+# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001b
+ BASE_NAME = Edk2OpensbiPlatformWrapperLib
+ FILE_GUID = 364395A3-21BA-400C-96F7-5D9817F6FEE5
+ MODULE_TYPE = SEC
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = Edk2OpensbiPlatformWrapperLib
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = RISCV64
+#
+
+[Sources]
+ Edk2OpensbiPlatformWrapperLib.c
+
+[Packages]
+ MdeModulePkg/MdeModulePkg.dec
+ MdePkg/MdePkg.dec
+ Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec
+ Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec
+
+[Pcd]
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFirmwareDomainBaseAddress
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFirmwareDomainSize
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFirmwareRegionBaseAddress
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFirmwareRegionSize
+
+[LibraryClasses]
+ BaseLib
+ DebugLib
+ DebugAgentLib
+ PcdLib
+ PrintLib
diff --git a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf
index dd5f01ab4d..ceb6d25222 100644
--- a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf
+++ b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf
@@ -23,7 +23,6 @@
[Sources]
SecMain.c
- Edk2OpenSbiPlatform.c
[Sources.RISCV64]
Riscv64/SecEntry.S
@@ -40,6 +39,7 @@
BaseMemoryLib
DebugAgentLib
DebugLib
+ Edk2OpensbiPlatformWrapperLib
ExtractGuidedSectionLib
FdtLib
IoLib
@@ -62,14 +62,10 @@
[Pcd]
gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootHartId
gUefiRiscVPlatformPkgTokenSpaceGuid.PcdHartCount
- gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootableHartNumber
- gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootableHartIndexToId
gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRootFirmwareDomainBaseAddress
gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRootFirmwareDomainSize
- gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFirmwareDomainBaseAddress
- gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFirmwareDomainSize
- gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFirmwareRegionBaseAddress
- gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFirmwareRegionSize
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootableHartNumber
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootableHartIndexToId
gUefiRiscVPlatformPkgTokenSpaceGuid.PcdOpenSbiStackSize
gUefiRiscVPlatformPkgTokenSpaceGuid.PcdScratchRamBase
gUefiRiscVPlatformPkgTokenSpaceGuid.PcdScratchRamSize
diff --git a/Platform/RISC-V/PlatformPkg/Include/Library/Edk2OpensbiPlatformWrapperLib.h b/Platform/RISC-V/PlatformPkg/Include/Library/Edk2OpensbiPlatformWrapperLib.h
new file mode 100644
index 0000000000..4da0a64a8c
--- /dev/null
+++ b/Platform/RISC-V/PlatformPkg/Include/Library/Edk2OpensbiPlatformWrapperLib.h
@@ -0,0 +1,16 @@
+/** @file
+ Definition of EDK2 OpenSBI generic platform wrapper library
+
+ Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef EDK2_OPENSBI_PLATFORM_WRAPPER_LIB_
+#define EDK2_OPENSBI_PLATFORM_WRAPPER_LIB_
+
+#include <sbi/sbi_platform.h>
+
+extern struct sbi_platform_operations Edk2OpensbiPlatformOps;
+
+#endif
diff --git a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.h b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.h
index 496799efc0..6188778fc4 100644
--- a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.h
+++ b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.h
@@ -16,6 +16,7 @@
#include <Library/BaseMemoryLib.h>
#include <Library/DebugAgentLib.h>
#include <Library/DebugLib.h>
+#include <Library/Edk2OpensbiPlatformWrapperLib.h>
#include <Library/ExtractGuidedSectionLib.h>
#include <Library/IoLib.h>
#include <Library/HobLib.h>
diff --git a/Platform/RISC-V/PlatformPkg/Library/Edk2OpensbiPlatformWrapperLib/Edk2OpensbiPlatformWrapperLib.c b/Platform/RISC-V/PlatformPkg/Library/Edk2OpensbiPlatformWrapperLib/Edk2OpensbiPlatformWrapperLib.c
new file mode 100644
index 0000000000..6c5c1a789f
--- /dev/null
+++ b/Platform/RISC-V/PlatformPkg/Library/Edk2OpensbiPlatformWrapperLib/Edk2OpensbiPlatformWrapperLib.c
@@ -0,0 +1,530 @@
+/*
+ EDK2 OpenSBI generic platform wrapper library
+
+ Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ */
+
+#include <Library/DebugAgentLib.h>
+#include <Library/DebugLib.h>
+#include <IndustryStandard/RiscVOpensbi.h>
+#include <sbi/riscv_asm.h>
+#include <sbi/sbi_platform.h>
+#include <sbi/sbi_scratch.h>
+#include <sbi/sbi_domain.h>
+#include <sbi/sbi_math.h>
+
+extern struct sbi_platform_operations platform_ops;
+extern atomic_t BootHartDone;
+
+/**
+ Add firmware memory domain.
+
+ @retval OpenSBI error code.
+
+**/
+INT32
+SecSetEdk2FwMemoryRegions (
+ VOID
+ )
+{
+ INT32 Ret;
+ struct sbi_domain_memregion fw_memregs;
+
+ Ret = 0;
+
+ //
+ // EDK2 PEI domain memory region
+ //
+ fw_memregs.order = log2roundup(FixedPcdGet32(PcdFirmwareDomainSize));
+ fw_memregs.base = FixedPcdGet32(PcdFirmwareDomainBaseAddress);
+ fw_memregs.flags = SBI_DOMAIN_MEMREGION_EXECUTABLE | SBI_DOMAIN_MEMREGION_READABLE;
+ Ret = sbi_domain_root_add_memregion ((CONST struct sbi_domain_memregion *)&fw_memregs);
+ if (Ret != 0) {
+ DEBUG ((DEBUG_ERROR, "%a: Add firmware regiosn of FW Domain fail\n", __FUNCTION__));
+ }
+
+ //
+ // EDK2 EFI Variable domain memory region
+ //
+ fw_memregs.order = log2roundup(FixedPcdGet32(PcdVariableFirmwareRegionSize));
+ fw_memregs.base = FixedPcdGet32(PcdVariableFirmwareRegionBaseAddress);
+ fw_memregs.flags = SBI_DOMAIN_MEMREGION_READABLE | SBI_DOMAIN_MEMREGION_WRITEABLE;
+ Ret = sbi_domain_root_add_memregion ((CONST struct sbi_domain_memregion *)&fw_memregs);
+ if (Ret != 0) {
+ DEBUG ((DEBUG_ERROR, "%a: Add firmware regiosn of variable FW Domain fail\n", __FUNCTION__));
+ }
+ return Ret;
+}
+/**
+ OpenSBI platform early init hook.
+
+ @param[in] ColdBoot Is cold boot path or warm boot path.
+ @retval OpenSBI error code.
+
+**/
+INT32
+SecPostOpenSbiPlatformEarlylInit(
+ IN BOOLEAN ColdBoot
+ )
+{
+ UINT32 HartId;
+
+ if (!ColdBoot) {
+ HartId = current_hartid();
+ DEBUG ((DEBUG_INFO, "%a: Non boot hart %d.\n", __FUNCTION__, HartId));
+ return 0;
+ }
+ //
+ // Setup firmware memory region.
+ //
+ if (SecSetEdk2FwMemoryRegions () != 0) {
+ ASSERT (FALSE);
+ }
+
+ //
+ // Boot HART is already in the process of OpenSBI initialization.
+ // We can let other HART to keep booting.
+ //
+ DEBUG ((DEBUG_INFO, "%a: Set boot hart done.\n", __FUNCTION__));
+ atomic_write (&BootHartDone, (UINT64)TRUE);
+ return 0;
+}
+
+/**
+ OpenSBI platform final init hook.
+ We restore the next_arg1 to the pointer of EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT.
+
+ @param[in] ColdBoot Is cold boot path or warm boot path.
+ @retval OpenSBI error code.
+
+**/
+INT32
+SecPostOpenSbiPlatformFinalInit (
+ IN BOOLEAN ColdBoot
+ )
+{
+ UINT32 HartId;
+ struct sbi_scratch *SbiScratch;
+ struct sbi_scratch *ScratchSpace;
+ struct sbi_platform *SbiPlatform;
+ EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *FirmwareContext;
+
+ if (!ColdBoot) {
+ HartId = current_hartid();
+ DEBUG ((DEBUG_INFO, "%a: Non boot hart %d.\n", __FUNCTION__, HartId));
+ return 0;
+ }
+
+ DEBUG((DEBUG_INFO, "%a: Entry, preparing to jump to PEI Core\n\n", __FUNCTION__));
+
+ SbiScratch = sbi_scratch_thishart_ptr();
+ SbiPlatform = (struct sbi_platform *)sbi_platform_ptr(SbiScratch);
+ FirmwareContext = (EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *)SbiPlatform->firmware_context;
+
+ //
+ // Print out scratch address of each hart
+ //
+ DEBUG ((DEBUG_INFO, "%a: OpenSBI scratch address for each hart:\n", __FUNCTION__));
+ for (HartId = 0; HartId < SBI_HARTMASK_MAX_BITS; HartId ++) {
+ if (sbi_platform_hart_invalid(SbiPlatform, HartId)) {
+ continue;
+ }
+ ScratchSpace = sbi_hartid_to_scratch (HartId);
+ if(ScratchSpace != NULL) {
+ DEBUG((DEBUG_INFO, " Hart %d: 0x%x\n", HartId, ScratchSpace));
+ } else {
+ DEBUG((DEBUG_INFO, " Hart %d not initialized yet\n", HartId));
+ }
+ }
+
+ //
+ // Set firmware context Hart-specific pointer
+ //
+ for (HartId = 0; HartId < SBI_HARTMASK_MAX_BITS; HartId ++) {
+ if (sbi_platform_hart_invalid(SbiPlatform, HartId)) {
+ continue;
+ }
+ ScratchSpace = sbi_hartid_to_scratch (HartId);
+ if (ScratchSpace != NULL) {
+ FirmwareContext->HartSpecific[HartId] =
+ (EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC *)((UINT8 *)ScratchSpace - FIRMWARE_CONTEXT_HART_SPECIFIC_SIZE);
+ DEBUG ((DEBUG_INFO, "%a: OpenSBI Hart %d Firmware Context Hart-specific at address: 0x%x\n",
+ __FUNCTION__,
+ HartId,
+ FirmwareContext->HartSpecific [HartId]
+ ));
+ }
+ }
+
+ DEBUG((DEBUG_INFO, "%a: Will jump to PEI Core in OpenSBI with \n", __FUNCTION__));
+ DEBUG((DEBUG_INFO, " sbi_scratch = %x\n", SbiScratch));
+ DEBUG((DEBUG_INFO, " sbi_platform = %x\n", SbiPlatform));
+ DEBUG((DEBUG_INFO, " FirmwareContext = %x\n", FirmwareContext));
+ SbiScratch->next_arg1 = (unsigned long)FirmwareContext;
+
+ return 0;
+}
+/**
+ OpenSBI platform early init hook.
+
+ @param[in] ColdBoot Is cold boot path or warm boot path.
+ @retval OpenSBI error code.
+
+**/
+INT32
+Edk2OpensbiPlatformEarlyInit (
+ IN BOOLEAN ColdBoot
+ )
+{
+ INT32 ReturnCode;
+
+ DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));
+
+ if (platform_ops.early_init) {
+ ReturnCode = platform_ops.early_init (ColdBoot);
+ if (ReturnCode) {
+ return ReturnCode;
+ }
+ }
+ if (ColdBoot == TRUE) {
+ return SecPostOpenSbiPlatformEarlylInit(ColdBoot);
+ }
+ return 0;
+}
+/**
+ OpenSBI platform final init hook.
+
+ @param[in] ColdBoot Is cold boot path or warm boot path.
+ @retval OpenSBI error code.
+
+**/
+INT32
+Edk2OpensbiPlatformFinalInit (
+ IN BOOLEAN ColdBoot
+ )
+{
+ INT32 ReturnCode;
+
+ DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));
+
+ if (platform_ops.final_init) {
+ ReturnCode = platform_ops.final_init (ColdBoot);
+ if (ReturnCode) {
+ return ReturnCode;
+ }
+ }
+ if (ColdBoot == TRUE) {
+ return SecPostOpenSbiPlatformFinalInit(ColdBoot);
+ }
+ return 0;
+}
+/**
+ OpenSBI platform early exit hook.
+
+**/
+VOID
+Edk2OpensbiPlatformEarlyExit (
+ VOID
+)
+{
+ DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));
+
+ if (platform_ops.early_exit) {
+ return platform_ops.early_exit ();
+ }
+}
+
+/**
+ Platform final exit hook
+
+ **/
+VOID
+Edk2OpensbiPlatformFinalExit (
+ VOID
+ )
+{
+ DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));
+
+ if (platform_ops.early_exit) {
+ return platform_ops.early_exit ();
+ }
+}
+
+/**
+ For platforms that do not implement misa, non-standard
+ methods are needed to determine cpu extension.
+
+ @param[in] Extension Check ISA extension.
+ @retval OpenSBI error code.
+
+**/
+INT32
+Edk2OpensbiPlatforMMISACheckExtension (
+ IN CHAR8 Extension
+ )
+{
+ if (platform_ops.misa_check_extension) {
+ return platform_ops.misa_check_extension (Extension);
+ }
+ return 0;
+}
+
+/**
+ Get the XLEN.
+
+ @retval Return the XLEN
+
+**/
+INT32
+Edk2OpensbiPlatforMMISAGetXLEN (
+ VOID
+)
+{
+ if (platform_ops.misa_get_xlen) {
+ return platform_ops.misa_get_xlen ();
+ }
+ return 0;
+}
+
+/**
+ Initialize (or populate) domains for the platform*
+
+ @retval OpenSBI error code.
+
+**/
+INT32
+Edk2OpensbiPlatformDomainsInit (
+ VOID
+)
+{
+ DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));
+
+ if (platform_ops.domains_init) {
+ return platform_ops.domains_init ();
+ }
+ return 0;
+}
+
+/**
+ Initialize the platform console
+
+ @retval OpenSBI error code.
+
+**/
+INT32
+Edk2OpensbiPlatformSerialInit (
+ VOID
+)
+{
+ DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));
+
+ if (platform_ops.console_init) {
+ return platform_ops.console_init ();
+ }
+ return 0;
+}
+
+/**
+ Initialize the platform interrupt controller for current HART
+
+ @param[in] ColdBoot Is cold boot path or warm boot path.
+ @retval OpenSBI error code.
+
+**/
+INT32
+Edk2OpensbiPlatformIrqchipInit (
+ IN BOOLEAN ColdBoot
+)
+{
+ DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));
+
+ if (platform_ops.irqchip_init) {
+ return platform_ops.irqchip_init (ColdBoot);
+ }
+ return 0;
+}
+
+/**
+ Exit the platform interrupt controller for current HART
+
+**/
+VOID
+Edk2OpensbiPlatformIrqchipExit (
+ VOID
+)
+{
+ DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));
+
+ if (platform_ops.irqchip_exit) {
+ return platform_ops.irqchip_exit ();
+ }
+}
+
+/**
+ Initialize IPI for current HART
+
+ @param[in] ColdBoot Is cold boot path or warm boot path.
+ @retval OpenSBI error code.
+
+**/
+INT32
+Edk2OpensbiPlatformIpiInit (
+ IN BOOLEAN ColdBoot
+)
+{
+ DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));
+
+ if (platform_ops.ipi_init) {
+ return platform_ops.ipi_init (ColdBoot);
+ }
+ return 0;
+}
+
+/**
+ Exit IPI for current HART
+
+**/
+VOID
+Edk2OpensbiPlatformIpiExit (
+ VOID
+)
+{
+ DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));
+
+ if (platform_ops.ipi_exit) {
+ return platform_ops.ipi_exit ();
+ }
+}
+
+/**
+ Get tlb flush limit value
+
+ @retval Cache flush limit value.
+
+**/
+UINT64
+Edk2OpensbiPlatformTlbrFlushLimit (
+ VOID
+)
+{
+ DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));
+
+ if (platform_ops.get_tlbr_flush_limit) {
+ return platform_ops.get_tlbr_flush_limit ();
+ }
+ return 0;
+}
+
+/**
+ Initialize platform timer for current HART
+
+ @param[in] ColdBoot Is cold boot path or warm boot path.
+ @retval OpenSBI error code.
+
+**/
+INT32
+Edk2OpensbiPlatformTimerInit (
+ IN BOOLEAN ColdBoot
+)
+{
+ DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));
+
+ if (platform_ops.timer_init) {
+ return platform_ops.timer_init (ColdBoot);
+ }
+ return 0;
+}
+
+/**
+ Exit platform timer for current HART
+
+**/
+VOID
+Edk2OpensbiPlatformTimerExit (
+ VOID
+)
+{
+ DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));
+
+ if (platform_ops.timer_exit) {
+ return platform_ops.timer_exit ();
+ }
+}
+
+/**
+ Check platform vendor SBI extension.
+
+ @param[in] ExtId Extension ID.
+ @retval OpenSBI error code.
+
+ **/
+INT32
+Edk2OpensbiPlatformVendorExtCheck (
+ IN long ExtId
+)
+{
+ DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));
+
+ if (platform_ops.vendor_ext_check) {
+ return platform_ops.vendor_ext_check (ExtId);
+ }
+ return 0;
+}
+
+/**
+ Platform specific SBI extension implementation provider
+
+ @param[in] ExtId SBI extension ID.
+ @param[in] FuncId Function ID.
+ @param[in] Regs The trap register.
+ @param[in] OutValue Value returned from SBI.
+ @param[in] OutTrap The trap infomation after calling to SBI.
+
+ @retval OpenSBI error code.
+
+**/
+INT32
+Edk2OpensbiPlatformVendorExtProvider (
+ IN long ExtId,
+ IN long FuncId,
+ IN CONST struct sbi_trap_regs *Regs,
+ IN unsigned long *OutValue,
+ IN struct sbi_trap_info *OutTrap
+)
+{
+ DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));
+
+ if (platform_ops.vendor_ext_provider) {
+ return platform_ops.vendor_ext_provider (
+ ExtId,
+ FuncId,
+ Regs,
+ OutValue,
+ OutTrap
+ );
+ }
+ return 0;
+}
+
+CONST struct sbi_platform_operations Edk2OpensbiPlatformOps = {
+ .early_init = Edk2OpensbiPlatformEarlyInit,
+ .final_init = Edk2OpensbiPlatformFinalInit,
+ .early_exit = Edk2OpensbiPlatformEarlyExit,
+ .final_exit = Edk2OpensbiPlatformFinalExit,
+ .misa_check_extension = Edk2OpensbiPlatforMMISACheckExtension,
+ .misa_get_xlen = Edk2OpensbiPlatforMMISAGetXLEN,
+ .domains_init = Edk2OpensbiPlatformDomainsInit,
+ .console_init = Edk2OpensbiPlatformSerialInit,
+ .irqchip_init = Edk2OpensbiPlatformIrqchipInit,
+ .irqchip_exit = Edk2OpensbiPlatformIrqchipExit,
+ .ipi_init = Edk2OpensbiPlatformIpiInit,
+ .ipi_exit = Edk2OpensbiPlatformIpiExit,
+ .get_tlbr_flush_limit = Edk2OpensbiPlatformTlbrFlushLimit,
+ .timer_init = Edk2OpensbiPlatformTimerInit,
+ .timer_exit = Edk2OpensbiPlatformTimerExit,
+ .vendor_ext_check = Edk2OpensbiPlatformVendorExtCheck,
+ .vendor_ext_provider = Edk2OpensbiPlatformVendorExtProvider,
+};
diff --git a/Platform/RISC-V/PlatformPkg/Universal/Sec/Edk2OpenSbiPlatform.c b/Platform/RISC-V/PlatformPkg/Universal/Sec/Edk2OpenSbiPlatform.c
deleted file mode 100644
index 779705489c..0000000000
--- a/Platform/RISC-V/PlatformPkg/Universal/Sec/Edk2OpenSbiPlatform.c
+++ /dev/null
@@ -1,277 +0,0 @@
-/*
- Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
-
- SPDX-License-Identifier: BSD-2-Clause-Patent
-
- */
-
-#include <Library/DebugAgentLib.h>
-#include <Library/DebugLib.h>
-
-#include <libfdt.h>
-#include <sbi/riscv_asm.h>
-#include <sbi/sbi_domain.h>
-#include <sbi/sbi_hartmask.h>
-#include <sbi/sbi_platform.h>
-#include <sbi/sbi_string.h>
-#include <sbi/sbi_math.h>
-#include <sbi_utils/fdt/fdt_domain.h>
-#include <sbi_utils/fdt/fdt_fixup.h>
-#include <sbi_utils/fdt/fdt_helper.h>
-#include <sbi_utils/irqchip/fdt_irqchip.h>
-#include <sbi_utils/serial/fdt_serial.h>
-#include <sbi_utils/timer/fdt_timer.h>
-#include <sbi_utils/ipi/fdt_ipi.h>
-#include <sbi_utils/reset/fdt_reset.h>
-
-#include "SecMain.h"
-
-extern struct sbi_platform_operations platform_ops;
-
-int Edk2OpensbiPlatformEarlyInit (
- BOOLEAN ColdBoot
- )
-{
- int ReturnCode;
-
- DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));
-
- if (platform_ops.early_init) {
- ReturnCode = platform_ops.early_init (ColdBoot);
- if (ReturnCode) {
- return ReturnCode;
- }
- }
- if (ColdBoot == TRUE) {
- return SecPostOpenSbiPlatformEarlylInit(ColdBoot);
- }
- return 0;
-}
-
-int Edk2OpensbiPlatformFinalInit (
- BOOLEAN ColdBoot
- )
-{
- int ReturnCode;
-
- DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));
-
- if (platform_ops.final_init) {
- ReturnCode = platform_ops.final_init (ColdBoot);
- if (ReturnCode) {
- return ReturnCode;
- }
- }
- if (ColdBoot == TRUE) {
- return SecPostOpenSbiPlatformFinalInit(ColdBoot);
- }
- return 0;
-}
-
-VOID Edk2OpensbiPlatformEarlyExit (
- VOID
- )
-{
- DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));
-
- if (platform_ops.early_exit) {
- return platform_ops.early_exit ();
- }
-}
-
-/** Platform final exit */
-VOID Edk2OpensbiPlatformFinalExit (
- VOID
- )
-{
- DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));
-
- if (platform_ops.early_exit) {
- return platform_ops.early_exit ();
- }
-}
-
-/**
- For platforms that do not implement misa, non-standard
- methods are needed to determine cpu extension.
-**/
-int Edk2OpensbiPlatforMMISACheckExtension (
- CHAR8 Extension
- )
-{
- if (platform_ops.misa_check_extension) {
- return platform_ops.misa_check_extension (Extension);
- }
- return 0;
-}
-
-/**
- For platforms that do not implement misa, non-standard
- methods are needed to get MXL field of misa.
-**/
-int Edk2OpensbiPlatforMMISAGetXLEN (VOID)
-{
- if (platform_ops.misa_get_xlen) {
- return platform_ops.misa_get_xlen ();
- }
- return 0;
-}
-
-/** Initialize (or populate) domains for the platform */
-int Edk2OpensbiPlatformDomainsInit (VOID)
-{
- DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));
-
- if (platform_ops.domains_init) {
- return platform_ops.domains_init ();
- }
- return 0;
-}
-
-/** Initialize the platform console */
-int Edk2OpensbiPlatformSerialInit (VOID)
-{
- DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));
-
- if (platform_ops.console_init) {
- return platform_ops.console_init ();
- }
- return 0;
-}
-
-/** Initialize the platform interrupt controller for current HART */
-int Edk2OpensbiPlatformIrqchipInit (
- BOOLEAN ColdBoot
- )
-{
- DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));
-
- if (platform_ops.irqchip_init) {
- return platform_ops.irqchip_init (ColdBoot);
- }
- return 0;
-}
-
-/** Exit the platform interrupt controller for current HART */
-VOID Edk2OpensbiPlatformIrqchipExit (VOID)
-{
- DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));
-
- if (platform_ops.irqchip_exit) {
- return platform_ops.irqchip_exit ();
- }
-}
-
-/** Initialize IPI for current HART */
-int Edk2OpensbiPlatformIpiInit (
- BOOLEAN ColdBoot
- )
-{
- DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));
-
- if (platform_ops.ipi_init) {
- return platform_ops.ipi_init (ColdBoot);
- }
- return 0;
-}
-
-/** Exit IPI for current HART */
-VOID Edk2OpensbiPlatformIpiExit (VOID)
-{
- DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));
-
- if (platform_ops.ipi_exit) {
- return platform_ops.ipi_exit ();
- }
-}
-
-/** Get tlb flush limit value **/
-UINT64 Edk2OpensbiPlatformTlbrFlushLimit (VOID)
-{
- DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));
-
- if (platform_ops.get_tlbr_flush_limit) {
- return platform_ops.get_tlbr_flush_limit ();
- }
- return 0;
-}
-
-/** Initialize platform timer for current HART */
-int Edk2OpensbiPlatformTimerInit (
- BOOLEAN ColdBoot
- )
-{
- DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));
-
- if (platform_ops.timer_init) {
- return platform_ops.timer_init (ColdBoot);
- }
- return 0;
-}
-
-/** Exit platform timer for current HART */
-VOID Edk2OpensbiPlatformTimerExit (VOID)
-{
- DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));
-
- if (platform_ops.timer_exit) {
- return platform_ops.timer_exit ();
- }
-}
-
-/** platform specific SBI extension implementation probe function */
-int Edk2OpensbiPlatformVendorExtCheck (
- long ExtId
- )
-{
- DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));
-
- if (platform_ops.vendor_ext_check) {
- return platform_ops.vendor_ext_check (ExtId);
- }
- return 0;
-}
-
-
-/** platform specific SBI extension implementation provider */
-int Edk2OpensbiPlatformVendorExtProvider (
- long ExtId,
- long FuncId,
- const struct sbi_trap_regs *Regs,
- unsigned long *OutValue,
- struct sbi_trap_info *OutTrap
- )
-{
- DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));
-
- if (platform_ops.vendor_ext_provider) {
- return platform_ops.vendor_ext_provider (
- ExtId,
- FuncId,
- Regs,
- OutValue,
- OutTrap
- );
- }
- return 0;
-}
-
-const struct sbi_platform_operations Edk2OpensbiPlatformOps = {
- .early_init = Edk2OpensbiPlatformEarlyInit,
- .final_init = Edk2OpensbiPlatformFinalInit,
- .early_exit = Edk2OpensbiPlatformEarlyExit,
- .final_exit = Edk2OpensbiPlatformFinalExit,
- .misa_check_extension = Edk2OpensbiPlatforMMISACheckExtension,
- .misa_get_xlen = Edk2OpensbiPlatforMMISAGetXLEN,
- .domains_init = Edk2OpensbiPlatformDomainsInit,
- .console_init = Edk2OpensbiPlatformSerialInit,
- .irqchip_init = Edk2OpensbiPlatformIrqchipInit,
- .irqchip_exit = Edk2OpensbiPlatformIrqchipExit,
- .ipi_init = Edk2OpensbiPlatformIpiInit,
- .ipi_exit = Edk2OpensbiPlatformIpiExit,
- .get_tlbr_flush_limit = Edk2OpensbiPlatformTlbrFlushLimit,
- .timer_init = Edk2OpensbiPlatformTimerInit,
- .timer_exit = Edk2OpensbiPlatformTimerExit,
- .vendor_ext_check = Edk2OpensbiPlatformVendorExtCheck,
- .vendor_ext_provider = Edk2OpensbiPlatformVendorExtProvider,
-};
diff --git a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c
index 3bc3690047..f2b2c7b583 100644
--- a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c
+++ b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c
@@ -25,49 +25,12 @@
#include <sbi/sbi_ecall.h> // Reference to header file in opensbi
#include <sbi/sbi_trap.h> // Reference to header file in opensbi
-extern struct sbi_platform_operations Edk2OpensbiPlatformOps;
-
//
// Indicates the boot hart (PcdBootHartId) OpenSBI initialization is done.
//
atomic_t BootHartDone = ATOMIC_INITIALIZER(0);
atomic_t NonBootHartMessageLock = ATOMIC_INITIALIZER(0);
-int sbi_domain_root_add_memregion(const struct sbi_domain_memregion *reg);
-
-typedef struct sbi_scratch *(*hartid2scratch)(ulong hartid, ulong hartindex);
-
-struct sbi_domain_memregion fw_memregs;
-
-int SecSetEdk2FwMemoryRegions (VOID) {
- int Ret;
-
- Ret = 0;
-
- //
- // EDK2 PEI domain memory region
- //
- fw_memregs.order = log2roundup(FixedPcdGet32(PcdFirmwareDomainSize));
- fw_memregs.base = FixedPcdGet32(PcdFirmwareDomainBaseAddress);
- fw_memregs.flags = SBI_DOMAIN_MEMREGION_EXECUTABLE | SBI_DOMAIN_MEMREGION_READABLE;
- Ret = sbi_domain_root_add_memregion ((const struct sbi_domain_memregion *)&fw_memregs);
- if (Ret != 0) {
- DEBUG ((DEBUG_ERROR, "%a: Add firmware regiosn of FW Domain fail\n", __FUNCTION__));
- }
-
- //
- // EDK2 EFI Variable domain memory region
- //
- fw_memregs.order = log2roundup(FixedPcdGet32(PcdVariableFirmwareRegionSize));
- fw_memregs.base = FixedPcdGet32(PcdVariableFirmwareRegionBaseAddress);
- fw_memregs.flags = SBI_DOMAIN_MEMREGION_READABLE | SBI_DOMAIN_MEMREGION_WRITEABLE;
- Ret = sbi_domain_root_add_memregion ((const struct sbi_domain_memregion *)&fw_memregs);
- if (Ret != 0) {
- DEBUG ((DEBUG_ERROR, "%a: Add firmware regiosn of variable FW Domain fail\n", __FUNCTION__));
- }
- return Ret;
-}
-
/**
Locates a section within a series of sections
with the specified section type.
@@ -424,109 +387,6 @@ RegisterFirmwareSbiExtension (
return EFI_SUCCESS;
}
-/**
- OpenSBI platform early init hook.
-
-**/
-int
-SecPostOpenSbiPlatformEarlylInit(
- IN BOOLEAN ColdBoot
- )
-{
- UINT32 HartId;
-
- if (!ColdBoot) {
- HartId = current_hartid();
- DEBUG ((DEBUG_INFO, "%a: Non boot hart %d.\n", __FUNCTION__, HartId));
- return 0;
- }
- //
- // Setup firmware memory region.
- //
- if (SecSetEdk2FwMemoryRegions () != 0) {
- ASSERT (FALSE);
- }
-
- //
- // Boot HART is already in the process of OpenSBI initialization.
- // We can let other HART to keep booting.
- //
- DEBUG ((DEBUG_INFO, "%a: Set boot hart done.\n", __FUNCTION__));
- atomic_write (&BootHartDone, (UINT64)TRUE);
- return 0;
-}
-
-/**
- OpenSBI platform final init hook.
- We restore the next_arg1 to the pointer of EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT.
-
-**/
-int
-SecPostOpenSbiPlatformFinalInit (
- IN BOOLEAN ColdBoot
- )
-{
- UINT32 HartId;
- struct sbi_scratch *SbiScratch;
- struct sbi_scratch *ScratchSpace;
- struct sbi_platform *SbiPlatform;
- EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *FirmwareContext;
-
- if (!ColdBoot) {
- HartId = current_hartid();
- DEBUG ((DEBUG_INFO, "%a: Non boot hart %d.\n", __FUNCTION__, HartId));
- return 0;
- }
-
- DEBUG((DEBUG_INFO, "%a: Entry, preparing to jump to PEI Core\n\n", __FUNCTION__));
-
- SbiScratch = sbi_scratch_thishart_ptr();
- SbiPlatform = (struct sbi_platform *)sbi_platform_ptr(SbiScratch);
- FirmwareContext = (EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *)SbiPlatform->firmware_context;
-
- //
- // Print out scratch address of each hart
- //
- DEBUG ((DEBUG_INFO, "%a: OpenSBI scratch address for each hart:\n", __FUNCTION__));
- for (HartId = 0; HartId < SBI_HARTMASK_MAX_BITS; HartId ++) {
- if (sbi_platform_hart_invalid(SbiPlatform, HartId)) {
- continue;
- }
- ScratchSpace = sbi_hartid_to_scratch (HartId);
- if(ScratchSpace != NULL) {
- DEBUG((DEBUG_INFO, " Hart %d: 0x%x\n", HartId, ScratchSpace));
- } else {
- DEBUG((DEBUG_INFO, " Hart %d not initialized yet\n", HartId));
- }
- }
-
- //
- // Set firmware context Hart-specific pointer
- //
- for (HartId = 0; HartId < SBI_HARTMASK_MAX_BITS; HartId ++) {
- if (sbi_platform_hart_invalid(SbiPlatform, HartId)) {
- continue;
- }
- ScratchSpace = sbi_hartid_to_scratch (HartId);
- if (ScratchSpace != NULL) {
- FirmwareContext->HartSpecific[HartId] =
- (EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC *)((UINT8 *)ScratchSpace - FIRMWARE_CONTEXT_HART_SPECIFIC_SIZE);
- DEBUG ((DEBUG_INFO, "%a: OpenSBI Hart %d Firmware Context Hart-specific at address: 0x%x\n",
- __FUNCTION__,
- HartId,
- FirmwareContext->HartSpecific [HartId]
- ));
- }
- }
-
- DEBUG((DEBUG_INFO, "%a: Will jump to PEI Core in OpenSBI with \n", __FUNCTION__));
- DEBUG((DEBUG_INFO, " sbi_scratch = %x\n", SbiScratch));
- DEBUG((DEBUG_INFO, " sbi_platform = %x\n", SbiPlatform));
- DEBUG((DEBUG_INFO, " FirmwareContext = %x\n", FirmwareContext));
- SbiScratch->next_arg1 = (unsigned long)FirmwareContext;
-
- return 0;
-}
/** Transion from SEC phase to PEI phase.
@@ -787,7 +647,6 @@ VOID EFIAPI SecCoreStartUpWithStack(
//
ThisSbiPlatform = (struct sbi_platform *)sbi_platform_ptr(Scratch);
ThisSbiPlatform->platform_ops_addr = (unsigned long)&Edk2OpensbiPlatformOps;
-
if (HartId == FixedPcdGet32(PcdBootHartId)) {
Scratch->next_arg1 = (unsigned long)GetDeviceTreeAddress ();
--
2.31.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH 58/79] RISC-V/PlatformPkg: Determine hart number from DTB
2022-01-08 7:24 [PATCH 42/79] RISC-V: Use RISC-V PeiCoreEntryPoint library Abner Chang
` (14 preceding siblings ...)
2022-01-08 7:24 ` [PATCH 57/79] PlatformPkg/Sec: Separate EDK2 Opensbi platform hook Abner Chang
@ 2022-01-08 7:24 ` Abner Chang
2022-01-08 7:24 ` [PATCH 59/79] Silicon/RISC-V: Add PciCpuIoDxe driver Abner Chang
` (2 subsequent siblings)
18 siblings, 0 replies; 21+ messages in thread
From: Abner Chang @ 2022-01-08 7:24 UTC (permalink / raw)
To: devel; +Cc: abner.chang
(This is migrated from edk2-platforms:Platform)
Determine total number of hart from DTB instead of
using PCD.
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Cc: Daniel Schaefer <daniel.schaefer@hpe.com>
Cc: Sunil V L <sunilvl@ventanamicro.com>
Reviewed-by: Daniel Schaefer <daniel.schaefer@hpe.com>
Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
---
.../OpensbiPlatformLib/OpensbiPlatformLib.inf | 3 -
.../PlatformPkg/Universal/Sec/SecMain.inf | 1 -
.../PlatformPkg/Universal/Sec/SecMain.c | 12 ++--
.../Universal/Sec/Riscv64/SecEntry.S | 60 +++++++++++++------
4 files changed, 49 insertions(+), 27 deletions(-)
diff --git a/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/OpensbiPlatformLib.inf b/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/OpensbiPlatformLib.inf
index 2e1227733a..6661ee8204 100644
--- a/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/OpensbiPlatformLib.inf
+++ b/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/OpensbiPlatformLib.inf
@@ -46,9 +46,6 @@
RiscVSpecialPlatformLib
[FixedPcd]
- gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootHartId
- gUefiRiscVPlatformPkgTokenSpaceGuid.PcdHartCount
- gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootableHartNumber
gUefiRiscVPlatformPkgTokenSpaceGuid.PcdOpenSbiStackSize
diff --git a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf
index ceb6d25222..b949b6c470 100644
--- a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf
+++ b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf
@@ -61,7 +61,6 @@
[Pcd]
gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootHartId
- gUefiRiscVPlatformPkgTokenSpaceGuid.PcdHartCount
gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRootFirmwareDomainBaseAddress
gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRootFirmwareDomainSize
gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootableHartNumber
diff --git a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c
index f2b2c7b583..17f33a02cc 100644
--- a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c
+++ b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c
@@ -530,7 +530,7 @@ GetDeviceTreeAddress (
EFI_COMMON_SECTION_HEADER *FoundSection;
if (FixedPcdGet32 (PcdDeviceTreeAddress)) {
- DEBUG ((DEBUG_INFO, "Use fixed address of DBT from PcdDeviceTreeAddress 0x%x.\n", FixedPcdGet32 (PcdDeviceTreeAddress)));
+ DEBUG ((DEBUG_INFO, "Use fixed address of DBT from PcdDeviceTreeAddress 0x%x 0x%x.\n", FixedPcdGet32 (PcdDeviceTreeAddress), *((unsigned long *)FixedPcdGet32 (PcdDeviceTreeAddress))));
//
// Device tree address is pointed by PcdDeviceTreeAddress.
//
@@ -647,11 +647,10 @@ VOID EFIAPI SecCoreStartUpWithStack(
//
ThisSbiPlatform = (struct sbi_platform *)sbi_platform_ptr(Scratch);
ThisSbiPlatform->platform_ops_addr = (unsigned long)&Edk2OpensbiPlatformOps;
+ Scratch->next_arg1 = (unsigned long)GetDeviceTreeAddress ();
if (HartId == FixedPcdGet32(PcdBootHartId)) {
-
- Scratch->next_arg1 = (unsigned long)GetDeviceTreeAddress ();
if (Scratch->next_arg1 == (unsigned long)NULL) {
- DEBUG ((DEBUG_ERROR, "Platform Device Tree is not found\n"));
+ DEBUG ((DEBUG_ERROR, "Platform Device Tree is not found on boot hart\n"));
ASSERT (FALSE);
}
DEBUG ((DEBUG_INFO, "Device Tree at 0x%x\n", Scratch->next_arg1));
@@ -685,6 +684,11 @@ VOID EFIAPI SecCoreStartUpWithStack(
NonBootHartMessageLockValue = atomic_xchg(&NonBootHartMessageLock, TRUE);
};
DEBUG((DEBUG_INFO, "%a: Non boot hart %d initialization.\n", __FUNCTION__, HartId));
+ if (Scratch->next_arg1 == (unsigned long)NULL) {
+ DEBUG ((DEBUG_ERROR, "Platform Device Tree is not found\n"));
+ ASSERT (FALSE);
+ }
+ DEBUG((DEBUG_INFO, "%a: Non boot hart %d DTB is at 0x%x.\n", __FUNCTION__, HartId, Scratch->next_arg1));
NonBootHartMessageLockValue = atomic_xchg(&NonBootHartMessageLock, FALSE);
//
// Non boot hart wiil be halted waiting for SBI_HART_STARTING.
diff --git a/Platform/RISC-V/PlatformPkg/Universal/Sec/Riscv64/SecEntry.S b/Platform/RISC-V/PlatformPkg/Universal/Sec/Riscv64/SecEntry.S
index 96087738a3..0fc7817665 100644
--- a/Platform/RISC-V/PlatformPkg/Universal/Sec/Riscv64/SecEntry.S
+++ b/Platform/RISC-V/PlatformPkg/Universal/Sec/Riscv64/SecEntry.S
@@ -37,14 +37,39 @@ ASM_FUNC (_ModuleEntryPoint)
li a5, FixedPcdGet32 (PcdBootHartId)
bne a6, a5, _wait_for_boot_hart
- li ra, 0
- call _reset_regs
+ /*
+ * Initial the hart count reported in DTB
+ */
+ li a4, FixedPcdGet32 (PcdTemporaryRamBase)
+ li a5, FixedPcdGet32 (PcdTemporaryRamSize)
+ /* Use Temp memory as the stack for calling to C code */
+ add sp, a4, a5
+ /* Get the address of device tree and call generic fw_platform_init */
+ call GetDeviceTreeAddress /* a0 return the device tree address */
+ beqz a0, skip_fw_init
+ add a1, a0, 0 /* a1 is device tree */
+ csrr a0, CSR_MHARTID /* a0 is boot hart ID */
+ call fw_platform_init
+skip_fw_init:
/* Preload HART details
- * s7 -> HART Count
+ * s7 -> Total HART count from PCD or DTB
* s8 -> HART Stack Size
*/
- li s7, FixedPcdGet32 (PcdHartCount)
+ la a0, platform
+#if __riscv_xlen == 64
+ lwu s7, SBI_PLATFORM_HART_COUNT_OFFSET(a0)
+#else
+ lw s7, SBI_PLATFORM_HART_COUNT_OFFSET(a0)
+#endif
+ /*
+ * This is the number of HARTs described in
+ * DTB for this processor. We allocate the
+ * scratch buffer according to this number.
+ */
+ la a4, _pysical_hart_count
+ sd s7, (a4)
+
li s8, FixedPcdGet32 (PcdOpenSbiStackSize)
/*
@@ -113,20 +138,9 @@ _scratch_init:
li a4, FixedPcdGet32 (PcdTemporaryRamBase)
li a5, FixedPcdGet32 (PcdTemporaryRamSize)
-
/* Use Temp memory as the stack for calling to C code */
add sp, a4, a5
- /* Get the address of device tree and call generic fw_platform_init */
- call GetDeviceTreeAddress /* a0 return the device tree address */
- beqz a0, skip_fw_init
- add a1, a0, 0 /* a1 is device tree */
- csrr a0, CSR_MHARTID /* a0 is hart ID */
- call fw_platform_init
-skip_fw_init:
-
/* Zero out temporary memory */
- li a4, FixedPcdGet32 (PcdTemporaryRamBase)
- li a5, FixedPcdGet32 (PcdTemporaryRamSize)
add a5, a4, a5
1:
li a3, 0x0
@@ -167,7 +181,11 @@ _start_warm:
li s7, FixedPcdGet32 (PcdBootableHartNumber)
bnez s7, 1f
la a4, platform
- REG_L s7, SBI_PLATFORM_HART_COUNT_OFFSET(a4)
+#if __riscv_xlen == 64
+ lwu s7, SBI_PLATFORM_HART_COUNT_OFFSET(a4)
+#else
+ lw s7, SBI_PLATFORM_HART_COUNT_OFFSET(a4)
+#endif
1:
li s8, FixedPcdGet32 (PcdOpenSbiStackSize)
la a4, platform
@@ -209,7 +227,8 @@ _start_warm:
csrr a0, CSR_MHARTID
j _uninitialized_hart_wait
4:
- li s7, FixedPcdGet32 (PcdHartCount)
+ la a5, _pysical_hart_count
+ ld s7, (a5)
/* Find the scratch space for this hart
*
* Scratch buffer is on the top of stack buffer
@@ -275,6 +294,8 @@ _start_warm:
.section .data, "aw"
_boot_hart_done:
RISCV_PTR 0
+_pysical_hart_count:
+ RISCV_PTR 0
.align 3
.section .entry, "ax", %progbits
@@ -293,7 +314,7 @@ _hartid_to_scratch:
/*
* s0 -> HART Stack Size
* s1 -> HART Stack End
- * s2 -> Temporary
+ * s2 -> Total hart count
*/
la s2, platform
#if __riscv_xlen == 64
@@ -301,8 +322,9 @@ _hartid_to_scratch:
#else
lw s0, SBI_PLATFORM_HART_STACK_SIZE_OFFSET(s2)
#endif
- li s2, FixedPcdGet32 (PcdHartCount)
+ la s1, _pysical_hart_count /* total HART count */
+ ld s2, (s1)
mul s2, s2, s0
li s1, FixedPcdGet32 (PcdScratchRamBase)
add s1, s1, s2
--
2.31.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH 59/79] Silicon/RISC-V: Add PciCpuIoDxe driver
2022-01-08 7:24 [PATCH 42/79] RISC-V: Use RISC-V PeiCoreEntryPoint library Abner Chang
` (15 preceding siblings ...)
2022-01-08 7:24 ` [PATCH 58/79] RISC-V/PlatformPkg: Determine hart number from DTB Abner Chang
@ 2022-01-08 7:24 ` Abner Chang
2022-01-08 7:24 ` [PATCH 60/79] Platform/RISC-V: Add debug message to SecMain.c Abner Chang
2022-01-08 7:24 ` [PATCH 61/79] Platform/RISC-V: Initialize variable to zero Abner Chang
18 siblings, 0 replies; 21+ messages in thread
From: Abner Chang @ 2022-01-08 7:24 UTC (permalink / raw)
To: devel; +Cc: abner.chang
(This is migrated from edk2-platforms:Silicon)
Add PCI CpuIo protocol to RISC-V.
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Cc: Daniel Schaefer <daniel.schaefer@hpe.com>
Cc: Sunil V L <sunilvl@ventanamicro.com>
Reviewed-by: Daniel Schaefer <daniel.schaefer@hpe.com>
Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
---
.../RISC-V/ProcessorPkg/RiscVProcessorPkg.dsc | 1 +
.../Universal/PciCpuIo2Dxe/PciCpuIo2Dxe.inf | 47 ++
.../Universal/PciCpuIo2Dxe/PciCpuIo2Dxe.c | 554 ++++++++++++++++++
3 files changed, 602 insertions(+)
create mode 100644 Silicon/RISC-V/ProcessorPkg/Universal/PciCpuIo2Dxe/PciCpuIo2Dxe.inf
create mode 100644 Silicon/RISC-V/ProcessorPkg/Universal/PciCpuIo2Dxe/PciCpuIo2Dxe.c
diff --git a/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dsc b/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dsc
index 3b5738957d..5c7425421b 100644
--- a/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dsc
+++ b/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dsc
@@ -105,3 +105,4 @@
Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxe.inf
Silicon/RISC-V/ProcessorPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.inf
Silicon/RISC-V/ProcessorPkg/Universal/FdtDxe/FdtDxe.inf
+ Silicon/RISC-V/ProcessorPkg/Universal/PciCpuIo2Dxe/PciCpuIo2Dxe.inf
diff --git a/Silicon/RISC-V/ProcessorPkg/Universal/PciCpuIo2Dxe/PciCpuIo2Dxe.inf b/Silicon/RISC-V/ProcessorPkg/Universal/PciCpuIo2Dxe/PciCpuIo2Dxe.inf
new file mode 100644
index 0000000000..736143bf4c
--- /dev/null
+++ b/Silicon/RISC-V/ProcessorPkg/Universal/PciCpuIo2Dxe/PciCpuIo2Dxe.inf
@@ -0,0 +1,47 @@
+## @file
+# Produces the CPU I/O 2 Protocol by using the services of the I/O Library.
+#
+# Copyright (c) 2009 - 2014, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2016, Linaro Ltd. All rights reserved.<BR>
+# (C) Copyright 2021 Hewlett Packard Enterprise Development LP<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = PciCpuIo2Dxe
+ FILE_GUID = 4032D393-69E6-42BF-BBEA-08F3297374E8
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ ENTRY_POINT = PciCpuIo2Initialize
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = RISCV64
+#
+
+[Sources]
+ PciCpuIo2Dxe.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+
+[LibraryClasses]
+ UefiDriverEntryPoint
+ BaseLib
+ DebugLib
+ IoLib
+ PcdLib
+ UefiBootServicesTableLib
+
+[Pcd]
+ gEfiMdePkgTokenSpaceGuid.PcdPciIoTranslation
+
+[Protocols]
+ gEfiCpuIo2ProtocolGuid ## PRODUCES
+
+[Depex]
+ TRUE
diff --git a/Silicon/RISC-V/ProcessorPkg/Universal/PciCpuIo2Dxe/PciCpuIo2Dxe.c b/Silicon/RISC-V/ProcessorPkg/Universal/PciCpuIo2Dxe/PciCpuIo2Dxe.c
new file mode 100644
index 0000000000..03e3070682
--- /dev/null
+++ b/Silicon/RISC-V/ProcessorPkg/Universal/PciCpuIo2Dxe/PciCpuIo2Dxe.c
@@ -0,0 +1,554 @@
+/** @file
+ Produces the CPU I/O 2 Protocol.
+
+Copyright (c) 2009 - 2012, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2016, Linaro Ltd. All rights reserved.<BR>
+(C) Copyright 2021 Hewlett Packard Enterprise Development LP<BR>
+
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <PiDxe.h>
+
+#include <Protocol/CpuIo2.h>
+
+#include <Library/BaseLib.h>
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Library/PcdLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+
+#define MAX_IO_PORT_ADDRESS 0xFFFF
+
+//
+// Handle for the CPU I/O 2 Protocol
+//
+STATIC EFI_HANDLE mHandle = NULL;
+
+//
+// Lookup table for increment values based on transfer widths
+//
+STATIC CONST UINT8 mInStride[] = {
+ 1, // EfiCpuIoWidthUint8
+ 2, // EfiCpuIoWidthUint16
+ 4, // EfiCpuIoWidthUint32
+ 8, // EfiCpuIoWidthUint64
+ 0, // EfiCpuIoWidthFifoUint8
+ 0, // EfiCpuIoWidthFifoUint16
+ 0, // EfiCpuIoWidthFifoUint32
+ 0, // EfiCpuIoWidthFifoUint64
+ 1, // EfiCpuIoWidthFillUint8
+ 2, // EfiCpuIoWidthFillUint16
+ 4, // EfiCpuIoWidthFillUint32
+ 8 // EfiCpuIoWidthFillUint64
+};
+
+//
+// Lookup table for increment values based on transfer widths
+//
+STATIC CONST UINT8 mOutStride[] = {
+ 1, // EfiCpuIoWidthUint8
+ 2, // EfiCpuIoWidthUint16
+ 4, // EfiCpuIoWidthUint32
+ 8, // EfiCpuIoWidthUint64
+ 1, // EfiCpuIoWidthFifoUint8
+ 2, // EfiCpuIoWidthFifoUint16
+ 4, // EfiCpuIoWidthFifoUint32
+ 8, // EfiCpuIoWidthFifoUint64
+ 0, // EfiCpuIoWidthFillUint8
+ 0, // EfiCpuIoWidthFillUint16
+ 0, // EfiCpuIoWidthFillUint32
+ 0 // EfiCpuIoWidthFillUint64
+};
+
+/**
+ Check parameters to a CPU I/O 2 Protocol service request.
+
+ The I/O operations are carried out exactly as requested. The caller is responsible
+ for satisfying any alignment and I/O width restrictions that a PI System on a
+ platform might require. For example on some platforms, width requests of
+ EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will
+ be handled by the driver.
+
+ @param[in] MmioOperation TRUE for an MMIO operation, FALSE for I/O Port operation.
+ @param[in] Width Signifies the width of the I/O or Memory operation.
+ @param[in] Address The base address of the I/O operation.
+ @param[in] Count The number of I/O operations to perform. The number of
+ bytes moved is Width size * Count, starting at Address.
+ @param[in] Buffer For read operations, the destination buffer to store the results.
+ For write operations, the source buffer from which to write data.
+
+ @retval EFI_SUCCESS The parameters for this request pass the checks.
+ @retval EFI_INVALID_PARAMETER Width is invalid for this PI system.
+ @retval EFI_INVALID_PARAMETER Buffer is NULL.
+ @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.
+ @retval EFI_UNSUPPORTED The address range specified by Address, Width,
+ and Count is not valid for this PI system.
+
+**/
+STATIC
+EFI_STATUS
+CpuIoCheckParameter (
+ IN BOOLEAN MmioOperation,
+ IN EFI_CPU_IO_PROTOCOL_WIDTH Width,
+ IN UINT64 Address,
+ IN UINTN Count,
+ IN VOID *Buffer
+ )
+{
+ UINT64 MaxCount;
+ UINT64 Limit;
+
+ //
+ // Check to see if Buffer is NULL
+ //
+ if (Buffer == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ //
+ // Check to see if Width is in the valid range
+ //
+ if ((UINT32)Width >= EfiCpuIoWidthMaximum) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ //
+ // For FIFO type, the target address won't increase during the access,
+ // so treat Count as 1
+ //
+ if (Width >= EfiCpuIoWidthFifoUint8 && Width <= EfiCpuIoWidthFifoUint64) {
+ Count = 1;
+ }
+
+ //
+ // Check to see if Width is in the valid range for I/O Port operations
+ //
+ Width = (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03);
+ if (!MmioOperation && (Width == EfiCpuIoWidthUint64)) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ //
+ // Check to see if Address is aligned
+ //
+ if ((Address & (UINT64)(mInStride[Width] - 1)) != 0) {
+ return EFI_UNSUPPORTED;
+ }
+
+ //
+ // Check to see if any address associated with this transfer exceeds the maximum
+ // allowed address. The maximum address implied by the parameters passed in is
+ // Address + Size * Count. If the following condition is met, then the transfer
+ // is not supported.
+ //
+ // Address + Size * Count > (MmioOperation ? MAX_ADDRESS : MAX_IO_PORT_ADDRESS) + 1
+ //
+ // Since MAX_ADDRESS can be the maximum integer value supported by the CPU and Count
+ // can also be the maximum integer value supported by the CPU, this range
+ // check must be adjusted to avoid all overflow conditions.
+ //
+ // The following form of the range check is equivalent but assumes that
+ // MAX_ADDRESS and MAX_IO_PORT_ADDRESS are of the form (2^n - 1).
+ //
+ Limit = (MmioOperation ? MAX_ADDRESS : MAX_IO_PORT_ADDRESS);
+ if (Count == 0) {
+ if (Address > Limit) {
+ return EFI_UNSUPPORTED;
+ }
+ } else {
+ MaxCount = RShiftU64 (Limit, Width);
+ if (MaxCount < (Count - 1)) {
+ return EFI_UNSUPPORTED;
+ }
+ if (Address > LShiftU64 (MaxCount - Count + 1, Width)) {
+ return EFI_UNSUPPORTED;
+ }
+ }
+
+ //
+ // Check to see if Buffer is aligned
+ //
+ if (((UINTN)Buffer & ((MIN (sizeof (UINTN), mInStride[Width]) - 1))) != 0) {
+ return EFI_UNSUPPORTED;
+ }
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Reads memory-mapped registers.
+
+ The I/O operations are carried out exactly as requested. The caller is responsible
+ for satisfying any alignment and I/O width restrictions that a PI System on a
+ platform might require. For example on some platforms, width requests of
+ EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will
+ be handled by the driver.
+
+ If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32,
+ or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for
+ each of the Count operations that is performed.
+
+ If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16,
+ EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is
+ incremented for each of the Count operations that is performed. The read or
+ write operation is performed Count times on the same Address.
+
+ If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16,
+ EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is
+ incremented for each of the Count operations that is performed. The read or
+ write operation is performed Count times from the first element of Buffer.
+
+ @param[in] This A pointer to the EFI_CPU_IO2_PROTOCOL instance.
+ @param[in] Width Signifies the width of the I/O or Memory operation.
+ @param[in] Address The base address of the I/O operation.
+ @param[in] Count The number of I/O operations to perform. The number of
+ bytes moved is Width size * Count, starting at Address.
+ @param[out] Buffer For read operations, the destination buffer to store the results.
+ For write operations, the source buffer from which to write data.
+
+ @retval EFI_SUCCESS The data was read from or written to the PI system.
+ @retval EFI_INVALID_PARAMETER Width is invalid for this PI system.
+ @retval EFI_INVALID_PARAMETER Buffer is NULL.
+ @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.
+ @retval EFI_UNSUPPORTED The address range specified by Address, Width,
+ and Count is not valid for this PI system.
+
+**/
+STATIC
+EFI_STATUS
+EFIAPI
+CpuMemoryServiceRead (
+ IN EFI_CPU_IO2_PROTOCOL *This,
+ IN EFI_CPU_IO_PROTOCOL_WIDTH Width,
+ IN UINT64 Address,
+ IN UINTN Count,
+ OUT VOID *Buffer
+ )
+{
+ EFI_STATUS Status;
+ UINT8 InStride;
+ UINT8 OutStride;
+ EFI_CPU_IO_PROTOCOL_WIDTH OperationWidth;
+ UINT8 *Uint8Buffer;
+
+ Status = CpuIoCheckParameter (TRUE, Width, Address, Count, Buffer);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ //
+ // Select loop based on the width of the transfer
+ //
+ InStride = mInStride[Width];
+ OutStride = mOutStride[Width];
+ OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03);
+ for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) {
+ if (OperationWidth == EfiCpuIoWidthUint8) {
+ *Uint8Buffer = MmioRead8 ((UINTN)Address);
+ } else if (OperationWidth == EfiCpuIoWidthUint16) {
+ *((UINT16 *)Uint8Buffer) = MmioRead16 ((UINTN)Address);
+ } else if (OperationWidth == EfiCpuIoWidthUint32) {
+ *((UINT32 *)Uint8Buffer) = MmioRead32 ((UINTN)Address);
+ } else if (OperationWidth == EfiCpuIoWidthUint64) {
+ *((UINT64 *)Uint8Buffer) = MmioRead64 ((UINTN)Address);
+ }
+ }
+ return EFI_SUCCESS;
+}
+
+/**
+ Writes memory-mapped registers.
+
+ The I/O operations are carried out exactly as requested. The caller is responsible
+ for satisfying any alignment and I/O width restrictions that a PI System on a
+ platform might require. For example on some platforms, width requests of
+ EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will
+ be handled by the driver.
+
+ If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32,
+ or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for
+ each of the Count operations that is performed.
+
+ If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16,
+ EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is
+ incremented for each of the Count operations that is performed. The read or
+ write operation is performed Count times on the same Address.
+
+ If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16,
+ EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is
+ incremented for each of the Count operations that is performed. The read or
+ write operation is performed Count times from the first element of Buffer.
+
+ @param[in] This A pointer to the EFI_CPU_IO2_PROTOCOL instance.
+ @param[in] Width Signifies the width of the I/O or Memory operation.
+ @param[in] Address The base address of the I/O operation.
+ @param[in] Count The number of I/O operations to perform. The number of
+ bytes moved is Width size * Count, starting at Address.
+ @param[in] Buffer For read operations, the destination buffer to store the results.
+ For write operations, the source buffer from which to write data.
+
+ @retval EFI_SUCCESS The data was read from or written to the PI system.
+ @retval EFI_INVALID_PARAMETER Width is invalid for this PI system.
+ @retval EFI_INVALID_PARAMETER Buffer is NULL.
+ @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.
+ @retval EFI_UNSUPPORTED The address range specified by Address, Width,
+ and Count is not valid for this PI system.
+
+**/
+STATIC
+EFI_STATUS
+EFIAPI
+CpuMemoryServiceWrite (
+ IN EFI_CPU_IO2_PROTOCOL *This,
+ IN EFI_CPU_IO_PROTOCOL_WIDTH Width,
+ IN UINT64 Address,
+ IN UINTN Count,
+ IN VOID *Buffer
+ )
+{
+ EFI_STATUS Status;
+ UINT8 InStride;
+ UINT8 OutStride;
+ EFI_CPU_IO_PROTOCOL_WIDTH OperationWidth;
+ UINT8 *Uint8Buffer;
+
+ Status = CpuIoCheckParameter (TRUE, Width, Address, Count, Buffer);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ //
+ // Select loop based on the width of the transfer
+ //
+ InStride = mInStride[Width];
+ OutStride = mOutStride[Width];
+ OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03);
+ for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) {
+ if (OperationWidth == EfiCpuIoWidthUint8) {
+ MmioWrite8 ((UINTN)Address, *Uint8Buffer);
+ } else if (OperationWidth == EfiCpuIoWidthUint16) {
+ MmioWrite16 ((UINTN)Address, *((UINT16 *)Uint8Buffer));
+ } else if (OperationWidth == EfiCpuIoWidthUint32) {
+ MmioWrite32 ((UINTN)Address, *((UINT32 *)Uint8Buffer));
+ } else if (OperationWidth == EfiCpuIoWidthUint64) {
+ MmioWrite64 ((UINTN)Address, *((UINT64 *)Uint8Buffer));
+ }
+ }
+ return EFI_SUCCESS;
+}
+
+/**
+ Reads I/O registers.
+
+ The I/O operations are carried out exactly as requested. The caller is responsible
+ for satisfying any alignment and I/O width restrictions that a PI System on a
+ platform might require. For example on some platforms, width requests of
+ EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will
+ be handled by the driver.
+
+ If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32,
+ or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for
+ each of the Count operations that is performed.
+
+ If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16,
+ EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is
+ incremented for each of the Count operations that is performed. The read or
+ write operation is performed Count times on the same Address.
+
+ If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16,
+ EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is
+ incremented for each of the Count operations that is performed. The read or
+ write operation is performed Count times from the first element of Buffer.
+
+ @param[in] This A pointer to the EFI_CPU_IO2_PROTOCOL instance.
+ @param[in] Width Signifies the width of the I/O or Memory operation.
+ @param[in] Address The base address of the I/O operation.
+ @param[in] Count The number of I/O operations to perform. The number of
+ bytes moved is Width size * Count, starting at Address.
+ @param[out] Buffer For read operations, the destination buffer to store the results.
+ For write operations, the source buffer from which to write data.
+
+ @retval EFI_SUCCESS The data was read from or written to the PI system.
+ @retval EFI_INVALID_PARAMETER Width is invalid for this PI system.
+ @retval EFI_INVALID_PARAMETER Buffer is NULL.
+ @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.
+ @retval EFI_UNSUPPORTED The address range specified by Address, Width,
+ and Count is not valid for this PI system.
+
+**/
+STATIC
+EFI_STATUS
+EFIAPI
+CpuIoServiceRead (
+ IN EFI_CPU_IO2_PROTOCOL *This,
+ IN EFI_CPU_IO_PROTOCOL_WIDTH Width,
+ IN UINT64 Address,
+ IN UINTN Count,
+ OUT VOID *Buffer
+ )
+{
+ EFI_STATUS Status;
+ UINT8 InStride;
+ UINT8 OutStride;
+ EFI_CPU_IO_PROTOCOL_WIDTH OperationWidth;
+ UINT8 *Uint8Buffer;
+
+ Status = CpuIoCheckParameter (FALSE, Width, Address, Count, Buffer);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ Address += PcdGet64 (PcdPciIoTranslation);
+
+ //
+ // Select loop based on the width of the transfer
+ //
+ InStride = mInStride[Width];
+ OutStride = mOutStride[Width];
+ OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03);
+
+ for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) {
+ if (OperationWidth == EfiCpuIoWidthUint8) {
+ *Uint8Buffer = MmioRead8 ((UINTN)Address);
+ } else if (OperationWidth == EfiCpuIoWidthUint16) {
+ *((UINT16 *)Uint8Buffer) = MmioRead16 ((UINTN)Address);
+ } else if (OperationWidth == EfiCpuIoWidthUint32) {
+ *((UINT32 *)Uint8Buffer) = MmioRead32 ((UINTN)Address);
+ }
+ }
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Write I/O registers.
+
+ The I/O operations are carried out exactly as requested. The caller is responsible
+ for satisfying any alignment and I/O width restrictions that a PI System on a
+ platform might require. For example on some platforms, width requests of
+ EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will
+ be handled by the driver.
+
+ If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32,
+ or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for
+ each of the Count operations that is performed.
+
+ If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16,
+ EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is
+ incremented for each of the Count operations that is performed. The read or
+ write operation is performed Count times on the same Address.
+
+ If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16,
+ EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is
+ incremented for each of the Count operations that is performed. The read or
+ write operation is performed Count times from the first element of Buffer.
+
+ @param[in] This A pointer to the EFI_CPU_IO2_PROTOCOL instance.
+ @param[in] Width Signifies the width of the I/O or Memory operation.
+ @param[in] Address The base address of the I/O operation.
+ @param[in] Count The number of I/O operations to perform. The number of
+ bytes moved is Width size * Count, starting at Address.
+ @param[in] Buffer For read operations, the destination buffer to store the results.
+ For write operations, the source buffer from which to write data.
+
+ @retval EFI_SUCCESS The data was read from or written to the PI system.
+ @retval EFI_INVALID_PARAMETER Width is invalid for this PI system.
+ @retval EFI_INVALID_PARAMETER Buffer is NULL.
+ @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.
+ @retval EFI_UNSUPPORTED The address range specified by Address, Width,
+ and Count is not valid for this PI system.
+
+**/
+STATIC
+EFI_STATUS
+EFIAPI
+CpuIoServiceWrite (
+ IN EFI_CPU_IO2_PROTOCOL *This,
+ IN EFI_CPU_IO_PROTOCOL_WIDTH Width,
+ IN UINT64 Address,
+ IN UINTN Count,
+ IN VOID *Buffer
+ )
+{
+ EFI_STATUS Status;
+ UINT8 InStride;
+ UINT8 OutStride;
+ EFI_CPU_IO_PROTOCOL_WIDTH OperationWidth;
+ UINT8 *Uint8Buffer;
+
+ //
+ // Make sure the parameters are valid
+ //
+ Status = CpuIoCheckParameter (FALSE, Width, Address, Count, Buffer);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ Address += PcdGet64 (PcdPciIoTranslation);
+
+ //
+ // Select loop based on the width of the transfer
+ //
+ InStride = mInStride[Width];
+ OutStride = mOutStride[Width];
+ OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03);
+
+ for (Uint8Buffer = (UINT8 *)Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) {
+ if (OperationWidth == EfiCpuIoWidthUint8) {
+ MmioWrite8 ((UINTN)Address, *Uint8Buffer);
+ } else if (OperationWidth == EfiCpuIoWidthUint16) {
+ MmioWrite16 ((UINTN)Address, *((UINT16 *)Uint8Buffer));
+ } else if (OperationWidth == EfiCpuIoWidthUint32) {
+ MmioWrite32 ((UINTN)Address, *((UINT32 *)Uint8Buffer));
+ }
+ }
+
+ return EFI_SUCCESS;
+}
+
+//
+// CPU I/O 2 Protocol instance
+//
+STATIC EFI_CPU_IO2_PROTOCOL mCpuIo2 = {
+ {
+ CpuMemoryServiceRead,
+ CpuMemoryServiceWrite
+ },
+ {
+ CpuIoServiceRead,
+ CpuIoServiceWrite
+ }
+};
+
+
+/**
+ The user Entry Point for module CpuIo2Dxe. The user code starts with this function.
+
+ @param[in] ImageHandle The firmware allocated handle for the EFI image.
+ @param[in] SystemTable A pointer to the EFI System Table.
+
+ @retval EFI_SUCCESS The entry point is executed successfully.
+ @retval other Some error occurs when executing this entry point.
+
+**/
+EFI_STATUS
+EFIAPI
+PciCpuIo2Initialize (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+
+ ASSERT_PROTOCOL_ALREADY_INSTALLED (NULL, &gEfiCpuIo2ProtocolGuid);
+ Status = gBS->InstallMultipleProtocolInterfaces (
+ &mHandle,
+ &gEfiCpuIo2ProtocolGuid, &mCpuIo2,
+ NULL
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ return Status;
+}
--
2.31.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH 60/79] Platform/RISC-V: Add debug message to SecMain.c
2022-01-08 7:24 [PATCH 42/79] RISC-V: Use RISC-V PeiCoreEntryPoint library Abner Chang
` (16 preceding siblings ...)
2022-01-08 7:24 ` [PATCH 59/79] Silicon/RISC-V: Add PciCpuIoDxe driver Abner Chang
@ 2022-01-08 7:24 ` Abner Chang
2022-01-08 7:24 ` [PATCH 61/79] Platform/RISC-V: Initialize variable to zero Abner Chang
18 siblings, 0 replies; 21+ messages in thread
From: Abner Chang @ 2022-01-08 7:24 UTC (permalink / raw)
To: devel; +Cc: abner.chang
(This is migrated from edk2-platforms:Platform)
Add more debug messages when search FFS in SEC phase.
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Cc: Daniel Schaefer <daniel.schaefer@hpe.com>
Cc: Sunil V L <sunilvl@ventanamicro.com>
Reviewed-by: Daniel Schaefer <daniel.schaefer@hpe.com>
---
.../RISC-V/PlatformPkg/Universal/Sec/SecMain.c | 14 +++++++++++++-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c
index 17f33a02cc..05f228c44d 100644
--- a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c
+++ b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c
@@ -166,6 +166,8 @@ FindFfsFileAndSection (
UINT32 Size;
EFI_PHYSICAL_ADDRESS EndOfFile;
+ DEBUG ((DEBUG_INFO, "%a: DBT FV at 0x%x\n", __FUNCTION__, Fv));
+
if (Fv->Signature != EFI_FVH_SIGNATURE) {
DEBUG ((DEBUG_ERROR, "%a: FV at %p does not have FV header signature\n", __FUNCTION__, Fv));
return EFI_VOLUME_CORRUPTED;
@@ -181,17 +183,20 @@ FindFfsFileAndSection (
CurrentAddress = (EndOfFile + 7) & ~(7ULL);
if (CurrentAddress > EndOfFirmwareVolume) {
+ DEBUG ((DEBUG_ERROR, "%a: FV corrupted\n", __FUNCTION__));
return EFI_VOLUME_CORRUPTED;
}
File = (EFI_FFS_FILE_HEADER*)(UINTN) CurrentAddress;
Size = *(UINT32*) File->Size & 0xffffff;
if (Size < (sizeof (*File) + sizeof (EFI_COMMON_SECTION_HEADER))) {
+ DEBUG ((DEBUG_ERROR, "%a: FV corrupted\n", __FUNCTION__));
return EFI_VOLUME_CORRUPTED;
}
EndOfFile = CurrentAddress + Size;
if (EndOfFile > EndOfFirmwareVolume) {
+ DEBUG ((DEBUG_ERROR, "%a: FV corrupted\n", __FUNCTION__));
return EFI_VOLUME_CORRUPTED;
}
@@ -199,6 +204,7 @@ FindFfsFileAndSection (
// Look for the request file type
//
if (File->Type != FileType) {
+ DEBUG ((DEBUG_INFO, "%a: (File->Type != FileType), find next FFS\n", __FUNCTION__));
continue;
}
@@ -208,9 +214,15 @@ FindFfsFileAndSection (
SectionType,
FoundSection
);
- if (!EFI_ERROR (Status) || (Status == EFI_VOLUME_CORRUPTED)) {
+ if (!EFI_ERROR(Status)) {
+ DEBUG ((DEBUG_INFO, "%a: Get firmware file section\n", __FUNCTION__));
+ return Status;
+ }
+ if (Status == EFI_VOLUME_CORRUPTED) {
+ DEBUG ((DEBUG_ERROR, "%a: FV corrupted\n", __FUNCTION__));
return Status;
}
+ DEBUG ((DEBUG_INFO, "%a: Find next FFS\n", __FUNCTION__));
}
}
--
2.31.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH 61/79] Platform/RISC-V: Initialize variable to zero
2022-01-08 7:24 [PATCH 42/79] RISC-V: Use RISC-V PeiCoreEntryPoint library Abner Chang
` (17 preceding siblings ...)
2022-01-08 7:24 ` [PATCH 60/79] Platform/RISC-V: Add debug message to SecMain.c Abner Chang
@ 2022-01-08 7:24 ` Abner Chang
18 siblings, 0 replies; 21+ messages in thread
From: Abner Chang @ 2022-01-08 7:24 UTC (permalink / raw)
To: devel; +Cc: abner.chang
(This is migrated from edk2-platforms:Platform)
Initialize variable NumberOfPlatformInArray to 0.
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Cc: Daniel Schaefer <daniel.schaefer@hpe.com>
Cc: Sunil V L <sunilvl@ventanamicro.com>
Reviewed-by: Daniel Schaefer <daniel.schaefer@hpe.com>
---
.../RiscVSpecialPlatformLibNull/RiscVSpecialPlatformLib.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Platform/RISC-V/PlatformPkg/Library/RiscVSpecialPlatformLibNull/RiscVSpecialPlatformLib.c b/Platform/RISC-V/PlatformPkg/Library/RiscVSpecialPlatformLibNull/RiscVSpecialPlatformLib.c
index 18c152001c..f64bde4535 100644
--- a/Platform/RISC-V/PlatformPkg/Library/RiscVSpecialPlatformLibNull/RiscVSpecialPlatformLib.c
+++ b/Platform/RISC-V/PlatformPkg/Library/RiscVSpecialPlatformLibNull/RiscVSpecialPlatformLib.c
@@ -16,5 +16,5 @@
const struct platform_override *special_platforms = NULL;
const struct platform_override *SpecialPlatformArray = NULL;
-INTN NumberOfPlaformsInArray;
+INTN NumberOfPlaformsInArray = 0;
--
2.31.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
end of thread, other threads:[~2022-01-08 8:26 UTC | newest]
Thread overview: 21+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2022-01-08 7:24 [PATCH 42/79] RISC-V: Use RISC-V PeiCoreEntryPoint library Abner Chang
2022-01-08 7:24 ` [PATCH 43/79] Platform/RISC-V: Add library to get PPI descriptor Abner Chang
2022-01-08 7:24 ` [PATCH 44/79] Platform/RISC-V: Use PlatformSecPpiLib Abner Chang
2022-01-08 7:24 ` [PATCH 45/79] Platform/RISC-V: Add NULL library instance of RiscVSpecialPlatformLib Abner Chang
2022-01-08 7:24 ` [PATCH 46/79] Platform/RISC-V: Remove platform dependency from common platform lib Abner Chang
2022-01-08 7:24 ` [PATCH 47/79] Platform/RISC-V: Remove Null instance of OpensbiPlatformLibNull Abner Chang
2022-01-08 7:24 ` [PATCH 48/79] RiscVPlatformPkg/Sec: Initial hart_index2Id array Abner Chang
2022-01-08 7:24 ` [PATCH 49/79] RiscVPlatformPkg/OpensbiPlatformLib: Remove platform code Abner Chang
2022-01-08 7:24 ` [PATCH 50/79] RiscVPlatformPkg/RiscVSpecialPlatformLib: Rename module name Abner Chang
2022-01-08 7:24 ` [PATCH 51/79] RiscVPkg: Update opensbi library Abner Chang
2022-01-08 7:24 ` [PATCH 52/79] RiscVPlatformPkg/Sec: Check Cold/Warm hart Abner Chang
2022-01-08 7:24 ` [PATCH 53/79] RiscVPlatformPkg/Sec: Add more comments to Secmain.c Abner Chang
2022-01-08 7:24 ` [PATCH 54/79] RiscV/ProcessorPkg: Create read mtime CSR library instances Abner Chang
2022-01-08 7:24 ` [PATCH 55/79] RiscV/ProcessorPkg: Use mtime CSR library Abner Chang
2022-01-08 7:24 ` [PATCH 56/79] RISC-V/PlatformPkg: Updates for the latest OpenSBI Abner Chang
2022-01-08 7:24 ` [PATCH 57/79] PlatformPkg/Sec: Separate EDK2 Opensbi platform hook Abner Chang
2022-01-08 7:24 ` [PATCH 58/79] RISC-V/PlatformPkg: Determine hart number from DTB Abner Chang
2022-01-08 7:24 ` [PATCH 59/79] Silicon/RISC-V: Add PciCpuIoDxe driver Abner Chang
2022-01-08 7:24 ` [PATCH 60/79] Platform/RISC-V: Add debug message to SecMain.c Abner Chang
2022-01-08 7:24 ` [PATCH 61/79] Platform/RISC-V: Initialize variable to zero Abner Chang
[not found] <20220108044518.16375-1-abner.chang@hpe.com>
2022-01-08 4:45 ` [PATCH 56/79] RISC-V/PlatformPkg: Updates for the latest OpenSBI Abner Chang
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