From: "Abner Chang" <abner.chang@hpe.com>
To: devel@edk2.groups.io
Cc: abner.chang@hpe.com, Daniel Schaefer <daniel.schaefer@hpe.com>,
Sunil V L <sunilvl@ventanamicro.com>
Subject: [PATCH 75/79] RiscVPkg: Address Core CI Spelling errors.
Date: Sat, 8 Jan 2022 15:27:33 +0800 [thread overview]
Message-ID: <20220108072737.17962-14-abner.chang@hpe.com> (raw)
In-Reply-To: <20220108072737.17962-1-abner.chang@hpe.com>
From: changab <abner.chang@hpe.com>
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Cc: Daniel Schaefer <daniel.schaefer@hpe.com>
Cc: Sunil V L <sunilvl@ventanamicro.com>
---
RiscVPkg/RiscVPkg.dec | 4 ++--
.../RiscVFirmwareContextSbiLib.inf | 6 +++---
.../RiscVFirmwareContextSscratchLib.inf | 4 ++--
.../RiscVFirmwareContextStvecLib.inf | 6 +++---
RiscVPkg/Include/Library/RiscVEdk2SbiLib.h | 16 ++++++++--------
RiscVPkg/Include/OpensbiTypes.h | 4 ++--
RiscVPkg/Include/ProcessorSpecificHobData.h | 2 +-
RiscVPkg/Include/SmbiosProcessorSpecificData.h | 4 ++--
.../Library/RiscVEdk2SbiLib/RiscVEdk2SbiLib.c | 16 ++++++++--------
.../RiscVExceptionLib/CpuExceptionHandlerLib.c | 6 +++---
.../RiscVFirmwareContextSbiLib.c | 4 ++--
.../RiscVFirmwareContextStvecLib.c | 4 ++--
12 files changed, 38 insertions(+), 38 deletions(-)
diff --git a/RiscVPkg/RiscVPkg.dec b/RiscVPkg/RiscVPkg.dec
index 448124a1a0..893f017d52 100644
--- a/RiscVPkg/RiscVPkg.dec
+++ b/RiscVPkg/RiscVPkg.dec
@@ -1,7 +1,7 @@
-## @file RiscVProcesssorPkg.dec
+## @file RiscVProcessorPkg.dec
# This Package provides UEFI RISC-V processor modules and libraries.
#
-# Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+# Copyright (c) 2020-2022, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
diff --git a/RiscVPkg/Library/RiscVFirmwareContextSbiLib/RiscVFirmwareContextSbiLib.inf b/RiscVPkg/Library/RiscVFirmwareContextSbiLib/RiscVFirmwareContextSbiLib.inf
index e3dbc05007..3cdf59b3cc 100644
--- a/RiscVPkg/Library/RiscVFirmwareContextSbiLib/RiscVFirmwareContextSbiLib.inf
+++ b/RiscVPkg/Library/RiscVFirmwareContextSbiLib/RiscVFirmwareContextSbiLib.inf
@@ -1,9 +1,9 @@
## @file
-# Instance of OpebSBI Firmware Conext Library
+# Instance of OpenSBI Firmware Context Library
#
-# This iinstance uses RISC-V OpenSBI Firmware Extension SBI.
+# This instance uses RISC-V OpenSBI Firmware Extension SBI.
#
-# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+# Copyright (c) 2021-2022, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
diff --git a/RiscVPkg/Library/RiscVFirmwareContextSscratchLib/RiscVFirmwareContextSscratchLib.inf b/RiscVPkg/Library/RiscVFirmwareContextSscratchLib/RiscVFirmwareContextSscratchLib.inf
index c6a74e5edc..5aef9efc71 100644
--- a/RiscVPkg/Library/RiscVFirmwareContextSscratchLib/RiscVFirmwareContextSscratchLib.inf
+++ b/RiscVPkg/Library/RiscVFirmwareContextSscratchLib/RiscVFirmwareContextSscratchLib.inf
@@ -1,9 +1,9 @@
## @file
-# Instance of OpebSBI Firmware Conext Library
+# Instance of OpenSBI Firmware Context Library
#
# This instance uses RISC-V Supervisor mode SCRATCH CSR
#
-# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+# Copyright (c) 2021-2022, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
diff --git a/RiscVPkg/Library/RiscVFirmwareContextStvecLib/RiscVFirmwareContextStvecLib.inf b/RiscVPkg/Library/RiscVFirmwareContextStvecLib/RiscVFirmwareContextStvecLib.inf
index 9888cac81a..7c504c9c3c 100644
--- a/RiscVPkg/Library/RiscVFirmwareContextStvecLib/RiscVFirmwareContextStvecLib.inf
+++ b/RiscVPkg/Library/RiscVFirmwareContextStvecLib/RiscVFirmwareContextStvecLib.inf
@@ -1,9 +1,9 @@
## @file
-# Instance of OpebSBI Firmware Conext Library
+# Instance of OpenSBI Firmware Context Library
#
-# This iinstance Supervisor mode STVEC CSR
+# This instance Supervisor mode STVEC CSR
#
-# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+# Copyright (c) 2021-2022, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
diff --git a/RiscVPkg/Include/Library/RiscVEdk2SbiLib.h b/RiscVPkg/Include/Library/RiscVEdk2SbiLib.h
index 88d957f002..6089137373 100644
--- a/RiscVPkg/Include/Library/RiscVEdk2SbiLib.h
+++ b/RiscVPkg/Include/Library/RiscVEdk2SbiLib.h
@@ -1,7 +1,7 @@
/** @file
Library to call the RISC-V SBI ecalls
- Copyright (c) 2021, Hewlett Packard Development LP. All rights reserved.<BR>
+ Copyright (c) 2021-2022, Hewlett Packard Development LP. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -54,7 +54,7 @@ SbiGetSpecVersion (
/**
Get the SBI implementation ID
- This ID is used to idenetify a specific SBI implementation in order to work
+ This ID is used to identify a specific SBI implementation in order to work
around any quirks it might have.
@param[out] ImplId The ID of the SBI implementation.
@@ -275,7 +275,7 @@ SbiRemoteFenceI (
/**
Instructs the remote harts to execute one or more SFENCE.VMA instructions.
- The SFENCE.VMA covers the range of virtual addresses between StartAaddr and Size.
+ The SFENCE.VMA covers the range of virtual addresses between StartAddr and Size.
The remote fence function acts as a full tlb flush if * StartAddr and size
are both 0 * size is equal to 2^XLEN-1
@@ -305,7 +305,7 @@ SbiRemoteSfenceVma (
/**
Instructs the remote harts to execute one or more SFENCE.VMA instructions.
- The SFENCE.VMA covers the range of virtual addresses between StartAaddr and Size.
+ The SFENCE.VMA covers the range of virtual addresses between StartAddr and Size.
Covers only the given ASID.
The remote fence function acts as a full tlb flush if * StartAddr and size
@@ -337,7 +337,7 @@ SbiRemoteSfenceVmaAsid (
/**
Instructs the remote harts to execute one or more SFENCE.GVMA instructions.
- The SFENCE.GVMA covers the range of virtual addresses between StartAaddr and Size.
+ The SFENCE.GVMA covers the range of virtual addresses between StartAddr and Size.
Covers only the given VMID.
This function call is only valid for harts implementing the hypervisor extension.
@@ -373,7 +373,7 @@ SbiRemoteHfenceGvmaVmid (
/**
Instructs the remote harts to execute one or more SFENCE.GVMA instructions.
- The SFENCE.GVMA covers the range of virtual addresses between StartAaddr and Size.
+ The SFENCE.GVMA covers the range of virtual addresses between StartAddr and Size.
This function call is only valid for harts implementing the hypervisor extension.
The remote fence function acts as a full tlb flush if * StartAddr and size
@@ -407,7 +407,7 @@ SbiRemoteHfenceGvma (
/**
Instructs the remote harts to execute one or more SFENCE.VVMA instructions.
- The SFENCE.GVMA covers the range of virtual addresses between StartAaddr and Size.
+ The SFENCE.GVMA covers the range of virtual addresses between StartAddr and Size.
Covers only the given ASID.
This function call is only valid for harts implementing the hypervisor extension.
@@ -443,7 +443,7 @@ SbiRemoteHfenceVvmaAsid (
/**
Instructs the remote harts to execute one or more SFENCE.VVMA instructions.
- The SFENCE.GVMA covers the range of virtual addresses between StartAaddr and Size.
+ The SFENCE.GVMA covers the range of virtual addresses between StartAddr and Size.
This function call is only valid for harts implementing the hypervisor extension.
The remote fence function acts as a full tlb flush if * StartAddr and size
diff --git a/RiscVPkg/Include/OpensbiTypes.h b/RiscVPkg/Include/OpensbiTypes.h
index 8a6ea97708..ca7fc7a4ac 100644
--- a/RiscVPkg/Include/OpensbiTypes.h
+++ b/RiscVPkg/Include/OpensbiTypes.h
@@ -1,7 +1,7 @@
/** @file
- RISC-V OpesbSBI header file reference.
+ RISC-V OpensbiSBI header file reference.
- Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+ Copyright (c) 2020-2022, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
diff --git a/RiscVPkg/Include/ProcessorSpecificHobData.h b/RiscVPkg/Include/ProcessorSpecificHobData.h
index 97285289f7..4b2a92e2f2 100644
--- a/RiscVPkg/Include/ProcessorSpecificHobData.h
+++ b/RiscVPkg/Include/ProcessorSpecificHobData.h
@@ -29,7 +29,7 @@ typedef struct {
EFI_GUID CoreGuid;
VOID *Context; // The additional information of this core which
// built in PEI phase and carried to DXE phase.
- // The content is pocessor or platform specific.
+ // The content is processor or platform specific.
SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA ProcessorSpecificData;
} RISC_V_PROCESSOR_SPECIFIC_HOB_DATA;
diff --git a/RiscVPkg/Include/SmbiosProcessorSpecificData.h b/RiscVPkg/Include/SmbiosProcessorSpecificData.h
index 81e48cd068..85b8dcbe20 100644
--- a/RiscVPkg/Include/SmbiosProcessorSpecificData.h
+++ b/RiscVPkg/Include/SmbiosProcessorSpecificData.h
@@ -1,9 +1,9 @@
/** @file
Industry Standard Definitions of RISC-V Processor Specific data defined in
- below link for complaiant with SMBIOS Table Specification v3.3.0.
+ below link for compliant with SMBIOS Table Specification v3.3.0.
https://github.com/riscv/riscv-smbios
- Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+ Copyright (c) 2019-2022, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
diff --git a/RiscVPkg/Library/RiscVEdk2SbiLib/RiscVEdk2SbiLib.c b/RiscVPkg/Library/RiscVEdk2SbiLib/RiscVEdk2SbiLib.c
index 319526ed8f..a51139542d 100644
--- a/RiscVPkg/Library/RiscVEdk2SbiLib/RiscVEdk2SbiLib.c
+++ b/RiscVPkg/Library/RiscVEdk2SbiLib/RiscVEdk2SbiLib.c
@@ -15,7 +15,7 @@
- SbiLegacyRemoteSfenceVmaAsid -> Use SbiRemoteSfenceVmaAsid
- SbiLegacyShutdown -> Wait for new System Reset extension
- Copyright (c) 2021, Hewlett Packard Development LP. All rights reserved.<BR>
+ Copyright (c) 2021-2022, Hewlett Packard Development LP. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@par Revision Reference:
@@ -173,7 +173,7 @@ SbiGetSpecVersion (
/**
Get the SBI implementation ID
- This ID is used to idenetify a specific SBI implementation in order to work
+ This ID is used to identify a specific SBI implementation in order to work
around any quirks it might have.
@param[out] ImplId The ID of the SBI implementation.
@@ -441,7 +441,7 @@ SbiRemoteFenceI (
/**
Instructs the remote harts to execute one or more SFENCE.VMA instructions.
- The SFENCE.VMA covers the range of virtual addresses between StartAaddr and Size.
+ The SFENCE.VMA covers the range of virtual addresses between StartAddr and Size.
The remote fence function acts as a full tlb flush if * StartAddr and size
are both 0 * size is equal to 2^XLEN-1
@@ -483,7 +483,7 @@ SbiRemoteSfenceVma (
/**
Instructs the remote harts to execute one or more SFENCE.VMA instructions.
- The SFENCE.VMA covers the range of virtual addresses between StartAaddr and Size.
+ The SFENCE.VMA covers the range of virtual addresses between StartAddr and Size.
Covers only the given ASID.
The remote fence function acts as a full tlb flush if * StartAddr and size
@@ -528,7 +528,7 @@ SbiRemoteSfenceVmaAsid (
/**
Instructs the remote harts to execute one or more SFENCE.GVMA instructions.
- The SFENCE.GVMA covers the range of virtual addresses between StartAaddr and Size.
+ The SFENCE.GVMA covers the range of virtual addresses between StartAddr and Size.
Covers only the given VMID.
This function call is only valid for harts implementing the hypervisor extension.
@@ -577,7 +577,7 @@ SbiRemoteHFenceGvmaVmid (
/**
Instructs the remote harts to execute one or more SFENCE.GVMA instructions.
- The SFENCE.GVMA covers the range of virtual addresses between StartAaddr and Size.
+ The SFENCE.GVMA covers the range of virtual addresses between StartAddr and Size.
This function call is only valid for harts implementing the hypervisor extension.
The remote fence function acts as a full tlb flush if * StartAddr and size
@@ -623,7 +623,7 @@ SbiRemoteHFenceGvma (
/**
Instructs the remote harts to execute one or more SFENCE.VVMA instructions.
- The SFENCE.GVMA covers the range of virtual addresses between StartAaddr and Size.
+ The SFENCE.GVMA covers the range of virtual addresses between StartAddr and Size.
Covers only the given ASID.
This function call is only valid for harts implementing the hypervisor extension.
@@ -672,7 +672,7 @@ SbiRemoteHFenceVvmaAsid (
/**
Instructs the remote harts to execute one or more SFENCE.VVMA instructions.
- The SFENCE.GVMA covers the range of virtual addresses between StartAaddr and Size.
+ The SFENCE.GVMA covers the range of virtual addresses between StartAddr and Size.
This function call is only valid for harts implementing the hypervisor extension.
The remote fence function acts as a full tlb flush if * StartAddr and size
diff --git a/RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerLib.c b/RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerLib.c
index a9316ae758..43130336f3 100644
--- a/RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerLib.c
+++ b/RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerLib.c
@@ -1,7 +1,7 @@
/** @file
- RISC-V Exception Handler library implementition.
+ RISC-V Exception Handler library implementation.
- Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+ Copyright (c) 2016 - 2022, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -186,7 +186,7 @@ CpuExceptionHandlerLibConstructor (
)
{
//
- // Set Superviosr mode trap handler.
+ // Set Supervisor mode trap handler.
//
csr_write(CSR_STVEC, SupervisorModeTrap);
diff --git a/RiscVPkg/Library/RiscVFirmwareContextSbiLib/RiscVFirmwareContextSbiLib.c b/RiscVPkg/Library/RiscVFirmwareContextSbiLib/RiscVFirmwareContextSbiLib.c
index 6125618eaf..a2a18d3eb7 100644
--- a/RiscVPkg/Library/RiscVFirmwareContextSbiLib/RiscVFirmwareContextSbiLib.c
+++ b/RiscVPkg/Library/RiscVFirmwareContextSbiLib/RiscVFirmwareContextSbiLib.c
@@ -1,8 +1,8 @@
/** @file
- This iinstance uses RISC-V OpenSBI Firmware Extension SBI to
+ This instance uses RISC-V OpenSBI Firmware Extension SBI to
get the pointer of firmware context.
- Copyright (c) 2021 Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+ Copyright (c) 2021-2022 Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
diff --git a/RiscVPkg/Library/RiscVFirmwareContextStvecLib/RiscVFirmwareContextStvecLib.c b/RiscVPkg/Library/RiscVFirmwareContextStvecLib/RiscVFirmwareContextStvecLib.c
index 7d1675355a..d08b51d3d9 100644
--- a/RiscVPkg/Library/RiscVFirmwareContextStvecLib/RiscVFirmwareContextStvecLib.c
+++ b/RiscVPkg/Library/RiscVFirmwareContextStvecLib/RiscVFirmwareContextStvecLib.c
@@ -1,8 +1,8 @@
/** @file
- This instance uses This iinstance Supervisor mode STVEC CSR to
+ This instance uses This instance Supervisor mode STVEC CSR to
get/set the pointer of firmware context.
- Copyright (c) 2021 Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+ Copyright (c) 2021-2022 Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
--
2.31.1
next prev parent reply other threads:[~2022-01-08 8:28 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-01-08 7:27 [PATCH 62/79] RiscVPlatformPkg: Rename PlatformPkg to RiscVPlatformPkg Abner Chang
2022-01-08 7:27 ` [PATCH 63/79] RiscVPkg: Rename ProcessorPkg to RiscVPkg Abner Chang
2022-01-08 7:27 ` [PATCH 64/79] RiscVPkg: Fix build fail on RiscVPkg package Abner Chang
2022-01-08 7:27 ` [PATCH 65/79] RiscVPkg/PlatformPei: Fix the build error Abner Chang
2022-01-08 7:27 ` [PATCH 66/79] edk2:.gitmodules Abner Chang
2022-01-08 7:27 ` [PATCH 67/79] RiscVPlatformPkg: Address Core CI ECC errors Abner Chang
2022-01-08 7:27 ` [PATCH 68/79] RiscVPlatformVPkg: Address Core CI Spelling errors Abner Chang
2022-01-08 7:27 ` [PATCH 69/79] RiscVPlatformVPkg: Address Core CI package dependency check errors Abner Chang
2022-01-08 7:27 ` [PATCH 70/79] RiscVPlatformVPkg: Address Core CI license " Abner Chang
2022-01-08 7:27 ` [PATCH 71/79] RiscVPlatformVPkg: Address Core CI library header " Abner Chang
2022-01-08 7:27 ` [PATCH 72/79] RiscVPlatformVPkg: Address Core CI Uncrustify errors Abner Chang
2022-01-08 7:27 ` [PATCH 73/79] RiscVPkg: Address Core CI ECC errors Abner Chang
2022-01-08 7:27 ` [PATCH 74/79] RiscVPkg: Address Core CI library header check errors Abner Chang
2022-01-08 7:27 ` Abner Chang [this message]
2022-01-08 7:27 ` [PATCH 76/79] RiscVPkg: Address Core CI Uncrustify errors Abner Chang
2022-01-08 7:27 ` [PATCH 77/79] edk2: RiscVPlatformPkg Core CI YAML file Abner Chang
2022-01-08 7:27 ` [PATCH 78/79] edk2: RiscVPkg " Abner Chang
2022-01-08 7:27 ` [PATCH 79/79] edk2: Enable Core CI on RiscV*Pkg Abner Chang
[not found] <20220108041420.16064-1-abner.chang@hpe.com>
[not found] ` <20220108041420.16064-14-abner.chang@hpe.com>
2022-01-09 15:39 ` [PATCH 75/79] RiscVPkg: Address Core CI Spelling errors Sunil V L
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