From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mx0a-002e3701.pphosted.com (mx0a-002e3701.pphosted.com [148.163.147.86]) by mx.groups.io with SMTP id smtpd.web10.3744.1641630521492859242 for ; Sat, 08 Jan 2022 00:28:41 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@hpe.com header.s=pps0720 header.b=OlgWJ33b; spf=permerror, err=parse error for token &{10 18 %{ir}.%{v}.%{d}.spf.has.pphosted.com}: invalid domain name (domain: hpe.com, ip: 148.163.147.86, mailfrom: prvs=000704d8ca=abner.chang@hpe.com) Received: from pps.filterd (m0134422.ppops.net [127.0.0.1]) by mx0b-002e3701.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 20851r3R008586; Sat, 8 Jan 2022 08:28:41 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=hpe.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding; s=pps0720; bh=LrhiE5Q3ZZDPny0T8DO2FL7ts+/NFDaS4whx8oE5Olc=; b=OlgWJ33bY8DyQR4wqPSI9LnWgR11ygGp25yngrGVRlzxjnsKXs/vKzfbRm56z6a6Yrdp Tx6ClOczJNUv+7zoMnHeAh+10FRUT++iFrFIXwYwy6oKrPcbfmHtwFPSEeqoeU0cqN6I tT2cpXzzerqUjk9EdWgi/V+fpazF4PmHDfKwjdYgrx2GYHk5uuxADmsBF5V1B+jZuOxK yfc9gtB2L4sZvq2ARVLbkHeXFRECdKoTTZw8RRpQ8rbcgfJUU7fBe+/lEHLGsju8jhJq E6ga+7UWRUWYOhy3tXx5qG5Wrfs7lZt0Q0O1Dcr6Yiz+6obwmkLg9mxZh0ctR6ds+4PV 4A== Received: from g2t2352.austin.hpe.com (g2t2352.austin.hpe.com [15.233.44.25]) by mx0b-002e3701.pphosted.com (PPS) with ESMTPS id 3df40k8pw5-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Sat, 08 Jan 2022 08:28:40 +0000 Received: from g2t2360.austin.hpecorp.net (g2t2360.austin.hpecorp.net [16.196.225.135]) by g2t2352.austin.hpe.com (Postfix) with ESMTP id 3799B62; Sat, 8 Jan 2022 08:28:40 +0000 (UTC) Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.229]) by g2t2360.austin.hpecorp.net (Postfix) with ESMTP id F392D3A; Sat, 8 Jan 2022 08:28:38 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com, Daniel Schaefer , Sunil V L Subject: [PATCH 63/79] RiscVPkg: Rename ProcessorPkg to RiscVPkg Date: Sat, 8 Jan 2022 15:27:21 +0800 Message-Id: <20220108072737.17962-2-abner.chang@hpe.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20220108072737.17962-1-abner.chang@hpe.com> References: <20220108072737.17962-1-abner.chang@hpe.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: 0VRZP-KBYWcdpkzPcJPkyaZW3Rj2CPob X-Proofpoint-GUID: 0VRZP-KBYWcdpkzPcJPkyaZW3Rj2CPob X-HPE-SCL: -1 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.790,Hydra:6.0.425,FMLib:17.11.62.513 definitions=2022-01-08_03,2022-01-07_01,2021-12-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 adultscore=0 priorityscore=1501 malwarescore=0 spamscore=0 clxscore=1015 phishscore=0 impostorscore=0 mlxscore=0 mlxlogscore=999 bulkscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2110150000 definitions=main-2201080064 Content-Transfer-Encoding: quoted-printable ProcessorPkg is migrated from edk2-platforms for RISC-V (Silicon/RISC-V/ProcessorPkg). Rename it to RiscVPkg under edk2. Signed-off-by: Abner Chang Cc: Daniel Schaefer Cc: Sunil V L --- .../RiscVPkg.dec | 6 +- .../RiscVPkg.dsc | 58 +++++++++---------- RiscVPlatformPkg/RiscVPlatformPkg.dsc | 6 +- .../PeiServicesTablePointerLibOpenSbi.inf | 2 +- .../Library/RiscVCpuLib/RiscVCpuLib.inf | 2 +- .../RiscVEdk2SbiLib/RiscVEdk2SbiLib.inf | 4 +- .../CpuExceptionHandlerDxeLib.inf | 2 +- .../RiscVFirmwareContextSbiLib.inf | 2 +- .../RiscVFirmwareContextSscratchLib.inf | 2 +- .../RiscVFirmwareContextStvecLib.inf | 2 +- .../RiscVOpensbiLib/RiscVOpensbiLib.inf | 2 +- .../RiscVPlatformTimerLib.inf | 0 .../EmulatedMachineModeTimerLib.inf | 2 +- .../MachineModeTimerLib.inf | 2 +- .../RiscVTimerLib/BaseRiscVTimerLib.inf | 2 +- .../Universal/CpuDxe/CpuDxe.inf | 2 +- .../Universal/FdtDxe/FdtDxe.inf | 2 +- .../Universal/PciCpuIo2Dxe/PciCpuIo2Dxe.inf | 0 .../Universal/SmbiosDxe/RiscVSmbiosDxe.inf | 2 +- .../Edk2OpensbiPlatformWrapperLib.inf | 2 +- .../FirmwareContextProcessorSpecificLib.inf | 2 +- .../OpensbiPlatformLib/OpensbiPlatformLib.inf | 2 +- .../PeiCoreEntryPoint/PeiCoreEntryPoint.inf | 2 +- .../PeiCoreInfoHobLib.inf | 2 +- .../PlatformSecPpiLibNull.inf | 1 - .../Library/ResetSystemLib/ResetSystemLib.inf | 2 +- .../RiscVSpecialPlatformLibNull.inf | 2 +- .../Universal/FdtPeim/FdtPeim.inf | 2 +- .../Universal/Pei/PlatformPei/PlatformPei.inf | 2 +- RiscVPlatformPkg/Universal/Sec/SecMain.inf | 2 +- .../Include/IndustryStandard/RiscV.h | 0 .../Include/IndustryStandard/RiscVOpensbi.h | 0 .../Include/Library/RiscVCpuLib.h | 0 .../Include/Library/RiscVEdk2SbiLib.h | 0 .../Include/Library/RiscVFirmwareContextLib.h | 0 .../Include/OpensbiTypes.h | 0 .../Include/ProcessorSpecificHobData.h | 0 .../Include/RiscVImpl.h | 0 .../Include/SmbiosProcessorSpecificData.h | 0 .../CpuExceptionHandlerLib.h | 0 .../Universal/CpuDxe/CpuDxe.h | 0 .../Universal/SmbiosDxe/RiscVSmbiosDxe.h | 0 .../PeiServicesTablePointerOpenSbi.c | 0 .../Library/RiscVEdk2SbiLib/RiscVEdk2SbiLib.c | 0 .../CpuExceptionHandlerLib.c | 0 .../RiscVFirmwareContextSbiLib.c | 0 .../RiscVFirmwareContextSscratchLib.c | 0 .../RiscVFirmwareContextStvecLib.c | 0 .../Library/RiscVTimerLib/RiscVTimerLib.c | 0 .../Universal/CpuDxe/CpuDxe.c | 0 .../Universal/FdtDxe/FdtDxe.c | 0 .../Universal/PciCpuIo2Dxe/PciCpuIo2Dxe.c | 0 .../Universal/SmbiosDxe/RiscVSmbiosDxe.c | 0 .../PeiServicesTablePointerLibOpenSbi.uni | 0 .../Library/RiscVCpuLib/Cpu.S | 0 .../CpuExceptionHandlerLib.uni | 0 .../RiscVExceptionLib/SupervisorTrapHandler.S | 0 .../RiscVPlatformTimerLibNull.S | 0 .../EmulatedMachineModeTimerLib.S | 0 .../MachineModeTimerLib/MachineModeTimerLib.S | 0 .../RiscVPkg.uni | 2 +- .../RiscVPkgExtra.uni | 2 +- .../Universal/CpuDxe/CpuDxe.uni | 0 .../Universal/CpuDxe/CpuDxeExtra.uni | 0 .../Universal/SmbiosDxe/RiscVSmbiosDxe.uni | 0 .../SmbiosDxe/RiscVSmbiosDxeExtra.uni | 0 .../Library/RiscVOpensbiLib/opensbi | 1 - 67 files changed, 62 insertions(+), 64 deletions(-) rename Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec =3D> RiscVPkg/Ris= cVPkg.dec (92%) rename Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dsc =3D> RiscVPkg/Ris= cVPkg.dsc (54%) rename {Silicon/RISC-V/ProcessorPkg =3D> RiscVPkg}/Library/PeiServicesTabl= ePointerLibOpenSbi/PeiServicesTablePointerLibOpenSbi.inf (92%) rename {Silicon/RISC-V/ProcessorPkg =3D> RiscVPkg}/Library/RiscVCpuLib/Ris= cVCpuLib.inf (89%) rename {Silicon/RISC-V/ProcessorPkg =3D> RiscVPkg}/Library/RiscVEdk2SbiLib= /RiscVEdk2SbiLib.inf (79%) rename {Silicon/RISC-V/ProcessorPkg =3D> RiscVPkg}/Library/RiscVExceptionL= ib/CpuExceptionHandlerDxeLib.inf (91%) rename {Silicon/RISC-V/ProcessorPkg =3D> RiscVPkg}/Library/RiscVFirmwareCo= ntextSbiLib/RiscVFirmwareContextSbiLib.inf (90%) rename {Silicon/RISC-V/ProcessorPkg =3D> RiscVPkg}/Library/RiscVFirmwareCo= ntextSscratchLib/RiscVFirmwareContextSscratchLib.inf (90%) rename {Silicon/RISC-V/ProcessorPkg =3D> RiscVPkg}/Library/RiscVFirmwareCo= ntextStvecLib/RiscVFirmwareContextStvecLib.inf (89%) rename {Silicon/RISC-V/ProcessorPkg =3D> RiscVPkg}/Library/RiscVOpensbiLib= /RiscVOpensbiLib.inf (95%) rename {Silicon/RISC-V/ProcessorPkg =3D> RiscVPkg}/Library/RiscVPlatformTi= merLibNull/RiscVPlatformTimerLib.inf (100%) rename {Silicon/RISC-V/ProcessorPkg =3D> RiscVPkg}/Library/RiscVReadMachin= eModeTimer/EmulatedMachineModeTimerLib/EmulatedMachineModeTimerLib.inf (89%) rename {Silicon/RISC-V/ProcessorPkg =3D> RiscVPkg}/Library/RiscVReadMachin= eModeTimer/MachineModeTimerLib/MachineModeTimerLib.inf (89%) rename {Silicon/RISC-V/ProcessorPkg =3D> RiscVPkg}/Library/RiscVTimerLib/B= aseRiscVTimerLib.inf (88%) rename {Silicon/RISC-V/ProcessorPkg =3D> RiscVPkg}/Universal/CpuDxe/CpuDxe= .inf (91%) rename {Silicon/RISC-V/ProcessorPkg =3D> RiscVPkg}/Universal/FdtDxe/FdtDxe= .inf (90%) rename {Silicon/RISC-V/ProcessorPkg =3D> RiscVPkg}/Universal/PciCpuIo2Dxe/= PciCpuIo2Dxe.inf (100%) rename {Silicon/RISC-V/ProcessorPkg =3D> RiscVPkg}/Universal/SmbiosDxe/Ris= cVSmbiosDxe.inf (92%) rename {Silicon/RISC-V/ProcessorPkg =3D> RiscVPkg}/Include/IndustryStandar= d/RiscV.h (100%) rename {Silicon/RISC-V/ProcessorPkg =3D> RiscVPkg}/Include/IndustryStandar= d/RiscVOpensbi.h (100%) rename {Silicon/RISC-V/ProcessorPkg =3D> RiscVPkg}/Include/Library/RiscVCp= uLib.h (100%) rename {Silicon/RISC-V/ProcessorPkg =3D> RiscVPkg}/Include/Library/RiscVEd= k2SbiLib.h (100%) rename {Silicon/RISC-V/ProcessorPkg =3D> RiscVPkg}/Include/Library/RiscVFi= rmwareContextLib.h (100%) rename {Silicon/RISC-V/ProcessorPkg =3D> RiscVPkg}/Include/OpensbiTypes.h = (100%) rename {Silicon/RISC-V/ProcessorPkg =3D> RiscVPkg}/Include/ProcessorSpecif= icHobData.h (100%) rename {Silicon/RISC-V/ProcessorPkg =3D> RiscVPkg}/Include/RiscVImpl.h (10= 0%) rename {Silicon/RISC-V/ProcessorPkg =3D> RiscVPkg}/Include/SmbiosProcessor= SpecificData.h (100%) rename {Silicon/RISC-V/ProcessorPkg =3D> RiscVPkg}/Library/RiscVExceptionL= ib/CpuExceptionHandlerLib.h (100%) rename {Silicon/RISC-V/ProcessorPkg =3D> RiscVPkg}/Universal/CpuDxe/CpuDxe= .h (100%) rename {Silicon/RISC-V/ProcessorPkg =3D> RiscVPkg}/Universal/SmbiosDxe/Ris= cVSmbiosDxe.h (100%) rename {Silicon/RISC-V/ProcessorPkg =3D> RiscVPkg}/Library/PeiServicesTabl= ePointerLibOpenSbi/PeiServicesTablePointerOpenSbi.c (100%) rename {Silicon/RISC-V/ProcessorPkg =3D> RiscVPkg}/Library/RiscVEdk2SbiLib= /RiscVEdk2SbiLib.c (100%) rename {Silicon/RISC-V/ProcessorPkg =3D> RiscVPkg}/Library/RiscVExceptionL= ib/CpuExceptionHandlerLib.c (100%) rename {Silicon/RISC-V/ProcessorPkg =3D> RiscVPkg}/Library/RiscVFirmwareCo= ntextSbiLib/RiscVFirmwareContextSbiLib.c (100%) rename {Silicon/RISC-V/ProcessorPkg =3D> RiscVPkg}/Library/RiscVFirmwareCo= ntextSscratchLib/RiscVFirmwareContextSscratchLib.c (100%) rename {Silicon/RISC-V/ProcessorPkg =3D> RiscVPkg}/Library/RiscVFirmwareCo= ntextStvecLib/RiscVFirmwareContextStvecLib.c (100%) rename {Silicon/RISC-V/ProcessorPkg =3D> RiscVPkg}/Library/RiscVTimerLib/R= iscVTimerLib.c (100%) rename {Silicon/RISC-V/ProcessorPkg =3D> RiscVPkg}/Universal/CpuDxe/CpuDxe= .c (100%) rename {Silicon/RISC-V/ProcessorPkg =3D> RiscVPkg}/Universal/FdtDxe/FdtDxe= .c (100%) rename {Silicon/RISC-V/ProcessorPkg =3D> RiscVPkg}/Universal/PciCpuIo2Dxe/= PciCpuIo2Dxe.c (100%) rename {Silicon/RISC-V/ProcessorPkg =3D> RiscVPkg}/Universal/SmbiosDxe/Ris= cVSmbiosDxe.c (100%) rename {Silicon/RISC-V/ProcessorPkg =3D> RiscVPkg}/Library/PeiServicesTabl= ePointerLibOpenSbi/PeiServicesTablePointerLibOpenSbi.uni (100%) rename {Silicon/RISC-V/ProcessorPkg =3D> RiscVPkg}/Library/RiscVCpuLib/Cpu= .S (100%) rename {Silicon/RISC-V/ProcessorPkg =3D> RiscVPkg}/Library/RiscVExceptionL= ib/CpuExceptionHandlerLib.uni (100%) rename {Silicon/RISC-V/ProcessorPkg =3D> RiscVPkg}/Library/RiscVExceptionL= ib/SupervisorTrapHandler.S (100%) rename {Silicon/RISC-V/ProcessorPkg =3D> RiscVPkg}/Library/RiscVPlatformTi= merLibNull/RiscVPlatformTimerLibNull.S (100%) rename {Silicon/RISC-V/ProcessorPkg =3D> RiscVPkg}/Library/RiscVReadMachin= eModeTimer/EmulatedMachineModeTimerLib/EmulatedMachineModeTimerLib.S (100%) rename {Silicon/RISC-V/ProcessorPkg =3D> RiscVPkg}/Library/RiscVReadMachin= eModeTimer/MachineModeTimerLib/MachineModeTimerLib.S (100%) rename Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.uni =3D> RiscVPkg/Ris= cVPkg.uni (85%) rename Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkgExtra.uni =3D> RiscVPk= g/RiscVPkgExtra.uni (87%) rename {Silicon/RISC-V/ProcessorPkg =3D> RiscVPkg}/Universal/CpuDxe/CpuDxe= .uni (100%) rename {Silicon/RISC-V/ProcessorPkg =3D> RiscVPkg}/Universal/CpuDxe/CpuDxe= Extra.uni (100%) rename {Silicon/RISC-V/ProcessorPkg =3D> RiscVPkg}/Universal/SmbiosDxe/Ris= cVSmbiosDxe.uni (100%) rename {Silicon/RISC-V/ProcessorPkg =3D> RiscVPkg}/Universal/SmbiosDxe/Ris= cVSmbiosDxeExtra.uni (100%) delete mode 160000 Silicon/RISC-V/ProcessorPkg/Library/RiscVOpensbiLib/ope= nsbi diff --git a/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec b/RiscVPkg/R= iscVPkg.dec similarity index 92% rename from Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec rename to RiscVPkg/RiscVPkg.dec index 9c8b57cce3..f23d3c0135 100644 --- a/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec +++ b/RiscVPkg/RiscVPkg.dec @@ -9,8 +9,8 @@ =0D [Defines]=0D DEC_SPECIFICATION =3D 0x0001001b=0D - PACKAGE_NAME =3D RiscVProcessorPkg=0D - PACKAGE_UNI_FILE =3D RiscVProcessorPkg.uni=0D + PACKAGE_NAME =3D RiscVPkg=0D + PACKAGE_UNI_FILE =3D RiscVPkg.uni=0D PACKAGE_GUID =3D 993C7CAC-C87C-4F08-A2CF-AD3AABA859D1= =0D PACKAGE_VERSION =3D 1.0=0D =0D @@ -46,4 +46,4 @@ gUefiRiscVPkgTokenSpaceGuid.PcdRiscVMachineTimerFrequencyInHerz|10000000= |UINT64|0x00001011=0D =0D [UserExtensions.TianoCore."ExtraFiles"]=0D - RiscVProcessorPkgExtra.uni=0D + RiscVPkgExtra.uni=0D diff --git a/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dsc b/RiscVPkg/R= iscVPkg.dsc similarity index 54% rename from Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dsc rename to RiscVPkg/RiscVPkg.dsc index 5c7425421b..41933160d6 100644 --- a/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dsc +++ b/RiscVPkg/RiscVPkg.dsc @@ -1,5 +1,5 @@ #/** @file=0D -# RISC-V processor package.=0D +# RISC-V package.=0D #=0D # Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All right= s reserved.
=0D #=0D @@ -13,7 +13,7 @@ #=0D ##########################################################################= ######=0D [Defines]=0D - PLATFORM_NAME =3D RiscVProcessor=0D + PLATFORM_NAME =3D RiscV=0D PLATFORM_GUID =3D 55D77916-B270-41B4-9325-2CE9DCE0926E= =0D PLATFORM_VERSION =3D 0.1=0D DSC_SPECIFICATION =3D 0x0001001c=0D @@ -39,13 +39,13 @@ !include MdePkg/MdeLibs.dsc.inc=0D =0D [LibraryClasses.common]=0D - CpuExceptionHandlerLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVExceptio= nLib/CpuExceptionHandlerDxeLib.inf=0D - RiscVCpuLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVCpuLib/RiscVCpuLib.= inf=0D - RiscVEdk2SbiLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVEdk2SbiLib/Risc= VEdk2SbiLib.inf=0D - RiscVOpensbiLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVOpensbiLib/Risc= VOpensbiLib.inf=0D - TimerLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVTimerLib/BaseRiscVTime= rLib.inf=0D - MachineModeTimerLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVReadMachine= ModeTimer/MachineModeTimerLib/MachineModeTimerLib.inf=0D - #MachineModeTimerLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVReadMachin= eModeTimer/EmulatedMachineModeTimerLib/EmulatedMachineModeTimerLib.inf=0D + CpuExceptionHandlerLib|RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHa= ndlerDxeLib.inf=0D + RiscVCpuLib|RiscVPkg/Library/RiscVCpuLib/RiscVCpuLib.inf=0D + RiscVEdk2SbiLib|RiscVPkg/Library/RiscVEdk2SbiLib/RiscVEdk2SbiLib.inf=0D + RiscVOpensbiLib|RiscVPkg/Library/RiscVOpensbiLib/RiscVOpensbiLib.inf=0D + TimerLib|RiscVPkg/Library/RiscVTimerLib/BaseRiscVTimerLib.inf=0D + MachineModeTimerLib|RiscVPkg/Library/RiscVReadMachineModeTimer/MachineMo= deTimerLib/MachineModeTimerLib.inf=0D + #MachineModeTimerLib|RiscVPkg/Library/RiscVReadMachineModeTimer/Emulated= MachineModeTimerLib/EmulatedMachineModeTimerLib.inf=0D BaseLib|MdePkg/Library/BaseLib/BaseLib.inf=0D BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf=0D DebugAgentLib|MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLibNull.i= nf=0D @@ -66,43 +66,43 @@ UefiApplicationEntryPoint|MdePkg/Library/UefiApplicationEntryPoint/UefiA= pplicationEntryPoint.inf=0D UefiLib|MdePkg/Library/UefiLib/UefiLib.inf=0D DevicePathLib|MdePkg/Library/UefiDevicePathLibDevicePathProtocol/UefiDev= icePathLibDevicePathProtocol.inf=0D - RiscVPlatformTimerLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVPlatformT= imerLibNull/RiscVPlatformTimerLib.inf=0D + RiscVPlatformTimerLib|RiscVPkg/Library/RiscVPlatformTimerLibNull/RiscVPl= atformTimerLib.inf=0D =0D [LibraryClasses.common.PEI_CORE]=0D - PeiServicesTablePointerLib|Silicon/RISC-V/ProcessorPkg/Library/PeiServic= esTablePointerLibOpenSbi/PeiServicesTablePointerLibOpenSbi.inf=0D - RiscVFirmwareContextLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwar= eContextSbiLib/RiscVFirmwareContextSbiLib.inf=0D + PeiServicesTablePointerLib|RiscVPkg/Library/PeiServicesTablePointerLibOp= enSbi/PeiServicesTablePointerLibOpenSbi.inf=0D + RiscVFirmwareContextLib|RiscVPkg/Library/RiscVFirmwareContextSbiLib/Risc= VFirmwareContextSbiLib.inf=0D =0D [LibraryClasses.common.PEIM]=0D - PeiServicesTablePointerLib|Silicon/RISC-V/ProcessorPkg/Library/PeiServic= esTablePointerLibOpenSbi/PeiServicesTablePointerLibOpenSbi.inf=0D - RiscVFirmwareContextLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwar= eContextSbiLib/RiscVFirmwareContextSbiLib.inf=0D + PeiServicesTablePointerLib|RiscVPkg/Library/PeiServicesTablePointerLibOp= enSbi/PeiServicesTablePointerLibOpenSbi.inf=0D + RiscVFirmwareContextLib|RiscVPkg/Library/RiscVFirmwareContextSbiLib/Risc= VFirmwareContextSbiLib.inf=0D HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf=0D MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAlloc= ationLib.inf=0D PeimEntryPoint|MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf=0D =0D [LibraryClasses.common.DXE_CORE]=0D - TimerLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVTimerLib/BaseRiscVTime= rLib.inf=0D + TimerLib|RiscVPkg/Library/RiscVTimerLib/BaseRiscVTimerLib.inf=0D =0D [LibraryClasses.common.DXE_DRIVER]=0D PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf=0D PlatformBootManagerLib|Platform/RISC-V/PlatformPkg/Library/PlatformBootM= anagerLib/PlatformBootManagerLib.inf=0D =0D [LibraryClasses.common.DXE_RUNTIME_DRIVER]=0D - TimerLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVTimerLib/BaseRiscVTime= rLib.inf=0D + TimerLib|RiscVPkg/Library/RiscVTimerLib/BaseRiscVTimerLib.inf=0D =0D [LibraryClasses.common.UEFI_DRIVER]=0D - TimerLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVTimerLib/BaseRiscVTime= rLib.inf=0D + TimerLib|RiscVPkg/Library/RiscVTimerLib/BaseRiscVTimerLib.inf=0D =0D [Components]=0D - Silicon/RISC-V/ProcessorPkg/Library/RiscVTimerLib/BaseRiscVTimerLib.inf= =0D - Silicon/RISC-V/ProcessorPkg/Library/RiscVExceptionLib/CpuExceptionHandle= rDxeLib.inf=0D - Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSbiLib/RiscVFirm= wareContextSbiLib.inf=0D - Silicon/RISC-V/ProcessorPkg/Library/PeiServicesTablePointerLibOpenSbi/Pe= iServicesTablePointerLibOpenSbi.inf=0D - Silicon/RISC-V/ProcessorPkg/Library/RiscVOpensbiLib/RiscVOpensbiLib.inf= =0D - Silicon/RISC-V/ProcessorPkg/Library/RiscVPlatformTimerLibNull/RiscVPlatf= ormTimerLib.inf=0D - Silicon/RISC-V/ProcessorPkg/Library/RiscVCpuLib/RiscVCpuLib.inf=0D - Silicon/RISC-V/ProcessorPkg/Library/RiscVEdk2SbiLib/RiscVEdk2SbiLib.inf= =0D + RiscVPkg/Library/RiscVTimerLib/BaseRiscVTimerLib.inf=0D + RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerDxeLib.inf=0D + RiscVPkg/Library/RiscVFirmwareContextSbiLib/RiscVFirmwareContextSbiLib.i= nf=0D + RiscVPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePoint= erLibOpenSbi.inf=0D + RiscVPkg/Library/RiscVOpensbiLib/RiscVOpensbiLib.inf=0D + RiscVPkg/Library/RiscVPlatformTimerLibNull/RiscVPlatformTimerLib.inf=0D + RiscVPkg/Library/RiscVCpuLib/RiscVCpuLib.inf=0D + RiscVPkg/Library/RiscVEdk2SbiLib/RiscVEdk2SbiLib.inf=0D =0D - Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxe.inf=0D - Silicon/RISC-V/ProcessorPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.inf=0D - Silicon/RISC-V/ProcessorPkg/Universal/FdtDxe/FdtDxe.inf=0D - Silicon/RISC-V/ProcessorPkg/Universal/PciCpuIo2Dxe/PciCpuIo2Dxe.inf=0D + RiscVPkg/Universal/CpuDxe/CpuDxe.inf=0D + RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.inf=0D + RiscVPkg/Universal/FdtDxe/FdtDxe.inf=0D + RiscVPkg/Universal/PciCpuIo2Dxe/PciCpuIo2Dxe.inf=0D diff --git a/RiscVPlatformPkg/RiscVPlatformPkg.dsc b/RiscVPlatformPkg/RiscV= PlatformPkg.dsc index 2997465170..f7f5c3f7cd 100644 --- a/RiscVPlatformPkg/RiscVPlatformPkg.dsc +++ b/RiscVPlatformPkg/RiscVPlatformPkg.dsc @@ -41,8 +41,8 @@ [LibraryClasses.common]=0D FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib.inf=0D RiscVOpensbiPlatformLib|RiscVPlatformPkg/Library/OpensbiPlatformLib/Open= sbiPlatformLib.inf=0D - RiscVCpuLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVCpuLib/RiscVCpuLib.= inf=0D - RiscVEdk2SbiLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVEdk2SbiLib/Risc= VEdk2SbiLib.inf=0D + RiscVCpuLib|RiscVPkg/Library/RiscVCpuLib/RiscVCpuLib.inf=0D + RiscVEdk2SbiLib|RiscVPkg/Library/RiscVEdk2SbiLib/RiscVEdk2SbiLib.inf=0D BaseLib|MdePkg/Library/BaseLib/BaseLib.inf=0D BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf=0D DebugAgentLib|MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLibNull.i= nf=0D @@ -71,7 +71,7 @@ =0D [LibraryClasses.common.SEC]=0D ExtractGuidedSectionLib|MdePkg/Library/BaseExtractGuidedSectionLib/BaseE= xtractGuidedSectionLib.inf=0D - RiscVOpensbiLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVOpensbiLib/Risc= VOpensbiLib.inf=0D + RiscVOpensbiLib|RiscVPkg/Library/RiscVOpensbiLib/RiscVOpensbiLib.inf=0D Edk2OpensbiPlatformWrapperLib|RiscVPlatformPkg/Library/Edk2OpensbiPlatfo= rmWrapperLib/Edk2OpensbiPlatformWrapperLib.inf=0D RiscVSpecialPlatformLib|RiscVPlatformPkg/Library/RiscVSpecialPlatformLib= Null/RiscVSpecialPlatformLibNull.inf=0D =0D diff --git a/Silicon/RISC-V/ProcessorPkg/Library/PeiServicesTablePointerLib= OpenSbi/PeiServicesTablePointerLibOpenSbi.inf b/RiscVPkg/Library/PeiService= sTablePointerLibOpenSbi/PeiServicesTablePointerLibOpenSbi.inf similarity index 92% rename from Silicon/RISC-V/ProcessorPkg/Library/PeiServicesTablePointerLibO= penSbi/PeiServicesTablePointerLibOpenSbi.inf rename to RiscVPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTab= lePointerLibOpenSbi.inf index fa9fe78518..d821168f3b 100644 --- a/Silicon/RISC-V/ProcessorPkg/Library/PeiServicesTablePointerLibOpenSbi= /PeiServicesTablePointerLibOpenSbi.inf +++ b/RiscVPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePo= interLibOpenSbi.inf @@ -30,7 +30,7 @@ =0D [Packages]=0D MdePkg/MdePkg.dec=0D - Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec=0D + RiscVPkg/RiscVPkg.dec=0D =0D [LibraryClasses]=0D DebugLib=0D diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVCpuLib/RiscVCpuLib.in= f b/RiscVPkg/Library/RiscVCpuLib/RiscVCpuLib.inf similarity index 89% rename from Silicon/RISC-V/ProcessorPkg/Library/RiscVCpuLib/RiscVCpuLib.inf rename to RiscVPkg/Library/RiscVCpuLib/RiscVCpuLib.inf index 7928dd5536..9d44dc4343 100644 --- a/Silicon/RISC-V/ProcessorPkg/Library/RiscVCpuLib/RiscVCpuLib.inf +++ b/RiscVPkg/Library/RiscVCpuLib/RiscVCpuLib.inf @@ -29,6 +29,6 @@ [Packages]=0D MdeModulePkg/MdeModulePkg.dec=0D MdePkg/MdePkg.dec=0D - Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec=0D + RiscVPkg/RiscVPkg.dec=0D =0D =0D diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVEdk2SbiLib/RiscVEdk2S= biLib.inf b/RiscVPkg/Library/RiscVEdk2SbiLib/RiscVEdk2SbiLib.inf similarity index 79% rename from Silicon/RISC-V/ProcessorPkg/Library/RiscVEdk2SbiLib/RiscVEdk2Sb= iLib.inf rename to RiscVPkg/Library/RiscVEdk2SbiLib/RiscVEdk2SbiLib.inf index 18d6ebc2ac..75ef7c5b84 100644 --- a/Silicon/RISC-V/ProcessorPkg/Library/RiscVEdk2SbiLib/RiscVEdk2SbiLib.i= nf +++ b/RiscVPkg/Library/RiscVEdk2SbiLib/RiscVEdk2SbiLib.inf @@ -20,8 +20,8 @@ =0D [Packages]=0D MdePkg/MdePkg.dec=0D - Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec=0D - Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec=0D + RiscVPkg/RiscVPkg.dec=0D + RiscVPlatformPkg/RiscVPlatformPkg.dec=0D =0D [LibraryClasses]=0D BaseLib=0D diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVExceptionLib/CpuExcep= tionHandlerDxeLib.inf b/RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHand= lerDxeLib.inf similarity index 91% rename from Silicon/RISC-V/ProcessorPkg/Library/RiscVExceptionLib/CpuExcept= ionHandlerDxeLib.inf rename to RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerDxeLib.inf index fc200d3cca..2463bac815 100644 --- a/Silicon/RISC-V/ProcessorPkg/Library/RiscVExceptionLib/CpuExceptionHan= dlerDxeLib.inf +++ b/RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerDxeLib.inf @@ -39,5 +39,5 @@ [Packages]=0D MdePkg/MdePkg.dec=0D MdeModulePkg/MdeModulePkg.dec=0D - Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec=0D + RiscVPkg/RiscVPkg.dec=0D =0D diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSbiLib= /RiscVFirmwareContextSbiLib.inf b/RiscVPkg/Library/RiscVFirmwareContextSbiL= ib/RiscVFirmwareContextSbiLib.inf similarity index 90% rename from Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSbiLib/= RiscVFirmwareContextSbiLib.inf rename to RiscVPkg/Library/RiscVFirmwareContextSbiLib/RiscVFirmwareContextS= biLib.inf index 168b705453..db30d7e551 100644 --- a/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSbiLib/RiscVF= irmwareContextSbiLib.inf +++ b/RiscVPkg/Library/RiscVFirmwareContextSbiLib/RiscVFirmwareContextSbiLi= b.inf @@ -25,7 +25,7 @@ =0D [Packages]=0D MdePkg/MdePkg.dec=0D - Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec=0D + RiscVPkg/RiscVPkg.dec=0D =0D [LibraryClasses]=0D DebugLib=0D diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSscrat= chLib/RiscVFirmwareContextSscratchLib.inf b/RiscVPkg/Library/RiscVFirmwareC= ontextSscratchLib/RiscVFirmwareContextSscratchLib.inf similarity index 90% rename from Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSscratc= hLib/RiscVFirmwareContextSscratchLib.inf rename to RiscVPkg/Library/RiscVFirmwareContextSscratchLib/RiscVFirmwareCon= textSscratchLib.inf index 750c1cf51f..c6a74e5edc 100644 --- a/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSscratchLib/R= iscVFirmwareContextSscratchLib.inf +++ b/RiscVPkg/Library/RiscVFirmwareContextSscratchLib/RiscVFirmwareContext= SscratchLib.inf @@ -25,7 +25,7 @@ =0D [Packages]=0D MdePkg/MdePkg.dec=0D - Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec=0D + RiscVPkg/RiscVPkg.dec=0D =0D [LibraryClasses]=0D DebugLib=0D diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextStvecL= ib/RiscVFirmwareContextStvecLib.inf b/RiscVPkg/Library/RiscVFirmwareContext= StvecLib/RiscVFirmwareContextStvecLib.inf similarity index 89% rename from Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextStvecLi= b/RiscVFirmwareContextStvecLib.inf rename to RiscVPkg/Library/RiscVFirmwareContextStvecLib/RiscVFirmwareContex= tStvecLib.inf index fa894cda91..9888cac81a 100644 --- a/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextStvecLib/Risc= VFirmwareContextStvecLib.inf +++ b/RiscVPkg/Library/RiscVFirmwareContextStvecLib/RiscVFirmwareContextStv= ecLib.inf @@ -25,7 +25,7 @@ =0D [Packages]=0D MdePkg/MdePkg.dec=0D - Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec=0D + RiscVPkg/RiscVPkg.dec=0D =0D [LibraryClasses]=0D DebugLib=0D diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVOpensbiLib/RiscVOpens= biLib.inf b/RiscVPkg/Library/RiscVOpensbiLib/RiscVOpensbiLib.inf similarity index 95% rename from Silicon/RISC-V/ProcessorPkg/Library/RiscVOpensbiLib/RiscVOpensb= iLib.inf rename to RiscVPkg/Library/RiscVOpensbiLib/RiscVOpensbiLib.inf index e40a797896..31bdc9e4a7 100644 --- a/Silicon/RISC-V/ProcessorPkg/Library/RiscVOpensbiLib/RiscVOpensbiLib.i= nf +++ b/RiscVPkg/Library/RiscVOpensbiLib/RiscVOpensbiLib.inf @@ -83,7 +83,7 @@ [Packages]=0D EmbeddedPkg/EmbeddedPkg.dec # For libfdt.=0D MdePkg/MdePkg.dec=0D - Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec=0D + RiscVPkg/RiscVPkg.dec=0D =0D [BuildOptions]=0D GCC:*_*_*_PP_FLAGS =3D -D__ASSEMBLY__=0D diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVPlatformTimerLibNull/= RiscVPlatformTimerLib.inf b/RiscVPkg/Library/RiscVPlatformTimerLibNull/Risc= VPlatformTimerLib.inf similarity index 100% rename from Silicon/RISC-V/ProcessorPkg/Library/RiscVPlatformTimerLibNull/R= iscVPlatformTimerLib.inf rename to RiscVPkg/Library/RiscVPlatformTimerLibNull/RiscVPlatformTimerLib.= inf diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVReadMachineModeTimer/= EmulatedMachineModeTimerLib/EmulatedMachineModeTimerLib.inf b/RiscVPkg/Libr= ary/RiscVReadMachineModeTimer/EmulatedMachineModeTimerLib/EmulatedMachineMo= deTimerLib.inf similarity index 89% rename from Silicon/RISC-V/ProcessorPkg/Library/RiscVReadMachineModeTimer/E= mulatedMachineModeTimerLib/EmulatedMachineModeTimerLib.inf rename to RiscVPkg/Library/RiscVReadMachineModeTimer/EmulatedMachineModeTim= erLib/EmulatedMachineModeTimerLib.inf index 369028a9a6..7a21a4267c 100644 --- a/Silicon/RISC-V/ProcessorPkg/Library/RiscVReadMachineModeTimer/Emulate= dMachineModeTimerLib/EmulatedMachineModeTimerLib.inf +++ b/RiscVPkg/Library/RiscVReadMachineModeTimer/EmulatedMachineModeTimerLi= b/EmulatedMachineModeTimerLib.inf @@ -28,7 +28,7 @@ =0D [Packages]=0D MdePkg/MdePkg.dec=0D - Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec=0D + RiscVPkg/RiscVPkg.dec=0D =0D =0D =0D diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVReadMachineModeTimer/= MachineModeTimerLib/MachineModeTimerLib.inf b/RiscVPkg/Library/RiscVReadMac= hineModeTimer/MachineModeTimerLib/MachineModeTimerLib.inf similarity index 89% rename from Silicon/RISC-V/ProcessorPkg/Library/RiscVReadMachineModeTimer/M= achineModeTimerLib/MachineModeTimerLib.inf rename to RiscVPkg/Library/RiscVReadMachineModeTimer/MachineModeTimerLib/Ma= chineModeTimerLib.inf index 71d4315445..fb67ce8bba 100644 --- a/Silicon/RISC-V/ProcessorPkg/Library/RiscVReadMachineModeTimer/Machine= ModeTimerLib/MachineModeTimerLib.inf +++ b/RiscVPkg/Library/RiscVReadMachineModeTimer/MachineModeTimerLib/Machin= eModeTimerLib.inf @@ -28,7 +28,7 @@ =0D [Packages]=0D MdePkg/MdePkg.dec=0D - Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec=0D + RiscVPkg/RiscVPkg.dec=0D =0D [LibraryClasses]=0D RiscVCpuLib=0D diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVTimerLib/BaseRiscVTim= erLib.inf b/RiscVPkg/Library/RiscVTimerLib/BaseRiscVTimerLib.inf similarity index 88% rename from Silicon/RISC-V/ProcessorPkg/Library/RiscVTimerLib/BaseRiscVTime= rLib.inf rename to RiscVPkg/Library/RiscVTimerLib/BaseRiscVTimerLib.inf index 3c61149da8..5fb1adf160 100644 --- a/Silicon/RISC-V/ProcessorPkg/Library/RiscVTimerLib/BaseRiscVTimerLib.i= nf +++ b/RiscVPkg/Library/RiscVTimerLib/BaseRiscVTimerLib.inf @@ -20,7 +20,7 @@ =0D [Packages]=0D MdePkg/MdePkg.dec=0D - Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec=0D + RiscVPkg/RiscVPkg.dec=0D =0D [Pcd]=0D gUefiRiscVPkgTokenSpaceGuid.PcdRiscVMachineTimerTickInNanoSecond=0D diff --git a/Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxe.inf b/Risc= VPkg/Universal/CpuDxe/CpuDxe.inf similarity index 91% rename from Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxe.inf rename to RiscVPkg/Universal/CpuDxe/CpuDxe.inf index a422c12e32..77e8273ab9 100644 --- a/Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxe.inf +++ b/RiscVPkg/Universal/CpuDxe/CpuDxe.inf @@ -19,7 +19,7 @@ [Packages]=0D MdeModulePkg/MdeModulePkg.dec=0D MdePkg/MdePkg.dec=0D - Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec=0D + RiscVPkg/RiscVPkg.dec=0D =0D [LibraryClasses]=0D BaseLib=0D diff --git a/Silicon/RISC-V/ProcessorPkg/Universal/FdtDxe/FdtDxe.inf b/Risc= VPkg/Universal/FdtDxe/FdtDxe.inf similarity index 90% rename from Silicon/RISC-V/ProcessorPkg/Universal/FdtDxe/FdtDxe.inf rename to RiscVPkg/Universal/FdtDxe/FdtDxe.inf index ae6468f9f5..acc7d1da15 100644 --- a/Silicon/RISC-V/ProcessorPkg/Universal/FdtDxe/FdtDxe.inf +++ b/RiscVPkg/Universal/FdtDxe/FdtDxe.inf @@ -25,7 +25,7 @@ EmbeddedPkg/EmbeddedPkg.dec=0D MdeModulePkg/MdeModulePkg.dec=0D MdePkg/MdePkg.dec=0D - Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec=0D + RiscVPlatformPkg/RiscVPlatformPkg.dec=0D EmbeddedPkg/EmbeddedPkg.dec=0D =0D [LibraryClasses]=0D diff --git a/Silicon/RISC-V/ProcessorPkg/Universal/PciCpuIo2Dxe/PciCpuIo2Dx= e.inf b/RiscVPkg/Universal/PciCpuIo2Dxe/PciCpuIo2Dxe.inf similarity index 100% rename from Silicon/RISC-V/ProcessorPkg/Universal/PciCpuIo2Dxe/PciCpuIo2Dxe= .inf rename to RiscVPkg/Universal/PciCpuIo2Dxe/PciCpuIo2Dxe.inf diff --git a/Silicon/RISC-V/ProcessorPkg/Universal/SmbiosDxe/RiscVSmbiosDxe= .inf b/RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.inf similarity index 92% rename from Silicon/RISC-V/ProcessorPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.= inf rename to RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.inf index 0fcfe1d3ad..7a3c51700a 100644 --- a/Silicon/RISC-V/ProcessorPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.inf +++ b/RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.inf @@ -19,7 +19,7 @@ [Packages]=0D MdeModulePkg/MdeModulePkg.dec=0D MdePkg/MdePkg.dec=0D - Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec=0D + RiscVPkg/RiscVPkg.dec=0D =0D [LibraryClasses]=0D BaseLib=0D diff --git a/RiscVPlatformPkg/Library/Edk2OpensbiPlatformWrapperLib/Edk2Ope= nsbiPlatformWrapperLib.inf b/RiscVPlatformPkg/Library/Edk2OpensbiPlatformWr= apperLib/Edk2OpensbiPlatformWrapperLib.inf index 92723840c4..f19dd6b0e6 100644 --- a/RiscVPlatformPkg/Library/Edk2OpensbiPlatformWrapperLib/Edk2OpensbiPla= tformWrapperLib.inf +++ b/RiscVPlatformPkg/Library/Edk2OpensbiPlatformWrapperLib/Edk2OpensbiPla= tformWrapperLib.inf @@ -28,7 +28,7 @@ MdeModulePkg/MdeModulePkg.dec=0D MdePkg/MdePkg.dec=0D RiscVPlatformPkg/RiscVPlatformPkg.dec=0D - Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec=0D + RiscVPkg/RiscVPkg.dec=0D =0D [Pcd]=0D gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFirmwareDomainBaseAddress=0D diff --git a/RiscVPlatformPkg/Library/FirmwareContextProcessorSpecificLib/F= irmwareContextProcessorSpecificLib.inf b/RiscVPlatformPkg/Library/FirmwareC= ontextProcessorSpecificLib/FirmwareContextProcessorSpecificLib.inf index 69568511ce..8ea37ae4f4 100644 --- a/RiscVPlatformPkg/Library/FirmwareContextProcessorSpecificLib/Firmware= ContextProcessorSpecificLib.inf +++ b/RiscVPlatformPkg/Library/FirmwareContextProcessorSpecificLib/Firmware= ContextProcessorSpecificLib.inf @@ -20,7 +20,7 @@ [Packages]=0D MdeModulePkg/MdeModulePkg.dec=0D MdePkg/MdePkg.dec=0D - Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec=0D + RiscVPkg/RiscVPkg.dec=0D =0D [LibraryClasses]=0D BaseLib=0D diff --git a/RiscVPlatformPkg/Library/OpensbiPlatformLib/OpensbiPlatformLib= .inf b/RiscVPlatformPkg/Library/OpensbiPlatformLib/OpensbiPlatformLib.inf index b073dd914c..8e3f07d833 100644 --- a/RiscVPlatformPkg/Library/OpensbiPlatformLib/OpensbiPlatformLib.inf +++ b/RiscVPlatformPkg/Library/OpensbiPlatformLib/OpensbiPlatformLib.inf @@ -32,7 +32,7 @@ MdePkg/MdePkg.dec=0D Platform/SiFive/U5SeriesPkg/U5SeriesPkg.dec=0D RiscVPlatformPkg/RiscVPlatformPkg.dec=0D - Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec=0D + RiscVPkg/RiscVPkg.dec=0D =0D [LibraryClasses]=0D BaseLib=0D diff --git a/RiscVPlatformPkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.i= nf b/RiscVPlatformPkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.inf index fe6d28c038..af453f6650 100644 --- a/RiscVPlatformPkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.inf +++ b/RiscVPlatformPkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.inf @@ -27,7 +27,7 @@ [Packages]=0D MdePkg/MdePkg.dec=0D RiscVPlatformPkg/RiscVPlatformPkg.dec=0D - Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec=0D + RiscVPkg/RiscVPkg.dec=0D =0D [LibraryClasses]=0D BaseLib=0D diff --git a/RiscVPlatformPkg/Library/PeiCoreInfoHobLibNull/PeiCoreInfoHobL= ib.inf b/RiscVPlatformPkg/Library/PeiCoreInfoHobLibNull/PeiCoreInfoHobLib.i= nf index 2a0c3f6fd8..51facae79a 100644 --- a/RiscVPlatformPkg/Library/PeiCoreInfoHobLibNull/PeiCoreInfoHobLib.inf +++ b/RiscVPlatformPkg/Library/PeiCoreInfoHobLibNull/PeiCoreInfoHobLib.inf @@ -28,7 +28,7 @@ MdePkg/MdePkg.dec=0D MdeModulePkg/MdeModulePkg.dec=0D RiscVPlatformPkg/RiscVPlatformPkg.dec=0D - Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec=0D + RiscVPkg/RiscVPkg.dec=0D =0D [LibraryClasses]=0D BaseLib=0D diff --git a/RiscVPlatformPkg/Library/PlatformSecPpiLibNull/PlatformSecPpiL= ibNull.inf b/RiscVPlatformPkg/Library/PlatformSecPpiLibNull/PlatformSecPpiL= ibNull.inf index 3712b20554..5b3570ce6d 100644 --- a/RiscVPlatformPkg/Library/PlatformSecPpiLibNull/PlatformSecPpiLibNull.= inf +++ b/RiscVPlatformPkg/Library/PlatformSecPpiLibNull/PlatformSecPpiLibNull.= inf @@ -28,7 +28,6 @@ MdePkg/MdePkg.dec=0D MdeModulePkg/MdeModulePkg.dec=0D RiscVPlatformPkg/RiscVPlatformPkg.dec=0D - #Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec=0D =0D [LibraryClasses]=0D #BaseLib=0D diff --git a/RiscVPlatformPkg/Library/ResetSystemLib/ResetSystemLib.inf b/R= iscVPlatformPkg/Library/ResetSystemLib/ResetSystemLib.inf index f876ae2056..0ce1e90b70 100644 --- a/RiscVPlatformPkg/Library/ResetSystemLib/ResetSystemLib.inf +++ b/RiscVPlatformPkg/Library/ResetSystemLib/ResetSystemLib.inf @@ -26,7 +26,7 @@ [Packages]=0D MdePkg/MdePkg.dec=0D MdeModulePkg/MdeModulePkg.dec=0D - Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec=0D + RiscVPkg/RiscVPkg.dec=0D =0D [LibraryClasses]=0D DebugLib=0D diff --git a/RiscVPlatformPkg/Library/RiscVSpecialPlatformLibNull/RiscVSpec= ialPlatformLibNull.inf b/RiscVPlatformPkg/Library/RiscVSpecialPlatformLibNu= ll/RiscVSpecialPlatformLibNull.inf index 1bcd550d8b..3f2e5eec18 100644 --- a/RiscVPlatformPkg/Library/RiscVSpecialPlatformLibNull/RiscVSpecialPlat= formLibNull.inf +++ b/RiscVPlatformPkg/Library/RiscVSpecialPlatformLibNull/RiscVSpecialPlat= formLibNull.inf @@ -30,7 +30,7 @@ MdePkg/MdePkg.dec=0D MdeModulePkg/MdeModulePkg.dec=0D RiscVPlatformPkg/RiscVPlatformPkg.dec=0D - Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec=0D + RiscVPkg/RiscVPkg.dec=0D =0D [LibraryClasses]=0D BaseLib=0D diff --git a/RiscVPlatformPkg/Universal/FdtPeim/FdtPeim.inf b/RiscVPlatform= Pkg/Universal/FdtPeim/FdtPeim.inf index 8dc58f0a8b..33b7f89805 100644 --- a/RiscVPlatformPkg/Universal/FdtPeim/FdtPeim.inf +++ b/RiscVPlatformPkg/Universal/FdtPeim/FdtPeim.inf @@ -30,7 +30,7 @@ EmbeddedPkg/EmbeddedPkg.dec=0D MdePkg/MdePkg.dec=0D MdeModulePkg/MdeModulePkg.dec=0D - Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec=0D + RiscVPkg/RiscVPkg.dec=0D =0D [LibraryClasses]=0D DebugLib=0D diff --git a/RiscVPlatformPkg/Universal/Pei/PlatformPei/PlatformPei.inf b/R= iscVPlatformPkg/Universal/Pei/PlatformPei/PlatformPei.inf index 06243bc8c3..4b8e074b16 100644 --- a/RiscVPlatformPkg/Universal/Pei/PlatformPei/PlatformPei.inf +++ b/RiscVPlatformPkg/Universal/Pei/PlatformPei/PlatformPei.inf @@ -32,7 +32,7 @@ MdeModulePkg/MdeModulePkg.dec=0D MdePkg/MdePkg.dec=0D RiscVPlatformPkg/RiscVPlatformPkg.dec=0D - Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec=0D + RiscVPkg/RiscVPkg.dec=0D UefiCpuPkg/UefiCpuPkg.dec=0D =0D [Guids]=0D diff --git a/RiscVPlatformPkg/Universal/Sec/SecMain.inf b/RiscVPlatformPkg/= Universal/Sec/SecMain.inf index 8f4b167ed2..caed51a54c 100644 --- a/RiscVPlatformPkg/Universal/Sec/SecMain.inf +++ b/RiscVPlatformPkg/Universal/Sec/SecMain.inf @@ -31,7 +31,7 @@ EmbeddedPkg/EmbeddedPkg.dec=0D MdeModulePkg/MdeModulePkg.dec=0D MdePkg/MdePkg.dec=0D - Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec=0D + RiscVPkg/RiscVPkg.dec=0D RiscVPlatformPkg/RiscVPlatformPkg.dec=0D =0D [LibraryClasses]=0D diff --git a/Silicon/RISC-V/ProcessorPkg/Include/IndustryStandard/RiscV.h b= /RiscVPkg/Include/IndustryStandard/RiscV.h similarity index 100% rename from Silicon/RISC-V/ProcessorPkg/Include/IndustryStandard/RiscV.h rename to RiscVPkg/Include/IndustryStandard/RiscV.h diff --git a/Silicon/RISC-V/ProcessorPkg/Include/IndustryStandard/RiscVOpen= sbi.h b/RiscVPkg/Include/IndustryStandard/RiscVOpensbi.h similarity index 100% rename from Silicon/RISC-V/ProcessorPkg/Include/IndustryStandard/RiscVOpens= bi.h rename to RiscVPkg/Include/IndustryStandard/RiscVOpensbi.h diff --git a/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVCpuLib.h b/Ri= scVPkg/Include/Library/RiscVCpuLib.h similarity index 100% rename from Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVCpuLib.h rename to RiscVPkg/Include/Library/RiscVCpuLib.h diff --git a/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVEdk2SbiLib.h = b/RiscVPkg/Include/Library/RiscVEdk2SbiLib.h similarity index 100% rename from Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVEdk2SbiLib.h rename to RiscVPkg/Include/Library/RiscVEdk2SbiLib.h diff --git a/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVFirmwareConte= xtLib.h b/RiscVPkg/Include/Library/RiscVFirmwareContextLib.h similarity index 100% rename from Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVFirmwareContex= tLib.h rename to RiscVPkg/Include/Library/RiscVFirmwareContextLib.h diff --git a/Silicon/RISC-V/ProcessorPkg/Include/OpensbiTypes.h b/RiscVPkg/= Include/OpensbiTypes.h similarity index 100% rename from Silicon/RISC-V/ProcessorPkg/Include/OpensbiTypes.h rename to RiscVPkg/Include/OpensbiTypes.h diff --git a/Silicon/RISC-V/ProcessorPkg/Include/ProcessorSpecificHobData.h= b/RiscVPkg/Include/ProcessorSpecificHobData.h similarity index 100% rename from Silicon/RISC-V/ProcessorPkg/Include/ProcessorSpecificHobData.h rename to RiscVPkg/Include/ProcessorSpecificHobData.h diff --git a/Silicon/RISC-V/ProcessorPkg/Include/RiscVImpl.h b/RiscVPkg/Inc= lude/RiscVImpl.h similarity index 100% rename from Silicon/RISC-V/ProcessorPkg/Include/RiscVImpl.h rename to RiscVPkg/Include/RiscVImpl.h diff --git a/Silicon/RISC-V/ProcessorPkg/Include/SmbiosProcessorSpecificDat= a.h b/RiscVPkg/Include/SmbiosProcessorSpecificData.h similarity index 100% rename from Silicon/RISC-V/ProcessorPkg/Include/SmbiosProcessorSpecificData= .h rename to RiscVPkg/Include/SmbiosProcessorSpecificData.h diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVExceptionLib/CpuExcep= tionHandlerLib.h b/RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerLi= b.h similarity index 100% rename from Silicon/RISC-V/ProcessorPkg/Library/RiscVExceptionLib/CpuExcept= ionHandlerLib.h rename to RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerLib.h diff --git a/Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxe.h b/RiscVP= kg/Universal/CpuDxe/CpuDxe.h similarity index 100% rename from Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxe.h rename to RiscVPkg/Universal/CpuDxe/CpuDxe.h diff --git a/Silicon/RISC-V/ProcessorPkg/Universal/SmbiosDxe/RiscVSmbiosDxe= .h b/RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.h similarity index 100% rename from Silicon/RISC-V/ProcessorPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.h rename to RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.h diff --git a/Silicon/RISC-V/ProcessorPkg/Library/PeiServicesTablePointerLib= OpenSbi/PeiServicesTablePointerOpenSbi.c b/RiscVPkg/Library/PeiServicesTabl= ePointerLibOpenSbi/PeiServicesTablePointerOpenSbi.c similarity index 100% rename from Silicon/RISC-V/ProcessorPkg/Library/PeiServicesTablePointerLibO= penSbi/PeiServicesTablePointerOpenSbi.c rename to RiscVPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTab= lePointerOpenSbi.c diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVEdk2SbiLib/RiscVEdk2S= biLib.c b/RiscVPkg/Library/RiscVEdk2SbiLib/RiscVEdk2SbiLib.c similarity index 100% rename from Silicon/RISC-V/ProcessorPkg/Library/RiscVEdk2SbiLib/RiscVEdk2Sb= iLib.c rename to RiscVPkg/Library/RiscVEdk2SbiLib/RiscVEdk2SbiLib.c diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVExceptionLib/CpuExcep= tionHandlerLib.c b/RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerLi= b.c similarity index 100% rename from Silicon/RISC-V/ProcessorPkg/Library/RiscVExceptionLib/CpuExcept= ionHandlerLib.c rename to RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerLib.c diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSbiLib= /RiscVFirmwareContextSbiLib.c b/RiscVPkg/Library/RiscVFirmwareContextSbiLib= /RiscVFirmwareContextSbiLib.c similarity index 100% rename from Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSbiLib/= RiscVFirmwareContextSbiLib.c rename to RiscVPkg/Library/RiscVFirmwareContextSbiLib/RiscVFirmwareContextS= biLib.c diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSscrat= chLib/RiscVFirmwareContextSscratchLib.c b/RiscVPkg/Library/RiscVFirmwareCon= textSscratchLib/RiscVFirmwareContextSscratchLib.c similarity index 100% rename from Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSscratc= hLib/RiscVFirmwareContextSscratchLib.c rename to RiscVPkg/Library/RiscVFirmwareContextSscratchLib/RiscVFirmwareCon= textSscratchLib.c diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextStvecL= ib/RiscVFirmwareContextStvecLib.c b/RiscVPkg/Library/RiscVFirmwareContextSt= vecLib/RiscVFirmwareContextStvecLib.c similarity index 100% rename from Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextStvecLi= b/RiscVFirmwareContextStvecLib.c rename to RiscVPkg/Library/RiscVFirmwareContextStvecLib/RiscVFirmwareContex= tStvecLib.c diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVTimerLib/RiscVTimerLi= b.c b/RiscVPkg/Library/RiscVTimerLib/RiscVTimerLib.c similarity index 100% rename from Silicon/RISC-V/ProcessorPkg/Library/RiscVTimerLib/RiscVTimerLib= .c rename to RiscVPkg/Library/RiscVTimerLib/RiscVTimerLib.c diff --git a/Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxe.c b/RiscVP= kg/Universal/CpuDxe/CpuDxe.c similarity index 100% rename from Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxe.c rename to RiscVPkg/Universal/CpuDxe/CpuDxe.c diff --git a/Silicon/RISC-V/ProcessorPkg/Universal/FdtDxe/FdtDxe.c b/RiscVP= kg/Universal/FdtDxe/FdtDxe.c similarity index 100% rename from Silicon/RISC-V/ProcessorPkg/Universal/FdtDxe/FdtDxe.c rename to RiscVPkg/Universal/FdtDxe/FdtDxe.c diff --git a/Silicon/RISC-V/ProcessorPkg/Universal/PciCpuIo2Dxe/PciCpuIo2Dx= e.c b/RiscVPkg/Universal/PciCpuIo2Dxe/PciCpuIo2Dxe.c similarity index 100% rename from Silicon/RISC-V/ProcessorPkg/Universal/PciCpuIo2Dxe/PciCpuIo2Dxe= .c rename to RiscVPkg/Universal/PciCpuIo2Dxe/PciCpuIo2Dxe.c diff --git a/Silicon/RISC-V/ProcessorPkg/Universal/SmbiosDxe/RiscVSmbiosDxe= .c b/RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.c similarity index 100% rename from Silicon/RISC-V/ProcessorPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.c rename to RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.c diff --git a/Silicon/RISC-V/ProcessorPkg/Library/PeiServicesTablePointerLib= OpenSbi/PeiServicesTablePointerLibOpenSbi.uni b/RiscVPkg/Library/PeiService= sTablePointerLibOpenSbi/PeiServicesTablePointerLibOpenSbi.uni similarity index 100% rename from Silicon/RISC-V/ProcessorPkg/Library/PeiServicesTablePointerLibO= penSbi/PeiServicesTablePointerLibOpenSbi.uni rename to RiscVPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTab= lePointerLibOpenSbi.uni diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVCpuLib/Cpu.S b/RiscVP= kg/Library/RiscVCpuLib/Cpu.S similarity index 100% rename from Silicon/RISC-V/ProcessorPkg/Library/RiscVCpuLib/Cpu.S rename to RiscVPkg/Library/RiscVCpuLib/Cpu.S diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVExceptionLib/CpuExcep= tionHandlerLib.uni b/RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandler= Lib.uni similarity index 100% rename from Silicon/RISC-V/ProcessorPkg/Library/RiscVExceptionLib/CpuExcept= ionHandlerLib.uni rename to RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerLib.uni diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVExceptionLib/Supervis= orTrapHandler.S b/RiscVPkg/Library/RiscVExceptionLib/SupervisorTrapHandler.S similarity index 100% rename from Silicon/RISC-V/ProcessorPkg/Library/RiscVExceptionLib/Superviso= rTrapHandler.S rename to RiscVPkg/Library/RiscVExceptionLib/SupervisorTrapHandler.S diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVPlatformTimerLibNull/= RiscVPlatformTimerLibNull.S b/RiscVPkg/Library/RiscVPlatformTimerLibNull/Ri= scVPlatformTimerLibNull.S similarity index 100% rename from Silicon/RISC-V/ProcessorPkg/Library/RiscVPlatformTimerLibNull/R= iscVPlatformTimerLibNull.S rename to RiscVPkg/Library/RiscVPlatformTimerLibNull/RiscVPlatformTimerLibN= ull.S diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVReadMachineModeTimer/= EmulatedMachineModeTimerLib/EmulatedMachineModeTimerLib.S b/RiscVPkg/Librar= y/RiscVReadMachineModeTimer/EmulatedMachineModeTimerLib/EmulatedMachineMode= TimerLib.S similarity index 100% rename from Silicon/RISC-V/ProcessorPkg/Library/RiscVReadMachineModeTimer/E= mulatedMachineModeTimerLib/EmulatedMachineModeTimerLib.S rename to RiscVPkg/Library/RiscVReadMachineModeTimer/EmulatedMachineModeTim= erLib/EmulatedMachineModeTimerLib.S diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVReadMachineModeTimer/= MachineModeTimerLib/MachineModeTimerLib.S b/RiscVPkg/Library/RiscVReadMachi= neModeTimer/MachineModeTimerLib/MachineModeTimerLib.S similarity index 100% rename from Silicon/RISC-V/ProcessorPkg/Library/RiscVReadMachineModeTimer/M= achineModeTimerLib/MachineModeTimerLib.S rename to RiscVPkg/Library/RiscVReadMachineModeTimer/MachineModeTimerLib/Ma= chineModeTimerLib.S diff --git a/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.uni b/RiscVPkg/R= iscVPkg.uni similarity index 85% rename from Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.uni rename to RiscVPkg/RiscVPkg.uni index 83da92fe40..7e470eb531 100644 --- a/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.uni +++ b/RiscVPkg/RiscVPkg.uni @@ -1,5 +1,5 @@ // /** @file=0D -// RISC-V Processor Package Localized Strings and Content.=0D +// RISC-V Package Localized Strings and Content.=0D //=0D // Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
=0D //=0D diff --git a/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkgExtra.uni b/RiscV= Pkg/RiscVPkgExtra.uni similarity index 87% rename from Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkgExtra.uni rename to RiscVPkg/RiscVPkgExtra.uni index 207adfb671..f0f2019337 100644 --- a/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkgExtra.uni +++ b/RiscVPkg/RiscVPkgExtra.uni @@ -9,5 +9,5 @@ =0D #string STR_PROPERTIES_PACKAGE_NAME=0D #language en-US=0D -"RISC-V processor package"=0D +"RISC-V package"=0D =0D diff --git a/Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxe.uni b/Risc= VPkg/Universal/CpuDxe/CpuDxe.uni similarity index 100% rename from Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxe.uni rename to RiscVPkg/Universal/CpuDxe/CpuDxe.uni diff --git a/Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxeExtra.uni b= /RiscVPkg/Universal/CpuDxe/CpuDxeExtra.uni similarity index 100% rename from Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxeExtra.uni rename to RiscVPkg/Universal/CpuDxe/CpuDxeExtra.uni diff --git a/Silicon/RISC-V/ProcessorPkg/Universal/SmbiosDxe/RiscVSmbiosDxe= .uni b/RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.uni similarity index 100% rename from Silicon/RISC-V/ProcessorPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.= uni rename to RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.uni diff --git a/Silicon/RISC-V/ProcessorPkg/Universal/SmbiosDxe/RiscVSmbiosDxe= Extra.uni b/RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxeExtra.uni similarity index 100% rename from Silicon/RISC-V/ProcessorPkg/Universal/SmbiosDxe/RiscVSmbiosDxeE= xtra.uni rename to RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxeExtra.uni diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVOpensbiLib/opensbi b/= Silicon/RISC-V/ProcessorPkg/Library/RiscVOpensbiLib/opensbi deleted file mode 160000 index a731c7e369..0000000000 --- a/Silicon/RISC-V/ProcessorPkg/Library/RiscVOpensbiLib/opensbi +++ /dev/null @@ -1 +0,0 @@ -Subproject commit a731c7e36988c3308e1978ecde491f2f6182d490 --=20 2.31.1