* [PATCH 73/79] RiscVPkg: Address Core CI ECC errors.
2022-01-08 7:27 [PATCH 62/79] RiscVPlatformPkg: Rename PlatformPkg to RiscVPlatformPkg Abner Chang
@ 2022-01-08 7:27 ` Abner Chang
0 siblings, 0 replies; 7+ messages in thread
From: Abner Chang @ 2022-01-08 7:27 UTC (permalink / raw)
To: devel; +Cc: abner.chang, Daniel Schaefer, Sunil V L
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Cc: Daniel Schaefer <daniel.schaefer@hpe.com>
Cc: Sunil V L <sunilvl@ventanamicro.com>
---
RiscVPkg/RiscVPkg.dec | 2 ++
RiscVPkg/RiscVPkg.dsc | 4 ++--
.../RiscVFirmwareContextSbiLib.inf | 2 +-
.../Include/Library/MachineModeTimerLib.h | 15 +++++++++++++
.../Include/Library/RiscVPlatformTimerLib.h | 21 +++++++++++++++++++
.../CpuExceptionHandlerLib.h | 2 +-
RiscVPkg/RiscVPkg.uni | 18 +++++++++++++++-
7 files changed, 59 insertions(+), 5 deletions(-)
create mode 100644 RiscVPkg/Include/Library/MachineModeTimerLib.h
create mode 100644 RiscVPkg/Include/Library/RiscVPlatformTimerLib.h
diff --git a/RiscVPkg/RiscVPkg.dec b/RiscVPkg/RiscVPkg.dec
index f23d3c0135..1e2d2fac0d 100644
--- a/RiscVPkg/RiscVPkg.dec
+++ b/RiscVPkg/RiscVPkg.dec
@@ -26,6 +26,8 @@
RiscVCpuLib|Include/Library/RiscVCpuLib.h
RiscVEdk2SbiLib|Include/Library/RiscVEdk2SbiLib.h
RiscVFirmwareContextLib|Include/Library/RiscVFirmwareContextLib.h
+ RiscVPlatformTimerLib|Include/Library/RiscVPlatformTimerLib.h
+ MachineModeTimerLib|Include/Library/MachineModeTimerLib.h
[Guids]
gUefiRiscVPkgTokenSpaceGuid = { 0x4261e9c8, 0x52c0, 0x4b34, { 0x85, 0x3d, 0x48, 0x46, 0xea, 0xd3, 0xb7, 0x2c}}
diff --git a/RiscVPkg/RiscVPkg.dsc b/RiscVPkg/RiscVPkg.dsc
index 7e8c8f599c..c1cd11a161 100644
--- a/RiscVPkg/RiscVPkg.dsc
+++ b/RiscVPkg/RiscVPkg.dsc
@@ -1,11 +1,11 @@
-#/** @file
+## @file
# RISC-V package.
#
# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
-#**/
+#
################################################################################
#
diff --git a/RiscVPkg/Library/RiscVFirmwareContextSbiLib/RiscVFirmwareContextSbiLib.inf b/RiscVPkg/Library/RiscVFirmwareContextSbiLib/RiscVFirmwareContextSbiLib.inf
index db30d7e551..e3dbc05007 100644
--- a/RiscVPkg/Library/RiscVFirmwareContextSbiLib/RiscVFirmwareContextSbiLib.inf
+++ b/RiscVPkg/Library/RiscVFirmwareContextSbiLib/RiscVFirmwareContextSbiLib.inf
@@ -12,7 +12,7 @@
[Defines]
INF_VERSION = 0x0001001b
BASE_NAME = RiscVFirmwareContextSbiLib
- FILE_GUID = 3709E048-6794-427A-B728-BFE3FFD6D461
+ FILE_GUID = 308117C0-400A-79C5-6ED4-AB9763A202E5
MODULE_TYPE = PEIM
VERSION_STRING = 1.0
LIBRARY_CLASS = RiscVFirmwareContextLib|PEIM PEI_CORE
diff --git a/RiscVPkg/Include/Library/MachineModeTimerLib.h b/RiscVPkg/Include/Library/MachineModeTimerLib.h
new file mode 100644
index 0000000000..a27391cca3
--- /dev/null
+++ b/RiscVPkg/Include/Library/MachineModeTimerLib.h
@@ -0,0 +1,15 @@
+/** @file
+ RISC-V Machine Mode Timer Library Definition
+
+ Copyright (c) 2022, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef MACHINE_MODE_TIMER_LIB_H_
+#define MACHINE_MODE_TIMER_LIB_H_
+
+UINT64
+RiscVReadMachineTimerInterface (VOID);
+
+#endif
diff --git a/RiscVPkg/Include/Library/RiscVPlatformTimerLib.h b/RiscVPkg/Include/Library/RiscVPlatformTimerLib.h
new file mode 100644
index 0000000000..dcd8734eb5
--- /dev/null
+++ b/RiscVPkg/Include/Library/RiscVPlatformTimerLib.h
@@ -0,0 +1,21 @@
+/** @file
+ RISC-V Platform Timer library definitions.
+
+ Copyright (c) 2022, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef RISCV_PLATFORM_TIMER_LIB_H_
+#define RISCV_PLATFORM_TIMER_LIB_H_
+
+UINT64
+RiscVReadMachineTimer (VOID);
+
+VOID
+RiscVSetMachineTimerCmp (UINT64);
+
+UINT64
+RiscVReadMachineTimerCmp(VOID);
+
+#endif
diff --git a/RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerLib.h b/RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerLib.h
index 3e480e9b09..b316510020 100644
--- a/RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerLib.h
+++ b/RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerLib.h
@@ -1,4 +1,4 @@
-/**@file
+/** @file
RISC-V Exception Handler library definition file.
diff --git a/RiscVPkg/RiscVPkg.uni b/RiscVPkg/RiscVPkg.uni
index 7e470eb531..d459272444 100644
--- a/RiscVPkg/RiscVPkg.uni
+++ b/RiscVPkg/RiscVPkg.uni
@@ -8,6 +8,22 @@
// **/
#string STR_PACKAGE_ABSTRACT #language en-US "Provides UEFI compatible RISC-V processor modules and libraries"
-
#string STR_PACKAGE_DESCRIPTION #language en-US "This Package provides UEFI compatible RISC-V processor modules and libraries."
+#string STR_gUefiRiscVPkgTokenSpaceGuid_PcdProcessorSpecificDataGuidHobGuid_PROMPT #language en-US "Processor Specific Data HOB GUID"
+#string STR_gUefiRiscVPkgTokenSpaceGuid_PcdProcessorSpecificDataGuidHobGuid_HELP #language en-US "This is the GUID definition of HOB that passes the "
+ "processor specific data to DXE phase."
+#string STR_gUefiRiscVPkgTokenSpaceGuid_PcdProcessorSmbiosGuidHobGuid_PROMPT #language en-US "RISC-V SMBIOS Data HOB GUID"
+#string STR_gUefiRiscVPkgTokenSpaceGuid_PcdProcessorSmbiosGuidHobGuid_HELP #language en-US "This is the GUID definition of HOB that passes RISC-V SMBIOS"
+ "Data to DXE phase."
+#string STR_gUefiRiscVPkgTokenSpaceGuid_PcdProcessorSmbiosType4GuidHobGuid_PROMPT #language en-US "RISC-V SMBIOS Type 4 Data HOB GUID"
+#string STR_gUefiRiscVPkgTokenSpaceGuid_PcdProcessorSmbiosType4GuidHobGuid_HELP #language en-US "This is the GUID definition of HOB that passes RISC-V SMBIOS"
+ "Type 4 information to DXE phase for building up SMBIOS record."
+#string STR_gUefiRiscVPkgTokenSpaceGuid_PcdProcessorSmbiosType7GuidHobGuid_PROMPT #language en-US "RISC-V SMBIOS Type 7 Data HOB GUID"
+#string STR_gUefiRiscVPkgTokenSpaceGuid_PcdProcessorSmbiosType7GuidHobGuid_HELP #language en-US "This is the GUID definition of HOB that passes RISC-V SMBIOS"
+ "Type 7 information to DXE phase for building up SMBIOS record."
+#string STR_gUefiRiscVPkgTokenSpaceGuid_PcdRiscVMachineTimerTickInNanoSecond_PROMPT #language en-US "RISC-V Machine Mode Timer Duration"
+#string STR_gUefiRiscVPkgTokenSpaceGuid_PcdRiscVMachineTimerTickInNanoSecond_HELP #language en-US "RISC-V Machine Mode Timer Duration in nanosecond."
+#string STR_gUefiRiscVPkgTokenSpaceGuid_PcdRiscVMachineTimerFrequencyInHerz_PROMPT #language en-US "RISC-V Machine Mode Timer frequency."
+#string STR_gUefiRiscVPkgTokenSpaceGuid_PcdRiscVMachineTimerFrequencyInHerz_HELP #language en-US "RISC-V Machine Mode Timer frequency in Herz"
+
--
2.31.1
^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH 63/79] RiscVPkg: Rename ProcessorPkg to RiscVPkg
[not found] ` <20220108041420.16064-2-abner.chang@hpe.com>
@ 2022-01-09 14:27 ` Sunil V L
0 siblings, 0 replies; 7+ messages in thread
From: Sunil V L @ 2022-01-09 14:27 UTC (permalink / raw)
To: Abner Chang; +Cc: devel, Daniel Schaefer
On Sat, Jan 08, 2022 at 12:14:04PM +0800, Abner Chang wrote:
> ProcessorPkg is migrated from edk2-platforms for
> RISC-V (Silicon/RISC-V/ProcessorPkg). Rename it to
> RiscVPkg under edk2.
>
> Signed-off-by: Abner Chang <abner.chang@hpe.com>
> Cc: Daniel Schaefer <daniel.schaefer@hpe.com>
> Cc: Sunil V L <sunilvl@ventanamicro.com>
> ---
> .../RiscVPkg.dec | 6 +-
> .../RiscVPkg.dsc | 58 +++++++++----------
> RiscVPlatformPkg/RiscVPlatformPkg.dsc | 6 +-
> .../PeiServicesTablePointerLibOpenSbi.inf | 2 +-
> .../Library/RiscVCpuLib/RiscVCpuLib.inf | 2 +-
> .../RiscVEdk2SbiLib/RiscVEdk2SbiLib.inf | 4 +-
> .../CpuExceptionHandlerDxeLib.inf | 2 +-
> .../RiscVFirmwareContextSbiLib.inf | 2 +-
> .../RiscVFirmwareContextSscratchLib.inf | 2 +-
> .../RiscVFirmwareContextStvecLib.inf | 2 +-
> .../RiscVOpensbiLib/RiscVOpensbiLib.inf | 2 +-
> .../RiscVPlatformTimerLib.inf | 0
> .../EmulatedMachineModeTimerLib.inf | 2 +-
> .../MachineModeTimerLib.inf | 2 +-
> .../RiscVTimerLib/BaseRiscVTimerLib.inf | 2 +-
> .../Universal/CpuDxe/CpuDxe.inf | 2 +-
> .../Universal/FdtDxe/FdtDxe.inf | 2 +-
> .../Universal/PciCpuIo2Dxe/PciCpuIo2Dxe.inf | 0
> .../Universal/SmbiosDxe/RiscVSmbiosDxe.inf | 2 +-
> .../Edk2OpensbiPlatformWrapperLib.inf | 2 +-
> .../FirmwareContextProcessorSpecificLib.inf | 2 +-
> .../OpensbiPlatformLib/OpensbiPlatformLib.inf | 2 +-
> .../PeiCoreEntryPoint/PeiCoreEntryPoint.inf | 2 +-
> .../PeiCoreInfoHobLib.inf | 2 +-
> .../PlatformSecPpiLibNull.inf | 1 -
> .../Library/ResetSystemLib/ResetSystemLib.inf | 2 +-
> .../RiscVSpecialPlatformLibNull.inf | 2 +-
> .../Universal/FdtPeim/FdtPeim.inf | 2 +-
> .../Universal/Pei/PlatformPei/PlatformPei.inf | 2 +-
> RiscVPlatformPkg/Universal/Sec/SecMain.inf | 2 +-
> .../Include/IndustryStandard/RiscV.h | 0
> .../Include/IndustryStandard/RiscVOpensbi.h | 0
> .../Include/Library/RiscVCpuLib.h | 0
> .../Include/Library/RiscVEdk2SbiLib.h | 0
> .../Include/Library/RiscVFirmwareContextLib.h | 0
> .../Include/OpensbiTypes.h | 0
> .../Include/ProcessorSpecificHobData.h | 0
> .../Include/RiscVImpl.h | 0
> .../Include/SmbiosProcessorSpecificData.h | 0
> .../CpuExceptionHandlerLib.h | 0
> .../Universal/CpuDxe/CpuDxe.h | 0
> .../Universal/SmbiosDxe/RiscVSmbiosDxe.h | 0
> .../PeiServicesTablePointerOpenSbi.c | 0
> .../Library/RiscVEdk2SbiLib/RiscVEdk2SbiLib.c | 0
> .../CpuExceptionHandlerLib.c | 0
> .../RiscVFirmwareContextSbiLib.c | 0
> .../RiscVFirmwareContextSscratchLib.c | 0
> .../RiscVFirmwareContextStvecLib.c | 0
> .../Library/RiscVTimerLib/RiscVTimerLib.c | 0
> .../Universal/CpuDxe/CpuDxe.c | 0
> .../Universal/FdtDxe/FdtDxe.c | 0
> .../Universal/PciCpuIo2Dxe/PciCpuIo2Dxe.c | 0
> .../Universal/SmbiosDxe/RiscVSmbiosDxe.c | 0
> .../PeiServicesTablePointerLibOpenSbi.uni | 0
> .../Library/RiscVCpuLib/Cpu.S | 0
> .../CpuExceptionHandlerLib.uni | 0
> .../RiscVExceptionLib/SupervisorTrapHandler.S | 0
> .../RiscVPlatformTimerLibNull.S | 0
> .../EmulatedMachineModeTimerLib.S | 0
> .../MachineModeTimerLib/MachineModeTimerLib.S | 0
> .../RiscVPkg.uni | 2 +-
> .../RiscVPkgExtra.uni | 2 +-
> .../Universal/CpuDxe/CpuDxe.uni | 0
> .../Universal/CpuDxe/CpuDxeExtra.uni | 0
> .../Universal/SmbiosDxe/RiscVSmbiosDxe.uni | 0
> .../SmbiosDxe/RiscVSmbiosDxeExtra.uni | 0
> .../Library/RiscVOpensbiLib/opensbi | 1 -
> 67 files changed, 62 insertions(+), 64 deletions(-)
> rename Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec => RiscVPkg/RiscVPkg.dec (92%)
> rename Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dsc => RiscVPkg/RiscVPkg.dsc (54%)
> rename {Silicon/RISC-V/ProcessorPkg => RiscVPkg}/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerLibOpenSbi.inf (92%)
> rename {Silicon/RISC-V/ProcessorPkg => RiscVPkg}/Library/RiscVCpuLib/RiscVCpuLib.inf (89%)
> rename {Silicon/RISC-V/ProcessorPkg => RiscVPkg}/Library/RiscVEdk2SbiLib/RiscVEdk2SbiLib.inf (79%)
> rename {Silicon/RISC-V/ProcessorPkg => RiscVPkg}/Library/RiscVExceptionLib/CpuExceptionHandlerDxeLib.inf (91%)
> rename {Silicon/RISC-V/ProcessorPkg => RiscVPkg}/Library/RiscVFirmwareContextSbiLib/RiscVFirmwareContextSbiLib.inf (90%)
> rename {Silicon/RISC-V/ProcessorPkg => RiscVPkg}/Library/RiscVFirmwareContextSscratchLib/RiscVFirmwareContextSscratchLib.inf (90%)
> rename {Silicon/RISC-V/ProcessorPkg => RiscVPkg}/Library/RiscVFirmwareContextStvecLib/RiscVFirmwareContextStvecLib.inf (89%)
> rename {Silicon/RISC-V/ProcessorPkg => RiscVPkg}/Library/RiscVOpensbiLib/RiscVOpensbiLib.inf (95%)
> rename {Silicon/RISC-V/ProcessorPkg => RiscVPkg}/Library/RiscVPlatformTimerLibNull/RiscVPlatformTimerLib.inf (100%)
> rename {Silicon/RISC-V/ProcessorPkg => RiscVPkg}/Library/RiscVReadMachineModeTimer/EmulatedMachineModeTimerLib/EmulatedMachineModeTimerLib.inf (89%)
> rename {Silicon/RISC-V/ProcessorPkg => RiscVPkg}/Library/RiscVReadMachineModeTimer/MachineModeTimerLib/MachineModeTimerLib.inf (89%)
> rename {Silicon/RISC-V/ProcessorPkg => RiscVPkg}/Library/RiscVTimerLib/BaseRiscVTimerLib.inf (88%)
> rename {Silicon/RISC-V/ProcessorPkg => RiscVPkg}/Universal/CpuDxe/CpuDxe.inf (91%)
> rename {Silicon/RISC-V/ProcessorPkg => RiscVPkg}/Universal/FdtDxe/FdtDxe.inf (90%)
> rename {Silicon/RISC-V/ProcessorPkg => RiscVPkg}/Universal/PciCpuIo2Dxe/PciCpuIo2Dxe.inf (100%)
> rename {Silicon/RISC-V/ProcessorPkg => RiscVPkg}/Universal/SmbiosDxe/RiscVSmbiosDxe.inf (92%)
> rename {Silicon/RISC-V/ProcessorPkg => RiscVPkg}/Include/IndustryStandard/RiscV.h (100%)
> rename {Silicon/RISC-V/ProcessorPkg => RiscVPkg}/Include/IndustryStandard/RiscVOpensbi.h (100%)
> rename {Silicon/RISC-V/ProcessorPkg => RiscVPkg}/Include/Library/RiscVCpuLib.h (100%)
> rename {Silicon/RISC-V/ProcessorPkg => RiscVPkg}/Include/Library/RiscVEdk2SbiLib.h (100%)
> rename {Silicon/RISC-V/ProcessorPkg => RiscVPkg}/Include/Library/RiscVFirmwareContextLib.h (100%)
> rename {Silicon/RISC-V/ProcessorPkg => RiscVPkg}/Include/OpensbiTypes.h (100%)
> rename {Silicon/RISC-V/ProcessorPkg => RiscVPkg}/Include/ProcessorSpecificHobData.h (100%)
> rename {Silicon/RISC-V/ProcessorPkg => RiscVPkg}/Include/RiscVImpl.h (100%)
> rename {Silicon/RISC-V/ProcessorPkg => RiscVPkg}/Include/SmbiosProcessorSpecificData.h (100%)
> rename {Silicon/RISC-V/ProcessorPkg => RiscVPkg}/Library/RiscVExceptionLib/CpuExceptionHandlerLib.h (100%)
> rename {Silicon/RISC-V/ProcessorPkg => RiscVPkg}/Universal/CpuDxe/CpuDxe.h (100%)
> rename {Silicon/RISC-V/ProcessorPkg => RiscVPkg}/Universal/SmbiosDxe/RiscVSmbiosDxe.h (100%)
> rename {Silicon/RISC-V/ProcessorPkg => RiscVPkg}/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerOpenSbi.c (100%)
> rename {Silicon/RISC-V/ProcessorPkg => RiscVPkg}/Library/RiscVEdk2SbiLib/RiscVEdk2SbiLib.c (100%)
> rename {Silicon/RISC-V/ProcessorPkg => RiscVPkg}/Library/RiscVExceptionLib/CpuExceptionHandlerLib.c (100%)
> rename {Silicon/RISC-V/ProcessorPkg => RiscVPkg}/Library/RiscVFirmwareContextSbiLib/RiscVFirmwareContextSbiLib.c (100%)
> rename {Silicon/RISC-V/ProcessorPkg => RiscVPkg}/Library/RiscVFirmwareContextSscratchLib/RiscVFirmwareContextSscratchLib.c (100%)
> rename {Silicon/RISC-V/ProcessorPkg => RiscVPkg}/Library/RiscVFirmwareContextStvecLib/RiscVFirmwareContextStvecLib.c (100%)
> rename {Silicon/RISC-V/ProcessorPkg => RiscVPkg}/Library/RiscVTimerLib/RiscVTimerLib.c (100%)
> rename {Silicon/RISC-V/ProcessorPkg => RiscVPkg}/Universal/CpuDxe/CpuDxe.c (100%)
> rename {Silicon/RISC-V/ProcessorPkg => RiscVPkg}/Universal/FdtDxe/FdtDxe.c (100%)
> rename {Silicon/RISC-V/ProcessorPkg => RiscVPkg}/Universal/PciCpuIo2Dxe/PciCpuIo2Dxe.c (100%)
> rename {Silicon/RISC-V/ProcessorPkg => RiscVPkg}/Universal/SmbiosDxe/RiscVSmbiosDxe.c (100%)
> rename {Silicon/RISC-V/ProcessorPkg => RiscVPkg}/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerLibOpenSbi.uni (100%)
> rename {Silicon/RISC-V/ProcessorPkg => RiscVPkg}/Library/RiscVCpuLib/Cpu.S (100%)
> rename {Silicon/RISC-V/ProcessorPkg => RiscVPkg}/Library/RiscVExceptionLib/CpuExceptionHandlerLib.uni (100%)
> rename {Silicon/RISC-V/ProcessorPkg => RiscVPkg}/Library/RiscVExceptionLib/SupervisorTrapHandler.S (100%)
> rename {Silicon/RISC-V/ProcessorPkg => RiscVPkg}/Library/RiscVPlatformTimerLibNull/RiscVPlatformTimerLibNull.S (100%)
> rename {Silicon/RISC-V/ProcessorPkg => RiscVPkg}/Library/RiscVReadMachineModeTimer/EmulatedMachineModeTimerLib/EmulatedMachineModeTimerLib.S (100%)
> rename {Silicon/RISC-V/ProcessorPkg => RiscVPkg}/Library/RiscVReadMachineModeTimer/MachineModeTimerLib/MachineModeTimerLib.S (100%)
> rename Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.uni => RiscVPkg/RiscVPkg.uni (85%)
> rename Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkgExtra.uni => RiscVPkg/RiscVPkgExtra.uni (87%)
> rename {Silicon/RISC-V/ProcessorPkg => RiscVPkg}/Universal/CpuDxe/CpuDxe.uni (100%)
> rename {Silicon/RISC-V/ProcessorPkg => RiscVPkg}/Universal/CpuDxe/CpuDxeExtra.uni (100%)
> rename {Silicon/RISC-V/ProcessorPkg => RiscVPkg}/Universal/SmbiosDxe/RiscVSmbiosDxe.uni (100%)
> rename {Silicon/RISC-V/ProcessorPkg => RiscVPkg}/Universal/SmbiosDxe/RiscVSmbiosDxeExtra.uni (100%)
> delete mode 160000 Silicon/RISC-V/ProcessorPkg/Library/RiscVOpensbiLib/opensbi
>
> diff --git a/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec b/RiscVPkg/RiscVPkg.dec
> similarity index 92%
> rename from Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec
> rename to RiscVPkg/RiscVPkg.dec
> index 9c8b57cce3..f23d3c0135 100644
> --- a/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec
> +++ b/RiscVPkg/RiscVPkg.dec
> @@ -9,8 +9,8 @@
>
> [Defines]
> DEC_SPECIFICATION = 0x0001001b
> - PACKAGE_NAME = RiscVProcessorPkg
> - PACKAGE_UNI_FILE = RiscVProcessorPkg.uni
> + PACKAGE_NAME = RiscVPkg
> + PACKAGE_UNI_FILE = RiscVPkg.uni
> PACKAGE_GUID = 993C7CAC-C87C-4F08-A2CF-AD3AABA859D1
> PACKAGE_VERSION = 1.0
>
> @@ -46,4 +46,4 @@
> gUefiRiscVPkgTokenSpaceGuid.PcdRiscVMachineTimerFrequencyInHerz|10000000|UINT64|0x00001011
>
> [UserExtensions.TianoCore."ExtraFiles"]
> - RiscVProcessorPkgExtra.uni
> + RiscVPkgExtra.uni
> diff --git a/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dsc b/RiscVPkg/RiscVPkg.dsc
> similarity index 54%
> rename from Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dsc
> rename to RiscVPkg/RiscVPkg.dsc
> index 5c7425421b..41933160d6 100644
> --- a/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dsc
> +++ b/RiscVPkg/RiscVPkg.dsc
> @@ -1,5 +1,5 @@
> #/** @file
> -# RISC-V processor package.
> +# RISC-V package.
> #
> # Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> #
> @@ -13,7 +13,7 @@
> #
> ################################################################################
> [Defines]
> - PLATFORM_NAME = RiscVProcessor
> + PLATFORM_NAME = RiscV
> PLATFORM_GUID = 55D77916-B270-41B4-9325-2CE9DCE0926E
> PLATFORM_VERSION = 0.1
> DSC_SPECIFICATION = 0x0001001c
> @@ -39,13 +39,13 @@
> !include MdePkg/MdeLibs.dsc.inc
>
> [LibraryClasses.common]
> - CpuExceptionHandlerLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVExceptionLib/CpuExceptionHandlerDxeLib.inf
> - RiscVCpuLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVCpuLib/RiscVCpuLib.inf
> - RiscVEdk2SbiLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVEdk2SbiLib/RiscVEdk2SbiLib.inf
> - RiscVOpensbiLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVOpensbiLib/RiscVOpensbiLib.inf
> - TimerLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVTimerLib/BaseRiscVTimerLib.inf
> - MachineModeTimerLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVReadMachineModeTimer/MachineModeTimerLib/MachineModeTimerLib.inf
> - #MachineModeTimerLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVReadMachineModeTimer/EmulatedMachineModeTimerLib/EmulatedMachineModeTimerLib.inf
> + CpuExceptionHandlerLib|RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerDxeLib.inf
> + RiscVCpuLib|RiscVPkg/Library/RiscVCpuLib/RiscVCpuLib.inf
> + RiscVEdk2SbiLib|RiscVPkg/Library/RiscVEdk2SbiLib/RiscVEdk2SbiLib.inf
> + RiscVOpensbiLib|RiscVPkg/Library/RiscVOpensbiLib/RiscVOpensbiLib.inf
> + TimerLib|RiscVPkg/Library/RiscVTimerLib/BaseRiscVTimerLib.inf
> + MachineModeTimerLib|RiscVPkg/Library/RiscVReadMachineModeTimer/MachineModeTimerLib/MachineModeTimerLib.inf
> + #MachineModeTimerLib|RiscVPkg/Library/RiscVReadMachineModeTimer/EmulatedMachineModeTimerLib/EmulatedMachineModeTimerLib.inf
Is there a reason not to remove this?
Regards
Sunil
> BaseLib|MdePkg/Library/BaseLib/BaseLib.inf
> BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
> DebugAgentLib|MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLibNull.inf
> @@ -66,43 +66,43 @@
> UefiApplicationEntryPoint|MdePkg/Library/UefiApplicationEntryPoint/UefiApplicationEntryPoint.inf
> UefiLib|MdePkg/Library/UefiLib/UefiLib.inf
> DevicePathLib|MdePkg/Library/UefiDevicePathLibDevicePathProtocol/UefiDevicePathLibDevicePathProtocol.inf
> - RiscVPlatformTimerLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVPlatformTimerLibNull/RiscVPlatformTimerLib.inf
> + RiscVPlatformTimerLib|RiscVPkg/Library/RiscVPlatformTimerLibNull/RiscVPlatformTimerLib.inf
>
> [LibraryClasses.common.PEI_CORE]
> - PeiServicesTablePointerLib|Silicon/RISC-V/ProcessorPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerLibOpenSbi.inf
> - RiscVFirmwareContextLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSbiLib/RiscVFirmwareContextSbiLib.inf
> + PeiServicesTablePointerLib|RiscVPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerLibOpenSbi.inf
> + RiscVFirmwareContextLib|RiscVPkg/Library/RiscVFirmwareContextSbiLib/RiscVFirmwareContextSbiLib.inf
>
> [LibraryClasses.common.PEIM]
> - PeiServicesTablePointerLib|Silicon/RISC-V/ProcessorPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerLibOpenSbi.inf
> - RiscVFirmwareContextLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSbiLib/RiscVFirmwareContextSbiLib.inf
> + PeiServicesTablePointerLib|RiscVPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerLibOpenSbi.inf
> + RiscVFirmwareContextLib|RiscVPkg/Library/RiscVFirmwareContextSbiLib/RiscVFirmwareContextSbiLib.inf
> HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
> MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf
> PeimEntryPoint|MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf
>
> [LibraryClasses.common.DXE_CORE]
> - TimerLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVTimerLib/BaseRiscVTimerLib.inf
> + TimerLib|RiscVPkg/Library/RiscVTimerLib/BaseRiscVTimerLib.inf
>
> [LibraryClasses.common.DXE_DRIVER]
> PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
> PlatformBootManagerLib|Platform/RISC-V/PlatformPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
>
> [LibraryClasses.common.DXE_RUNTIME_DRIVER]
> - TimerLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVTimerLib/BaseRiscVTimerLib.inf
> + TimerLib|RiscVPkg/Library/RiscVTimerLib/BaseRiscVTimerLib.inf
>
> [LibraryClasses.common.UEFI_DRIVER]
> - TimerLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVTimerLib/BaseRiscVTimerLib.inf
> + TimerLib|RiscVPkg/Library/RiscVTimerLib/BaseRiscVTimerLib.inf
>
> [Components]
> - Silicon/RISC-V/ProcessorPkg/Library/RiscVTimerLib/BaseRiscVTimerLib.inf
> - Silicon/RISC-V/ProcessorPkg/Library/RiscVExceptionLib/CpuExceptionHandlerDxeLib.inf
> - Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSbiLib/RiscVFirmwareContextSbiLib.inf
> - Silicon/RISC-V/ProcessorPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerLibOpenSbi.inf
> - Silicon/RISC-V/ProcessorPkg/Library/RiscVOpensbiLib/RiscVOpensbiLib.inf
> - Silicon/RISC-V/ProcessorPkg/Library/RiscVPlatformTimerLibNull/RiscVPlatformTimerLib.inf
> - Silicon/RISC-V/ProcessorPkg/Library/RiscVCpuLib/RiscVCpuLib.inf
> - Silicon/RISC-V/ProcessorPkg/Library/RiscVEdk2SbiLib/RiscVEdk2SbiLib.inf
> + RiscVPkg/Library/RiscVTimerLib/BaseRiscVTimerLib.inf
> + RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerDxeLib.inf
> + RiscVPkg/Library/RiscVFirmwareContextSbiLib/RiscVFirmwareContextSbiLib.inf
> + RiscVPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerLibOpenSbi.inf
> + RiscVPkg/Library/RiscVOpensbiLib/RiscVOpensbiLib.inf
> + RiscVPkg/Library/RiscVPlatformTimerLibNull/RiscVPlatformTimerLib.inf
> + RiscVPkg/Library/RiscVCpuLib/RiscVCpuLib.inf
> + RiscVPkg/Library/RiscVEdk2SbiLib/RiscVEdk2SbiLib.inf
>
> - Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxe.inf
> - Silicon/RISC-V/ProcessorPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.inf
> - Silicon/RISC-V/ProcessorPkg/Universal/FdtDxe/FdtDxe.inf
> - Silicon/RISC-V/ProcessorPkg/Universal/PciCpuIo2Dxe/PciCpuIo2Dxe.inf
> + RiscVPkg/Universal/CpuDxe/CpuDxe.inf
> + RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.inf
> + RiscVPkg/Universal/FdtDxe/FdtDxe.inf
> + RiscVPkg/Universal/PciCpuIo2Dxe/PciCpuIo2Dxe.inf
> diff --git a/RiscVPlatformPkg/RiscVPlatformPkg.dsc b/RiscVPlatformPkg/RiscVPlatformPkg.dsc
> index 2997465170..f7f5c3f7cd 100644
> --- a/RiscVPlatformPkg/RiscVPlatformPkg.dsc
> +++ b/RiscVPlatformPkg/RiscVPlatformPkg.dsc
> @@ -41,8 +41,8 @@
> [LibraryClasses.common]
> FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib.inf
> RiscVOpensbiPlatformLib|RiscVPlatformPkg/Library/OpensbiPlatformLib/OpensbiPlatformLib.inf
> - RiscVCpuLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVCpuLib/RiscVCpuLib.inf
> - RiscVEdk2SbiLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVEdk2SbiLib/RiscVEdk2SbiLib.inf
> + RiscVCpuLib|RiscVPkg/Library/RiscVCpuLib/RiscVCpuLib.inf
> + RiscVEdk2SbiLib|RiscVPkg/Library/RiscVEdk2SbiLib/RiscVEdk2SbiLib.inf
> BaseLib|MdePkg/Library/BaseLib/BaseLib.inf
> BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
> DebugAgentLib|MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLibNull.inf
> @@ -71,7 +71,7 @@
>
> [LibraryClasses.common.SEC]
> ExtractGuidedSectionLib|MdePkg/Library/BaseExtractGuidedSectionLib/BaseExtractGuidedSectionLib.inf
> - RiscVOpensbiLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVOpensbiLib/RiscVOpensbiLib.inf
> + RiscVOpensbiLib|RiscVPkg/Library/RiscVOpensbiLib/RiscVOpensbiLib.inf
> Edk2OpensbiPlatformWrapperLib|RiscVPlatformPkg/Library/Edk2OpensbiPlatformWrapperLib/Edk2OpensbiPlatformWrapperLib.inf
> RiscVSpecialPlatformLib|RiscVPlatformPkg/Library/RiscVSpecialPlatformLibNull/RiscVSpecialPlatformLibNull.inf
>
> diff --git a/Silicon/RISC-V/ProcessorPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerLibOpenSbi.inf b/RiscVPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerLibOpenSbi.inf
> similarity index 92%
> rename from Silicon/RISC-V/ProcessorPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerLibOpenSbi.inf
> rename to RiscVPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerLibOpenSbi.inf
> index fa9fe78518..d821168f3b 100644
> --- a/Silicon/RISC-V/ProcessorPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerLibOpenSbi.inf
> +++ b/RiscVPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerLibOpenSbi.inf
> @@ -30,7 +30,7 @@
>
> [Packages]
> MdePkg/MdePkg.dec
> - Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec
> + RiscVPkg/RiscVPkg.dec
>
> [LibraryClasses]
> DebugLib
> diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVCpuLib/RiscVCpuLib.inf b/RiscVPkg/Library/RiscVCpuLib/RiscVCpuLib.inf
> similarity index 89%
> rename from Silicon/RISC-V/ProcessorPkg/Library/RiscVCpuLib/RiscVCpuLib.inf
> rename to RiscVPkg/Library/RiscVCpuLib/RiscVCpuLib.inf
> index 7928dd5536..9d44dc4343 100644
> --- a/Silicon/RISC-V/ProcessorPkg/Library/RiscVCpuLib/RiscVCpuLib.inf
> +++ b/RiscVPkg/Library/RiscVCpuLib/RiscVCpuLib.inf
> @@ -29,6 +29,6 @@
> [Packages]
> MdeModulePkg/MdeModulePkg.dec
> MdePkg/MdePkg.dec
> - Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec
> + RiscVPkg/RiscVPkg.dec
>
>
> diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVEdk2SbiLib/RiscVEdk2SbiLib.inf b/RiscVPkg/Library/RiscVEdk2SbiLib/RiscVEdk2SbiLib.inf
> similarity index 79%
> rename from Silicon/RISC-V/ProcessorPkg/Library/RiscVEdk2SbiLib/RiscVEdk2SbiLib.inf
> rename to RiscVPkg/Library/RiscVEdk2SbiLib/RiscVEdk2SbiLib.inf
> index 18d6ebc2ac..75ef7c5b84 100644
> --- a/Silicon/RISC-V/ProcessorPkg/Library/RiscVEdk2SbiLib/RiscVEdk2SbiLib.inf
> +++ b/RiscVPkg/Library/RiscVEdk2SbiLib/RiscVEdk2SbiLib.inf
> @@ -20,8 +20,8 @@
>
> [Packages]
> MdePkg/MdePkg.dec
> - Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec
> - Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec
> + RiscVPkg/RiscVPkg.dec
> + RiscVPlatformPkg/RiscVPlatformPkg.dec
>
> [LibraryClasses]
> BaseLib
> diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVExceptionLib/CpuExceptionHandlerDxeLib.inf b/RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerDxeLib.inf
> similarity index 91%
> rename from Silicon/RISC-V/ProcessorPkg/Library/RiscVExceptionLib/CpuExceptionHandlerDxeLib.inf
> rename to RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerDxeLib.inf
> index fc200d3cca..2463bac815 100644
> --- a/Silicon/RISC-V/ProcessorPkg/Library/RiscVExceptionLib/CpuExceptionHandlerDxeLib.inf
> +++ b/RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerDxeLib.inf
> @@ -39,5 +39,5 @@
> [Packages]
> MdePkg/MdePkg.dec
> MdeModulePkg/MdeModulePkg.dec
> - Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec
> + RiscVPkg/RiscVPkg.dec
>
> diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSbiLib/RiscVFirmwareContextSbiLib.inf b/RiscVPkg/Library/RiscVFirmwareContextSbiLib/RiscVFirmwareContextSbiLib.inf
> similarity index 90%
> rename from Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSbiLib/RiscVFirmwareContextSbiLib.inf
> rename to RiscVPkg/Library/RiscVFirmwareContextSbiLib/RiscVFirmwareContextSbiLib.inf
> index 168b705453..db30d7e551 100644
> --- a/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSbiLib/RiscVFirmwareContextSbiLib.inf
> +++ b/RiscVPkg/Library/RiscVFirmwareContextSbiLib/RiscVFirmwareContextSbiLib.inf
> @@ -25,7 +25,7 @@
>
> [Packages]
> MdePkg/MdePkg.dec
> - Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec
> + RiscVPkg/RiscVPkg.dec
>
> [LibraryClasses]
> DebugLib
> diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSscratchLib/RiscVFirmwareContextSscratchLib.inf b/RiscVPkg/Library/RiscVFirmwareContextSscratchLib/RiscVFirmwareContextSscratchLib.inf
> similarity index 90%
> rename from Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSscratchLib/RiscVFirmwareContextSscratchLib.inf
> rename to RiscVPkg/Library/RiscVFirmwareContextSscratchLib/RiscVFirmwareContextSscratchLib.inf
> index 750c1cf51f..c6a74e5edc 100644
> --- a/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSscratchLib/RiscVFirmwareContextSscratchLib.inf
> +++ b/RiscVPkg/Library/RiscVFirmwareContextSscratchLib/RiscVFirmwareContextSscratchLib.inf
> @@ -25,7 +25,7 @@
>
> [Packages]
> MdePkg/MdePkg.dec
> - Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec
> + RiscVPkg/RiscVPkg.dec
>
> [LibraryClasses]
> DebugLib
> diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextStvecLib/RiscVFirmwareContextStvecLib.inf b/RiscVPkg/Library/RiscVFirmwareContextStvecLib/RiscVFirmwareContextStvecLib.inf
> similarity index 89%
> rename from Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextStvecLib/RiscVFirmwareContextStvecLib.inf
> rename to RiscVPkg/Library/RiscVFirmwareContextStvecLib/RiscVFirmwareContextStvecLib.inf
> index fa894cda91..9888cac81a 100644
> --- a/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextStvecLib/RiscVFirmwareContextStvecLib.inf
> +++ b/RiscVPkg/Library/RiscVFirmwareContextStvecLib/RiscVFirmwareContextStvecLib.inf
> @@ -25,7 +25,7 @@
>
> [Packages]
> MdePkg/MdePkg.dec
> - Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec
> + RiscVPkg/RiscVPkg.dec
>
> [LibraryClasses]
> DebugLib
> diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVOpensbiLib/RiscVOpensbiLib.inf b/RiscVPkg/Library/RiscVOpensbiLib/RiscVOpensbiLib.inf
> similarity index 95%
> rename from Silicon/RISC-V/ProcessorPkg/Library/RiscVOpensbiLib/RiscVOpensbiLib.inf
> rename to RiscVPkg/Library/RiscVOpensbiLib/RiscVOpensbiLib.inf
> index e40a797896..31bdc9e4a7 100644
> --- a/Silicon/RISC-V/ProcessorPkg/Library/RiscVOpensbiLib/RiscVOpensbiLib.inf
> +++ b/RiscVPkg/Library/RiscVOpensbiLib/RiscVOpensbiLib.inf
> @@ -83,7 +83,7 @@
> [Packages]
> EmbeddedPkg/EmbeddedPkg.dec # For libfdt.
> MdePkg/MdePkg.dec
> - Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec
> + RiscVPkg/RiscVPkg.dec
>
> [BuildOptions]
> GCC:*_*_*_PP_FLAGS = -D__ASSEMBLY__
> diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVPlatformTimerLibNull/RiscVPlatformTimerLib.inf b/RiscVPkg/Library/RiscVPlatformTimerLibNull/RiscVPlatformTimerLib.inf
> similarity index 100%
> rename from Silicon/RISC-V/ProcessorPkg/Library/RiscVPlatformTimerLibNull/RiscVPlatformTimerLib.inf
> rename to RiscVPkg/Library/RiscVPlatformTimerLibNull/RiscVPlatformTimerLib.inf
> diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVReadMachineModeTimer/EmulatedMachineModeTimerLib/EmulatedMachineModeTimerLib.inf b/RiscVPkg/Library/RiscVReadMachineModeTimer/EmulatedMachineModeTimerLib/EmulatedMachineModeTimerLib.inf
> similarity index 89%
> rename from Silicon/RISC-V/ProcessorPkg/Library/RiscVReadMachineModeTimer/EmulatedMachineModeTimerLib/EmulatedMachineModeTimerLib.inf
> rename to RiscVPkg/Library/RiscVReadMachineModeTimer/EmulatedMachineModeTimerLib/EmulatedMachineModeTimerLib.inf
> index 369028a9a6..7a21a4267c 100644
> --- a/Silicon/RISC-V/ProcessorPkg/Library/RiscVReadMachineModeTimer/EmulatedMachineModeTimerLib/EmulatedMachineModeTimerLib.inf
> +++ b/RiscVPkg/Library/RiscVReadMachineModeTimer/EmulatedMachineModeTimerLib/EmulatedMachineModeTimerLib.inf
> @@ -28,7 +28,7 @@
>
> [Packages]
> MdePkg/MdePkg.dec
> - Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec
> + RiscVPkg/RiscVPkg.dec
>
>
>
> diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVReadMachineModeTimer/MachineModeTimerLib/MachineModeTimerLib.inf b/RiscVPkg/Library/RiscVReadMachineModeTimer/MachineModeTimerLib/MachineModeTimerLib.inf
> similarity index 89%
> rename from Silicon/RISC-V/ProcessorPkg/Library/RiscVReadMachineModeTimer/MachineModeTimerLib/MachineModeTimerLib.inf
> rename to RiscVPkg/Library/RiscVReadMachineModeTimer/MachineModeTimerLib/MachineModeTimerLib.inf
> index 71d4315445..fb67ce8bba 100644
> --- a/Silicon/RISC-V/ProcessorPkg/Library/RiscVReadMachineModeTimer/MachineModeTimerLib/MachineModeTimerLib.inf
> +++ b/RiscVPkg/Library/RiscVReadMachineModeTimer/MachineModeTimerLib/MachineModeTimerLib.inf
> @@ -28,7 +28,7 @@
>
> [Packages]
> MdePkg/MdePkg.dec
> - Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec
> + RiscVPkg/RiscVPkg.dec
>
> [LibraryClasses]
> RiscVCpuLib
> diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVTimerLib/BaseRiscVTimerLib.inf b/RiscVPkg/Library/RiscVTimerLib/BaseRiscVTimerLib.inf
> similarity index 88%
> rename from Silicon/RISC-V/ProcessorPkg/Library/RiscVTimerLib/BaseRiscVTimerLib.inf
> rename to RiscVPkg/Library/RiscVTimerLib/BaseRiscVTimerLib.inf
> index 3c61149da8..5fb1adf160 100644
> --- a/Silicon/RISC-V/ProcessorPkg/Library/RiscVTimerLib/BaseRiscVTimerLib.inf
> +++ b/RiscVPkg/Library/RiscVTimerLib/BaseRiscVTimerLib.inf
> @@ -20,7 +20,7 @@
>
> [Packages]
> MdePkg/MdePkg.dec
> - Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec
> + RiscVPkg/RiscVPkg.dec
>
> [Pcd]
> gUefiRiscVPkgTokenSpaceGuid.PcdRiscVMachineTimerTickInNanoSecond
> diff --git a/Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxe.inf b/RiscVPkg/Universal/CpuDxe/CpuDxe.inf
> similarity index 91%
> rename from Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxe.inf
> rename to RiscVPkg/Universal/CpuDxe/CpuDxe.inf
> index a422c12e32..77e8273ab9 100644
> --- a/Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxe.inf
> +++ b/RiscVPkg/Universal/CpuDxe/CpuDxe.inf
> @@ -19,7 +19,7 @@
> [Packages]
> MdeModulePkg/MdeModulePkg.dec
> MdePkg/MdePkg.dec
> - Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec
> + RiscVPkg/RiscVPkg.dec
>
> [LibraryClasses]
> BaseLib
> diff --git a/Silicon/RISC-V/ProcessorPkg/Universal/FdtDxe/FdtDxe.inf b/RiscVPkg/Universal/FdtDxe/FdtDxe.inf
> similarity index 90%
> rename from Silicon/RISC-V/ProcessorPkg/Universal/FdtDxe/FdtDxe.inf
> rename to RiscVPkg/Universal/FdtDxe/FdtDxe.inf
> index ae6468f9f5..acc7d1da15 100644
> --- a/Silicon/RISC-V/ProcessorPkg/Universal/FdtDxe/FdtDxe.inf
> +++ b/RiscVPkg/Universal/FdtDxe/FdtDxe.inf
> @@ -25,7 +25,7 @@
> EmbeddedPkg/EmbeddedPkg.dec
> MdeModulePkg/MdeModulePkg.dec
> MdePkg/MdePkg.dec
> - Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec
> + RiscVPlatformPkg/RiscVPlatformPkg.dec
> EmbeddedPkg/EmbeddedPkg.dec
>
> [LibraryClasses]
> diff --git a/Silicon/RISC-V/ProcessorPkg/Universal/PciCpuIo2Dxe/PciCpuIo2Dxe.inf b/RiscVPkg/Universal/PciCpuIo2Dxe/PciCpuIo2Dxe.inf
> similarity index 100%
> rename from Silicon/RISC-V/ProcessorPkg/Universal/PciCpuIo2Dxe/PciCpuIo2Dxe.inf
> rename to RiscVPkg/Universal/PciCpuIo2Dxe/PciCpuIo2Dxe.inf
> diff --git a/Silicon/RISC-V/ProcessorPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.inf b/RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.inf
> similarity index 92%
> rename from Silicon/RISC-V/ProcessorPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.inf
> rename to RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.inf
> index 0fcfe1d3ad..7a3c51700a 100644
> --- a/Silicon/RISC-V/ProcessorPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.inf
> +++ b/RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.inf
> @@ -19,7 +19,7 @@
> [Packages]
> MdeModulePkg/MdeModulePkg.dec
> MdePkg/MdePkg.dec
> - Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec
> + RiscVPkg/RiscVPkg.dec
>
> [LibraryClasses]
> BaseLib
> diff --git a/RiscVPlatformPkg/Library/Edk2OpensbiPlatformWrapperLib/Edk2OpensbiPlatformWrapperLib.inf b/RiscVPlatformPkg/Library/Edk2OpensbiPlatformWrapperLib/Edk2OpensbiPlatformWrapperLib.inf
> index 92723840c4..f19dd6b0e6 100644
> --- a/RiscVPlatformPkg/Library/Edk2OpensbiPlatformWrapperLib/Edk2OpensbiPlatformWrapperLib.inf
> +++ b/RiscVPlatformPkg/Library/Edk2OpensbiPlatformWrapperLib/Edk2OpensbiPlatformWrapperLib.inf
> @@ -28,7 +28,7 @@
> MdeModulePkg/MdeModulePkg.dec
> MdePkg/MdePkg.dec
> RiscVPlatformPkg/RiscVPlatformPkg.dec
> - Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec
> + RiscVPkg/RiscVPkg.dec
>
> [Pcd]
> gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFirmwareDomainBaseAddress
> diff --git a/RiscVPlatformPkg/Library/FirmwareContextProcessorSpecificLib/FirmwareContextProcessorSpecificLib.inf b/RiscVPlatformPkg/Library/FirmwareContextProcessorSpecificLib/FirmwareContextProcessorSpecificLib.inf
> index 69568511ce..8ea37ae4f4 100644
> --- a/RiscVPlatformPkg/Library/FirmwareContextProcessorSpecificLib/FirmwareContextProcessorSpecificLib.inf
> +++ b/RiscVPlatformPkg/Library/FirmwareContextProcessorSpecificLib/FirmwareContextProcessorSpecificLib.inf
> @@ -20,7 +20,7 @@
> [Packages]
> MdeModulePkg/MdeModulePkg.dec
> MdePkg/MdePkg.dec
> - Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec
> + RiscVPkg/RiscVPkg.dec
>
> [LibraryClasses]
> BaseLib
> diff --git a/RiscVPlatformPkg/Library/OpensbiPlatformLib/OpensbiPlatformLib.inf b/RiscVPlatformPkg/Library/OpensbiPlatformLib/OpensbiPlatformLib.inf
> index b073dd914c..8e3f07d833 100644
> --- a/RiscVPlatformPkg/Library/OpensbiPlatformLib/OpensbiPlatformLib.inf
> +++ b/RiscVPlatformPkg/Library/OpensbiPlatformLib/OpensbiPlatformLib.inf
> @@ -32,7 +32,7 @@
> MdePkg/MdePkg.dec
> Platform/SiFive/U5SeriesPkg/U5SeriesPkg.dec
> RiscVPlatformPkg/RiscVPlatformPkg.dec
> - Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec
> + RiscVPkg/RiscVPkg.dec
>
> [LibraryClasses]
> BaseLib
> diff --git a/RiscVPlatformPkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.inf b/RiscVPlatformPkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.inf
> index fe6d28c038..af453f6650 100644
> --- a/RiscVPlatformPkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.inf
> +++ b/RiscVPlatformPkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.inf
> @@ -27,7 +27,7 @@
> [Packages]
> MdePkg/MdePkg.dec
> RiscVPlatformPkg/RiscVPlatformPkg.dec
> - Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec
> + RiscVPkg/RiscVPkg.dec
>
> [LibraryClasses]
> BaseLib
> diff --git a/RiscVPlatformPkg/Library/PeiCoreInfoHobLibNull/PeiCoreInfoHobLib.inf b/RiscVPlatformPkg/Library/PeiCoreInfoHobLibNull/PeiCoreInfoHobLib.inf
> index 2a0c3f6fd8..51facae79a 100644
> --- a/RiscVPlatformPkg/Library/PeiCoreInfoHobLibNull/PeiCoreInfoHobLib.inf
> +++ b/RiscVPlatformPkg/Library/PeiCoreInfoHobLibNull/PeiCoreInfoHobLib.inf
> @@ -28,7 +28,7 @@
> MdePkg/MdePkg.dec
> MdeModulePkg/MdeModulePkg.dec
> RiscVPlatformPkg/RiscVPlatformPkg.dec
> - Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec
> + RiscVPkg/RiscVPkg.dec
>
> [LibraryClasses]
> BaseLib
> diff --git a/RiscVPlatformPkg/Library/PlatformSecPpiLibNull/PlatformSecPpiLibNull.inf b/RiscVPlatformPkg/Library/PlatformSecPpiLibNull/PlatformSecPpiLibNull.inf
> index 3712b20554..5b3570ce6d 100644
> --- a/RiscVPlatformPkg/Library/PlatformSecPpiLibNull/PlatformSecPpiLibNull.inf
> +++ b/RiscVPlatformPkg/Library/PlatformSecPpiLibNull/PlatformSecPpiLibNull.inf
> @@ -28,7 +28,6 @@
> MdePkg/MdePkg.dec
> MdeModulePkg/MdeModulePkg.dec
> RiscVPlatformPkg/RiscVPlatformPkg.dec
> - #Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec
>
> [LibraryClasses]
> #BaseLib
> diff --git a/RiscVPlatformPkg/Library/ResetSystemLib/ResetSystemLib.inf b/RiscVPlatformPkg/Library/ResetSystemLib/ResetSystemLib.inf
> index f876ae2056..0ce1e90b70 100644
> --- a/RiscVPlatformPkg/Library/ResetSystemLib/ResetSystemLib.inf
> +++ b/RiscVPlatformPkg/Library/ResetSystemLib/ResetSystemLib.inf
> @@ -26,7 +26,7 @@
> [Packages]
> MdePkg/MdePkg.dec
> MdeModulePkg/MdeModulePkg.dec
> - Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec
> + RiscVPkg/RiscVPkg.dec
>
> [LibraryClasses]
> DebugLib
> diff --git a/RiscVPlatformPkg/Library/RiscVSpecialPlatformLibNull/RiscVSpecialPlatformLibNull.inf b/RiscVPlatformPkg/Library/RiscVSpecialPlatformLibNull/RiscVSpecialPlatformLibNull.inf
> index 1bcd550d8b..3f2e5eec18 100644
> --- a/RiscVPlatformPkg/Library/RiscVSpecialPlatformLibNull/RiscVSpecialPlatformLibNull.inf
> +++ b/RiscVPlatformPkg/Library/RiscVSpecialPlatformLibNull/RiscVSpecialPlatformLibNull.inf
> @@ -30,7 +30,7 @@
> MdePkg/MdePkg.dec
> MdeModulePkg/MdeModulePkg.dec
> RiscVPlatformPkg/RiscVPlatformPkg.dec
> - Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec
> + RiscVPkg/RiscVPkg.dec
>
> [LibraryClasses]
> BaseLib
> diff --git a/RiscVPlatformPkg/Universal/FdtPeim/FdtPeim.inf b/RiscVPlatformPkg/Universal/FdtPeim/FdtPeim.inf
> index 8dc58f0a8b..33b7f89805 100644
> --- a/RiscVPlatformPkg/Universal/FdtPeim/FdtPeim.inf
> +++ b/RiscVPlatformPkg/Universal/FdtPeim/FdtPeim.inf
> @@ -30,7 +30,7 @@
> EmbeddedPkg/EmbeddedPkg.dec
> MdePkg/MdePkg.dec
> MdeModulePkg/MdeModulePkg.dec
> - Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec
> + RiscVPkg/RiscVPkg.dec
>
> [LibraryClasses]
> DebugLib
> diff --git a/RiscVPlatformPkg/Universal/Pei/PlatformPei/PlatformPei.inf b/RiscVPlatformPkg/Universal/Pei/PlatformPei/PlatformPei.inf
> index 06243bc8c3..4b8e074b16 100644
> --- a/RiscVPlatformPkg/Universal/Pei/PlatformPei/PlatformPei.inf
> +++ b/RiscVPlatformPkg/Universal/Pei/PlatformPei/PlatformPei.inf
> @@ -32,7 +32,7 @@
> MdeModulePkg/MdeModulePkg.dec
> MdePkg/MdePkg.dec
> RiscVPlatformPkg/RiscVPlatformPkg.dec
> - Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec
> + RiscVPkg/RiscVPkg.dec
> UefiCpuPkg/UefiCpuPkg.dec
>
> [Guids]
> diff --git a/RiscVPlatformPkg/Universal/Sec/SecMain.inf b/RiscVPlatformPkg/Universal/Sec/SecMain.inf
> index 8f4b167ed2..caed51a54c 100644
> --- a/RiscVPlatformPkg/Universal/Sec/SecMain.inf
> +++ b/RiscVPlatformPkg/Universal/Sec/SecMain.inf
> @@ -31,7 +31,7 @@
> EmbeddedPkg/EmbeddedPkg.dec
> MdeModulePkg/MdeModulePkg.dec
> MdePkg/MdePkg.dec
> - Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec
> + RiscVPkg/RiscVPkg.dec
> RiscVPlatformPkg/RiscVPlatformPkg.dec
>
> [LibraryClasses]
> diff --git a/Silicon/RISC-V/ProcessorPkg/Include/IndustryStandard/RiscV.h b/RiscVPkg/Include/IndustryStandard/RiscV.h
> similarity index 100%
> rename from Silicon/RISC-V/ProcessorPkg/Include/IndustryStandard/RiscV.h
> rename to RiscVPkg/Include/IndustryStandard/RiscV.h
> diff --git a/Silicon/RISC-V/ProcessorPkg/Include/IndustryStandard/RiscVOpensbi.h b/RiscVPkg/Include/IndustryStandard/RiscVOpensbi.h
> similarity index 100%
> rename from Silicon/RISC-V/ProcessorPkg/Include/IndustryStandard/RiscVOpensbi.h
> rename to RiscVPkg/Include/IndustryStandard/RiscVOpensbi.h
> diff --git a/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVCpuLib.h b/RiscVPkg/Include/Library/RiscVCpuLib.h
> similarity index 100%
> rename from Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVCpuLib.h
> rename to RiscVPkg/Include/Library/RiscVCpuLib.h
> diff --git a/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVEdk2SbiLib.h b/RiscVPkg/Include/Library/RiscVEdk2SbiLib.h
> similarity index 100%
> rename from Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVEdk2SbiLib.h
> rename to RiscVPkg/Include/Library/RiscVEdk2SbiLib.h
> diff --git a/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVFirmwareContextLib.h b/RiscVPkg/Include/Library/RiscVFirmwareContextLib.h
> similarity index 100%
> rename from Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVFirmwareContextLib.h
> rename to RiscVPkg/Include/Library/RiscVFirmwareContextLib.h
> diff --git a/Silicon/RISC-V/ProcessorPkg/Include/OpensbiTypes.h b/RiscVPkg/Include/OpensbiTypes.h
> similarity index 100%
> rename from Silicon/RISC-V/ProcessorPkg/Include/OpensbiTypes.h
> rename to RiscVPkg/Include/OpensbiTypes.h
> diff --git a/Silicon/RISC-V/ProcessorPkg/Include/ProcessorSpecificHobData.h b/RiscVPkg/Include/ProcessorSpecificHobData.h
> similarity index 100%
> rename from Silicon/RISC-V/ProcessorPkg/Include/ProcessorSpecificHobData.h
> rename to RiscVPkg/Include/ProcessorSpecificHobData.h
> diff --git a/Silicon/RISC-V/ProcessorPkg/Include/RiscVImpl.h b/RiscVPkg/Include/RiscVImpl.h
> similarity index 100%
> rename from Silicon/RISC-V/ProcessorPkg/Include/RiscVImpl.h
> rename to RiscVPkg/Include/RiscVImpl.h
> diff --git a/Silicon/RISC-V/ProcessorPkg/Include/SmbiosProcessorSpecificData.h b/RiscVPkg/Include/SmbiosProcessorSpecificData.h
> similarity index 100%
> rename from Silicon/RISC-V/ProcessorPkg/Include/SmbiosProcessorSpecificData.h
> rename to RiscVPkg/Include/SmbiosProcessorSpecificData.h
> diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVExceptionLib/CpuExceptionHandlerLib.h b/RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerLib.h
> similarity index 100%
> rename from Silicon/RISC-V/ProcessorPkg/Library/RiscVExceptionLib/CpuExceptionHandlerLib.h
> rename to RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerLib.h
> diff --git a/Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxe.h b/RiscVPkg/Universal/CpuDxe/CpuDxe.h
> similarity index 100%
> rename from Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxe.h
> rename to RiscVPkg/Universal/CpuDxe/CpuDxe.h
> diff --git a/Silicon/RISC-V/ProcessorPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.h b/RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.h
> similarity index 100%
> rename from Silicon/RISC-V/ProcessorPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.h
> rename to RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.h
> diff --git a/Silicon/RISC-V/ProcessorPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerOpenSbi.c b/RiscVPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerOpenSbi.c
> similarity index 100%
> rename from Silicon/RISC-V/ProcessorPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerOpenSbi.c
> rename to RiscVPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerOpenSbi.c
> diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVEdk2SbiLib/RiscVEdk2SbiLib.c b/RiscVPkg/Library/RiscVEdk2SbiLib/RiscVEdk2SbiLib.c
> similarity index 100%
> rename from Silicon/RISC-V/ProcessorPkg/Library/RiscVEdk2SbiLib/RiscVEdk2SbiLib.c
> rename to RiscVPkg/Library/RiscVEdk2SbiLib/RiscVEdk2SbiLib.c
> diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVExceptionLib/CpuExceptionHandlerLib.c b/RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerLib.c
> similarity index 100%
> rename from Silicon/RISC-V/ProcessorPkg/Library/RiscVExceptionLib/CpuExceptionHandlerLib.c
> rename to RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerLib.c
> diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSbiLib/RiscVFirmwareContextSbiLib.c b/RiscVPkg/Library/RiscVFirmwareContextSbiLib/RiscVFirmwareContextSbiLib.c
> similarity index 100%
> rename from Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSbiLib/RiscVFirmwareContextSbiLib.c
> rename to RiscVPkg/Library/RiscVFirmwareContextSbiLib/RiscVFirmwareContextSbiLib.c
> diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSscratchLib/RiscVFirmwareContextSscratchLib.c b/RiscVPkg/Library/RiscVFirmwareContextSscratchLib/RiscVFirmwareContextSscratchLib.c
> similarity index 100%
> rename from Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSscratchLib/RiscVFirmwareContextSscratchLib.c
> rename to RiscVPkg/Library/RiscVFirmwareContextSscratchLib/RiscVFirmwareContextSscratchLib.c
> diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextStvecLib/RiscVFirmwareContextStvecLib.c b/RiscVPkg/Library/RiscVFirmwareContextStvecLib/RiscVFirmwareContextStvecLib.c
> similarity index 100%
> rename from Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextStvecLib/RiscVFirmwareContextStvecLib.c
> rename to RiscVPkg/Library/RiscVFirmwareContextStvecLib/RiscVFirmwareContextStvecLib.c
> diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVTimerLib/RiscVTimerLib.c b/RiscVPkg/Library/RiscVTimerLib/RiscVTimerLib.c
> similarity index 100%
> rename from Silicon/RISC-V/ProcessorPkg/Library/RiscVTimerLib/RiscVTimerLib.c
> rename to RiscVPkg/Library/RiscVTimerLib/RiscVTimerLib.c
> diff --git a/Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxe.c b/RiscVPkg/Universal/CpuDxe/CpuDxe.c
> similarity index 100%
> rename from Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxe.c
> rename to RiscVPkg/Universal/CpuDxe/CpuDxe.c
> diff --git a/Silicon/RISC-V/ProcessorPkg/Universal/FdtDxe/FdtDxe.c b/RiscVPkg/Universal/FdtDxe/FdtDxe.c
> similarity index 100%
> rename from Silicon/RISC-V/ProcessorPkg/Universal/FdtDxe/FdtDxe.c
> rename to RiscVPkg/Universal/FdtDxe/FdtDxe.c
> diff --git a/Silicon/RISC-V/ProcessorPkg/Universal/PciCpuIo2Dxe/PciCpuIo2Dxe.c b/RiscVPkg/Universal/PciCpuIo2Dxe/PciCpuIo2Dxe.c
> similarity index 100%
> rename from Silicon/RISC-V/ProcessorPkg/Universal/PciCpuIo2Dxe/PciCpuIo2Dxe.c
> rename to RiscVPkg/Universal/PciCpuIo2Dxe/PciCpuIo2Dxe.c
> diff --git a/Silicon/RISC-V/ProcessorPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.c b/RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.c
> similarity index 100%
> rename from Silicon/RISC-V/ProcessorPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.c
> rename to RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.c
> diff --git a/Silicon/RISC-V/ProcessorPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerLibOpenSbi.uni b/RiscVPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerLibOpenSbi.uni
> similarity index 100%
> rename from Silicon/RISC-V/ProcessorPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerLibOpenSbi.uni
> rename to RiscVPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerLibOpenSbi.uni
> diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVCpuLib/Cpu.S b/RiscVPkg/Library/RiscVCpuLib/Cpu.S
> similarity index 100%
> rename from Silicon/RISC-V/ProcessorPkg/Library/RiscVCpuLib/Cpu.S
> rename to RiscVPkg/Library/RiscVCpuLib/Cpu.S
> diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVExceptionLib/CpuExceptionHandlerLib.uni b/RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerLib.uni
> similarity index 100%
> rename from Silicon/RISC-V/ProcessorPkg/Library/RiscVExceptionLib/CpuExceptionHandlerLib.uni
> rename to RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerLib.uni
> diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVExceptionLib/SupervisorTrapHandler.S b/RiscVPkg/Library/RiscVExceptionLib/SupervisorTrapHandler.S
> similarity index 100%
> rename from Silicon/RISC-V/ProcessorPkg/Library/RiscVExceptionLib/SupervisorTrapHandler.S
> rename to RiscVPkg/Library/RiscVExceptionLib/SupervisorTrapHandler.S
> diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVPlatformTimerLibNull/RiscVPlatformTimerLibNull.S b/RiscVPkg/Library/RiscVPlatformTimerLibNull/RiscVPlatformTimerLibNull.S
> similarity index 100%
> rename from Silicon/RISC-V/ProcessorPkg/Library/RiscVPlatformTimerLibNull/RiscVPlatformTimerLibNull.S
> rename to RiscVPkg/Library/RiscVPlatformTimerLibNull/RiscVPlatformTimerLibNull.S
> diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVReadMachineModeTimer/EmulatedMachineModeTimerLib/EmulatedMachineModeTimerLib.S b/RiscVPkg/Library/RiscVReadMachineModeTimer/EmulatedMachineModeTimerLib/EmulatedMachineModeTimerLib.S
> similarity index 100%
> rename from Silicon/RISC-V/ProcessorPkg/Library/RiscVReadMachineModeTimer/EmulatedMachineModeTimerLib/EmulatedMachineModeTimerLib.S
> rename to RiscVPkg/Library/RiscVReadMachineModeTimer/EmulatedMachineModeTimerLib/EmulatedMachineModeTimerLib.S
> diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVReadMachineModeTimer/MachineModeTimerLib/MachineModeTimerLib.S b/RiscVPkg/Library/RiscVReadMachineModeTimer/MachineModeTimerLib/MachineModeTimerLib.S
> similarity index 100%
> rename from Silicon/RISC-V/ProcessorPkg/Library/RiscVReadMachineModeTimer/MachineModeTimerLib/MachineModeTimerLib.S
> rename to RiscVPkg/Library/RiscVReadMachineModeTimer/MachineModeTimerLib/MachineModeTimerLib.S
> diff --git a/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.uni b/RiscVPkg/RiscVPkg.uni
> similarity index 85%
> rename from Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.uni
> rename to RiscVPkg/RiscVPkg.uni
> index 83da92fe40..7e470eb531 100644
> --- a/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.uni
> +++ b/RiscVPkg/RiscVPkg.uni
> @@ -1,5 +1,5 @@
> // /** @file
> -// RISC-V Processor Package Localized Strings and Content.
> +// RISC-V Package Localized Strings and Content.
> //
> // Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> //
> diff --git a/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkgExtra.uni b/RiscVPkg/RiscVPkgExtra.uni
> similarity index 87%
> rename from Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkgExtra.uni
> rename to RiscVPkg/RiscVPkgExtra.uni
> index 207adfb671..f0f2019337 100644
> --- a/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkgExtra.uni
> +++ b/RiscVPkg/RiscVPkgExtra.uni
> @@ -9,5 +9,5 @@
>
> #string STR_PROPERTIES_PACKAGE_NAME
> #language en-US
> -"RISC-V processor package"
> +"RISC-V package"
>
> diff --git a/Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxe.uni b/RiscVPkg/Universal/CpuDxe/CpuDxe.uni
> similarity index 100%
> rename from Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxe.uni
> rename to RiscVPkg/Universal/CpuDxe/CpuDxe.uni
> diff --git a/Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxeExtra.uni b/RiscVPkg/Universal/CpuDxe/CpuDxeExtra.uni
> similarity index 100%
> rename from Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxeExtra.uni
> rename to RiscVPkg/Universal/CpuDxe/CpuDxeExtra.uni
> diff --git a/Silicon/RISC-V/ProcessorPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.uni b/RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.uni
> similarity index 100%
> rename from Silicon/RISC-V/ProcessorPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.uni
> rename to RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.uni
> diff --git a/Silicon/RISC-V/ProcessorPkg/Universal/SmbiosDxe/RiscVSmbiosDxeExtra.uni b/RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxeExtra.uni
> similarity index 100%
> rename from Silicon/RISC-V/ProcessorPkg/Universal/SmbiosDxe/RiscVSmbiosDxeExtra.uni
> rename to RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxeExtra.uni
> diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVOpensbiLib/opensbi b/Silicon/RISC-V/ProcessorPkg/Library/RiscVOpensbiLib/opensbi
> deleted file mode 160000
> index a731c7e369..0000000000
> --- a/Silicon/RISC-V/ProcessorPkg/Library/RiscVOpensbiLib/opensbi
> +++ /dev/null
> @@ -1 +0,0 @@
> -Subproject commit a731c7e36988c3308e1978ecde491f2f6182d490
> --
> 2.31.1
>
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 65/79] RiscVPkg/PlatformPei: Fix the build error
[not found] ` <20220108041420.16064-4-abner.chang@hpe.com>
@ 2022-01-09 14:28 ` Sunil V L
0 siblings, 0 replies; 7+ messages in thread
From: Sunil V L @ 2022-01-09 14:28 UTC (permalink / raw)
To: Abner Chang; +Cc: devel, Daniel Schaefer
On Sat, Jan 08, 2022 at 12:14:06PM +0800, Abner Chang wrote:
> Fix the build error caused by the dependency with edk2-platform code.
>
> Signed-off-by: Abner Chang <abner.chang@hpe.com>
> Cc: Daniel Schaefer <daniel.schaefer@hpe.com>
> Cc: Sunil V L <sunilvl@ventanamicro.com>
> ---
> .../Universal/Pei/PlatformPei/PlatformPei.inf | 3 ---
> RiscVPlatformPkg/Universal/Pei/PlatformPei/Platform.h | 11 +++++++++++
> RiscVPlatformPkg/Universal/Pei/PlatformPei/Platform.c | 2 --
> 3 files changed, 11 insertions(+), 5 deletions(-)
>
> diff --git a/RiscVPlatformPkg/Universal/Pei/PlatformPei/PlatformPei.inf b/RiscVPlatformPkg/Universal/Pei/PlatformPei/PlatformPei.inf
> index 4b8e074b16..7a88099150 100644
> --- a/RiscVPlatformPkg/Universal/Pei/PlatformPei/PlatformPei.inf
> +++ b/RiscVPlatformPkg/Universal/Pei/PlatformPei/PlatformPei.inf
> @@ -37,7 +37,6 @@
>
> [Guids]
> gEfiMemoryTypeInformationGuid
> - gSiFiveU5SeriesPlatformsPkgTokenSpaceGuid
>
> [LibraryClasses]
> DebugLib
> @@ -62,8 +61,6 @@
> gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVDxeFvSize
> gUefiRiscVPlatformPkgTokenSpaceGuid.PcdTemporaryRamBase
> gUefiRiscVPlatformPkgTokenSpaceGuid.PcdTemporaryRamSize
> - gSiFiveU5SeriesPlatformsPkgTokenSpaceGuid.PcdNumberofU5Cores
> - gSiFiveU5SeriesPlatformsPkgTokenSpaceGuid.PcdE5MCSupported
>
> [Ppis]
> gEfiPeiMasterBootModePpiGuid
> diff --git a/RiscVPlatformPkg/Universal/Pei/PlatformPei/Platform.h b/RiscVPlatformPkg/Universal/Pei/PlatformPei/Platform.h
> index c2cdd6d75b..00cf7f9dd7 100644
> --- a/RiscVPlatformPkg/Universal/Pei/PlatformPei/Platform.h
> +++ b/RiscVPlatformPkg/Universal/Pei/PlatformPei/Platform.h
> @@ -83,4 +83,15 @@ InitializeXen (
> VOID
> );
>
> +/**
> + Build processor and platform information for the U5 platform
Update the comment to remove U5?
Regards
Sunil
> +
> + @return EFI_SUCCESS Status.
> +
> +**/
> +EFI_STATUS
> +BuildRiscVSmbiosHobs (
> + VOID
> +);
> +
> #endif // _PLATFORM_PEI_H_INCLUDED_
> diff --git a/RiscVPlatformPkg/Universal/Pei/PlatformPei/Platform.c b/RiscVPlatformPkg/Universal/Pei/PlatformPei/Platform.c
> index 8586a94b62..1cc64b3e9c 100644
> --- a/RiscVPlatformPkg/Universal/Pei/PlatformPei/Platform.c
> +++ b/RiscVPlatformPkg/Universal/Pei/PlatformPei/Platform.c
> @@ -30,8 +30,6 @@
> #include <Ppi/MasterBootMode.h>
> #include <IndustryStandard/Pci22.h>
>
> -#include <SiFiveU5MCCoreplex.h>
> -
> #include "Platform.h"
>
> EFI_MEMORY_TYPE_INFORMATION mDefaultMemoryTypeInformation[] = {
> --
> 2.31.1
>
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 67/79] RiscVPlatformPkg: Address Core CI ECC errors.
[not found] ` <20220108041420.16064-6-abner.chang@hpe.com>
@ 2022-01-09 14:42 ` Sunil V L
0 siblings, 0 replies; 7+ messages in thread
From: Sunil V L @ 2022-01-09 14:42 UTC (permalink / raw)
To: Abner Chang; +Cc: devel, Daniel Schaefer
On Sat, Jan 08, 2022 at 12:14:08PM +0800, Abner Chang wrote:
> Signed-off-by: Abner Chang <abner.chang@hpe.com>
> Cc: Daniel Schaefer <daniel.schaefer@hpe.com>
> Cc: Sunil V L <sunilvl@ventanamicro.com>
> ---
> RiscVPlatformPkg/RiscVPlatformPkg.dec | 1 -
> RiscVPlatformPkg/RiscVPlatformPkg.dsc | 4 +-
> .../FirmwareContextProcessorSpecificLib.inf | 6 +-
> .../OpensbiPlatformLib/OpensbiPlatformLib.inf | 2 +-
> .../PeiCoreEntryPoint/PeiCoreEntryPoint.inf | 1 -
> .../PlatformBootManagerLib.inf | 13 +---
> .../PlatformMemoryTestLibNull.inf | 6 +-
> .../PlatformSecPpiLibNull.inf | 7 +-
> .../PlatformUpdateProgressLibNull.inf | 7 +-
> .../Library/ResetSystemLib/ResetSystemLib.inf | 1 -
> .../Universal/FdtPeim/FdtPeim.inf | 3 -
> .../Universal/Pei/PlatformPei/PlatformPei.inf | 8 +--
> RiscVPlatformPkg/Universal/Sec/SecMain.inf | 1 +
> .../FirmwareContextProcessorSpecificLib.h | 4 +-
> .../PlatformBootManager.h | 10 +--
> RiscVPlatformPkg/Universal/Sec/SecMain.h | 29 +++++---
> .../Edk2OpensbiPlatformWrapperLib.c | 8 +--
> .../FirmwareContextProcessorSpecificLib.c | 4 +-
> .../{Platform.c => OpensbiPlatform.c} | 0
> .../PeiCoreEntryPoint/PeiCoreEntryPoint.c | 2 +-
> .../PeiCoreInfoHobLibNull/CoreInfoHob.c | 2 +-
> .../PlatformBootManager.c | 7 ++
> .../PlatformBootManagerLib/PlatformData.c | 2 +-
> .../PlatformSecPpiLibNull/PlatformSecPpiLib.c | 2 +-
> .../RiscVSpecialPlatformLib.c | 2 +-
> RiscVPlatformPkg/Universal/FdtPeim/FdtPeim.c | 3 +-
> .../Universal/Pei/PlatformPei/MemDetect.c | 6 +-
> .../Universal/Pei/PlatformPei/Platform.c | 71 ++++++++++++++++++-
> RiscVPlatformPkg/Universal/Sec/SecMain.c | 51 +++++++------
> RiscVPlatformPkg/RiscVPlatformPkg.uni | 69 ++++++++++++++++++
> 30 files changed, 229 insertions(+), 103 deletions(-)
> rename RiscVPlatformPkg/Library/OpensbiPlatformLib/{Platform.c => OpensbiPlatform.c} (100%)
>
> diff --git a/RiscVPlatformPkg/RiscVPlatformPkg.dec b/RiscVPlatformPkg/RiscVPlatformPkg.dec
> index 19206556ce..53d424c901 100644
> --- a/RiscVPlatformPkg/RiscVPlatformPkg.dec
> +++ b/RiscVPlatformPkg/RiscVPlatformPkg.dec
> @@ -85,7 +85,6 @@
> [PcdsPatchableInModule]
>
> [PcdsFeatureFlag]
> - gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootlogoOnlyEnable|FALSE|BOOLEAN|0x00001200
>
> [PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx]
>
> diff --git a/RiscVPlatformPkg/RiscVPlatformPkg.dsc b/RiscVPlatformPkg/RiscVPlatformPkg.dsc
> index f7f5c3f7cd..366dcaefab 100644
> --- a/RiscVPlatformPkg/RiscVPlatformPkg.dsc
> +++ b/RiscVPlatformPkg/RiscVPlatformPkg.dsc
> @@ -1,11 +1,11 @@
> -#/** @file
> +## @file
> # RISC-V platform package.
> #
> # Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> #
> # SPDX-License-Identifier: BSD-2-Clause-Patent
> #
> -#**/
> +#
>
> ################################################################################
> #
> diff --git a/RiscVPlatformPkg/Library/FirmwareContextProcessorSpecificLib/FirmwareContextProcessorSpecificLib.inf b/RiscVPlatformPkg/Library/FirmwareContextProcessorSpecificLib/FirmwareContextProcessorSpecificLib.inf
> index 8ea37ae4f4..4da78178a9 100644
> --- a/RiscVPlatformPkg/Library/FirmwareContextProcessorSpecificLib/FirmwareContextProcessorSpecificLib.inf
> +++ b/RiscVPlatformPkg/Library/FirmwareContextProcessorSpecificLib/FirmwareContextProcessorSpecificLib.inf
> @@ -1,10 +1,11 @@
> -#/** @file
> +## @file
> +# This is the library module of RISC-V EDK2 OpenSBI Firmware Context
> +# Processor Specific hwardware information.
> #
> # Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> #
> # SPDX-License-Identifier: BSD-2-Clause-Patent
> #
> -#**/
>
> [Defines]
> INF_VERSION = 0x0001001b
> @@ -28,4 +29,3 @@
> MemoryAllocationLib
> PrintLib
>
> -
> diff --git a/RiscVPlatformPkg/Library/OpensbiPlatformLib/OpensbiPlatformLib.inf b/RiscVPlatformPkg/Library/OpensbiPlatformLib/OpensbiPlatformLib.inf
> index 8e3f07d833..d53b7ec0c4 100644
> --- a/RiscVPlatformPkg/Library/OpensbiPlatformLib/OpensbiPlatformLib.inf
> +++ b/RiscVPlatformPkg/Library/OpensbiPlatformLib/OpensbiPlatformLib.inf
> @@ -24,7 +24,7 @@
> #
>
> [Sources]
> - Platform.c
> + OpensbiPlatform.c
>
> [Packages]
> EmbeddedPkg/EmbeddedPkg.dec
> diff --git a/RiscVPlatformPkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.inf b/RiscVPlatformPkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.inf
> index af453f6650..f22999d9d4 100644
> --- a/RiscVPlatformPkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.inf
> +++ b/RiscVPlatformPkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.inf
> @@ -33,5 +33,4 @@
> BaseLib
> DebugLib
> PlatformSecPpiLib
> - RiscVFirmwareContextLib
>
> diff --git a/RiscVPlatformPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf b/RiscVPlatformPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
> index 8022372fa6..3d88b004f2 100644
> --- a/RiscVPlatformPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
> +++ b/RiscVPlatformPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
> @@ -34,18 +34,11 @@
>
> [LibraryClasses]
> BaseLib
> - UefiBootServicesTableLib
> - UefiRuntimeServicesTableLib
> - UefiLib
> - UefiBootManagerLib
> PcdLib
> - PlatformMemoryTestLib
> - PlatformUpdateProgressLib
> - DxeServicesLib
> MemoryAllocationLib
> - DevicePathLib
> - HiiLib
> PrintLib
> + PlatformMemoryTestLib
> + PlatformUpdateProgressLib
>
> [Guids]
> gEfiEndOfDxeEventGroupGuid
> @@ -59,4 +52,4 @@
> gEfiMdeModulePkgTokenSpaceGuid.PcdConOutRow
> gEfiMdeModulePkgTokenSpaceGuid.PcdConOutColumn
> gEfiMdeModulePkgTokenSpaceGuid.PcdConInConnectOnDemand
> - gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootlogoOnlyEnable
> +
> diff --git a/RiscVPlatformPkg/Library/PlatformMemoryTestLibNull/PlatformMemoryTestLibNull.inf b/RiscVPlatformPkg/Library/PlatformMemoryTestLibNull/PlatformMemoryTestLibNull.inf
> index a1b503ebc2..9905448909 100644
> --- a/RiscVPlatformPkg/Library/PlatformMemoryTestLibNull/PlatformMemoryTestLibNull.inf
> +++ b/RiscVPlatformPkg/Library/PlatformMemoryTestLibNull/PlatformMemoryTestLibNull.inf
> @@ -1,10 +1,10 @@
> -#/** @file
> +## @file
> +# Platform NULL memory test library instance.
> #
> # Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> #
> # SPDX-License-Identifier: BSD-2-Clause-Patent
> #
> -#**/
>
> [Defines]
> INF_VERSION = 0x0001001b
> @@ -22,8 +22,6 @@
> MdePkg/MdePkg.dec
>
> [LibraryClasses]
> - UefiLib
> - DebugLib
>
> [Pcd]
>
> diff --git a/RiscVPlatformPkg/Library/PlatformSecPpiLibNull/PlatformSecPpiLibNull.inf b/RiscVPlatformPkg/Library/PlatformSecPpiLibNull/PlatformSecPpiLibNull.inf
> index 5b3570ce6d..cf5da8443e 100644
> --- a/RiscVPlatformPkg/Library/PlatformSecPpiLibNull/PlatformSecPpiLibNull.inf
> +++ b/RiscVPlatformPkg/Library/PlatformSecPpiLibNull/PlatformSecPpiLibNull.inf
> @@ -1,17 +1,16 @@
> ## @file
> -# Library instance to to provide PPI before PEI Core
> +# NULL library instance of PlatformSecPpiLib
> #
> # Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> #
> # SPDX-License-Identifier: BSD-2-Clause-Patent
> #
> -##
>
> [Defines]
> INF_VERSION = 0x0001001b
> BASE_NAME = PlatformSecPpiLib
> FILE_GUID = A2CDDADC-CB65-4EED-9CAE-192B0BDD6C84
> - MODULE_TYPE = PEIM
> + MODULE_TYPE = BASE
> VERSION_STRING = 1.0
> LIBRARY_CLASS = PlatformSecPpiLib|PEI_CORE
>
> @@ -30,6 +29,4 @@
> RiscVPlatformPkg/RiscVPlatformPkg.dec
>
> [LibraryClasses]
> - #BaseLib
> - #PrintLib
>
> diff --git a/RiscVPlatformPkg/Library/PlatformUpdateProgressLibNull/PlatformUpdateProgressLibNull.inf b/RiscVPlatformPkg/Library/PlatformUpdateProgressLibNull/PlatformUpdateProgressLibNull.inf
> index fdba00c053..1411015809 100644
> --- a/RiscVPlatformPkg/Library/PlatformUpdateProgressLibNull/PlatformUpdateProgressLibNull.inf
> +++ b/RiscVPlatformPkg/Library/PlatformUpdateProgressLibNull/PlatformUpdateProgressLibNull.inf
> @@ -1,10 +1,11 @@
> -#/** @file
> +## @file
> +# Platform Update Progress NULL library
> #
> # Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> #
> # SPDX-License-Identifier: BSD-2-Clause-Patent
> #
> -#**/
> +#
>
> [Defines]
> INF_VERSION = 0x0001001b
> @@ -22,8 +23,6 @@
> MdePkg/MdePkg.dec
>
> [LibraryClasses]
> - UefiLib
> - DebugLib
>
> [Pcd]
>
> diff --git a/RiscVPlatformPkg/Library/ResetSystemLib/ResetSystemLib.inf b/RiscVPlatformPkg/Library/ResetSystemLib/ResetSystemLib.inf
> index 0ce1e90b70..7e92a00fa0 100644
> --- a/RiscVPlatformPkg/Library/ResetSystemLib/ResetSystemLib.inf
> +++ b/RiscVPlatformPkg/Library/ResetSystemLib/ResetSystemLib.inf
> @@ -4,7 +4,6 @@
> # Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> # SPDX-License-Identifier: BSD-2-Clause-Patent
> #
> -##
>
> [Defines]
> INF_VERSION = 0x00010005
> diff --git a/RiscVPlatformPkg/Universal/FdtPeim/FdtPeim.inf b/RiscVPlatformPkg/Universal/FdtPeim/FdtPeim.inf
> index 33b7f89805..cc870b8a91 100644
> --- a/RiscVPlatformPkg/Universal/FdtPeim/FdtPeim.inf
> +++ b/RiscVPlatformPkg/Universal/FdtPeim/FdtPeim.inf
> @@ -33,14 +33,11 @@
> RiscVPkg/RiscVPkg.dec
>
> [LibraryClasses]
> - DebugLib
> DebugLib
> HobLib
> FdtLib
> PcdLib
> - PeiServicesLib
> PeimEntryPoint
> - RiscVFirmwareContextLib
>
> [Guids]
> gFdtHobGuid ## PRODUCES
> diff --git a/RiscVPlatformPkg/Universal/Pei/PlatformPei/PlatformPei.inf b/RiscVPlatformPkg/Universal/Pei/PlatformPei/PlatformPei.inf
> index 7a88099150..e62c6f9563 100644
> --- a/RiscVPlatformPkg/Universal/Pei/PlatformPei/PlatformPei.inf
> +++ b/RiscVPlatformPkg/Universal/Pei/PlatformPei/PlatformPei.inf
> @@ -27,6 +27,7 @@
> Fv.c
> MemDetect.c
> Platform.c
> + Platform.h
>
> [Packages]
> MdeModulePkg/MdeModulePkg.dec
> @@ -42,12 +43,9 @@
> DebugLib
> HobLib
> IoLib
> - PciLib
> - PeiResourcePublicationLib
> - PeiServicesLib
> - PeiServicesTablePointerLib
> - PeimEntryPoint
> PcdLib
> + PeimEntryPoint
> + PeiResourcePublicationLib
> RiscVCoreplexInfoLib
>
> [Pcd]
> diff --git a/RiscVPlatformPkg/Universal/Sec/SecMain.inf b/RiscVPlatformPkg/Universal/Sec/SecMain.inf
> index caed51a54c..0e78b8ba31 100644
> --- a/RiscVPlatformPkg/Universal/Sec/SecMain.inf
> +++ b/RiscVPlatformPkg/Universal/Sec/SecMain.inf
> @@ -22,6 +22,7 @@
> #
>
> [Sources]
> + SecMain.h
> SecMain.c
>
> [Sources.RISCV64]
> diff --git a/RiscVPlatformPkg/Include/Library/FirmwareContextProcessorSpecificLib.h b/RiscVPlatformPkg/Include/Library/FirmwareContextProcessorSpecificLib.h
> index f3b096c257..3920c61155 100644
> --- a/RiscVPlatformPkg/Include/Library/FirmwareContextProcessorSpecificLib.h
> +++ b/RiscVPlatformPkg/Include/Library/FirmwareContextProcessorSpecificLib.h
> @@ -6,8 +6,8 @@
> SPDX-License-Identifier: BSD-2-Clause-Patent
>
> **/
> -#ifndef FIRMWARE_CONTEXT_PROCESSOR_SPECIFIC_LIB_H
> -#define FIRMWARE_CONTEXT_PROCESSOR_SPECIFIC_LIB_H
> +#ifndef FIRMWARE_CONTEXT_PROCESSOR_SPECIFIC_LIB_H_
> +#define FIRMWARE_CONTEXT_PROCESSOR_SPECIFIC_LIB_H_
>
> #include <IndustryStandard/RiscVOpensbi.h>
> #include <PiPei.h>
> diff --git a/RiscVPlatformPkg/Library/PlatformBootManagerLib/PlatformBootManager.h b/RiscVPlatformPkg/Library/PlatformBootManagerLib/PlatformBootManager.h
> index 58c363a48b..01c26f307e 100644
> --- a/RiscVPlatformPkg/Library/PlatformBootManagerLib/PlatformBootManager.h
> +++ b/RiscVPlatformPkg/Library/PlatformBootManagerLib/PlatformBootManager.h
> @@ -1,4 +1,4 @@
> -/**@file
> +/** @file
> Head file for BDS Platform specific code
>
> Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> @@ -39,14 +39,6 @@ typedef struct {
>
> extern PLATFORM_CONSOLE_CONNECT_ENTRY gPlatformConsole[];
>
> -#define gEndEntire \
> - { \
> - END_DEVICE_PATH_TYPE,\
> - END_ENTIRE_DEVICE_PATH_SUBTYPE,\
> - END_DEVICE_PATH_LENGTH,\
> - 0\
> - }
> -
> #define CONSOLE_OUT BIT0
> #define CONSOLE_IN BIT1
> #define STD_ERROR BIT2
> diff --git a/RiscVPlatformPkg/Universal/Sec/SecMain.h b/RiscVPlatformPkg/Universal/Sec/SecMain.h
> index 6188778fc4..63a610fbd0 100644
> --- a/RiscVPlatformPkg/Universal/Sec/SecMain.h
> +++ b/RiscVPlatformPkg/Universal/Sec/SecMain.h
> @@ -27,25 +27,38 @@
> #include <Library/PeiServicesLib.h>
> #include <Library/RiscVCpuLib.h>
>
> -int
> +/**
> + OpenSBI platform early init hook.
> +
> + @param[in] ColdBoot Is cold boot path or warm boot path.
> + @retval OpenSBI error code.
> +
> +**/
> +INT32
> SecPostOpenSbiPlatformEarlylInit(
> IN BOOLEAN ColdBoot
> );
>
> -int
> +/**
> + OpenSBI platform final init hook.
> + We restore the next_arg1 to the pointer of EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT.
> +
> + @param[in] ColdBoot Is cold boot path or warm boot path.
> + @retval OpenSBI error code.
> +
> +**/
> +INT32
> SecPostOpenSbiPlatformFinalInit (
> IN BOOLEAN ColdBoot
> );
>
> +/**
> + SEC machine mode trap handler.
> +
> +**/
> VOID
> SecMachineModeTrapHandler (
> IN VOID
> );
>
> -VOID
> -EFIAPI
> -SecStartupPhase2 (
> - IN VOID *Context
> - );
> -
> #endif // _SECMAIN_H_
> diff --git a/RiscVPlatformPkg/Library/Edk2OpensbiPlatformWrapperLib/Edk2OpensbiPlatformWrapperLib.c b/RiscVPlatformPkg/Library/Edk2OpensbiPlatformWrapperLib/Edk2OpensbiPlatformWrapperLib.c
> index 6c5c1a789f..2137c6c619 100644
> --- a/RiscVPlatformPkg/Library/Edk2OpensbiPlatformWrapperLib/Edk2OpensbiPlatformWrapperLib.c
> +++ b/RiscVPlatformPkg/Library/Edk2OpensbiPlatformWrapperLib/Edk2OpensbiPlatformWrapperLib.c
> @@ -1,11 +1,11 @@
> -/*
> +/** @file
> EDK2 OpenSBI generic platform wrapper library
>
> Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
>
> SPDX-License-Identifier: BSD-2-Clause-Patent
>
> - */
> + **/
>
> #include <Library/DebugAgentLib.h>
> #include <Library/DebugLib.h>
> @@ -189,7 +189,7 @@ Edk2OpensbiPlatformEarlyInit (
> return ReturnCode;
> }
> }
> - if (ColdBoot == TRUE) {
> + if (ColdBoot) {
> return SecPostOpenSbiPlatformEarlylInit(ColdBoot);
> }
> return 0;
> @@ -216,7 +216,7 @@ Edk2OpensbiPlatformFinalInit (
> return ReturnCode;
> }
> }
> - if (ColdBoot == TRUE) {
> + if (ColdBoot) {
> return SecPostOpenSbiPlatformFinalInit(ColdBoot);
> }
> return 0;
> diff --git a/RiscVPlatformPkg/Library/FirmwareContextProcessorSpecificLib/FirmwareContextProcessorSpecificLib.c b/RiscVPlatformPkg/Library/FirmwareContextProcessorSpecificLib/FirmwareContextProcessorSpecificLib.c
> index c62f77bc49..143c18d62c 100644
> --- a/RiscVPlatformPkg/Library/FirmwareContextProcessorSpecificLib/FirmwareContextProcessorSpecificLib.c
> +++ b/RiscVPlatformPkg/Library/FirmwareContextProcessorSpecificLib/FirmwareContextProcessorSpecificLib.c
> @@ -1,4 +1,4 @@
> -/**@file
> +/** @file
> Common library to build upfirmware context processor-specific information
>
> Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> @@ -93,7 +93,7 @@ CommonFirmwareContextHartSpecificInfo (
> }
>
> /**
> - Print debug information of the processor specific data for a hart
> + Print debug information of the processor specific data for a hart.
>
> @param ProcessorSpecificDataHob Pointer to RISC_V_PROCESSOR_SPECIFIC_DATA_HOB
> **/
> diff --git a/RiscVPlatformPkg/Library/OpensbiPlatformLib/Platform.c b/RiscVPlatformPkg/Library/OpensbiPlatformLib/OpensbiPlatform.c
> similarity index 100%
> rename from RiscVPlatformPkg/Library/OpensbiPlatformLib/Platform.c
> rename to RiscVPlatformPkg/Library/OpensbiPlatformLib/OpensbiPlatform.c
> diff --git a/RiscVPlatformPkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.c b/RiscVPlatformPkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.c
> index 16488b7bc9..50de969947 100644
> --- a/RiscVPlatformPkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.c
> +++ b/RiscVPlatformPkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.c
> @@ -45,7 +45,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
> **/
> VOID
> EFIAPI
> -_ModuleEntryPoint(
> +_ModuleEntryPoint (
> IN CONST EFI_SEC_PEI_HAND_OFF *SecCoreData,
> IN CONST EFI_PEI_PPI_DESCRIPTOR *PpiList
> )
> diff --git a/RiscVPlatformPkg/Library/PeiCoreInfoHobLibNull/CoreInfoHob.c b/RiscVPlatformPkg/Library/PeiCoreInfoHobLibNull/CoreInfoHob.c
> index 9aad7991bc..ae80b2404d 100644
> --- a/RiscVPlatformPkg/Library/PeiCoreInfoHobLibNull/CoreInfoHob.c
> +++ b/RiscVPlatformPkg/Library/PeiCoreInfoHobLibNull/CoreInfoHob.c
> @@ -1,4 +1,4 @@
> -/**@file
> +/** @file
> Build up platform processor information.
>
> Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> diff --git a/RiscVPlatformPkg/Library/PlatformBootManagerLib/PlatformBootManager.c b/RiscVPlatformPkg/Library/PlatformBootManagerLib/PlatformBootManager.c
> index d67f4836fc..deaad7d5a1 100644
> --- a/RiscVPlatformPkg/Library/PlatformBootManagerLib/PlatformBootManager.c
> +++ b/RiscVPlatformPkg/Library/PlatformBootManagerLib/PlatformBootManager.c
> @@ -86,6 +86,13 @@ PlatformFindLoadOption (
> return -1;
> }
>
> +/**
> + Register a boot option using a file GUID in the FV.
> +
> + @param FileGuid The file GUID name in FV.
> + @param Description The boot option description.
> + @param Attributes The attributes used for the boot option loading.
> +**/
> VOID
> PlatformRegisterFvBootOption (
> EFI_GUID *FileGuid,
> diff --git a/RiscVPlatformPkg/Library/PlatformBootManagerLib/PlatformData.c b/RiscVPlatformPkg/Library/PlatformBootManagerLib/PlatformData.c
> index 3208051e16..c1dbbf451e 100644
> --- a/RiscVPlatformPkg/Library/PlatformBootManagerLib/PlatformData.c
> +++ b/RiscVPlatformPkg/Library/PlatformBootManagerLib/PlatformData.c
> @@ -1,4 +1,4 @@
> -/**@file
> +/** @file
> Defined the platform specific device path which will be filled to
> ConIn/ConOut variables.
>
> diff --git a/RiscVPlatformPkg/Library/PlatformSecPpiLibNull/PlatformSecPpiLib.c b/RiscVPlatformPkg/Library/PlatformSecPpiLibNull/PlatformSecPpiLib.c
> index d5c089b02d..bcb345c4e9 100644
> --- a/RiscVPlatformPkg/Library/PlatformSecPpiLibNull/PlatformSecPpiLib.c
> +++ b/RiscVPlatformPkg/Library/PlatformSecPpiLibNull/PlatformSecPpiLib.c
> @@ -1,4 +1,4 @@
> -/**@file
> +/** @file
> NULL library instance of PlatformSecPpiLib
>
> Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> diff --git a/RiscVPlatformPkg/Library/RiscVSpecialPlatformLibNull/RiscVSpecialPlatformLib.c b/RiscVPlatformPkg/Library/RiscVSpecialPlatformLibNull/RiscVSpecialPlatformLib.c
> index f64bde4535..44f6ad6aed 100644
> --- a/RiscVPlatformPkg/Library/RiscVSpecialPlatformLibNull/RiscVSpecialPlatformLib.c
> +++ b/RiscVPlatformPkg/Library/RiscVSpecialPlatformLibNull/RiscVSpecialPlatformLib.c
> @@ -1,4 +1,4 @@
> -/**@file
> +/** @file
> Library to provide platform_override for the special
> RISC-V platform. This module incorporates with
> OpensbiPlatformLib and RISC-V Opensbi library.
> diff --git a/RiscVPlatformPkg/Universal/FdtPeim/FdtPeim.c b/RiscVPlatformPkg/Universal/FdtPeim/FdtPeim.c
> index 2cd94f291c..3487a5faf4 100644
> --- a/RiscVPlatformPkg/Universal/FdtPeim/FdtPeim.c
> +++ b/RiscVPlatformPkg/Universal/FdtPeim/FdtPeim.c
> @@ -22,7 +22,8 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
> @param FileHandle Handle of the file being invoked.
> @param PeiServices Describes the list of possible PEI Services.
>
> - @retval TODO
> + @retval EFI_SUCCESS The address of FDT is passed in HOB.
> + EFI_UNSUPPORTED Can't locate FDT.
> **/
> EFI_STATUS
> EFIAPI
> diff --git a/RiscVPlatformPkg/Universal/Pei/PlatformPei/MemDetect.c b/RiscVPlatformPkg/Universal/Pei/PlatformPei/MemDetect.c
> index c15d6bb5d4..9b52eb5189 100644
> --- a/RiscVPlatformPkg/Universal/Pei/PlatformPei/MemDetect.c
> +++ b/RiscVPlatformPkg/Universal/Pei/PlatformPei/MemDetect.c
> @@ -1,4 +1,4 @@
> -/**@file
> +/** @file
> Memory Detection for Virtual Machines.
>
> Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> @@ -32,7 +32,7 @@ Module Name:
>
>
> /**
> - Publish PEI core memory
> + Publish PEI core memory.
>
> @return EFI_SUCCESS The PEIM initialized successfully.
>
> @@ -65,7 +65,7 @@ PublishPeiMemory (
> }
>
> /**
> - Publish system RAM and reserve memory regions
> + Publish system RAM and reserve memory regions.
>
> **/
> VOID
> diff --git a/RiscVPlatformPkg/Universal/Pei/PlatformPei/Platform.c b/RiscVPlatformPkg/Universal/Pei/PlatformPei/Platform.c
> index 1cc64b3e9c..8a248f3630 100644
> --- a/RiscVPlatformPkg/Universal/Pei/PlatformPei/Platform.c
> +++ b/RiscVPlatformPkg/Universal/Pei/PlatformPei/Platform.c
> @@ -1,4 +1,4 @@
> -/**@file
> +/** @file
> Platform PEI driver
>
> Copyright (c) 2019-2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> @@ -54,6 +54,14 @@ EFI_PEI_PPI_DESCRIPTOR mPpiBootMode[] = {
>
> STATIC EFI_BOOT_MODE mBootMode = BOOT_WITH_FULL_CONFIGURATION;
>
> +/**
> + Build memory map I/O range resource HOB using the
> + base address and size.
> +
> + @param MemoryBase Memory map I/O base.
> + @param MemorySize Memory map I/O size.
> +
> +**/
> VOID
> AddIoMemoryBaseSizeHob (
> EFI_PHYSICAL_ADDRESS MemoryBase,
> @@ -71,6 +79,13 @@ AddIoMemoryBaseSizeHob (
> );
> }
>
> +/**
> + Build reserved memory range resource HOB.
> +
> + @param MemoryBase Reserved memory range base address.
> + @param MemorySize Reserved memory range size.
> +
> +**/
> VOID
> AddReservedMemoryBaseSizeHob (
> EFI_PHYSICAL_ADDRESS MemoryBase,
> @@ -88,6 +103,14 @@ AddReservedMemoryBaseSizeHob (
> );
> }
>
> +/**
> + Build memory map I/O resource using the base address
> + and the top address of memory range.
> +
> + @param MemoryBase Memory map I/O range base address.
> + @param MemoryLimit The top address of memory map I/O range
> +
> +**/
> VOID
> AddIoMemoryRangeHob (
> EFI_PHYSICAL_ADDRESS MemoryBase,
> @@ -97,7 +120,14 @@ AddIoMemoryRangeHob (
> AddIoMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));
> }
>
> +/**
> + Create memory range resource HOB using the memory base
> + address and size.
> +
> + @param MemoryBase Memory range base address.
> + @param MemorySize Memory range size.
>
> +**/
> VOID
> AddMemoryBaseSizeHob (
> EFI_PHYSICAL_ADDRESS MemoryBase,
> @@ -118,7 +148,14 @@ AddMemoryBaseSizeHob (
> );
> }
>
> +/**
> + Create memory range resource HOB using memory base
> + address and top address of the memory range.
> +
> + @param MemoryBase Memory range base address.
> + @param MemoryLimit Memory range size.
>
> +**/
> VOID
> AddMemoryRangeHob (
> EFI_PHYSICAL_ADDRESS MemoryBase,
> @@ -128,7 +165,14 @@ AddMemoryRangeHob (
> AddMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));
> }
>
> +/**
> + Create untested memory range resource HOB using memory base
> + address and top address of the memory range.
> +
> + @param MemoryBase Memory range base address.
> + @param MemorySize Memory range size.
>
> +**/
> VOID
> AddUntestedMemoryBaseSizeHob (
> EFI_PHYSICAL_ADDRESS MemoryBase,
> @@ -148,6 +192,14 @@ AddUntestedMemoryBaseSizeHob (
> );
> }
>
> +/**
> + Create untested memory range resource HOB using memory base
> + address and top address of the memory range.
> +
> + @param MemoryBase Memory range base address.
> + @param MemoryLimit Memory range size.
> +
> +**/
> VOID
> AddUntestedMemoryRangeHob (
> EFI_PHYSICAL_ADDRESS MemoryBase,
> @@ -157,6 +209,10 @@ AddUntestedMemoryRangeHob (
> AddUntestedMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));
> }
>
> +/**
> + Add PCI resource.
> +
> +**/
> VOID
> AddPciResource (
> VOID
> @@ -167,6 +223,10 @@ AddPciResource (
> //
> }
>
> +/**
> + Platform memory map initialization.
> +
> +**/
> VOID
> MemMapInitialization (
> VOID
> @@ -187,6 +247,10 @@ MemMapInitialization (
> AddPciResource ();
> }
>
> +/**
> + Platform misc initialization.
> +
> +**/
> VOID
> MiscInitialization (
> VOID
> @@ -221,7 +285,10 @@ CheckResumeFromS3 (
> return FALSE;
> }
>
> +/**
> + Platform boot mode initialization.
>
> +**/
> VOID
> BootModeInitialization (
> VOID
> @@ -229,7 +296,7 @@ BootModeInitialization (
> {
> EFI_STATUS Status;
>
> - if (CheckResumeFromS3 () == TRUE) {
> + if (CheckResumeFromS3) {
> DEBUG ((DEBUG_INFO, "This is wake from S3\n"));
> } else {
> DEBUG ((DEBUG_INFO, "This is normal boot\n"));
> diff --git a/RiscVPlatformPkg/Universal/Sec/SecMain.c b/RiscVPlatformPkg/Universal/Sec/SecMain.c
> index 05f228c44d..1fafed2799 100644
> --- a/RiscVPlatformPkg/Universal/Sec/SecMain.c
> +++ b/RiscVPlatformPkg/Universal/Sec/SecMain.c
> @@ -227,10 +227,10 @@ FindFfsFileAndSection (
> }
>
> /**
> - Locates the PEI Core entry point address
> + Locates the PEI Core entry point address.
>
> @param[in] Fv The firmware volume to search
> - @param[out] PeiCoreEntryPoint The entry point of the PEI Core image
> + @param[out] PeiCoreImageBase The entry point of the PEI Core image
>
> @retval EFI_SUCCESS The file and section was found
> @retval EFI_NOT_FOUND The file and section was not found
> @@ -270,14 +270,10 @@ FindPeiCoreImageBaseInFv (
> }
>
> /**
> - Locates the PEI Core entry point address
> + Locates the PEI Core entry point address.
>
> - @param[in,out] Fv The firmware volume to search
> - @param[out] PeiCoreEntryPoint The entry point of the PEI Core image
> -
> - @retval EFI_SUCCESS The file and section was found
> - @retval EFI_NOT_FOUND The file and section was not found
> - @retval EFI_VOLUME_CORRUPTED The firmware volume was corrupted
> + @param[in,out] BootFv The firmware volume to search
> + @param[out] PeiCoreImageBase The entry point of the PEI Core image
>
> **/
> VOID
> @@ -292,12 +288,16 @@ FindPeiCoreImageBase (
> FindPeiCoreImageBaseInFv (*BootFv, PeiCoreImageBase);
> }
>
> -/*
> +/**
> Find and return Pei Core entry point.
>
> It also find SEC and PEI Core file debug inforamtion. It will report them if
> remote debug is enabled.
>
> + @param[in] BootFirmwareVolumePtr The firmware volume pointer to search
> + @param[out] PeiCoreEntryPoint The entry point of the PEI Core image
> +
> +
> **/
> VOID
> FindAndReportEntryPoints (
> @@ -330,7 +330,7 @@ FindAndReportEntryPoints (
>
> @param[in] ExtId The extension ID of the FW extension.
> @param[in] FuncId The called function ID.
> - @param[in] Args The args to the function.
> + @param[in] TrapRegs The args to the function.
> @param[out] OutVal The value the function returns to the caller.
> @param[out] OutTrap Trap info for trapping further, see OpenSBI code.
> Is ignored if return value is not SBI_ETRAP.
> @@ -339,7 +339,8 @@ FindAndReportEntryPoints (
> @retval SBI_ENOTSUPP If there's no function with the given ID.
> @retval SBI_ETRAP If the called SBI functions wants to trap further.
> **/
> -STATIC int SbiEcallFirmwareHandler (
> +int
> +SbiEcallFirmwareHandler (
> IN unsigned long ExtId,
> IN unsigned long FuncId,
> IN CONST struct sbi_trap_regs *TrapRegs,
> @@ -347,8 +348,9 @@ STATIC int SbiEcallFirmwareHandler (
> OUT struct sbi_trap_info *OutTrap
> )
> {
> - int Ret = SBI_OK;
> + int Ret;
>
> + Ret = SBI_OK;
> switch (FuncId) {
> case SBI_EXT_FW_MSCRATCH_FUNC:
> *OutVal = (unsigned long) sbi_scratch_thishart_ptr();
> @@ -408,17 +410,20 @@ RegisterFirmwareSbiExtension (
> @param[in] Scratch Pointer to sbi_scratch structure.
>
> **/
> -VOID EFIAPI PeiCore (
> +VOID
> +EFIAPI
> +PeiCore (
> IN UINTN BootHartId,
> IN struct sbi_scratch *Scratch
> )
> {
> EFI_SEC_PEI_HAND_OFF SecCoreData;
> EFI_PEI_CORE_ENTRY_POINT PeiCoreEntryPoint;
> - EFI_FIRMWARE_VOLUME_HEADER *BootFv = (EFI_FIRMWARE_VOLUME_HEADER *)FixedPcdGet32(PcdRiscVPeiFvBase);
> + EFI_FIRMWARE_VOLUME_HEADER *BootFv;
> EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT FirmwareContext;
> - struct sbi_platform *ThisSbiPlatform;
> + struct sbi_platform *ThisSbiPlatform;
>
> + BootFv = (EFI_FIRMWARE_VOLUME_HEADER *)FixedPcdGet32(PcdRiscVPeiFvBase);
> FindAndReportEntryPoints (&BootFv, &PeiCoreEntryPoint);
>
> SecCoreData.DataSize = sizeof(EFI_SEC_PEI_HAND_OFF);
> @@ -571,8 +576,6 @@ GetDeviceTreeAddress (
> bootable harts other than those declared in Device Tree
>
> @param[in] SbiPlatform Pointer to SBI platform
> - @retval hart_index2id Index to ID value may be overwrote.
> - @retval hart_count Index to ID value may be overwrote.
>
> **/
> VOID
> @@ -626,7 +629,9 @@ Edk2PlatformHartIndex2Id (
> @param[in] Scratch Pointer to sbi_scratch structure.
>
> **/
> -VOID EFIAPI SecCoreStartUpWithStack(
> +VOID
> +EFIAPI
> +SecCoreStartUpWithStack(
> IN UINTN HartId,
> IN struct sbi_scratch *Scratch
> )
> @@ -710,11 +715,3 @@ VOID EFIAPI SecCoreStartUpWithStack(
> sbi_init(Scratch);
> }
>
> -VOID OpensbiDebugPrint (CHAR8 *debugstr, ...)
> -{
> - VA_LIST Marker;
> -
> - VA_START (Marker, debugstr);
> - DebugVPrint (DEBUG_INFO, debugstr, Marker);
> - VA_END (Marker);
> -}
> diff --git a/RiscVPlatformPkg/RiscVPlatformPkg.uni b/RiscVPlatformPkg/RiscVPlatformPkg.uni
> index deb91fa10c..d2caf7b4e7 100644
> --- a/RiscVPlatformPkg/RiscVPlatformPkg.uni
> +++ b/RiscVPlatformPkg/RiscVPlatformPkg.uni
> @@ -12,4 +12,73 @@
>
> #string STR_PACKAGE_DESCRIPTION #language en-US "This Package provides UEFI compatible RISC-V platform modules and libraries."
>
> +#string STR_gUefiRiscVPlatformPkgTokenSpaceGuid_PcdRiscVSecFvBase_PROMPT #language en-US "SEC FV base address"
> +#string STR_gUefiRiscVPlatformPkgTokenSpaceGuid_PcdRiscVSecFvBase_HELP #language en-US "RISC-V platform SEC Firmware Volume base address."
> +#string STR_gUefiRiscVPlatformPkgTokenSpaceGuid_PcdRiscVSecFvSize_PROMPT #language en-US "SEC FV Size"
> +#string STR_gUefiRiscVPlatformPkgTokenSpaceGuid_PcdRiscVSecFvSize_HELP #language en-US "RISC-V platform SEC Firmware Volume size."
> +#string STR_gUefiRiscVPlatformPkgTokenSpaceGuid_PcdRiscVPeiFvBase_PROMPT #language en-US "PEI FV base address"
> +#string STR_gUefiRiscVPlatformPkgTokenSpaceGuid_PcdRiscVPeiFvBase_HELP #language en-US "RISC-V platform PEI Firmware Volume base address."
> +#string STR_gUefiRiscVPlatformPkgTokenSpaceGuid_PcdRiscVPeiFvSize_PROMPT #language en-US "PEI FV Size"
> +#string STR_gUefiRiscVPlatformPkgTokenSpaceGuid_PcdRiscVPeiFvSize_HELP #language en-US "RISC-V platform PEI Firmware Volume size.
> +#string STR_gUefiRiscVPlatformPkgTokenSpaceGuid_PcdRiscVDxeFvBase_PROMPT #language en-US "DXE FV base address"
> +#string STR_gUefiRiscVPlatformPkgTokenSpaceGuid_PcdRiscVDxeFvBase_HELP #language en-US "RISC-V platform DXE Firmware Volume base address."
> +#string STR_gUefiRiscVPlatformPkgTokenSpaceGuid_PcdRiscVDxeFvSize_PROMPT #language en-US "DXE FV Size"
> +#string STR_gUefiRiscVPlatformPkgTokenSpaceGuid_PcdRiscVDxeFvSize_HELP #language en-US "RISC-V platform DXE Firmware Volume size."
> +#string STR_gUefiRiscVPlatformPkgTokenSpaceGuid_PcdRiscVDtbFvBase_PROMPT #language en-US "DBT FV base address."
> +#string STR_gUefiRiscVPlatformPkgTokenSpaceGuid_PcdRiscVDtbFvBase_HELP #language en-US "RISC-V platform Device Tree Firmware Volume base address."
> +#string STR_gUefiRiscVPlatformPkgTokenSpaceGuid_PcdRiscVDtbFvSize_PROMPT #language en-US "DBT FV Size".
> +#string STR_gUefiRiscVPlatformPkgTokenSpaceGuid_PcdRiscVDtbFvSize_HELP #language en-US "RISC-V platform Device Tree Firmware Volume size."
> +#string STR_gUefiRiscVPlatformPkgTokenSpaceGuid_PcdRootFirmwareDomainBaseAddress_PROMPT #language en-US "OpenSBI Root Firmware Domain address"
> +#string STR_gUefiRiscVPlatformPkgTokenSpaceGuid_PcdRootFirmwareDomainBaseAddress_HELP #language en-US "The base address of OpenSBI Root Firmware Domain."
> +#string STR_gUefiRiscVPlatformPkgTokenSpaceGuid_PcdRootFirmwareDomainSize_PROMPT #language en-US "EDK2 OpenSBI Root Firmware Domain size"
> +#string STR_gUefiRiscVPlatformPkgTokenSpaceGuid_PcdRootFirmwareDomainSize_HELP #language en-US "This is the base address of EKD2 OpenSBI Root Firmware Domain."
The comment should be size instead of base address. Also, better to be
consistent to use EDK2 OpenSBI or just OpenSBI.
> +#string STR_gUefiRiscVPlatformPkgTokenSpaceGuid_PcdFirmwareDomainBaseAddress_PROMPT #language en-US "EDK2 OpenSBI Firmware Domain address"
> +#string STR_gUefiRiscVPlatformPkgTokenSpaceGuid_PcdFirmwareDomainBaseAddress_HELP #language en-US "This is the base address of EDK2 OpenSBI Root Firmware Domain."
This is not Root Firmware Domain, correct? Should it be explicit to say
Non-Root Firmware Domain?
> +#string STR_gUefiRiscVPlatformPkgTokenSpaceGuid_PcdFirmwareDomainSize_PROMPT #language en-US "EDK2 OpenSBI Firmware Domain size"
> +#string STR_gUefiRiscVPlatformPkgTokenSpaceGuid_PcdFirmwareDomainSize_HELP #language en-US "The size of EDK2 OpenSBI Firmware Domain."
> +#string STR_gUefiRiscVPlatformPkgTokenSpaceGuid_PcdVariableFirmwareRegionBaseAddress_PROMPT #language en-US "EFI Variable FV base address"
> +#string STR_gUefiRiscVPlatformPkgTokenSpaceGuid_PcdVariableFirmwareRegionBaseAddress_HELP #language en-US "The base address of EFI Variable Firmware Volume."
> +#string STR_gUefiRiscVPlatformPkgTokenSpaceGuid_PcdVariableFirmwareRegionSize_PROMPT #language en-US "EFI Variable FV size"
> +#string STR_gUefiRiscVPlatformPkgTokenSpaceGuid_PcdVariableFirmwareRegionSize_HELP #language en-US "The size of EFI Variable Firmware Volume."
> +#string STR_gUefiRiscVPlatformPkgTokenSpaceGuid_PcdVariableFdBaseAddress_PROMPT #language en-US "FD base address"
> +#string STR_gUefiRiscVPlatformPkgTokenSpaceGuid_PcdVariableFdBaseAddress_HELP #language en-US "The base address of Firmware Device."
> +#string STR_gUefiRiscVPlatformPkgTokenSpaceGuid_PcdVariableFdSize_PROMPT #language en-US "FD size"
> +#string STR_gUefiRiscVPlatformPkgTokenSpaceGuid_PcdVariableFdSize_HELP #language en-US "The size of Firmware Device."
> +#string STR_gUefiRiscVPlatformPkgTokenSpaceGuid_PcdVariableFdBlockSize_PROMPT #language en-US "FD block size"
> +#string STR_gUefiRiscVPlatformPkgTokenSpaceGuid_PcdVariableFdBlockSize_HELP #language en-US "The block size of Firmware Device"
> +#string STR_gUefiRiscVPlatformPkgTokenSpaceGuid_PcdPlatformFlashNvStorageVariableBase_PROMPT #language en-US "Base address of flash NV variable range"
> +#string STR_gUefiRiscVPlatformPkgTokenSpaceGuid_PcdPlatformFlashNvStorageVariableBase_HELP #language en-US "Base address of the NV variable range in flash device."
> +#string STR_gUefiRiscVPlatformPkgTokenSpaceGuid_PcdPlatformFlashNvStorageFtwWorkingBase_PROMPT #language en-US "Base address of flash FTW working block range"
> +#string STR_gUefiRiscVPlatformPkgTokenSpaceGuid_PcdPlatformFlashNvStorageFtwWorkingBase_HELP #language en-US "Base address of the FTW working block range in flash device. If PcdFlashNvStorageFtwWorkingSize is larger than one block size, this value should be block size aligned."
> +#string STR_gUefiRiscVPlatformPkgTokenSpaceGuid_PcdPlatformFlashNvStorageFtwSpareBase_PROMPT #language en-US "Base address of flash FTW spare block range"
> +#string STR_gUefiRiscVPlatformPkgTokenSpaceGuid_PcdPlatformFlashNvStorageFtwSpareBase_HELP #language en-US "Base address of the FTW spare block range in flash device. Note that this value should be block size aligned."
> +#string STR_gUefiRiscVPlatformPkgTokenSpaceGuid_PcdHartCount_PROMPT #language en-US "RISC-V HART Count"
> +#string STR_gUefiRiscVPlatformPkgTokenSpaceGuid_PcdHartCount_HELP #language en-US "The HART count of the RISC-V processor."
> +#string STR_gUefiRiscVPlatformPkgTokenSpaceGuid_PcdBootHartId_PROMPT #language en-US "RISC-V Boot HART ID"
> +#string STR_gUefiRiscVPlatformPkgTokenSpaceGuid_PcdBootHartId_HELP #language en-US "The ID number of booting HART of RISC-V processor."
> +#string STR_gUefiRiscVPlatformPkgTokenSpaceGuid_PcdBootableHartNumber_PROMPT #language en-US "RISC-V Bootable HART number"
> +#string STR_gUefiRiscVPlatformPkgTokenSpaceGuid_PcdBootableHartNumber_HELP #language en-US "The bootable hart core number, which incorporates with OpenSBI platform hart_index2id value.<BR>"
> + "PcdBootableHartNumber = 0 means the number of bootable hart comes from Device Tree.<BR>"
> + "Otherwise the number assigned in PcdBootableHartNumber overwrite it."
> +#string STR_gUefiRiscVPlatformPkgTokenSpaceGuid_PcdBootableHartIndexToId_PROMPT #language en-US "RISC-V HARD ID to indxe tanslation"
> +#string STR_gUefiRiscVPlatformPkgTokenSpaceGuid_PcdBootableHartIndexToId_HELP #language en-US "PcdBootableHartIndexToId is valid if PcdBootableHartNumber != 0.<BR>"
> + "If PcdBootableHartNumber != 0, then PcdBootableHartIndexToId is an array of<BR>"
> + "bootable hart ID.<BR>"
> + "For example,<BR>"
> + " if PcdBootableHartNumber == 3 then PcdBootableHartIndexToId could be defined<BR>"
> + " as {0x1, 0x2, 0x3}."
> +#string STR_gUefiRiscVPlatformPkgTokenSpaceGuid_PcdScratchRamBase_PROMPT #language en-US "Scratch buffer base address"
> +#string STR_gUefiRiscVPlatformPkgTokenSpaceGuid_PcdScratchRamBase_HELP #language en-US "The base address of scratch buffer used by OpenSBI when initialize the HARTs."
> +#string STR_gUefiRiscVPlatformPkgTokenSpaceGuid_PcdScratchRamSize_PROMPT #language en-US "Scratch buffer size"
> +#string STR_gUefiRiscVPlatformPkgTokenSpaceGuid_PcdScratchRamSize_HELP #language en-US "The bsize of scratch buffer used by OpenSBI when initialize RISC-V HARTs."
bsize > size. Should it be "while initializing the" RISC-V HARTS?
> +#string STR_gUefiRiscVPlatformPkgTokenSpaceGuid_PcdOpenSbiStackSize_PROMPT #language en-US "Stack base address"
> +#string STR_gUefiRiscVPlatformPkgTokenSpaceGuid_PcdOpenSbiStackSize_HELP #language en-US "The base address of stack used by OpenSBI when initialize RISC-V HARTs.
The variable is StackSize. Is it base address or size?
> +#string STR_gUefiRiscVPlatformPkgTokenSpaceGuid_PcdTemporaryRamBase_PROMPT #language en-US "Temporary RAM for PEI phase"
> +#string STR_gUefiRiscVPlatformPkgTokenSpaceGuid_PcdTemporaryRamBase_HELP #language en-US "The temporary memory passed to PEI phase from SEC."
> +#string STR_gUefiRiscVPlatformPkgTokenSpaceGuid_PcdTemporaryRamSize_PROMPT #language en-US "Size of Temporary RAM for PEI phase"
> +#string STR_gUefiRiscVPlatformPkgTokenSpaceGuid_PcdTemporaryRamSize_HELP #language en-US "The size of temporary memory passed to PEI phase from SEC."
> +#string STR_gUefiRiscVPlatformPkgTokenSpaceGuid_PcdPeiCorePrivilegeMode_PROMPT #language en-US "RISC-V Privilege mode in PEI phase "
> +#string STR_gUefiRiscVPlatformPkgTokenSpaceGuid_PcdPeiCorePrivilegeMode_HELP #language en-US "The privilege mode the PEI phase is executed."
> +#string STR_gUefiRiscVPlatformPkgTokenSpaceGuid_PcdDeviceTreeAddress_PROMPT #language en-US "Device Tree base address"
> +#string STR_gUefiRiscVPlatformPkgTokenSpaceGuid_PcdDeviceTreeAddress_HELP #language en-US "The base address of Device Tree.<BR>"
>
> --
> 2.31.1
>
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 68/79] RiscVPlatformVPkg: Address Core CI Spelling errors.
[not found] ` <20220108041420.16064-7-abner.chang@hpe.com>
@ 2022-01-09 14:53 ` Sunil V L
0 siblings, 0 replies; 7+ messages in thread
From: Sunil V L @ 2022-01-09 14:53 UTC (permalink / raw)
To: Abner Chang; +Cc: devel, Daniel Schaefer
On Sat, Jan 08, 2022 at 12:14:09PM +0800, Abner Chang wrote:
> From: changab <abner.chang@hpe.com>
>
> Signed-off-by: Abner Chang <abner.chang@hpe.com>
> Cc: Daniel Schaefer <daniel.schaefer@hpe.com>
> Cc: Sunil V L <sunilvl@ventanamicro.com>
> ---
> RiscVPlatformPkg/RiscVPlatformPkg.dec | 4 ++--
> .../FirmwareContextProcessorSpecificLib.inf | 4 ++--
> RiscVPlatformPkg/Universal/FdtPeim/FdtPeim.inf | 2 +-
> RiscVPkg/Include/ProcessorSpecificHobData.h | 8 ++++----
> .../Library/FirmwareContextProcessorSpecificLib.h | 4 ++--
> RiscVPlatformPkg/Universal/Sec/SecMain.h | 4 ++--
> RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.c | 12 ++++++------
> .../Edk2OpensbiPlatformWrapperLib.c | 10 +++++-----
> .../FirmwareContextProcessorSpecificLib.c | 8 ++++----
> .../PlatformBootManagerLib/PlatformBootManager.c | 4 ++--
> .../Universal/Pei/PlatformPei/Platform.c | 4 ++--
> RiscVPlatformPkg/Universal/Sec/SecMain.c | 12 ++++++------
> RiscVPlatformPkg/Readme.md | 14 +++++++-------
> RiscVPlatformPkg/Universal/Sec/Riscv64/SecEntry.S | 10 +++++-----
> 14 files changed, 50 insertions(+), 50 deletions(-)
>
> diff --git a/RiscVPlatformPkg/RiscVPlatformPkg.dec b/RiscVPlatformPkg/RiscVPlatformPkg.dec
> index 53d424c901..f3217e4a05 100644
> --- a/RiscVPlatformPkg/RiscVPlatformPkg.dec
> +++ b/RiscVPlatformPkg/RiscVPlatformPkg.dec
> @@ -1,7 +1,7 @@
> ## @file RiscVPlatformPkg.dec
> # This Package provides UEFI RISC-V platform modules and libraries.
> #
> -# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> +# Copyright (c) 2021-2022, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> #
> # SPDX-License-Identifier: BSD-2-Clause-Patent
> #
> @@ -20,7 +20,7 @@
> [LibraryClasses]
> FirmwareContextProcessorSpecificLib|Include/Library/FirmwareContextProcessorSpecificLib.h
> RiscVPlatformTempMemoryInitLib|Include/Library/RiscVPlatformTempMemoryInitLib.h
> - Edk2OpensbiPlatformiLib|Include/Library/Edk2OpensbiPlatformiWrapperLib.h
> + Edk2OpensbiPlatformWrapperLib|Include/Library/Edk2OpensbiPlatformWrapperLib.h
>
> [Guids]
> gUefiRiscVPlatformPkgTokenSpaceGuid = {0x6A67AF99, 0x4592, 0x40F8, { 0xB6, 0xBE, 0x62, 0xBC, 0xA1, 0x0D, 0xA1, 0xEC}}
> diff --git a/RiscVPlatformPkg/Library/FirmwareContextProcessorSpecificLib/FirmwareContextProcessorSpecificLib.inf b/RiscVPlatformPkg/Library/FirmwareContextProcessorSpecificLib/FirmwareContextProcessorSpecificLib.inf
> index 4da78178a9..0d8aa9828f 100644
> --- a/RiscVPlatformPkg/Library/FirmwareContextProcessorSpecificLib/FirmwareContextProcessorSpecificLib.inf
> +++ b/RiscVPlatformPkg/Library/FirmwareContextProcessorSpecificLib/FirmwareContextProcessorSpecificLib.inf
> @@ -1,8 +1,8 @@
> ## @file
> # This is the library module of RISC-V EDK2 OpenSBI Firmware Context
> -# Processor Specific hwardware information.
> +# Processor Specific hardware information.
> #
> -# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> +# Copyright (c) 2019-2022, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> #
> # SPDX-License-Identifier: BSD-2-Clause-Patent
> #
> diff --git a/RiscVPlatformPkg/Universal/FdtPeim/FdtPeim.inf b/RiscVPlatformPkg/Universal/FdtPeim/FdtPeim.inf
> index cc870b8a91..45898c9dcd 100644
> --- a/RiscVPlatformPkg/Universal/FdtPeim/FdtPeim.inf
> +++ b/RiscVPlatformPkg/Universal/FdtPeim/FdtPeim.inf
> @@ -1,7 +1,7 @@
> ## @file
> # The FDT Peim driver is used to pass the device tree to DXE phase.
> #
> -# Copyright (c) 2021, Hewlett Packard Enterprise Developmente LP. All rights reserved.<BR>
> +# Copyright (c) 2021-2022, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> #
> # SPDX-License-Identifier: BSD-2-Clause-Patent
> #
> diff --git a/RiscVPkg/Include/ProcessorSpecificHobData.h b/RiscVPkg/Include/ProcessorSpecificHobData.h
> index 2f5847e53e..97285289f7 100644
> --- a/RiscVPkg/Include/ProcessorSpecificHobData.h
> +++ b/RiscVPkg/Include/ProcessorSpecificHobData.h
> @@ -1,7 +1,7 @@
> /** @file
> Definition of Processor Specific Data HOB.
>
> - Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> + Copyright (c) 2019-2022, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
>
> SPDX-License-Identifier: BSD-2-Clause-Patent
>
> @@ -24,7 +24,7 @@
> /// RISC-V processor specific data HOB
> ///
> typedef struct {
> - EFI_GUID ParentPrcessorGuid;
> + EFI_GUID ParentProcessorGuid;
> UINTN ParentProcessorUid;
> EFI_GUID CoreGuid;
> VOID *Context; // The additional information of this core which
> @@ -37,7 +37,7 @@ typedef struct {
> /// RISC-V SMBIOS type 4 (Processor) GUID data HOB
> ///
> typedef struct {
> - EFI_GUID PrcessorGuid;
> + EFI_GUID ProcessorGuid;
> UINTN ProcessorUid;
> SMBIOS_TABLE_TYPE4 SmbiosType4Processor;
> UINT16 EndingZero;
> @@ -75,7 +75,7 @@ typedef struct {
> /// RISC-V SMBIOS type 7 (Cache) GUID data HOB
> ///
> typedef struct {
> - EFI_GUID PrcessorGuid;
> + EFI_GUID ProcessorGuid;
> UINTN ProcessorUid;
> SMBIOS_TABLE_TYPE7 SmbiosType7Cache;
> UINT16 EndingZero;
> diff --git a/RiscVPlatformPkg/Include/Library/FirmwareContextProcessorSpecificLib.h b/RiscVPlatformPkg/Include/Library/FirmwareContextProcessorSpecificLib.h
> index 3920c61155..0eec62033b 100644
> --- a/RiscVPlatformPkg/Include/Library/FirmwareContextProcessorSpecificLib.h
> +++ b/RiscVPlatformPkg/Include/Library/FirmwareContextProcessorSpecificLib.h
> @@ -1,7 +1,7 @@
> /** @file
> Firmware Context Processor-specific common library
>
> - Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> + Copyright (c) 2019-2022, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
>
> SPDX-License-Identifier: BSD-2-Clause-Patent
>
> @@ -18,7 +18,7 @@
>
> @param FirmwareContextHartSpecific Pointer to EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC
> @param ParentProcessorGuid Pointer to GUID of Processor which contains this core
> - @param ParentProcessorUid Unique ID of pysical processor which owns this core.
> + @param ParentProcessorUid Unique ID of physical processor which owns this core.
> @param CoreGuid Pointer to GUID of core
> @param HartId Hart ID of this core.
> @param IsBootHart This is boot hart or not
> diff --git a/RiscVPlatformPkg/Universal/Sec/SecMain.h b/RiscVPlatformPkg/Universal/Sec/SecMain.h
> index 63a610fbd0..4098bd7d92 100644
> --- a/RiscVPlatformPkg/Universal/Sec/SecMain.h
> +++ b/RiscVPlatformPkg/Universal/Sec/SecMain.h
> @@ -1,7 +1,7 @@
> /** @file
> RISC-V SEC phase module definitions..
>
> - Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> + Copyright (c) 2019-2022, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
>
> SPDX-License-Identifier: BSD-2-Clause-Patent
>
> @@ -35,7 +35,7 @@
>
> **/
> INT32
> -SecPostOpenSbiPlatformEarlylInit(
> +SecPostOpenSbiPlatformEarlyInit(
> IN BOOLEAN ColdBoot
> );
>
> diff --git a/RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.c b/RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.c
> index b30f9d7f6a..14f62c4036 100644
> --- a/RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.c
> +++ b/RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.c
> @@ -1,7 +1,7 @@
> /** @file
> RISC-V generic SMBIOS DXE driver to build up SMBIOS type 4, type 7 and type 44 records.
>
> - Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> + Copyright (c) 2019-2022, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
>
> SPDX-License-Identifier: BSD-2-Clause-Patent
>
> @@ -33,7 +33,7 @@ BuildSmbiosType7 (
> EFI_STATUS Status;
> SMBIOS_HANDLE Handle;
>
> - if (!CompareGuid (&Type4HobData->PrcessorGuid, &Type7DataHob->PrcessorGuid) ||
> + if (!CompareGuid (&Type4HobData->ProcessorGuid, &Type7DataHob->ProcessorGuid) ||
> Type4HobData->ProcessorUid != Type7DataHob->ProcessorUid) {
> return EFI_INVALID_PARAMETER;
> }
> @@ -48,7 +48,7 @@ BuildSmbiosType7 (
> return Status;
> }
> DEBUG ((DEBUG_INFO, "SMBIOS Type 7 was added. SMBIOS Handle: 0x%x\n", Handle));
> - DEBUG ((DEBUG_VERBOSE, " Cache belone to processor GUID: %g\n", &Type7DataHob->PrcessorGuid));
> + DEBUG ((DEBUG_VERBOSE, " Cache belone to processor GUID: %g\n", &Type7DataHob->ProcessorGuid));
belone -> belongs?
> DEBUG ((DEBUG_VERBOSE, " Cache belone processor UID: %d\n", Type7DataHob->ProcessorUid));
> DEBUG ((DEBUG_VERBOSE, " ==============================\n"));
> DEBUG ((DEBUG_VERBOSE, " Socket Designation: %d\n", Type7DataHob->SmbiosType7Cache.SocketDesignation));
> @@ -90,7 +90,7 @@ BuildSmbiosType4 (
> EFI_STATUS Status;
>
> DEBUG ((DEBUG_INFO, "Building Type 4.\n"));
> - DEBUG ((DEBUG_INFO, " Processor GUID: %g\n", &Type4HobData->PrcessorGuid));
> + DEBUG ((DEBUG_INFO, " Processor GUID: %g\n", &Type4HobData->ProcessorGuid));
> DEBUG ((DEBUG_INFO, " Processor UUID: %d\n", Type4HobData->ProcessorUid));
>
> Type4HobData->SmbiosType4Processor.L1CacheHandle = RISC_V_CACHE_INFO_NOT_PROVIDED;
> @@ -193,7 +193,7 @@ BuildSmbiosType44 (
> EFI_STATUS Status;
>
> DEBUG ((DEBUG_INFO, "Building Type 44 for...\n"));
> - DEBUG ((DEBUG_VERBOSE, " Processor GUID: %g\n", &Type4HobData->PrcessorGuid));
> + DEBUG ((DEBUG_VERBOSE, " Processor GUID: %g\n", &Type4HobData->ProcessorGuid));
> DEBUG ((DEBUG_VERBOSE, " Processor UUID: %d\n", Type4HobData->ProcessorUid));
>
> GuidHob = (EFI_HOB_GUID_TYPE *)GetFirstGuidHob ((EFI_GUID *)PcdGetPtr(PcdProcessorSpecificDataGuidHobGuid));
> @@ -206,7 +206,7 @@ BuildSmbiosType44 (
> //
> do {
> ProcessorSpecificData = (RISC_V_PROCESSOR_SPECIFIC_HOB_DATA *)GET_GUID_HOB_DATA (GuidHob);
> - if (!CompareGuid (&ProcessorSpecificData->ParentPrcessorGuid, &Type4HobData->PrcessorGuid) ||
> + if (!CompareGuid (&ProcessorSpecificData->ParentProcessorGuid, &Type4HobData->ProcessorGuid) ||
> ProcessorSpecificData->ParentProcessorUid != Type4HobData->ProcessorUid) {
> GuidHob = GetNextGuidHob((EFI_GUID *)PcdGetPtr(PcdProcessorSpecificDataGuidHobGuid), GET_NEXT_HOB(GuidHob));
> if (GuidHob == NULL) {
> diff --git a/RiscVPlatformPkg/Library/Edk2OpensbiPlatformWrapperLib/Edk2OpensbiPlatformWrapperLib.c b/RiscVPlatformPkg/Library/Edk2OpensbiPlatformWrapperLib/Edk2OpensbiPlatformWrapperLib.c
> index 2137c6c619..0bd1b44241 100644
> --- a/RiscVPlatformPkg/Library/Edk2OpensbiPlatformWrapperLib/Edk2OpensbiPlatformWrapperLib.c
> +++ b/RiscVPlatformPkg/Library/Edk2OpensbiPlatformWrapperLib/Edk2OpensbiPlatformWrapperLib.c
> @@ -1,7 +1,7 @@
> /** @file
> EDK2 OpenSBI generic platform wrapper library
>
> - Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> + Copyright (c) 2019-2022, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
>
> SPDX-License-Identifier: BSD-2-Clause-Patent
>
> @@ -43,7 +43,7 @@ SecSetEdk2FwMemoryRegions (
> fw_memregs.flags = SBI_DOMAIN_MEMREGION_EXECUTABLE | SBI_DOMAIN_MEMREGION_READABLE;
> Ret = sbi_domain_root_add_memregion ((CONST struct sbi_domain_memregion *)&fw_memregs);
> if (Ret != 0) {
> - DEBUG ((DEBUG_ERROR, "%a: Add firmware regiosn of FW Domain fail\n", __FUNCTION__));
> + DEBUG ((DEBUG_ERROR, "%a: Add firmware regions of FW Domain fail\n", __FUNCTION__));
> }
>
> //
> @@ -54,7 +54,7 @@ SecSetEdk2FwMemoryRegions (
> fw_memregs.flags = SBI_DOMAIN_MEMREGION_READABLE | SBI_DOMAIN_MEMREGION_WRITEABLE;
> Ret = sbi_domain_root_add_memregion ((CONST struct sbi_domain_memregion *)&fw_memregs);
> if (Ret != 0) {
> - DEBUG ((DEBUG_ERROR, "%a: Add firmware regiosn of variable FW Domain fail\n", __FUNCTION__));
> + DEBUG ((DEBUG_ERROR, "%a: Add firmware regions of variable FW Domain fail\n", __FUNCTION__));
> }
> return Ret;
> }
> @@ -66,7 +66,7 @@ SecSetEdk2FwMemoryRegions (
>
> **/
> INT32
> -SecPostOpenSbiPlatformEarlylInit(
> +SecPostOpenSbiPlatformEarlyInit(
> IN BOOLEAN ColdBoot
> )
> {
> @@ -190,7 +190,7 @@ Edk2OpensbiPlatformEarlyInit (
> }
> }
> if (ColdBoot) {
> - return SecPostOpenSbiPlatformEarlylInit(ColdBoot);
> + return SecPostOpenSbiPlatformEarlyInit(ColdBoot);
> }
> return 0;
> }
> diff --git a/RiscVPlatformPkg/Library/FirmwareContextProcessorSpecificLib/FirmwareContextProcessorSpecificLib.c b/RiscVPlatformPkg/Library/FirmwareContextProcessorSpecificLib/FirmwareContextProcessorSpecificLib.c
> index 143c18d62c..c94f7881c2 100644
> --- a/RiscVPlatformPkg/Library/FirmwareContextProcessorSpecificLib/FirmwareContextProcessorSpecificLib.c
> +++ b/RiscVPlatformPkg/Library/FirmwareContextProcessorSpecificLib/FirmwareContextProcessorSpecificLib.c
> @@ -1,7 +1,7 @@
> /** @file
> - Common library to build upfirmware context processor-specific information
> + Common library to build up firmware context processor-specific information
>
> - Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> + Copyright (c) 2019-2022, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
>
> SPDX-License-Identifier: BSD-2-Clause-Patent
>
> @@ -28,7 +28,7 @@
>
> @param FirmwareContextHartSpecific Pointer to EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC
> @param ParentProcessorGuid Pointer to GUID of Processor which contains this core
> - @param ParentProcessorUid Unique ID of pysical processor which owns this core.
> + @param ParentProcessorUid Unique ID of physical processor which owns this core.
> @param CoreGuid Pointer to GUID of core
> @param HartId Hart ID of this core.
> @param IsBootHart This is boot hart or not
> @@ -52,7 +52,7 @@ CommonFirmwareContextHartSpecificInfo (
> //
> // Build up RISC_V_PROCESSOR_SPECIFIC_DATA_HOB.
> //
> - CopyGuid (&ProcessorSpecificDataHob->ParentPrcessorGuid, ParentProcessorGuid);
> + CopyGuid (&ProcessorSpecificDataHob->ParentProcessorGuid, ParentProcessorGuid);
> ProcessorSpecificDataHob->ParentProcessorUid = ParentProcessorUid;
> CopyGuid (&ProcessorSpecificDataHob->CoreGuid, CoreGuid);
> ProcessorSpecificDataHob->Context = NULL;
> diff --git a/RiscVPlatformPkg/Library/PlatformBootManagerLib/PlatformBootManager.c b/RiscVPlatformPkg/Library/PlatformBootManagerLib/PlatformBootManager.c
> index deaad7d5a1..9ad4ef17db 100644
> --- a/RiscVPlatformPkg/Library/PlatformBootManagerLib/PlatformBootManager.c
> +++ b/RiscVPlatformPkg/Library/PlatformBootManagerLib/PlatformBootManager.c
> @@ -1,7 +1,7 @@
> /** @file
> This file include all platform actions
>
> -Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> +Copyright (c) 2021-2022, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
>
> SPDX-License-Identifier: BSD-2-Clause-Patent
> @@ -215,7 +215,7 @@ PlatformBootManagerBeforeConsole (
> Signal console ready platform customized event;
> Run diagnostics like memory testing;
> Connect certain devices;
> - Dispatch aditional option roms.
> + Dispatch additional option roms.
> **/
> VOID
> EFIAPI
> diff --git a/RiscVPlatformPkg/Universal/Pei/PlatformPei/Platform.c b/RiscVPlatformPkg/Universal/Pei/PlatformPei/Platform.c
> index 8a248f3630..c28b2ed373 100644
> --- a/RiscVPlatformPkg/Universal/Pei/PlatformPei/Platform.c
> +++ b/RiscVPlatformPkg/Universal/Pei/PlatformPei/Platform.c
> @@ -1,7 +1,7 @@
> /** @file
> Platform PEI driver
>
> - Copyright (c) 2019-2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> + Copyright (c) 2019-2022, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>
> Copyright (c) 2011, Andrei Warkentin <andreiw@motorola.com>
>
> @@ -357,7 +357,7 @@ InitializePlatform (
> MiscInitialization ();
> Status = BuildCoreInformationHob ();
> if (EFI_ERROR (Status)) {
> - DEBUG ((DEBUG_ERROR, "Fail to build processor informstion HOB.\n"));
> + DEBUG ((DEBUG_ERROR, "Fail to build processor information HOB.\n"));
> ASSERT(FALSE);
> }
> return EFI_SUCCESS;
> diff --git a/RiscVPlatformPkg/Universal/Sec/SecMain.c b/RiscVPlatformPkg/Universal/Sec/SecMain.c
> index 1fafed2799..f67dbdf059 100644
> --- a/RiscVPlatformPkg/Universal/Sec/SecMain.c
> +++ b/RiscVPlatformPkg/Universal/Sec/SecMain.c
> @@ -1,7 +1,7 @@
> /** @file
> RISC-V SEC phase module.
>
> - Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> + Copyright (c) 2021-2022, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
>
> SPDX-License-Identifier: BSD-2-Clause-Patent
>
> @@ -291,7 +291,7 @@ FindPeiCoreImageBase (
> /**
> Find and return Pei Core entry point.
>
> - It also find SEC and PEI Core file debug inforamtion. It will report them if
> + It also find SEC and PEI Core file debug information. It will report them if
find -> finds
Regards
Sunil
> remote debug is enabled.
>
> @param[in] BootFirmwareVolumePtr The firmware volume pointer to search
> @@ -516,7 +516,7 @@ LaunchPeiCore (
> @param[in] FuncArg1 Arg1 to pass to next phase entry point address.
> @param[in] NextAddr Entry point of next phase.
> @param[in] NextMode Privilege mode of next phase.
> - @param[in] NextVirt Next phase is in virtualiztion.
> + @param[in] NextVirt Next phase is in virtualization.
>
> **/
> VOID
> @@ -600,7 +600,7 @@ Edk2PlatformHartIndex2Id (
> }
>
> /**
> - This function initilizes hart specific information and SBI.
> + This function initializes hart specific information and SBI.
> For the boot hart, it boots system through PEI core and initial SBI in the DXE IPL.
> For others, it goes to initial SBI and halt.
>
> @@ -658,9 +658,9 @@ SecCoreStartUpWithStack(
> HartFirmwareContext->HartSwitchMode = RiscVOpenSbiHartSwitchMode;
>
> //
> - // Hook platorm_ops with EDK2 one. Thus we can have interface
> + // Hook platform_ops with EDK2 one. Thus we can have interface
> // call out to OEM EDK2 platform code in M-mode before switching
> - // to S-mode in opensbo init.
> + // to S-mode in opensbi init.
> //
> ThisSbiPlatform = (struct sbi_platform *)sbi_platform_ptr(Scratch);
> ThisSbiPlatform->platform_ops_addr = (unsigned long)&Edk2OpensbiPlatformOps;
> diff --git a/RiscVPlatformPkg/Readme.md b/RiscVPlatformPkg/Readme.md
> index 66fba15544..5a344a864a 100644
> --- a/RiscVPlatformPkg/Readme.md
> +++ b/RiscVPlatformPkg/Readme.md
> @@ -26,16 +26,16 @@ differently from the default settings according to the OEM platform design.
> to align with OpenSBI project. As mentioned earlier, ***RiscVOpensbiLib*** provides the RISC-V SBI
> implementation and initialize the OpenSBI boot flow. SEC module is also linked with below libraries,
> - edk2 [OpenSbiPlatformLib](#OpenSbiPlatformLib-library) library that provides the generic RISC-V platform initialization code.
> -- edk2 [RiscVSpecifialPlatformLib](#RiscVSpecifialPlatformLib-library) library which is provided by the RISC-V
> +- edk2 [RiscVSpecialPlatformLib](#RiscVSpecialPlatformLib-library) library which is provided by the RISC-V
> platform vendor for the platform-specific initialization. The underlying implementation of above two edk2 libraries
> are from OpenSBI project. edk2 libraries are introduced as the wrapper libraries that separates and organizes OpenSBI core and platform code based on edk2 framework and the the build mechanism for edk2 RISC-V platforms. ***RiscVOpensbiLib*** library is located under [RISC-V ProcessorPkg](https://github.com/tianocore/edk2-platforms/tree/master/Silicon/RISC-V/ProcessorPkg) while the platform code (e.g. OpenSbiPlatformLib) is located under [RISC-V PlatformPkg](https://github.com/tianocore/edk2-platforms/tree/master/Platform/RISC-V/PlatformPkg).
> -- edk2 [RiscVSpecifialPlatformLib](#riscvspecifialplatformlib) library is provided by the platform vendor and located under edk2 RISC-V platform-specific folder.
> +- edk2 [RiscVSpecialPlatformLib](#riscvspecialplatformlib) library is provided by the platform vendor and located under edk2 RISC-V platform-specific folder.
>
> ##### OpenSbiPlatformLib Library
> [Indicated as #2 in the figure](#risc-v-edk2-port-design-diagrams)
> > ***OpenSbiPlatformLib*** provides the generic RISC-V platform initialization code. Platform vendor can just utilize this library if they don't have additional requirements on the platform initialization.
>
> -##### RiscVSpecifialPlatformLib Library
> +##### RiscVSpecialPlatformLib Library
> [Indicated as #3 in the figure](#risc-v-edk2-port-design-diagrams)
> > The major use case of this library is to facilitate the interfaces for platform vendors to provide the special
> platform initialization based on the generic platform initialization library.
> @@ -57,7 +57,7 @@ privilege according to the PCD.
>
> #### PEI Phase
> SEC module hands off the boot process to PEI core in the privilege configured by ***PcdPeiCorePrivilegeMode*** PCD *(TODO, currently the privilege is forced to S-mode)*. PEI and later phases are allowed to executed in M-mode
> -if the platform doesn't require Hypervisor-extended Supervisor mode (HS-mode) for the virtualization. RISC-V edk2 port provides its own instance ***PeiCoreEntryPoint*** library [(indicated as #7 in the figure)](#risc-v-edk2-port-design-diagrams) and linked with [PlatformSecPpiLib](#platformsecppilib-library) in order to support the S-mode PEI phase. PEI core requires [RiscVFirmwareContextLib](#riscVfirmwarecontextlib-library) library to retrieve the information of RISC-V HARTs and platform (e.g. FDT) configurations that built up in SEC phase. ***PeiServicePointer*** is also maintained in the ***RISC-V OpenSBI FirmwareContext*** structure and the pointer is retrieved by [PeiServiceTablePointerOpensbi](#peiservicetablepointeropensbi-library) library.
> +if the platform doesn't require Hypervisor-extended Supervisor mode (HS-mode) for the virtualization. RISC-V edk2 port provides its own instance ***PeiCoreEntryPoint*** library [(indicated as #7 in the figure)](#risc-v-edk2-port-design-diagrams) and linked with [PlatformSecPpiLib](#platformsecppilib-library) in order to support the S-mode PEI phase. PEI core requires [RiscVFirmwareContextLib](#riscvfirmwarecontextlib-library) library to retrieve the information of RISC-V HARTs and platform (e.g. FDT) configurations that built up in SEC phase. ***PeiServicePointer*** is also maintained in the ***RISC-V OpenSBI FirmwareContext*** structure and the pointer is retrieved by [PeiServiceTablePointerOpensbi](#peiservicetablepointeropensbi-library) library.
>
> ##### PlatformSecPpiLib Library
> [Indicated as #8 in the figure](#risc-v-edk2-port-design-diagrams)
> @@ -178,7 +178,7 @@ The PCD settings regard to EFI Variable
> |PcdVariableFdSize| The EFI variable firmware device size|
> |PcdVariableFdBlockSize| The block size of EFI variable firmware device|
> |PcdPlatformFlashNvStorageVariableBase| EFI variable base address within firmware device|
> -|PcdPlatformFlashNvStorageFtwWorkingBase| The base address of EFI variable fault tolerance worksapce (FTW) within firmware device|
> +|PcdPlatformFlashNvStorageFtwWorkingBase| The base address of EFI variable fault tolerance workspace (FTW) within firmware device|
> |PcdPlatformFlashNvStorageFtwSpareBase| The base address of EFI variable spare FTW within firmware device|
>
> ### RISC-V Physical Memory Protection (PMP) Region Settings
> @@ -190,7 +190,7 @@ Below PCDs could be set in platform FDF file.
> |PcdRootFirmwareDomainSize| The size of root firmware domain|-|-|
> |PcdFirmwareDomainBaseAddress| The starting address of firmware domain that can be accessed and executed in S-mode|Full access|Readable and Executable|
> |PcdFirmwareDomainSize| The size of firmware domain|-|-|
> -|PcdVariableFirmwareRegionBaseAddress| The starting address of EFI variable region that can be accessed in S-mode|Full access|Readale and Writable|
> +|PcdVariableFirmwareRegionBaseAddress| The starting address of EFI variable region that can be accessed in S-mode|Full access|Readable and Writable|
> |PcdVariableFirmwareRegionSize| The size of EFI variable firmware region|-|-|
>
> ### RISC-V Processor HART Settings
> @@ -198,7 +198,7 @@ Below PCDs could be set in platform FDF file.
> | **PCD name** |**Usage**|
> |--------------|---------|
> |PcdHartCount| Number of RISC-V HARTs, the value is processor-implementation specific|
> -|PcdBootHartId| The ID of RISC-V HART to execute main fimrware code and boot system to OS|
> +|PcdBootHartId| The ID of RISC-V HART to execute main firmware code and boot system to OS|
> |PcdBootableHartNumber|The bootable HART number, which is incorporate with RISC-V OpenSBI platform hart_index2id value|
> |PcdBootableHartIndexToId| if PcdBootableHartNumber == 0, hart_index2id is built from Device Tree, otherwise this is an array of HART index to HART ID|
>
> diff --git a/RiscVPlatformPkg/Universal/Sec/Riscv64/SecEntry.S b/RiscVPlatformPkg/Universal/Sec/Riscv64/SecEntry.S
> index 0fc7817665..b7b41e4c11 100644
> --- a/RiscVPlatformPkg/Universal/Sec/Riscv64/SecEntry.S
> +++ b/RiscVPlatformPkg/Universal/Sec/Riscv64/SecEntry.S
> @@ -1,5 +1,5 @@
> /*
> - * Copyright (c) 2021 , Hewlett Packard Enterprise Development LP. All rights reserved.
> + * Copyright (c) 2021-2022 , Hewlett Packard Enterprise Development LP. All rights reserved.
> *
> * SPDX-License-Identifier: BSD-2-Clause
> *
> @@ -67,7 +67,7 @@ skip_fw_init:
> * DTB for this processor. We allocate the
> * scratch buffer according to this number.
> */
> - la a4, _pysical_hart_count
> + la a4, _physical_hart_count
> sd s7, (a4)
>
> li s8, FixedPcdGet32 (PcdOpenSbiStackSize)
> @@ -227,7 +227,7 @@ _start_warm:
> csrr a0, CSR_MHARTID
> j _uninitialized_hart_wait
> 4:
> - la a5, _pysical_hart_count
> + la a5, _physical_hart_count
> ld s7, (a5)
> /* Find the scratch space for this hart
> *
> @@ -294,7 +294,7 @@ _start_warm:
> .section .data, "aw"
> _boot_hart_done:
> RISCV_PTR 0
> -_pysical_hart_count:
> +_physical_hart_count:
> RISCV_PTR 0
>
> .align 3
> @@ -323,7 +323,7 @@ _hartid_to_scratch:
> lw s0, SBI_PLATFORM_HART_STACK_SIZE_OFFSET(s2)
> #endif
>
> - la s1, _pysical_hart_count /* total HART count */
> + la s1, _physical_hart_count /* total HART count */
> ld s2, (s1)
> mul s2, s2, s0
> li s1, FixedPcdGet32 (PcdScratchRamBase)
> --
> 2.31.1
>
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 73/79] RiscVPkg: Address Core CI ECC errors.
[not found] ` <20220108041420.16064-12-abner.chang@hpe.com>
@ 2022-01-09 15:32 ` Sunil V L
0 siblings, 0 replies; 7+ messages in thread
From: Sunil V L @ 2022-01-09 15:32 UTC (permalink / raw)
To: Abner Chang; +Cc: devel, Daniel Schaefer
On Sat, Jan 08, 2022 at 12:14:14PM +0800, Abner Chang wrote:
> Signed-off-by: Abner Chang <abner.chang@hpe.com>
> Cc: Daniel Schaefer <daniel.schaefer@hpe.com>
> Cc: Sunil V L <sunilvl@ventanamicro.com>
> ---
> RiscVPkg/RiscVPkg.dec | 2 ++
> RiscVPkg/RiscVPkg.dsc | 4 ++--
> .../RiscVFirmwareContextSbiLib.inf | 2 +-
> .../Include/Library/MachineModeTimerLib.h | 15 +++++++++++++
> .../Include/Library/RiscVPlatformTimerLib.h | 21 +++++++++++++++++++
> .../CpuExceptionHandlerLib.h | 2 +-
> RiscVPkg/RiscVPkg.uni | 18 +++++++++++++++-
> 7 files changed, 59 insertions(+), 5 deletions(-)
> create mode 100644 RiscVPkg/Include/Library/MachineModeTimerLib.h
> create mode 100644 RiscVPkg/Include/Library/RiscVPlatformTimerLib.h
>
> diff --git a/RiscVPkg/RiscVPkg.dec b/RiscVPkg/RiscVPkg.dec
> index f23d3c0135..1e2d2fac0d 100644
> --- a/RiscVPkg/RiscVPkg.dec
> +++ b/RiscVPkg/RiscVPkg.dec
> @@ -26,6 +26,8 @@
> RiscVCpuLib|Include/Library/RiscVCpuLib.h
> RiscVEdk2SbiLib|Include/Library/RiscVEdk2SbiLib.h
> RiscVFirmwareContextLib|Include/Library/RiscVFirmwareContextLib.h
> + RiscVPlatformTimerLib|Include/Library/RiscVPlatformTimerLib.h
> + MachineModeTimerLib|Include/Library/MachineModeTimerLib.h
>
> [Guids]
> gUefiRiscVPkgTokenSpaceGuid = { 0x4261e9c8, 0x52c0, 0x4b34, { 0x85, 0x3d, 0x48, 0x46, 0xea, 0xd3, 0xb7, 0x2c}}
> diff --git a/RiscVPkg/RiscVPkg.dsc b/RiscVPkg/RiscVPkg.dsc
> index 7e8c8f599c..c1cd11a161 100644
> --- a/RiscVPkg/RiscVPkg.dsc
> +++ b/RiscVPkg/RiscVPkg.dsc
> @@ -1,11 +1,11 @@
> -#/** @file
> +## @file
> # RISC-V package.
> #
> # Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> #
> # SPDX-License-Identifier: BSD-2-Clause-Patent
> #
> -#**/
> +#
>
> ################################################################################
> #
> diff --git a/RiscVPkg/Library/RiscVFirmwareContextSbiLib/RiscVFirmwareContextSbiLib.inf b/RiscVPkg/Library/RiscVFirmwareContextSbiLib/RiscVFirmwareContextSbiLib.inf
> index db30d7e551..e3dbc05007 100644
> --- a/RiscVPkg/Library/RiscVFirmwareContextSbiLib/RiscVFirmwareContextSbiLib.inf
> +++ b/RiscVPkg/Library/RiscVFirmwareContextSbiLib/RiscVFirmwareContextSbiLib.inf
> @@ -12,7 +12,7 @@
> [Defines]
> INF_VERSION = 0x0001001b
> BASE_NAME = RiscVFirmwareContextSbiLib
> - FILE_GUID = 3709E048-6794-427A-B728-BFE3FFD6D461
> + FILE_GUID = 308117C0-400A-79C5-6ED4-AB9763A202E5
Any reason to have new GUID?
> MODULE_TYPE = PEIM
> VERSION_STRING = 1.0
> LIBRARY_CLASS = RiscVFirmwareContextLib|PEIM PEI_CORE
> diff --git a/RiscVPkg/Include/Library/MachineModeTimerLib.h b/RiscVPkg/Include/Library/MachineModeTimerLib.h
> new file mode 100644
> index 0000000000..a27391cca3
> --- /dev/null
> +++ b/RiscVPkg/Include/Library/MachineModeTimerLib.h
> @@ -0,0 +1,15 @@
> +/** @file
> + RISC-V Machine Mode Timer Library Definition
> +
> + Copyright (c) 2022, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef MACHINE_MODE_TIMER_LIB_H_
> +#define MACHINE_MODE_TIMER_LIB_H_
> +
> +UINT64
> +RiscVReadMachineTimerInterface (VOID);
> +
> +#endif
> diff --git a/RiscVPkg/Include/Library/RiscVPlatformTimerLib.h b/RiscVPkg/Include/Library/RiscVPlatformTimerLib.h
> new file mode 100644
> index 0000000000..dcd8734eb5
> --- /dev/null
> +++ b/RiscVPkg/Include/Library/RiscVPlatformTimerLib.h
> @@ -0,0 +1,21 @@
> +/** @file
> + RISC-V Platform Timer library definitions.
> +
> + Copyright (c) 2022, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef RISCV_PLATFORM_TIMER_LIB_H_
> +#define RISCV_PLATFORM_TIMER_LIB_H_
> +
> +UINT64
> +RiscVReadMachineTimer (VOID);
> +
> +VOID
> +RiscVSetMachineTimerCmp (UINT64);
> +
> +UINT64
> +RiscVReadMachineTimerCmp(VOID);
> +
> +#endif
> diff --git a/RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerLib.h b/RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerLib.h
> index 3e480e9b09..b316510020 100644
> --- a/RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerLib.h
> +++ b/RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerLib.h
> @@ -1,4 +1,4 @@
> -/**@file
> +/** @file
>
> RISC-V Exception Handler library definition file.
>
> diff --git a/RiscVPkg/RiscVPkg.uni b/RiscVPkg/RiscVPkg.uni
> index 7e470eb531..d459272444 100644
> --- a/RiscVPkg/RiscVPkg.uni
> +++ b/RiscVPkg/RiscVPkg.uni
> @@ -8,6 +8,22 @@
> // **/
>
> #string STR_PACKAGE_ABSTRACT #language en-US "Provides UEFI compatible RISC-V processor modules and libraries"
> -
> #string STR_PACKAGE_DESCRIPTION #language en-US "This Package provides UEFI compatible RISC-V processor modules and libraries."
>
> +#string STR_gUefiRiscVPkgTokenSpaceGuid_PcdProcessorSpecificDataGuidHobGuid_PROMPT #language en-US "Processor Specific Data HOB GUID"
> +#string STR_gUefiRiscVPkgTokenSpaceGuid_PcdProcessorSpecificDataGuidHobGuid_HELP #language en-US "This is the GUID definition of HOB that passes the "
> + "processor specific data to DXE phase."
> +#string STR_gUefiRiscVPkgTokenSpaceGuid_PcdProcessorSmbiosGuidHobGuid_PROMPT #language en-US "RISC-V SMBIOS Data HOB GUID"
> +#string STR_gUefiRiscVPkgTokenSpaceGuid_PcdProcessorSmbiosGuidHobGuid_HELP #language en-US "This is the GUID definition of HOB that passes RISC-V SMBIOS"
> + "Data to DXE phase."
I think space is required between multi line help string. Same comment
for other places.
> +#string STR_gUefiRiscVPkgTokenSpaceGuid_PcdProcessorSmbiosType4GuidHobGuid_PROMPT #language en-US "RISC-V SMBIOS Type 4 Data HOB GUID"
> +#string STR_gUefiRiscVPkgTokenSpaceGuid_PcdProcessorSmbiosType4GuidHobGuid_HELP #language en-US "This is the GUID definition of HOB that passes RISC-V SMBIOS"
> + "Type 4 information to DXE phase for building up SMBIOS record."
> +#string STR_gUefiRiscVPkgTokenSpaceGuid_PcdProcessorSmbiosType7GuidHobGuid_PROMPT #language en-US "RISC-V SMBIOS Type 7 Data HOB GUID"
> +#string STR_gUefiRiscVPkgTokenSpaceGuid_PcdProcessorSmbiosType7GuidHobGuid_HELP #language en-US "This is the GUID definition of HOB that passes RISC-V SMBIOS"
> + "Type 7 information to DXE phase for building up SMBIOS record."
> +#string STR_gUefiRiscVPkgTokenSpaceGuid_PcdRiscVMachineTimerTickInNanoSecond_PROMPT #language en-US "RISC-V Machine Mode Timer Duration"
> +#string STR_gUefiRiscVPkgTokenSpaceGuid_PcdRiscVMachineTimerTickInNanoSecond_HELP #language en-US "RISC-V Machine Mode Timer Duration in nanosecond."
> +#string STR_gUefiRiscVPkgTokenSpaceGuid_PcdRiscVMachineTimerFrequencyInHerz_PROMPT #language en-US "RISC-V Machine Mode Timer frequency."
> +#string STR_gUefiRiscVPkgTokenSpaceGuid_PcdRiscVMachineTimerFrequencyInHerz_HELP #language en-US "RISC-V Machine Mode Timer frequency in Herz"
Should this Hertz instead of Herz?
Regards
Sunil
> +
> --
> 2.31.1
>
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 75/79] RiscVPkg: Address Core CI Spelling errors.
[not found] ` <20220108041420.16064-14-abner.chang@hpe.com>
@ 2022-01-09 15:39 ` Sunil V L
0 siblings, 0 replies; 7+ messages in thread
From: Sunil V L @ 2022-01-09 15:39 UTC (permalink / raw)
To: Abner Chang; +Cc: devel, Daniel Schaefer
On Sat, Jan 08, 2022 at 12:14:16PM +0800, Abner Chang wrote:
> From: changab <abner.chang@hpe.com>
>
> Signed-off-by: Abner Chang <abner.chang@hpe.com>
> Cc: Daniel Schaefer <daniel.schaefer@hpe.com>
> Cc: Sunil V L <sunilvl@ventanamicro.com>
> ---
> RiscVPkg/RiscVPkg.dec | 4 ++--
> .../RiscVFirmwareContextSbiLib.inf | 6 +++---
> .../RiscVFirmwareContextSscratchLib.inf | 4 ++--
> .../RiscVFirmwareContextStvecLib.inf | 6 +++---
> RiscVPkg/Include/Library/RiscVEdk2SbiLib.h | 16 ++++++++--------
> RiscVPkg/Include/OpensbiTypes.h | 4 ++--
> RiscVPkg/Include/ProcessorSpecificHobData.h | 2 +-
> RiscVPkg/Include/SmbiosProcessorSpecificData.h | 4 ++--
> .../Library/RiscVEdk2SbiLib/RiscVEdk2SbiLib.c | 16 ++++++++--------
> .../RiscVExceptionLib/CpuExceptionHandlerLib.c | 6 +++---
> .../RiscVFirmwareContextSbiLib.c | 4 ++--
> .../RiscVFirmwareContextStvecLib.c | 4 ++--
> 12 files changed, 38 insertions(+), 38 deletions(-)
>
> diff --git a/RiscVPkg/RiscVPkg.dec b/RiscVPkg/RiscVPkg.dec
> index 448124a1a0..893f017d52 100644
> --- a/RiscVPkg/RiscVPkg.dec
> +++ b/RiscVPkg/RiscVPkg.dec
> @@ -1,7 +1,7 @@
> -## @file RiscVProcesssorPkg.dec
> +## @file RiscVProcessorPkg.dec
> # This Package provides UEFI RISC-V processor modules and libraries.
> #
> -# Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> +# Copyright (c) 2020-2022, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> #
> # SPDX-License-Identifier: BSD-2-Clause-Patent
> #
> diff --git a/RiscVPkg/Library/RiscVFirmwareContextSbiLib/RiscVFirmwareContextSbiLib.inf b/RiscVPkg/Library/RiscVFirmwareContextSbiLib/RiscVFirmwareContextSbiLib.inf
> index e3dbc05007..3cdf59b3cc 100644
> --- a/RiscVPkg/Library/RiscVFirmwareContextSbiLib/RiscVFirmwareContextSbiLib.inf
> +++ b/RiscVPkg/Library/RiscVFirmwareContextSbiLib/RiscVFirmwareContextSbiLib.inf
> @@ -1,9 +1,9 @@
> ## @file
> -# Instance of OpebSBI Firmware Conext Library
> +# Instance of OpenSBI Firmware Context Library
> #
> -# This iinstance uses RISC-V OpenSBI Firmware Extension SBI.
> +# This instance uses RISC-V OpenSBI Firmware Extension SBI.
> #
> -# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> +# Copyright (c) 2021-2022, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> #
> # SPDX-License-Identifier: BSD-2-Clause-Patent
> #
> diff --git a/RiscVPkg/Library/RiscVFirmwareContextSscratchLib/RiscVFirmwareContextSscratchLib.inf b/RiscVPkg/Library/RiscVFirmwareContextSscratchLib/RiscVFirmwareContextSscratchLib.inf
> index c6a74e5edc..5aef9efc71 100644
> --- a/RiscVPkg/Library/RiscVFirmwareContextSscratchLib/RiscVFirmwareContextSscratchLib.inf
> +++ b/RiscVPkg/Library/RiscVFirmwareContextSscratchLib/RiscVFirmwareContextSscratchLib.inf
> @@ -1,9 +1,9 @@
> ## @file
> -# Instance of OpebSBI Firmware Conext Library
> +# Instance of OpenSBI Firmware Context Library
> #
> # This instance uses RISC-V Supervisor mode SCRATCH CSR
> #
> -# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> +# Copyright (c) 2021-2022, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> #
> # SPDX-License-Identifier: BSD-2-Clause-Patent
> #
> diff --git a/RiscVPkg/Library/RiscVFirmwareContextStvecLib/RiscVFirmwareContextStvecLib.inf b/RiscVPkg/Library/RiscVFirmwareContextStvecLib/RiscVFirmwareContextStvecLib.inf
> index 9888cac81a..7c504c9c3c 100644
> --- a/RiscVPkg/Library/RiscVFirmwareContextStvecLib/RiscVFirmwareContextStvecLib.inf
> +++ b/RiscVPkg/Library/RiscVFirmwareContextStvecLib/RiscVFirmwareContextStvecLib.inf
> @@ -1,9 +1,9 @@
> ## @file
> -# Instance of OpebSBI Firmware Conext Library
> +# Instance of OpenSBI Firmware Context Library
> #
> -# This iinstance Supervisor mode STVEC CSR
> +# This instance Supervisor mode STVEC CSR
Should this be This instance "uses" ?
> #
> -# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> +# Copyright (c) 2021-2022, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> #
> # SPDX-License-Identifier: BSD-2-Clause-Patent
> #
> diff --git a/RiscVPkg/Include/Library/RiscVEdk2SbiLib.h b/RiscVPkg/Include/Library/RiscVEdk2SbiLib.h
> index 88d957f002..6089137373 100644
> --- a/RiscVPkg/Include/Library/RiscVEdk2SbiLib.h
> +++ b/RiscVPkg/Include/Library/RiscVEdk2SbiLib.h
> @@ -1,7 +1,7 @@
> /** @file
> Library to call the RISC-V SBI ecalls
>
> - Copyright (c) 2021, Hewlett Packard Development LP. All rights reserved.<BR>
> + Copyright (c) 2021-2022, Hewlett Packard Development LP. All rights reserved.<BR>
>
> SPDX-License-Identifier: BSD-2-Clause-Patent
>
> @@ -54,7 +54,7 @@ SbiGetSpecVersion (
> /**
> Get the SBI implementation ID
>
> - This ID is used to idenetify a specific SBI implementation in order to work
> + This ID is used to identify a specific SBI implementation in order to work
> around any quirks it might have.
>
> @param[out] ImplId The ID of the SBI implementation.
> @@ -275,7 +275,7 @@ SbiRemoteFenceI (
> /**
> Instructs the remote harts to execute one or more SFENCE.VMA instructions.
>
> - The SFENCE.VMA covers the range of virtual addresses between StartAaddr and Size.
> + The SFENCE.VMA covers the range of virtual addresses between StartAddr and Size.
>
> The remote fence function acts as a full tlb flush if * StartAddr and size
> are both 0 * size is equal to 2^XLEN-1
> @@ -305,7 +305,7 @@ SbiRemoteSfenceVma (
> /**
> Instructs the remote harts to execute one or more SFENCE.VMA instructions.
>
> - The SFENCE.VMA covers the range of virtual addresses between StartAaddr and Size.
> + The SFENCE.VMA covers the range of virtual addresses between StartAddr and Size.
> Covers only the given ASID.
>
> The remote fence function acts as a full tlb flush if * StartAddr and size
> @@ -337,7 +337,7 @@ SbiRemoteSfenceVmaAsid (
> /**
> Instructs the remote harts to execute one or more SFENCE.GVMA instructions.
>
> - The SFENCE.GVMA covers the range of virtual addresses between StartAaddr and Size.
> + The SFENCE.GVMA covers the range of virtual addresses between StartAddr and Size.
> Covers only the given VMID.
> This function call is only valid for harts implementing the hypervisor extension.
>
> @@ -373,7 +373,7 @@ SbiRemoteHfenceGvmaVmid (
> /**
> Instructs the remote harts to execute one or more SFENCE.GVMA instructions.
>
> - The SFENCE.GVMA covers the range of virtual addresses between StartAaddr and Size.
> + The SFENCE.GVMA covers the range of virtual addresses between StartAddr and Size.
> This function call is only valid for harts implementing the hypervisor extension.
>
> The remote fence function acts as a full tlb flush if * StartAddr and size
> @@ -407,7 +407,7 @@ SbiRemoteHfenceGvma (
> /**
> Instructs the remote harts to execute one or more SFENCE.VVMA instructions.
>
> - The SFENCE.GVMA covers the range of virtual addresses between StartAaddr and Size.
> + The SFENCE.GVMA covers the range of virtual addresses between StartAddr and Size.
> Covers only the given ASID.
> This function call is only valid for harts implementing the hypervisor extension.
>
> @@ -443,7 +443,7 @@ SbiRemoteHfenceVvmaAsid (
> /**
> Instructs the remote harts to execute one or more SFENCE.VVMA instructions.
>
> - The SFENCE.GVMA covers the range of virtual addresses between StartAaddr and Size.
> + The SFENCE.GVMA covers the range of virtual addresses between StartAddr and Size.
> This function call is only valid for harts implementing the hypervisor extension.
>
> The remote fence function acts as a full tlb flush if * StartAddr and size
> diff --git a/RiscVPkg/Include/OpensbiTypes.h b/RiscVPkg/Include/OpensbiTypes.h
> index 8a6ea97708..ca7fc7a4ac 100644
> --- a/RiscVPkg/Include/OpensbiTypes.h
> +++ b/RiscVPkg/Include/OpensbiTypes.h
> @@ -1,7 +1,7 @@
> /** @file
> - RISC-V OpesbSBI header file reference.
> + RISC-V OpensbiSBI header file reference.
Why opensbiSBI? Shouldn't this be just openSBI?
>
> - Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> + Copyright (c) 2020-2022, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
>
> SPDX-License-Identifier: BSD-2-Clause-Patent
>
> diff --git a/RiscVPkg/Include/ProcessorSpecificHobData.h b/RiscVPkg/Include/ProcessorSpecificHobData.h
> index 97285289f7..4b2a92e2f2 100644
> --- a/RiscVPkg/Include/ProcessorSpecificHobData.h
> +++ b/RiscVPkg/Include/ProcessorSpecificHobData.h
> @@ -29,7 +29,7 @@ typedef struct {
> EFI_GUID CoreGuid;
> VOID *Context; // The additional information of this core which
> // built in PEI phase and carried to DXE phase.
> - // The content is pocessor or platform specific.
> + // The content is processor or platform specific.
> SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA ProcessorSpecificData;
> } RISC_V_PROCESSOR_SPECIFIC_HOB_DATA;
>
> diff --git a/RiscVPkg/Include/SmbiosProcessorSpecificData.h b/RiscVPkg/Include/SmbiosProcessorSpecificData.h
> index 81e48cd068..85b8dcbe20 100644
> --- a/RiscVPkg/Include/SmbiosProcessorSpecificData.h
> +++ b/RiscVPkg/Include/SmbiosProcessorSpecificData.h
> @@ -1,9 +1,9 @@
> /** @file
> Industry Standard Definitions of RISC-V Processor Specific data defined in
> - below link for complaiant with SMBIOS Table Specification v3.3.0.
> + below link for compliant with SMBIOS Table Specification v3.3.0.
> https://github.com/riscv/riscv-smbios
>
> - Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> + Copyright (c) 2019-2022, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
>
> SPDX-License-Identifier: BSD-2-Clause-Patent
>
> diff --git a/RiscVPkg/Library/RiscVEdk2SbiLib/RiscVEdk2SbiLib.c b/RiscVPkg/Library/RiscVEdk2SbiLib/RiscVEdk2SbiLib.c
> index 319526ed8f..a51139542d 100644
> --- a/RiscVPkg/Library/RiscVEdk2SbiLib/RiscVEdk2SbiLib.c
> +++ b/RiscVPkg/Library/RiscVEdk2SbiLib/RiscVEdk2SbiLib.c
> @@ -15,7 +15,7 @@
> - SbiLegacyRemoteSfenceVmaAsid -> Use SbiRemoteSfenceVmaAsid
> - SbiLegacyShutdown -> Wait for new System Reset extension
>
> - Copyright (c) 2021, Hewlett Packard Development LP. All rights reserved.<BR>
> + Copyright (c) 2021-2022, Hewlett Packard Development LP. All rights reserved.<BR>
> SPDX-License-Identifier: BSD-2-Clause-Patent
>
> @par Revision Reference:
> @@ -173,7 +173,7 @@ SbiGetSpecVersion (
> /**
> Get the SBI implementation ID
>
> - This ID is used to idenetify a specific SBI implementation in order to work
> + This ID is used to identify a specific SBI implementation in order to work
> around any quirks it might have.
>
> @param[out] ImplId The ID of the SBI implementation.
> @@ -441,7 +441,7 @@ SbiRemoteFenceI (
> /**
> Instructs the remote harts to execute one or more SFENCE.VMA instructions.
>
> - The SFENCE.VMA covers the range of virtual addresses between StartAaddr and Size.
> + The SFENCE.VMA covers the range of virtual addresses between StartAddr and Size.
>
> The remote fence function acts as a full tlb flush if * StartAddr and size
> are both 0 * size is equal to 2^XLEN-1
> @@ -483,7 +483,7 @@ SbiRemoteSfenceVma (
> /**
> Instructs the remote harts to execute one or more SFENCE.VMA instructions.
>
> - The SFENCE.VMA covers the range of virtual addresses between StartAaddr and Size.
> + The SFENCE.VMA covers the range of virtual addresses between StartAddr and Size.
> Covers only the given ASID.
>
> The remote fence function acts as a full tlb flush if * StartAddr and size
> @@ -528,7 +528,7 @@ SbiRemoteSfenceVmaAsid (
> /**
> Instructs the remote harts to execute one or more SFENCE.GVMA instructions.
>
> - The SFENCE.GVMA covers the range of virtual addresses between StartAaddr and Size.
> + The SFENCE.GVMA covers the range of virtual addresses between StartAddr and Size.
> Covers only the given VMID.
> This function call is only valid for harts implementing the hypervisor extension.
>
> @@ -577,7 +577,7 @@ SbiRemoteHFenceGvmaVmid (
> /**
> Instructs the remote harts to execute one or more SFENCE.GVMA instructions.
>
> - The SFENCE.GVMA covers the range of virtual addresses between StartAaddr and Size.
> + The SFENCE.GVMA covers the range of virtual addresses between StartAddr and Size.
> This function call is only valid for harts implementing the hypervisor extension.
>
> The remote fence function acts as a full tlb flush if * StartAddr and size
> @@ -623,7 +623,7 @@ SbiRemoteHFenceGvma (
> /**
> Instructs the remote harts to execute one or more SFENCE.VVMA instructions.
>
> - The SFENCE.GVMA covers the range of virtual addresses between StartAaddr and Size.
> + The SFENCE.GVMA covers the range of virtual addresses between StartAddr and Size.
> Covers only the given ASID.
> This function call is only valid for harts implementing the hypervisor extension.
>
> @@ -672,7 +672,7 @@ SbiRemoteHFenceVvmaAsid (
> /**
> Instructs the remote harts to execute one or more SFENCE.VVMA instructions.
>
> - The SFENCE.GVMA covers the range of virtual addresses between StartAaddr and Size.
> + The SFENCE.GVMA covers the range of virtual addresses between StartAddr and Size.
> This function call is only valid for harts implementing the hypervisor extension.
>
> The remote fence function acts as a full tlb flush if * StartAddr and size
> diff --git a/RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerLib.c b/RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerLib.c
> index a9316ae758..43130336f3 100644
> --- a/RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerLib.c
> +++ b/RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerLib.c
> @@ -1,7 +1,7 @@
> /** @file
> - RISC-V Exception Handler library implementition.
> + RISC-V Exception Handler library implementation.
>
> - Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> + Copyright (c) 2016 - 2022, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
>
> SPDX-License-Identifier: BSD-2-Clause-Patent
>
> @@ -186,7 +186,7 @@ CpuExceptionHandlerLibConstructor (
> )
> {
> //
> - // Set Superviosr mode trap handler.
> + // Set Supervisor mode trap handler.
> //
> csr_write(CSR_STVEC, SupervisorModeTrap);
>
> diff --git a/RiscVPkg/Library/RiscVFirmwareContextSbiLib/RiscVFirmwareContextSbiLib.c b/RiscVPkg/Library/RiscVFirmwareContextSbiLib/RiscVFirmwareContextSbiLib.c
> index 6125618eaf..a2a18d3eb7 100644
> --- a/RiscVPkg/Library/RiscVFirmwareContextSbiLib/RiscVFirmwareContextSbiLib.c
> +++ b/RiscVPkg/Library/RiscVFirmwareContextSbiLib/RiscVFirmwareContextSbiLib.c
> @@ -1,8 +1,8 @@
> /** @file
> - This iinstance uses RISC-V OpenSBI Firmware Extension SBI to
> + This instance uses RISC-V OpenSBI Firmware Extension SBI to
> get the pointer of firmware context.
>
> - Copyright (c) 2021 Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> + Copyright (c) 2021-2022 Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
>
> SPDX-License-Identifier: BSD-2-Clause-Patent
> **/
> diff --git a/RiscVPkg/Library/RiscVFirmwareContextStvecLib/RiscVFirmwareContextStvecLib.c b/RiscVPkg/Library/RiscVFirmwareContextStvecLib/RiscVFirmwareContextStvecLib.c
> index 7d1675355a..d08b51d3d9 100644
> --- a/RiscVPkg/Library/RiscVFirmwareContextStvecLib/RiscVFirmwareContextStvecLib.c
> +++ b/RiscVPkg/Library/RiscVFirmwareContextStvecLib/RiscVFirmwareContextStvecLib.c
> @@ -1,8 +1,8 @@
> /** @file
> - This instance uses This iinstance Supervisor mode STVEC CSR to
> + This instance uses This instance Supervisor mode STVEC CSR to
Remove extra "This instance"
> get/set the pointer of firmware context.
>
> - Copyright (c) 2021 Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> + Copyright (c) 2021-2022 Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
>
> SPDX-License-Identifier: BSD-2-Clause-Patent
> **/
> --
> 2.31.1
>
^ permalink raw reply [flat|nested] 7+ messages in thread
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