From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-pf1-f170.google.com (mail-pf1-f170.google.com [209.85.210.170]) by mx.groups.io with SMTP id smtpd.web09.19224.1641742759303630793 for ; Sun, 09 Jan 2022 07:39:19 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@ventanamicro.com header.s=google header.b=jSFxMUAh; spf=pass (domain: ventanamicro.com, ip: 209.85.210.170, mailfrom: sunilvl@ventanamicro.com) Received: by mail-pf1-f170.google.com with SMTP id p37so8630646pfh.4 for ; Sun, 09 Jan 2022 07:39:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to; bh=PGmFtqH5whchlI/WvbymX1CPu7GEKMqxl51y0p2Ft/A=; b=jSFxMUAhxYFyHGM8X/gNGUvQPZB/j89hMRytp1Ztw0vnaNFk32BYermyzsZkd29vD3 O7tzTbzkHBePqJ9bBvzI/tmjPXEAaiV4b9ePXrl0/1Cvlf9zNptbU8aJsM/FeqgG8XhP /W0t+RuX5PNzBwo4OxQEmztLcHvPs/GoCjntdIJwnOER4ytxyo1yE4jdYsZ93CQJUIiX 2fWgV39SEz8+9xjuw/9GguKkKAyPDxJqkXU6amV/Rq6YTL5UsWStLs6K1xOyQt3kXiFt vxsDDJ+db57iiJTb4yzvhaL0UxvlLIl7/NV/tlw0hz2oUcRKzUHuBG2Txbv+w1pHK3Dx w2fw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=PGmFtqH5whchlI/WvbymX1CPu7GEKMqxl51y0p2Ft/A=; b=JiMJUIkpTNTTcQvAJuYELkEmSoRAxAjgAt3cFWLbJEBI3Q487Z5MTSGQfxepcIf7BE Eo2E/+yhxZvdfB2gcgg618ps3t5XwGFxguYTj+Ux9jLVqrYJAqVTM1YUIQX/Z2tumsnL sDYeldVopu0H1RAHLA3GoEkbNfvGDUHSh+dgEciF0zcbmDO7/O/s+JLf4St1Fgdwdu8I /dYgjhbY7+SiC6oENEl2dL4kXqQ8f+D/ZzOcx1Sztf0fcRHrV3G4F+OX2M7nSS02iETy p/lM9Ett4z6V2LwjW3gvAsitXmysEvKgyVzBSPSe4zEpX/ow22MWwGOYH5pJYuCiGx6b fKyQ== X-Gm-Message-State: AOAM530M5s2CM0WssJVwXYG8BeFiM2XZ8WP2JHuW+UYC710p/4vKT6eO SY8sL0ocIvHxdo5nnQpdsgzE1Q== X-Google-Smtp-Source: ABdhPJze+6GLJccVBaBmKc4Dv3x58XSk6SLLxzfYRAnXdoYYqMH32CVNhi+cLzaWpNsmeLaXRNZFeQ== X-Received: by 2002:a63:9a01:: with SMTP id o1mr63719354pge.449.1641742758570; Sun, 09 Jan 2022 07:39:18 -0800 (PST) Return-Path: Received: from sunil-ThinkPad-T490 ([49.206.3.187]) by smtp.gmail.com with ESMTPSA id z18sm4289916pfe.146.2022.01.09.07.39.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 09 Jan 2022 07:39:18 -0800 (PST) Date: Sun, 9 Jan 2022 21:09:14 +0530 From: "Sunil V L" To: Abner Chang Cc: devel@edk2.groups.io, Daniel Schaefer Subject: Re: [PATCH 75/79] RiscVPkg: Address Core CI Spelling errors. Message-ID: <20220109153914.GF4879@sunil-ThinkPad-T490> References: <20220108041420.16064-1-abner.chang@hpe.com> <20220108041420.16064-14-abner.chang@hpe.com> MIME-Version: 1.0 In-Reply-To: <20220108041420.16064-14-abner.chang@hpe.com> Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Sat, Jan 08, 2022 at 12:14:16PM +0800, Abner Chang wrote: > From: changab > > Signed-off-by: Abner Chang > Cc: Daniel Schaefer > Cc: Sunil V L > --- > RiscVPkg/RiscVPkg.dec | 4 ++-- > .../RiscVFirmwareContextSbiLib.inf | 6 +++--- > .../RiscVFirmwareContextSscratchLib.inf | 4 ++-- > .../RiscVFirmwareContextStvecLib.inf | 6 +++--- > RiscVPkg/Include/Library/RiscVEdk2SbiLib.h | 16 ++++++++-------- > RiscVPkg/Include/OpensbiTypes.h | 4 ++-- > RiscVPkg/Include/ProcessorSpecificHobData.h | 2 +- > RiscVPkg/Include/SmbiosProcessorSpecificData.h | 4 ++-- > .../Library/RiscVEdk2SbiLib/RiscVEdk2SbiLib.c | 16 ++++++++-------- > .../RiscVExceptionLib/CpuExceptionHandlerLib.c | 6 +++--- > .../RiscVFirmwareContextSbiLib.c | 4 ++-- > .../RiscVFirmwareContextStvecLib.c | 4 ++-- > 12 files changed, 38 insertions(+), 38 deletions(-) > > diff --git a/RiscVPkg/RiscVPkg.dec b/RiscVPkg/RiscVPkg.dec > index 448124a1a0..893f017d52 100644 > --- a/RiscVPkg/RiscVPkg.dec > +++ b/RiscVPkg/RiscVPkg.dec > @@ -1,7 +1,7 @@ > -## @file RiscVProcesssorPkg.dec > +## @file RiscVProcessorPkg.dec > # This Package provides UEFI RISC-V processor modules and libraries. > # > -# Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.
> +# Copyright (c) 2020-2022, Hewlett Packard Enterprise Development LP. All rights reserved.
> # > # SPDX-License-Identifier: BSD-2-Clause-Patent > # > diff --git a/RiscVPkg/Library/RiscVFirmwareContextSbiLib/RiscVFirmwareContextSbiLib.inf b/RiscVPkg/Library/RiscVFirmwareContextSbiLib/RiscVFirmwareContextSbiLib.inf > index e3dbc05007..3cdf59b3cc 100644 > --- a/RiscVPkg/Library/RiscVFirmwareContextSbiLib/RiscVFirmwareContextSbiLib.inf > +++ b/RiscVPkg/Library/RiscVFirmwareContextSbiLib/RiscVFirmwareContextSbiLib.inf > @@ -1,9 +1,9 @@ > ## @file > -# Instance of OpebSBI Firmware Conext Library > +# Instance of OpenSBI Firmware Context Library > # > -# This iinstance uses RISC-V OpenSBI Firmware Extension SBI. > +# This instance uses RISC-V OpenSBI Firmware Extension SBI. > # > -# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.
> +# Copyright (c) 2021-2022, Hewlett Packard Enterprise Development LP. All rights reserved.
> # > # SPDX-License-Identifier: BSD-2-Clause-Patent > # > diff --git a/RiscVPkg/Library/RiscVFirmwareContextSscratchLib/RiscVFirmwareContextSscratchLib.inf b/RiscVPkg/Library/RiscVFirmwareContextSscratchLib/RiscVFirmwareContextSscratchLib.inf > index c6a74e5edc..5aef9efc71 100644 > --- a/RiscVPkg/Library/RiscVFirmwareContextSscratchLib/RiscVFirmwareContextSscratchLib.inf > +++ b/RiscVPkg/Library/RiscVFirmwareContextSscratchLib/RiscVFirmwareContextSscratchLib.inf > @@ -1,9 +1,9 @@ > ## @file > -# Instance of OpebSBI Firmware Conext Library > +# Instance of OpenSBI Firmware Context Library > # > # This instance uses RISC-V Supervisor mode SCRATCH CSR > # > -# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.
> +# Copyright (c) 2021-2022, Hewlett Packard Enterprise Development LP. All rights reserved.
> # > # SPDX-License-Identifier: BSD-2-Clause-Patent > # > diff --git a/RiscVPkg/Library/RiscVFirmwareContextStvecLib/RiscVFirmwareContextStvecLib.inf b/RiscVPkg/Library/RiscVFirmwareContextStvecLib/RiscVFirmwareContextStvecLib.inf > index 9888cac81a..7c504c9c3c 100644 > --- a/RiscVPkg/Library/RiscVFirmwareContextStvecLib/RiscVFirmwareContextStvecLib.inf > +++ b/RiscVPkg/Library/RiscVFirmwareContextStvecLib/RiscVFirmwareContextStvecLib.inf > @@ -1,9 +1,9 @@ > ## @file > -# Instance of OpebSBI Firmware Conext Library > +# Instance of OpenSBI Firmware Context Library > # > -# This iinstance Supervisor mode STVEC CSR > +# This instance Supervisor mode STVEC CSR Should this be This instance "uses" ? > # > -# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.
> +# Copyright (c) 2021-2022, Hewlett Packard Enterprise Development LP. All rights reserved.
> # > # SPDX-License-Identifier: BSD-2-Clause-Patent > # > diff --git a/RiscVPkg/Include/Library/RiscVEdk2SbiLib.h b/RiscVPkg/Include/Library/RiscVEdk2SbiLib.h > index 88d957f002..6089137373 100644 > --- a/RiscVPkg/Include/Library/RiscVEdk2SbiLib.h > +++ b/RiscVPkg/Include/Library/RiscVEdk2SbiLib.h > @@ -1,7 +1,7 @@ > /** @file > Library to call the RISC-V SBI ecalls > > - Copyright (c) 2021, Hewlett Packard Development LP. All rights reserved.
> + Copyright (c) 2021-2022, Hewlett Packard Development LP. All rights reserved.
> > SPDX-License-Identifier: BSD-2-Clause-Patent > > @@ -54,7 +54,7 @@ SbiGetSpecVersion ( > /** > Get the SBI implementation ID > > - This ID is used to idenetify a specific SBI implementation in order to work > + This ID is used to identify a specific SBI implementation in order to work > around any quirks it might have. > > @param[out] ImplId The ID of the SBI implementation. > @@ -275,7 +275,7 @@ SbiRemoteFenceI ( > /** > Instructs the remote harts to execute one or more SFENCE.VMA instructions. > > - The SFENCE.VMA covers the range of virtual addresses between StartAaddr and Size. > + The SFENCE.VMA covers the range of virtual addresses between StartAddr and Size. > > The remote fence function acts as a full tlb flush if * StartAddr and size > are both 0 * size is equal to 2^XLEN-1 > @@ -305,7 +305,7 @@ SbiRemoteSfenceVma ( > /** > Instructs the remote harts to execute one or more SFENCE.VMA instructions. > > - The SFENCE.VMA covers the range of virtual addresses between StartAaddr and Size. > + The SFENCE.VMA covers the range of virtual addresses between StartAddr and Size. > Covers only the given ASID. > > The remote fence function acts as a full tlb flush if * StartAddr and size > @@ -337,7 +337,7 @@ SbiRemoteSfenceVmaAsid ( > /** > Instructs the remote harts to execute one or more SFENCE.GVMA instructions. > > - The SFENCE.GVMA covers the range of virtual addresses between StartAaddr and Size. > + The SFENCE.GVMA covers the range of virtual addresses between StartAddr and Size. > Covers only the given VMID. > This function call is only valid for harts implementing the hypervisor extension. > > @@ -373,7 +373,7 @@ SbiRemoteHfenceGvmaVmid ( > /** > Instructs the remote harts to execute one or more SFENCE.GVMA instructions. > > - The SFENCE.GVMA covers the range of virtual addresses between StartAaddr and Size. > + The SFENCE.GVMA covers the range of virtual addresses between StartAddr and Size. > This function call is only valid for harts implementing the hypervisor extension. > > The remote fence function acts as a full tlb flush if * StartAddr and size > @@ -407,7 +407,7 @@ SbiRemoteHfenceGvma ( > /** > Instructs the remote harts to execute one or more SFENCE.VVMA instructions. > > - The SFENCE.GVMA covers the range of virtual addresses between StartAaddr and Size. > + The SFENCE.GVMA covers the range of virtual addresses between StartAddr and Size. > Covers only the given ASID. > This function call is only valid for harts implementing the hypervisor extension. > > @@ -443,7 +443,7 @@ SbiRemoteHfenceVvmaAsid ( > /** > Instructs the remote harts to execute one or more SFENCE.VVMA instructions. > > - The SFENCE.GVMA covers the range of virtual addresses between StartAaddr and Size. > + The SFENCE.GVMA covers the range of virtual addresses between StartAddr and Size. > This function call is only valid for harts implementing the hypervisor extension. > > The remote fence function acts as a full tlb flush if * StartAddr and size > diff --git a/RiscVPkg/Include/OpensbiTypes.h b/RiscVPkg/Include/OpensbiTypes.h > index 8a6ea97708..ca7fc7a4ac 100644 > --- a/RiscVPkg/Include/OpensbiTypes.h > +++ b/RiscVPkg/Include/OpensbiTypes.h > @@ -1,7 +1,7 @@ > /** @file > - RISC-V OpesbSBI header file reference. > + RISC-V OpensbiSBI header file reference. Why opensbiSBI? Shouldn't this be just openSBI? > > - Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.
> + Copyright (c) 2020-2022, Hewlett Packard Enterprise Development LP. All rights reserved.
> > SPDX-License-Identifier: BSD-2-Clause-Patent > > diff --git a/RiscVPkg/Include/ProcessorSpecificHobData.h b/RiscVPkg/Include/ProcessorSpecificHobData.h > index 97285289f7..4b2a92e2f2 100644 > --- a/RiscVPkg/Include/ProcessorSpecificHobData.h > +++ b/RiscVPkg/Include/ProcessorSpecificHobData.h > @@ -29,7 +29,7 @@ typedef struct { > EFI_GUID CoreGuid; > VOID *Context; // The additional information of this core which > // built in PEI phase and carried to DXE phase. > - // The content is pocessor or platform specific. > + // The content is processor or platform specific. > SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA ProcessorSpecificData; > } RISC_V_PROCESSOR_SPECIFIC_HOB_DATA; > > diff --git a/RiscVPkg/Include/SmbiosProcessorSpecificData.h b/RiscVPkg/Include/SmbiosProcessorSpecificData.h > index 81e48cd068..85b8dcbe20 100644 > --- a/RiscVPkg/Include/SmbiosProcessorSpecificData.h > +++ b/RiscVPkg/Include/SmbiosProcessorSpecificData.h > @@ -1,9 +1,9 @@ > /** @file > Industry Standard Definitions of RISC-V Processor Specific data defined in > - below link for complaiant with SMBIOS Table Specification v3.3.0. > + below link for compliant with SMBIOS Table Specification v3.3.0. > https://github.com/riscv/riscv-smbios > > - Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.
> + Copyright (c) 2019-2022, Hewlett Packard Enterprise Development LP. All rights reserved.
> > SPDX-License-Identifier: BSD-2-Clause-Patent > > diff --git a/RiscVPkg/Library/RiscVEdk2SbiLib/RiscVEdk2SbiLib.c b/RiscVPkg/Library/RiscVEdk2SbiLib/RiscVEdk2SbiLib.c > index 319526ed8f..a51139542d 100644 > --- a/RiscVPkg/Library/RiscVEdk2SbiLib/RiscVEdk2SbiLib.c > +++ b/RiscVPkg/Library/RiscVEdk2SbiLib/RiscVEdk2SbiLib.c > @@ -15,7 +15,7 @@ > - SbiLegacyRemoteSfenceVmaAsid -> Use SbiRemoteSfenceVmaAsid > - SbiLegacyShutdown -> Wait for new System Reset extension > > - Copyright (c) 2021, Hewlett Packard Development LP. All rights reserved.
> + Copyright (c) 2021-2022, Hewlett Packard Development LP. All rights reserved.
> SPDX-License-Identifier: BSD-2-Clause-Patent > > @par Revision Reference: > @@ -173,7 +173,7 @@ SbiGetSpecVersion ( > /** > Get the SBI implementation ID > > - This ID is used to idenetify a specific SBI implementation in order to work > + This ID is used to identify a specific SBI implementation in order to work > around any quirks it might have. > > @param[out] ImplId The ID of the SBI implementation. > @@ -441,7 +441,7 @@ SbiRemoteFenceI ( > /** > Instructs the remote harts to execute one or more SFENCE.VMA instructions. > > - The SFENCE.VMA covers the range of virtual addresses between StartAaddr and Size. > + The SFENCE.VMA covers the range of virtual addresses between StartAddr and Size. > > The remote fence function acts as a full tlb flush if * StartAddr and size > are both 0 * size is equal to 2^XLEN-1 > @@ -483,7 +483,7 @@ SbiRemoteSfenceVma ( > /** > Instructs the remote harts to execute one or more SFENCE.VMA instructions. > > - The SFENCE.VMA covers the range of virtual addresses between StartAaddr and Size. > + The SFENCE.VMA covers the range of virtual addresses between StartAddr and Size. > Covers only the given ASID. > > The remote fence function acts as a full tlb flush if * StartAddr and size > @@ -528,7 +528,7 @@ SbiRemoteSfenceVmaAsid ( > /** > Instructs the remote harts to execute one or more SFENCE.GVMA instructions. > > - The SFENCE.GVMA covers the range of virtual addresses between StartAaddr and Size. > + The SFENCE.GVMA covers the range of virtual addresses between StartAddr and Size. > Covers only the given VMID. > This function call is only valid for harts implementing the hypervisor extension. > > @@ -577,7 +577,7 @@ SbiRemoteHFenceGvmaVmid ( > /** > Instructs the remote harts to execute one or more SFENCE.GVMA instructions. > > - The SFENCE.GVMA covers the range of virtual addresses between StartAaddr and Size. > + The SFENCE.GVMA covers the range of virtual addresses between StartAddr and Size. > This function call is only valid for harts implementing the hypervisor extension. > > The remote fence function acts as a full tlb flush if * StartAddr and size > @@ -623,7 +623,7 @@ SbiRemoteHFenceGvma ( > /** > Instructs the remote harts to execute one or more SFENCE.VVMA instructions. > > - The SFENCE.GVMA covers the range of virtual addresses between StartAaddr and Size. > + The SFENCE.GVMA covers the range of virtual addresses between StartAddr and Size. > Covers only the given ASID. > This function call is only valid for harts implementing the hypervisor extension. > > @@ -672,7 +672,7 @@ SbiRemoteHFenceVvmaAsid ( > /** > Instructs the remote harts to execute one or more SFENCE.VVMA instructions. > > - The SFENCE.GVMA covers the range of virtual addresses between StartAaddr and Size. > + The SFENCE.GVMA covers the range of virtual addresses between StartAddr and Size. > This function call is only valid for harts implementing the hypervisor extension. > > The remote fence function acts as a full tlb flush if * StartAddr and size > diff --git a/RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerLib.c b/RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerLib.c > index a9316ae758..43130336f3 100644 > --- a/RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerLib.c > +++ b/RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerLib.c > @@ -1,7 +1,7 @@ > /** @file > - RISC-V Exception Handler library implementition. > + RISC-V Exception Handler library implementation. > > - Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.
> + Copyright (c) 2016 - 2022, Hewlett Packard Enterprise Development LP. All rights reserved.
> > SPDX-License-Identifier: BSD-2-Clause-Patent > > @@ -186,7 +186,7 @@ CpuExceptionHandlerLibConstructor ( > ) > { > // > - // Set Superviosr mode trap handler. > + // Set Supervisor mode trap handler. > // > csr_write(CSR_STVEC, SupervisorModeTrap); > > diff --git a/RiscVPkg/Library/RiscVFirmwareContextSbiLib/RiscVFirmwareContextSbiLib.c b/RiscVPkg/Library/RiscVFirmwareContextSbiLib/RiscVFirmwareContextSbiLib.c > index 6125618eaf..a2a18d3eb7 100644 > --- a/RiscVPkg/Library/RiscVFirmwareContextSbiLib/RiscVFirmwareContextSbiLib.c > +++ b/RiscVPkg/Library/RiscVFirmwareContextSbiLib/RiscVFirmwareContextSbiLib.c > @@ -1,8 +1,8 @@ > /** @file > - This iinstance uses RISC-V OpenSBI Firmware Extension SBI to > + This instance uses RISC-V OpenSBI Firmware Extension SBI to > get the pointer of firmware context. > > - Copyright (c) 2021 Hewlett Packard Enterprise Development LP. All rights reserved.
> + Copyright (c) 2021-2022 Hewlett Packard Enterprise Development LP. All rights reserved.
> > SPDX-License-Identifier: BSD-2-Clause-Patent > **/ > diff --git a/RiscVPkg/Library/RiscVFirmwareContextStvecLib/RiscVFirmwareContextStvecLib.c b/RiscVPkg/Library/RiscVFirmwareContextStvecLib/RiscVFirmwareContextStvecLib.c > index 7d1675355a..d08b51d3d9 100644 > --- a/RiscVPkg/Library/RiscVFirmwareContextStvecLib/RiscVFirmwareContextStvecLib.c > +++ b/RiscVPkg/Library/RiscVFirmwareContextStvecLib/RiscVFirmwareContextStvecLib.c > @@ -1,8 +1,8 @@ > /** @file > - This instance uses This iinstance Supervisor mode STVEC CSR to > + This instance uses This instance Supervisor mode STVEC CSR to Remove extra "This instance" > get/set the pointer of firmware context. > > - Copyright (c) 2021 Hewlett Packard Enterprise Development LP. All rights reserved.
> + Copyright (c) 2021-2022 Hewlett Packard Enterprise Development LP. All rights reserved.
> > SPDX-License-Identifier: BSD-2-Clause-Patent > **/ > -- > 2.31.1 >