* [PATCH v2 1/6] MdeModulePkg: Replace Opcode with the corresponding instructions.
@ 2022-01-10 15:12 Jason Lou
2022-01-10 15:12 ` [PATCH v2 2/6] MdePkg: " Jason Lou
` (5 more replies)
0 siblings, 6 replies; 12+ messages in thread
From: Jason Lou @ 2022-01-10 15:12 UTC (permalink / raw)
To: devel; +Cc: Jason, Ray Ni, Dandan Bi, Liming Gao
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3790
Replace Opcode with the corresponding instructions.
The code changes have been verified with CompareBuild.py tool, which
can be used to compare the results of two different EDK II builds to
determine if they generate the same binaries.
(tool link: https://github.com/mdkinney/edk2/tree/sandbox/CompareBuild)
Signed-off-by: Jason Lou <yun.lou@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Dandan Bi <dandan.bi@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
---
MdeModulePkg/Universal/DebugSupportDxe/Ia32/AsmFuncs.nasm | 20 +++----------------
MdeModulePkg/Universal/DebugSupportDxe/X64/AsmFuncs.nasm | 21 +++-----------------
2 files changed, 6 insertions(+), 35 deletions(-)
diff --git a/MdeModulePkg/Universal/DebugSupportDxe/Ia32/AsmFuncs.nasm b/MdeModulePkg/Universal/DebugSupportDxe/Ia32/AsmFuncs.nasm
index cfb418748f..07fc912fe8 100644
--- a/MdeModulePkg/Universal/DebugSupportDxe/Ia32/AsmFuncs.nasm
+++ b/MdeModulePkg/Universal/DebugSupportDxe/Ia32/AsmFuncs.nasm
@@ -1,7 +1,7 @@
;/** @file
; Low leve IA32 specific debug support functions.
;
-; Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>
+; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR>
; SPDX-License-Identifier: BSD-2-Clause-Patent
;
;**/
@@ -26,20 +26,6 @@
%define FXSTOR_FLAG 0x1000000 ; bit cpuid 24 of feature flags
-;; The FXSTOR and FXRSTOR commands are used for saving and restoring the x87,
-;; MMX, SSE, SSE2, etc registers. The initialization of the debugsupport driver
-;; MUST check the CPUID feature flags to see that these instructions are available
-;; and fail to init if they are not.
-
-;; fxstor [edi]
-%macro FXSTOR_EDI 0
- db 0xf, 0xae, 00000111y ; mod = 00, reg/op = 000, r/m = 111 = [edi]
-%endmacro
-
-;; fxrstor [esi]
-%macro FXRSTOR_ESI 0
- db 0xf, 0xae, 00001110y ; mod = 00, reg/op = 001, r/m = 110 = [esi]
-%endmacro
SECTION .data
global ASM_PFX(OrigVector)
@@ -348,7 +334,7 @@ ExtraPushDone:
; IMPORTANT!! The debug stack has been carefully constructed to
; insure that esp and edi are 16 byte aligned when we get here.
; They MUST be. If they are not, a GP fault will occur.
- FXSTOR_EDI
+ fxsave [edi]
;; UEFI calling convention for IA32 requires that Direction flag in EFLAGs is clear
cld
@@ -372,7 +358,7 @@ ExtraPushDone:
;; FX_SAVE_STATE_IA32 FxSaveState;
mov esi, esp
- FXRSTOR_ESI
+ fxrstor [esi]
add esp, 512
;; UINT32 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
diff --git a/MdeModulePkg/Universal/DebugSupportDxe/X64/AsmFuncs.nasm b/MdeModulePkg/Universal/DebugSupportDxe/X64/AsmFuncs.nasm
index 9cc38a3128..c6c5e49189 100644
--- a/MdeModulePkg/Universal/DebugSupportDxe/X64/AsmFuncs.nasm
+++ b/MdeModulePkg/Universal/DebugSupportDxe/X64/AsmFuncs.nasm
@@ -1,7 +1,7 @@
;/** @file
; Low level x64 routines used by the debug support driver.
;
-; Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>
+; Copyright (c) 2007 - 2022, Intel Corporation. All rights reserved.<BR>
; SPDX-License-Identifier: BSD-2-Clause-Patent
;
;**/
@@ -26,21 +26,6 @@
%define FXSTOR_FLAG 0x1000000 ; bit cpuid 24 of feature flags
-;; The FXSTOR and FXRSTOR commands are used for saving and restoring the x87,
-;; MMX, SSE, SSE2, etc registers. The initialization of the debugsupport driver
-;; MUST check the CPUID feature flags to see that these instructions are available
-;; and fail to init if they are not.
-
-;; fxstor [rdi]
-%macro FXSTOR_RDI 0
- db 0xf, 0xae, 00000111y ; mod = 00, reg/op = 000, r/m = 111 = [rdi]
-%endmacro
-
-;; fxrstor [rsi]
-%macro FXRSTOR_RSI 0
- db 0xf, 0xae, 00001110y ; mod = 00, reg/op = 001, r/m = 110 = [rsi]
-%endmacro
-
SECTION .data
global ASM_PFX(OrigVector)
@@ -381,7 +366,7 @@ ExtraPushDone:
; IMPORTANT!! The debug stack has been carefully constructed to
; insure that rsp and rdi are 16 byte aligned when we get here.
; They MUST be. If they are not, a GP fault will occur.
- FXSTOR_RDI
+ fxsave [rdi]
;; UEFI calling convention for x64 requires that Direction flag in EFLAGs is clear
cld
@@ -404,7 +389,7 @@ ExtraPushDone:
;; FX_SAVE_STATE_X64 FxSaveState;
mov rsi, rsp
- FXRSTOR_RSI
+ fxrstor [rsi]
add rsp, 512
;; UINT64 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
--
2.28.0.windows.1
^ permalink raw reply related [flat|nested] 12+ messages in thread* [PATCH v2 2/6] MdePkg: Replace Opcode with the corresponding instructions. 2022-01-10 15:12 [PATCH v2 1/6] MdeModulePkg: Replace Opcode with the corresponding instructions Jason Lou @ 2022-01-10 15:12 ` Jason Lou 2022-01-11 0:55 ` 回复: [edk2-devel] " gaoliming 2022-01-10 15:12 ` [PATCH v2 3/6] SourceLevelDebugPkg: " Jason Lou ` (4 subsequent siblings) 5 siblings, 1 reply; 12+ messages in thread From: Jason Lou @ 2022-01-10 15:12 UTC (permalink / raw) To: devel; +Cc: Jason, Michael D Kinney, Liming Gao, Zhiguang Liu REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3790 Replace Opcode with the corresponding instructions. The code changes have been verified with CompareBuild.py tool, which can be used to compare the results of two different EDK II builds to determine if they generate the same binaries. (tool link: https://github.com/mdkinney/edk2/tree/sandbox/CompareBuild) Signed-off-by: Jason Lou <yun.lou@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> --- MdePkg/Library/BaseLib/Ia32/EnablePaging64.nasm | 20 ++++++++------------ MdePkg/Library/BaseLib/Ia32/LongJump.nasm | 6 +++--- MdePkg/Library/BaseLib/Ia32/Monitor.nasm | 4 ++-- MdePkg/Library/BaseLib/Ia32/Mwait.nasm | 4 ++-- MdePkg/Library/BaseLib/Ia32/RdRand.nasm | 13 +++++-------- MdePkg/Library/BaseLib/Ia32/ReadDr4.nasm | 6 +++--- MdePkg/Library/BaseLib/Ia32/ReadDr5.nasm | 6 +++--- MdePkg/Library/BaseLib/Ia32/SetJump.nasm | 6 +++--- MdePkg/Library/BaseLib/Ia32/WriteDr4.nasm | 6 +++--- MdePkg/Library/BaseLib/Ia32/WriteDr5.nasm | 6 +++--- MdePkg/Library/BaseLib/X64/DisablePaging64.nasm | 5 ++--- MdePkg/Library/BaseLib/X64/LongJump.nasm | 6 +++--- MdePkg/Library/BaseLib/X64/Monitor.nasm | 4 ++-- MdePkg/Library/BaseLib/X64/Mwait.nasm | 4 ++-- MdePkg/Library/BaseLib/X64/RdRand.nasm | 11 ++++------- MdePkg/Library/BaseLib/X64/ReadDr4.nasm | 4 ++-- MdePkg/Library/BaseLib/X64/ReadDr5.nasm | 4 ++-- MdePkg/Library/BaseLib/X64/ReadMm0.nasm | 7 ++----- MdePkg/Library/BaseLib/X64/ReadMm1.nasm | 7 ++----- MdePkg/Library/BaseLib/X64/ReadMm2.nasm | 7 ++----- MdePkg/Library/BaseLib/X64/ReadMm3.nasm | 7 ++----- MdePkg/Library/BaseLib/X64/ReadMm4.nasm | 7 ++----- MdePkg/Library/BaseLib/X64/ReadMm5.nasm | 7 ++----- MdePkg/Library/BaseLib/X64/ReadMm6.nasm | 7 ++----- MdePkg/Library/BaseLib/X64/ReadMm7.nasm | 7 ++----- MdePkg/Library/BaseLib/X64/SetJump.nasm | 6 +++--- MdePkg/Library/BaseLib/X64/WriteDr4.nasm | 4 ++-- MdePkg/Library/BaseLib/X64/WriteDr5.nasm | 4 ++-- MdePkg/Library/BaseLib/X64/WriteMm0.nasm | 7 ++----- MdePkg/Library/BaseLib/X64/WriteMm1.nasm | 7 ++----- MdePkg/Library/BaseLib/X64/WriteMm2.nasm | 7 ++----- MdePkg/Library/BaseLib/X64/WriteMm3.nasm | 7 ++----- MdePkg/Library/BaseLib/X64/WriteMm4.nasm | 7 ++----- MdePkg/Library/BaseLib/X64/WriteMm5.nasm | 7 ++----- MdePkg/Library/BaseLib/X64/WriteMm6.nasm | 7 ++----- MdePkg/Library/BaseLib/X64/WriteMm7.nasm | 7 ++----- MdePkg/Library/BaseMemoryLibMmx/X64/CopyMem.nasm | 10 +++++----- MdePkg/Library/BaseMemoryLibMmx/X64/SetMem.nasm | 8 ++++---- MdePkg/Library/BaseMemoryLibMmx/X64/SetMem16.nasm | 8 ++++---- MdePkg/Library/BaseMemoryLibMmx/X64/SetMem32.nasm | 10 +++++----- MdePkg/Library/BaseMemoryLibMmx/X64/SetMem64.nasm | 6 +++--- MdePkg/Library/BaseMemoryLibMmx/X64/ZeroMem.nasm | 8 ++++---- 42 files changed, 116 insertions(+), 175 deletions(-) diff --git a/MdePkg/Library/BaseLib/Ia32/EnablePaging64.nasm b/MdePkg/Library/BaseLib/Ia32/EnablePaging64.nasm index 544e3c3892..ef11458077 100644 --- a/MdePkg/Library/BaseLib/Ia32/EnablePaging64.nasm +++ b/MdePkg/Library/BaseLib/Ia32/EnablePaging64.nasm @@ -1,6 +1,6 @@ ;------------------------------------------------------------------------------ ; -; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR> +; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR> ; SPDX-License-Identifier: BSD-2-Clause-Patent ; ; Module Name: @@ -44,16 +44,12 @@ ASM_PFX(InternalX86EnablePaging64): mov cr0, eax ; enable paging retf ; topmost 2 dwords hold the address .0: - DB 0x67, 0x48 ; 32-bit address size, 64-bit operand size - mov ebx, [esp] ; mov rbx, [esp] - DB 0x67, 0x48 - mov ecx, [esp + 8] ; mov rcx, [esp + 8] - DB 0x67, 0x48 - mov edx, [esp + 0x10] ; mov rdx, [esp + 10h] - DB 0x67, 0x48 - mov esp, [esp + 0x18] ; mov rsp, [esp + 18h] - DB 0x48 - add esp, -0x20 ; add rsp, -20h - call ebx ; call rbx +BITS 64 + mov rbx, [esp] + mov rcx, [esp + 8] + mov rdx, [esp + 0x10] + mov rsp, [esp + 0x18] + add rsp, -0x20 + call rbx hlt ; no one should get here diff --git a/MdePkg/Library/BaseLib/Ia32/LongJump.nasm b/MdePkg/Library/BaseLib/Ia32/LongJump.nasm index f94d10f806..6c13dfe307 100644 --- a/MdePkg/Library/BaseLib/Ia32/LongJump.nasm +++ b/MdePkg/Library/BaseLib/Ia32/LongJump.nasm @@ -1,6 +1,6 @@ ;------------------------------------------------------------------------------ ; -; Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR> +; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR> ; SPDX-License-Identifier: BSD-2-Clause-Patent ; ; Module Name: @@ -39,12 +39,12 @@ ASM_PFX(InternalLongJump): mov edx, [esp + 4] ; edx = JumpBuffer mov edx, [edx + 24] ; edx = target SSP - READSSP_EAX + rdsspd eax sub edx, eax ; edx = delta mov eax, edx ; eax = delta shr eax, 2 ; eax = delta/sizeof(UINT32) - INCSSP_EAX + incsspd eax CetDone: diff --git a/MdePkg/Library/BaseLib/Ia32/Monitor.nasm b/MdePkg/Library/BaseLib/Ia32/Monitor.nasm index 28dc0ba70a..70dbe66e27 100644 --- a/MdePkg/Library/BaseLib/Ia32/Monitor.nasm +++ b/MdePkg/Library/BaseLib/Ia32/Monitor.nasm @@ -1,6 +1,6 @@ ;------------------------------------------------------------------------------ ; -; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR> +; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR> ; SPDX-License-Identifier: BSD-2-Clause-Patent ; ; Module Name: @@ -31,6 +31,6 @@ ASM_PFX(AsmMonitor): mov eax, [esp + 4] mov ecx, [esp + 8] mov edx, [esp + 12] - DB 0xf, 1, 0xc8 ; monitor + monitor ret diff --git a/MdePkg/Library/BaseLib/Ia32/Mwait.nasm b/MdePkg/Library/BaseLib/Ia32/Mwait.nasm index 3956940cab..2d36a97df6 100644 --- a/MdePkg/Library/BaseLib/Ia32/Mwait.nasm +++ b/MdePkg/Library/BaseLib/Ia32/Mwait.nasm @@ -1,6 +1,6 @@ ;------------------------------------------------------------------------------ ; -; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR> +; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR> ; SPDX-License-Identifier: BSD-2-Clause-Patent ; ; Module Name: @@ -29,6 +29,6 @@ global ASM_PFX(AsmMwait) ASM_PFX(AsmMwait): mov eax, [esp + 4] mov ecx, [esp + 8] - DB 0xf, 1, 0xc9 ; mwait + mwait ret diff --git a/MdePkg/Library/BaseLib/Ia32/RdRand.nasm b/MdePkg/Library/BaseLib/Ia32/RdRand.nasm index e12b8e9611..d818b6ef55 100644 --- a/MdePkg/Library/BaseLib/Ia32/RdRand.nasm +++ b/MdePkg/Library/BaseLib/Ia32/RdRand.nasm @@ -1,6 +1,6 @@ ;------------------------------------------------------------------------------ ; -; Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR> +; Copyright (c) 2015 - 2022, Intel Corporation. All rights reserved.<BR> ; SPDX-License-Identifier: BSD-2-Clause-Patent ; ; Module Name: @@ -25,9 +25,8 @@ SECTION .text ;------------------------------------------------------------------------------ global ASM_PFX(InternalX86RdRand16) ASM_PFX(InternalX86RdRand16): - ; rdrand ax ; generate a 16 bit RN into ax + rdrand eax ; generate a 16 bit RN into ax ; CF=1 if RN generated ok, otherwise CF=0 - db 0xf, 0xc7, 0xf0 ; rdrand r16: "0f c7 /6 ModRM:r/m(w)" jc rn16_ok ; jmp if CF=1 xor eax, eax ; reg=0 if CF=0 ret ; return with failure status @@ -45,9 +44,8 @@ rn16_ok: ;------------------------------------------------------------------------------ global ASM_PFX(InternalX86RdRand32) ASM_PFX(InternalX86RdRand32): - ; rdrand eax ; generate a 32 bit RN into eax + rdrand eax ; generate a 32 bit RN into eax ; CF=1 if RN generated ok, otherwise CF=0 - db 0xf, 0xc7, 0xf0 ; rdrand r32: "0f c7 /6 ModRM:r/m(w)" jc rn32_ok ; jmp if CF=1 xor eax, eax ; reg=0 if CF=0 ret ; return with failure status @@ -65,14 +63,13 @@ rn32_ok: ;------------------------------------------------------------------------------ global ASM_PFX(InternalX86RdRand64) ASM_PFX(InternalX86RdRand64): - ; rdrand eax ; generate a 32 bit RN into eax + rdrand eax ; generate a 32 bit RN into eax ; CF=1 if RN generated ok, otherwise CF=0 - db 0xf, 0xc7, 0xf0 ; rdrand r32: "0f c7 /6 ModRM:r/m(w)" jnc rn64_ret ; jmp if CF=0 mov edx, dword [esp + 4] mov [edx], eax - db 0xf, 0xc7, 0xf0 ; generate another 32 bit RN + rdrand eax ; generate another 32 bit RN jnc rn64_ret ; jmp if CF=0 mov [edx + 4], eax diff --git a/MdePkg/Library/BaseLib/Ia32/ReadDr4.nasm b/MdePkg/Library/BaseLib/Ia32/ReadDr4.nasm index 81c681de34..1c312b670d 100644 --- a/MdePkg/Library/BaseLib/Ia32/ReadDr4.nasm +++ b/MdePkg/Library/BaseLib/Ia32/ReadDr4.nasm @@ -1,6 +1,6 @@ ;------------------------------------------------------------------------------ ; -; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR> +; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR> ; SPDX-License-Identifier: BSD-2-Clause-Patent ; ; Module Name: @@ -31,8 +31,8 @@ ASM_PFX(AsmReadDr4): ; this register will cause a #UD exception. ; ; MS assembler doesn't support this instruction since no one would use it - ; under normal circustances. Here opcode is used. + ; under normal circustances. ; - DB 0xf, 0x21, 0xe0 + mov eax, dr4 ret diff --git a/MdePkg/Library/BaseLib/Ia32/ReadDr5.nasm b/MdePkg/Library/BaseLib/Ia32/ReadDr5.nasm index e2deacb832..07a1b44a00 100644 --- a/MdePkg/Library/BaseLib/Ia32/ReadDr5.nasm +++ b/MdePkg/Library/BaseLib/Ia32/ReadDr5.nasm @@ -1,6 +1,6 @@ ;------------------------------------------------------------------------------ ; -; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR> +; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR> ; SPDX-License-Identifier: BSD-2-Clause-Patent ; ; Module Name: @@ -31,8 +31,8 @@ ASM_PFX(AsmReadDr5): ; this register will cause a #UD exception. ; ; MS assembler doesn't support this instruction since no one would use it - ; under normal circustances. Here opcode is used. + ; under normal circustances. ; - DB 0xf, 0x21, 0xe8 + mov eax, dr5 ret diff --git a/MdePkg/Library/BaseLib/Ia32/SetJump.nasm b/MdePkg/Library/BaseLib/Ia32/SetJump.nasm index 364613b5f9..2577373241 100644 --- a/MdePkg/Library/BaseLib/Ia32/SetJump.nasm +++ b/MdePkg/Library/BaseLib/Ia32/SetJump.nasm @@ -1,6 +1,6 @@ ;------------------------------------------------------------------------------ ; -; Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR> +; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR> ; SPDX-License-Identifier: BSD-2-Clause-Patent ; ; Module Name: @@ -46,8 +46,8 @@ ASM_PFX(SetJump): jnc CetDone mov eax, 1 - INCSSP_EAX ; to read original SSP - READSSP_EAX + incsspd eax ; to read original SSP + rdsspd eax mov [edx + 0x24], eax ; save SSP CetDone: diff --git a/MdePkg/Library/BaseLib/Ia32/WriteDr4.nasm b/MdePkg/Library/BaseLib/Ia32/WriteDr4.nasm index 0d23fca111..b8479b39f7 100644 --- a/MdePkg/Library/BaseLib/Ia32/WriteDr4.nasm +++ b/MdePkg/Library/BaseLib/Ia32/WriteDr4.nasm @@ -1,6 +1,6 @@ ;------------------------------------------------------------------------------ ; -; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR> +; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR> ; SPDX-License-Identifier: BSD-2-Clause-Patent ; ; Module Name: @@ -32,8 +32,8 @@ ASM_PFX(AsmWriteDr4): ; this register will cause a #UD exception. ; ; MS assembler doesn't support this instruction since no one would use it - ; under normal circustances. Here opcode is used. + ; under normal circustances. ; - DB 0xf, 0x23, 0xe0 + mov dr4, eax ret diff --git a/MdePkg/Library/BaseLib/Ia32/WriteDr5.nasm b/MdePkg/Library/BaseLib/Ia32/WriteDr5.nasm index bc5f424b8d..3545561025 100644 --- a/MdePkg/Library/BaseLib/Ia32/WriteDr5.nasm +++ b/MdePkg/Library/BaseLib/Ia32/WriteDr5.nasm @@ -1,6 +1,6 @@ ;------------------------------------------------------------------------------ ; -; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR> +; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR> ; SPDX-License-Identifier: BSD-2-Clause-Patent ; ; Module Name: @@ -32,8 +32,8 @@ ASM_PFX(AsmWriteDr5): ; this register will cause a #UD exception. ; ; MS assembler doesn't support this instruction since no one would use it - ; under normal circustances. Here opcode is used. + ; under normal circustances. ; - DB 0xf, 0x23, 0xe8 + mov dr5, eax ret diff --git a/MdePkg/Library/BaseLib/X64/DisablePaging64.nasm b/MdePkg/Library/BaseLib/X64/DisablePaging64.nasm index c76ed1a76c..200c408d9a 100644 --- a/MdePkg/Library/BaseLib/X64/DisablePaging64.nasm +++ b/MdePkg/Library/BaseLib/X64/DisablePaging64.nasm @@ -1,6 +1,6 @@ ;------------------------------------------------------------------------------ ; -; Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR> +; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR> ; SPDX-License-Identifier: BSD-2-Clause-Patent ; ; Module Name: @@ -51,8 +51,7 @@ ASM_PFX(InternalX86DisablePaging64): sub eax, 4 ; eax <- One slot below transition code on the stack push rcx ; push Cs to stack push r10 ; push address of tansition code on stack - DB 0x48 ; prefix to composite "retq" with next "retf" - retf ; Use far return to load CS register from stack + retfq ; Start of transition code .0: diff --git a/MdePkg/Library/BaseLib/X64/LongJump.nasm b/MdePkg/Library/BaseLib/X64/LongJump.nasm index 59f7092169..2002f65cba 100644 --- a/MdePkg/Library/BaseLib/X64/LongJump.nasm +++ b/MdePkg/Library/BaseLib/X64/LongJump.nasm @@ -1,6 +1,6 @@ ;------------------------------------------------------------------------------ ; -; Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR> +; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR> ; SPDX-License-Identifier: BSD-2-Clause-Patent ; ; Module Name: @@ -41,12 +41,12 @@ ASM_PFX(InternalLongJump): push rdx ; save rdx mov rdx, [rcx + 0xF8] ; rdx = target SSP - READSSP_RAX + rdsspq rax sub rdx, rax ; rdx = delta mov rax, rdx ; rax = delta shr rax, 3 ; rax = delta/sizeof(UINT64) - INCSSP_RAX + incsspq rax pop rdx ; restore rdx CetDone: diff --git a/MdePkg/Library/BaseLib/X64/Monitor.nasm b/MdePkg/Library/BaseLib/X64/Monitor.nasm index e1ccb83a85..210037d402 100644 --- a/MdePkg/Library/BaseLib/X64/Monitor.nasm +++ b/MdePkg/Library/BaseLib/X64/Monitor.nasm @@ -1,6 +1,6 @@ ;------------------------------------------------------------------------------ ; -; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR> +; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR> ; SPDX-License-Identifier: BSD-2-Clause-Patent ; ; Module Name: @@ -32,6 +32,6 @@ ASM_PFX(AsmMonitor): mov eax, ecx mov ecx, edx mov edx, r8d - DB 0xf, 1, 0xc8 ; monitor + monitor ret diff --git a/MdePkg/Library/BaseLib/X64/Mwait.nasm b/MdePkg/Library/BaseLib/X64/Mwait.nasm index 83fc895491..c8ad59588b 100644 --- a/MdePkg/Library/BaseLib/X64/Mwait.nasm +++ b/MdePkg/Library/BaseLib/X64/Mwait.nasm @@ -1,6 +1,6 @@ ;------------------------------------------------------------------------------ ; -; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR> +; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR> ; SPDX-License-Identifier: BSD-2-Clause-Patent ; ; Module Name: @@ -30,6 +30,6 @@ global ASM_PFX(AsmMwait) ASM_PFX(AsmMwait): mov eax, ecx mov ecx, edx - DB 0xf, 1, 0xc9 ; mwait + mwait ret diff --git a/MdePkg/Library/BaseLib/X64/RdRand.nasm b/MdePkg/Library/BaseLib/X64/RdRand.nasm index 7e7fe99670..73479be8d3 100644 --- a/MdePkg/Library/BaseLib/X64/RdRand.nasm +++ b/MdePkg/Library/BaseLib/X64/RdRand.nasm @@ -1,6 +1,6 @@ ;------------------------------------------------------------------------------ ; -; Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR> +; Copyright (c) 2015 - 2022, Intel Corporation. All rights reserved.<BR> ; SPDX-License-Identifier: BSD-2-Clause-Patent ; ; Module Name: @@ -26,9 +26,8 @@ ;------------------------------------------------------------------------------ global ASM_PFX(InternalX86RdRand16) ASM_PFX(InternalX86RdRand16): - ; rdrand ax ; generate a 16 bit RN into eax, + rdrand eax ; generate a 16 bit RN into eax, ; CF=1 if RN generated ok, otherwise CF=0 - db 0xf, 0xc7, 0xf0 ; rdrand r16: "0f c7 /6 ModRM:r/m(w)" jc rn16_ok ; jmp if CF=1 xor rax, rax ; reg=0 if CF=0 ret ; return with failure status @@ -45,9 +44,8 @@ rn16_ok: ;------------------------------------------------------------------------------ global ASM_PFX(InternalX86RdRand32) ASM_PFX(InternalX86RdRand32): - ; rdrand eax ; generate a 32 bit RN into eax, + rdrand eax ; generate a 32 bit RN into eax, ; CF=1 if RN generated ok, otherwise CF=0 - db 0xf, 0xc7, 0xf0 ; rdrand r32: "0f c7 /6 ModRM:r/m(w)" jc rn32_ok ; jmp if CF=1 xor rax, rax ; reg=0 if CF=0 ret ; return with failure status @@ -64,9 +62,8 @@ rn32_ok: ;------------------------------------------------------------------------------ global ASM_PFX(InternalX86RdRand64) ASM_PFX(InternalX86RdRand64): - ; rdrand rax ; generate a 64 bit RN into rax, + rdrand rax ; generate a 64 bit RN into rax, ; CF=1 if RN generated ok, otherwise CF=0 - db 0x48, 0xf, 0xc7, 0xf0 ; rdrand r64: "REX.W + 0f c7 /6 ModRM:r/m(w)" jc rn64_ok ; jmp if CF=1 xor rax, rax ; reg=0 if CF=0 ret ; return with failure status diff --git a/MdePkg/Library/BaseLib/X64/ReadDr4.nasm b/MdePkg/Library/BaseLib/X64/ReadDr4.nasm index 82c0a9a588..90b2172cee 100644 --- a/MdePkg/Library/BaseLib/X64/ReadDr4.nasm +++ b/MdePkg/Library/BaseLib/X64/ReadDr4.nasm @@ -1,6 +1,6 @@ ;------------------------------------------------------------------------------ ; -; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR> +; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR> ; SPDX-License-Identifier: BSD-2-Clause-Patent ; ; Module Name: @@ -31,6 +31,6 @@ ASM_PFX(AsmReadDr4): ; There's no obvious reason to access this register, since it's aliased to ; DR7 when DE=0 or an exception generated when DE=1 ; - DB 0xf, 0x21, 0xe0 + mov rax, dr4 ret diff --git a/MdePkg/Library/BaseLib/X64/ReadDr5.nasm b/MdePkg/Library/BaseLib/X64/ReadDr5.nasm index c309c66dfe..c1143f4498 100644 --- a/MdePkg/Library/BaseLib/X64/ReadDr5.nasm +++ b/MdePkg/Library/BaseLib/X64/ReadDr5.nasm @@ -1,6 +1,6 @@ ;------------------------------------------------------------------------------ ; -; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR> +; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR> ; SPDX-License-Identifier: BSD-2-Clause-Patent ; ; Module Name: @@ -31,6 +31,6 @@ ASM_PFX(AsmReadDr5): ; There's no obvious reason to access this register, since it's aliased to ; DR7 when DE=0 or an exception generated when DE=1 ; - DB 0xf, 0x21, 0xe8 + mov rax, dr5 ret diff --git a/MdePkg/Library/BaseLib/X64/ReadMm0.nasm b/MdePkg/Library/BaseLib/X64/ReadMm0.nasm index 615721b6aa..e64b2c7882 100644 --- a/MdePkg/Library/BaseLib/X64/ReadMm0.nasm +++ b/MdePkg/Library/BaseLib/X64/ReadMm0.nasm @@ -1,6 +1,6 @@ ;------------------------------------------------------------------------------ ; -; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR> +; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR> ; SPDX-License-Identifier: BSD-2-Clause-Patent ; ; Module Name: @@ -27,9 +27,6 @@ ;------------------------------------------------------------------------------ global ASM_PFX(AsmReadMm0) ASM_PFX(AsmReadMm0): - ; - ; 64-bit MASM doesn't support MMX instructions, so use opcode here - ; - DB 0x48, 0xf, 0x7e, 0xc0 + movq rax, mm0 ret diff --git a/MdePkg/Library/BaseLib/X64/ReadMm1.nasm b/MdePkg/Library/BaseLib/X64/ReadMm1.nasm index 7b27393490..bec3c71207 100644 --- a/MdePkg/Library/BaseLib/X64/ReadMm1.nasm +++ b/MdePkg/Library/BaseLib/X64/ReadMm1.nasm @@ -1,6 +1,6 @@ ;------------------------------------------------------------------------------ ; -; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR> +; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR> ; SPDX-License-Identifier: BSD-2-Clause-Patent ; ; Module Name: @@ -27,9 +27,6 @@ ;------------------------------------------------------------------------------ global ASM_PFX(AsmReadMm1) ASM_PFX(AsmReadMm1): - ; - ; 64-bit MASM doesn't support MMX instructions, so use opcode here - ; - DB 0x48, 0xf, 0x7e, 0xc8 + movq rax, mm1 ret diff --git a/MdePkg/Library/BaseLib/X64/ReadMm2.nasm b/MdePkg/Library/BaseLib/X64/ReadMm2.nasm index c654b91a7a..4c880697cb 100644 --- a/MdePkg/Library/BaseLib/X64/ReadMm2.nasm +++ b/MdePkg/Library/BaseLib/X64/ReadMm2.nasm @@ -1,6 +1,6 @@ ;------------------------------------------------------------------------------ ; -; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR> +; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR> ; SPDX-License-Identifier: BSD-2-Clause-Patent ; ; Module Name: @@ -27,9 +27,6 @@ ;------------------------------------------------------------------------------ global ASM_PFX(AsmReadMm2) ASM_PFX(AsmReadMm2): - ; - ; 64-bit MASM doesn't support MMX instructions, so use opcode here - ; - DB 0x48, 0xf, 0x7e, 0xd0 + movq rax, mm2 ret diff --git a/MdePkg/Library/BaseLib/X64/ReadMm3.nasm b/MdePkg/Library/BaseLib/X64/ReadMm3.nasm index 88d51c0781..cf81e5a7ab 100644 --- a/MdePkg/Library/BaseLib/X64/ReadMm3.nasm +++ b/MdePkg/Library/BaseLib/X64/ReadMm3.nasm @@ -1,6 +1,6 @@ ;------------------------------------------------------------------------------ ; -; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR> +; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR> ; SPDX-License-Identifier: BSD-2-Clause-Patent ; ; Module Name: @@ -27,9 +27,6 @@ ;------------------------------------------------------------------------------ global ASM_PFX(AsmReadMm3) ASM_PFX(AsmReadMm3): - ; - ; 64-bit MASM doesn't support MMX instructions, so use opcode here - ; - DB 0x48, 0xf, 0x7e, 0xd8 + movq rax, mm3 ret diff --git a/MdePkg/Library/BaseLib/X64/ReadMm4.nasm b/MdePkg/Library/BaseLib/X64/ReadMm4.nasm index 4252d20bb1..17ba364e32 100644 --- a/MdePkg/Library/BaseLib/X64/ReadMm4.nasm +++ b/MdePkg/Library/BaseLib/X64/ReadMm4.nasm @@ -1,6 +1,6 @@ ;------------------------------------------------------------------------------ ; -; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR> +; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR> ; SPDX-License-Identifier: BSD-2-Clause-Patent ; ; Module Name: @@ -27,9 +27,6 @@ ;------------------------------------------------------------------------------ global ASM_PFX(AsmReadMm4) ASM_PFX(AsmReadMm4): - ; - ; 64-bit MASM doesn't support MMX instructions, so use opcode here - ; - DB 0x48, 0xf, 0x7e, 0xe0 + movq rax, mm4 ret diff --git a/MdePkg/Library/BaseLib/X64/ReadMm5.nasm b/MdePkg/Library/BaseLib/X64/ReadMm5.nasm index d8f530dec8..f1354dd68c 100644 --- a/MdePkg/Library/BaseLib/X64/ReadMm5.nasm +++ b/MdePkg/Library/BaseLib/X64/ReadMm5.nasm @@ -1,6 +1,6 @@ ;------------------------------------------------------------------------------ ; -; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR> +; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR> ; SPDX-License-Identifier: BSD-2-Clause-Patent ; ; Module Name: @@ -27,9 +27,6 @@ ;------------------------------------------------------------------------------ global ASM_PFX(AsmReadMm5) ASM_PFX(AsmReadMm5): - ; - ; 64-bit MASM doesn't support MMX instructions, so use opcode here - ; - DB 0x48, 0xf, 0x7e, 0xe8 + movq rax, mm5 ret diff --git a/MdePkg/Library/BaseLib/X64/ReadMm6.nasm b/MdePkg/Library/BaseLib/X64/ReadMm6.nasm index 6f6883c2b6..9d5a287218 100644 --- a/MdePkg/Library/BaseLib/X64/ReadMm6.nasm +++ b/MdePkg/Library/BaseLib/X64/ReadMm6.nasm @@ -1,6 +1,6 @@ ;------------------------------------------------------------------------------ ; -; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR> +; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR> ; SPDX-License-Identifier: BSD-2-Clause-Patent ; ; Module Name: @@ -27,9 +27,6 @@ ;------------------------------------------------------------------------------ global ASM_PFX(AsmReadMm6) ASM_PFX(AsmReadMm6): - ; - ; 64-bit MASM doesn't support MMX instructions, so use opcode here - ; - DB 0x48, 0xf, 0x7e, 0xf0 + movq rax, mm6 ret diff --git a/MdePkg/Library/BaseLib/X64/ReadMm7.nasm b/MdePkg/Library/BaseLib/X64/ReadMm7.nasm index 573f15dfc8..ae15f24d8b 100644 --- a/MdePkg/Library/BaseLib/X64/ReadMm7.nasm +++ b/MdePkg/Library/BaseLib/X64/ReadMm7.nasm @@ -1,6 +1,6 @@ ;------------------------------------------------------------------------------ ; -; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR> +; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR> ; SPDX-License-Identifier: BSD-2-Clause-Patent ; ; Module Name: @@ -27,9 +27,6 @@ ;------------------------------------------------------------------------------ global ASM_PFX(AsmReadMm7) ASM_PFX(AsmReadMm7): - ; - ; 64-bit MASM doesn't support MMX instructions, so use opcode here - ; - DB 0x48, 0xf, 0x7e, 0xf8 + movq rax, mm7 ret diff --git a/MdePkg/Library/BaseLib/X64/SetJump.nasm b/MdePkg/Library/BaseLib/X64/SetJump.nasm index 5a68396eec..5943a5ebe5 100644 --- a/MdePkg/Library/BaseLib/X64/SetJump.nasm +++ b/MdePkg/Library/BaseLib/X64/SetJump.nasm @@ -1,6 +1,6 @@ ;------------------------------------------------------------------------------ ; -; Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR> +; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR> ; SPDX-License-Identifier: BSD-2-Clause-Patent ; ; Module Name: @@ -48,8 +48,8 @@ ASM_PFX(SetJump): jnc CetDone mov rax, 1 - INCSSP_RAX ; to read original SSP - READSSP_RAX + incsspq rax ; to read original SSP + rdsspq rax mov [rcx + 0xF8], rax ; save SSP CetDone: diff --git a/MdePkg/Library/BaseLib/X64/WriteDr4.nasm b/MdePkg/Library/BaseLib/X64/WriteDr4.nasm index c4b12c9e92..5e4d96015e 100644 --- a/MdePkg/Library/BaseLib/X64/WriteDr4.nasm +++ b/MdePkg/Library/BaseLib/X64/WriteDr4.nasm @@ -1,6 +1,6 @@ ;------------------------------------------------------------------------------ ; -; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR> +; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR> ; SPDX-License-Identifier: BSD-2-Clause-Patent ; ; Module Name: @@ -31,7 +31,7 @@ ASM_PFX(AsmWriteDr4): ; There's no obvious reason to access this register, since it's aliased to ; DR6 when DE=0 or an exception generated when DE=1 ; - DB 0xf, 0x23, 0xe1 + mov dr4, rcx mov rax, rcx ret diff --git a/MdePkg/Library/BaseLib/X64/WriteDr5.nasm b/MdePkg/Library/BaseLib/X64/WriteDr5.nasm index 986a4a95d9..d5d4e2f324 100644 --- a/MdePkg/Library/BaseLib/X64/WriteDr5.nasm +++ b/MdePkg/Library/BaseLib/X64/WriteDr5.nasm @@ -1,6 +1,6 @@ ;------------------------------------------------------------------------------ ; -; Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR> +; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR> ; SPDX-License-Identifier: BSD-2-Clause-Patent ; ; Module Name: @@ -31,7 +31,7 @@ ASM_PFX(AsmWriteDr5): ; There's no obvious reason to access this register, since it's aliased to ; DR7 when DE=0 or an exception generated when DE=1 ; - DB 0xf, 0x23, 0xe9 + mov dr5, rcx mov rax, rcx ret diff --git a/MdePkg/Library/BaseLib/X64/WriteMm0.nasm b/MdePkg/Library/BaseLib/X64/WriteMm0.nasm index 3f03529edf..e6b5a0fc33 100644 --- a/MdePkg/Library/BaseLib/X64/WriteMm0.nasm +++ b/MdePkg/Library/BaseLib/X64/WriteMm0.nasm @@ -1,6 +1,6 @@ ;------------------------------------------------------------------------------ ; -; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR> +; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR> ; SPDX-License-Identifier: BSD-2-Clause-Patent ; ; Module Name: @@ -27,9 +27,6 @@ ;------------------------------------------------------------------------------ global ASM_PFX(AsmWriteMm0) ASM_PFX(AsmWriteMm0): - ; - ; 64-bit MASM doesn't support MMX instructions, so use opcode here - ; - DB 0x48, 0xf, 0x6e, 0xc1 + movq mm0, rcx ret diff --git a/MdePkg/Library/BaseLib/X64/WriteMm1.nasm b/MdePkg/Library/BaseLib/X64/WriteMm1.nasm index f552d40716..414c6af6da 100644 --- a/MdePkg/Library/BaseLib/X64/WriteMm1.nasm +++ b/MdePkg/Library/BaseLib/X64/WriteMm1.nasm @@ -1,6 +1,6 @@ ;------------------------------------------------------------------------------ ; -; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR> +; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR> ; SPDX-License-Identifier: BSD-2-Clause-Patent ; ; Module Name: @@ -27,9 +27,6 @@ ;------------------------------------------------------------------------------ global ASM_PFX(AsmWriteMm1) ASM_PFX(AsmWriteMm1): - ; - ; 64-bit MASM doesn't support MMX instructions, so use opcode here - ; - DB 0x48, 0xf, 0x6e, 0xc9 + movq mm1, rcx ret diff --git a/MdePkg/Library/BaseLib/X64/WriteMm2.nasm b/MdePkg/Library/BaseLib/X64/WriteMm2.nasm index 1bd176ced9..525740342a 100644 --- a/MdePkg/Library/BaseLib/X64/WriteMm2.nasm +++ b/MdePkg/Library/BaseLib/X64/WriteMm2.nasm @@ -1,6 +1,6 @@ ;------------------------------------------------------------------------------ ; -; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR> +; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR> ; SPDX-License-Identifier: BSD-2-Clause-Patent ; ; Module Name: @@ -27,9 +27,6 @@ ;------------------------------------------------------------------------------ global ASM_PFX(AsmWriteMm2) ASM_PFX(AsmWriteMm2): - ; - ; 64-bit MASM doesn't support MMX instructions, so use opcode here - ; - DB 0x48, 0xf, 0x6e, 0xd1 + movq mm2, rcx ret diff --git a/MdePkg/Library/BaseLib/X64/WriteMm3.nasm b/MdePkg/Library/BaseLib/X64/WriteMm3.nasm index 403f140736..abf11bfb17 100644 --- a/MdePkg/Library/BaseLib/X64/WriteMm3.nasm +++ b/MdePkg/Library/BaseLib/X64/WriteMm3.nasm @@ -1,6 +1,6 @@ ;------------------------------------------------------------------------------ ; -; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR> +; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR> ; SPDX-License-Identifier: BSD-2-Clause-Patent ; ; Module Name: @@ -27,9 +27,6 @@ ;------------------------------------------------------------------------------ global ASM_PFX(AsmWriteMm3) ASM_PFX(AsmWriteMm3): - ; - ; 64-bit MASM doesn't support MMX instructions, so use opcode here - ; - DB 0x48, 0xf, 0x6e, 0xd9 + movq mm3, rcx ret diff --git a/MdePkg/Library/BaseLib/X64/WriteMm4.nasm b/MdePkg/Library/BaseLib/X64/WriteMm4.nasm index d99709d495..7cbd25e70a 100644 --- a/MdePkg/Library/BaseLib/X64/WriteMm4.nasm +++ b/MdePkg/Library/BaseLib/X64/WriteMm4.nasm @@ -1,6 +1,6 @@ ;------------------------------------------------------------------------------ ; -; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR> +; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR> ; SPDX-License-Identifier: BSD-2-Clause-Patent ; ; Module Name: @@ -27,9 +27,6 @@ ;------------------------------------------------------------------------------ global ASM_PFX(AsmWriteMm4) ASM_PFX(AsmWriteMm4): - ; - ; 64-bit MASM doesn't support MMX instructions, so use opcode here - ; - DB 0x48, 0xf, 0x6e, 0xe1 + movq mm4, rcx ret diff --git a/MdePkg/Library/BaseLib/X64/WriteMm5.nasm b/MdePkg/Library/BaseLib/X64/WriteMm5.nasm index 0467ac4220..9edfd0db83 100644 --- a/MdePkg/Library/BaseLib/X64/WriteMm5.nasm +++ b/MdePkg/Library/BaseLib/X64/WriteMm5.nasm @@ -1,6 +1,6 @@ ;------------------------------------------------------------------------------ ; -; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR> +; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR> ; SPDX-License-Identifier: BSD-2-Clause-Patent ; ; Module Name: @@ -27,9 +27,6 @@ ;------------------------------------------------------------------------------ global ASM_PFX(AsmWriteMm5) ASM_PFX(AsmWriteMm5): - ; - ; 64-bit MASM doesn't support MMX instructions, so use opcode here - ; - DB 0x48, 0xf, 0x6e, 0xe9 + movq mm5, rcx ret diff --git a/MdePkg/Library/BaseLib/X64/WriteMm6.nasm b/MdePkg/Library/BaseLib/X64/WriteMm6.nasm index 6d2e5eb8fb..4555563a55 100644 --- a/MdePkg/Library/BaseLib/X64/WriteMm6.nasm +++ b/MdePkg/Library/BaseLib/X64/WriteMm6.nasm @@ -1,6 +1,6 @@ ;------------------------------------------------------------------------------ ; -; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR> +; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR> ; SPDX-License-Identifier: BSD-2-Clause-Patent ; ; Module Name: @@ -27,9 +27,6 @@ ;------------------------------------------------------------------------------ global ASM_PFX(AsmWriteMm6) ASM_PFX(AsmWriteMm6): - ; - ; 64-bit MASM doesn't support MMX instructions, so use opcode here - ; - DB 0x48, 0xf, 0x6e, 0xf1 + movq mm6, rcx ret diff --git a/MdePkg/Library/BaseLib/X64/WriteMm7.nasm b/MdePkg/Library/BaseLib/X64/WriteMm7.nasm index de72adf685..4ef0eb5271 100644 --- a/MdePkg/Library/BaseLib/X64/WriteMm7.nasm +++ b/MdePkg/Library/BaseLib/X64/WriteMm7.nasm @@ -1,6 +1,6 @@ ;------------------------------------------------------------------------------ ; -; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR> +; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR> ; SPDX-License-Identifier: BSD-2-Clause-Patent ; ; Module Name: @@ -27,9 +27,6 @@ ;------------------------------------------------------------------------------ global ASM_PFX(AsmWriteMm7) ASM_PFX(AsmWriteMm7): - ; - ; 64-bit MASM doesn't support MMX instructions, so use opcode here - ; - DB 0x48, 0xf, 0x6e, 0xf9 + movq mm7, rcx ret diff --git a/MdePkg/Library/BaseMemoryLibMmx/X64/CopyMem.nasm b/MdePkg/Library/BaseMemoryLibMmx/X64/CopyMem.nasm index 5769c00bf9..3b336c6bdf 100644 --- a/MdePkg/Library/BaseMemoryLibMmx/X64/CopyMem.nasm +++ b/MdePkg/Library/BaseMemoryLibMmx/X64/CopyMem.nasm @@ -1,6 +1,6 @@ ;------------------------------------------------------------------------------ ; -; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR> +; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR> ; SPDX-License-Identifier: BSD-2-Clause-Patent ; ; Module Name: @@ -44,15 +44,15 @@ ASM_PFX(InternalMemCopyMem): and r8, 7 shr rcx, 3 ; rcx <- # of Qwords to copy jz @CopyBytes - DB 0x49, 0xf, 0x7e, 0xc2 ; movd r10, mm0 (Save mm0 in r10) + movq r10, mm0 .1: - DB 0xf, 0x6f, 0x6 ; movd mm0, [rsi] - DB 0xf, 0xe7, 0x7 ; movntq [rdi], mm0 + movq mm0, [rsi] + movntq [rdi], mm0 add rsi, 8 add rdi, 8 loop .1 mfence - DB 0x49, 0xf, 0x6e, 0xc2 ; movd mm0, r10 (Restore mm0) + movq mm0, r10 jmp @CopyBytes @CopyBackward: mov rsi, r9 ; rsi <- End of Source diff --git a/MdePkg/Library/BaseMemoryLibMmx/X64/SetMem.nasm b/MdePkg/Library/BaseMemoryLibMmx/X64/SetMem.nasm index 450113ba84..af584e3d34 100644 --- a/MdePkg/Library/BaseMemoryLibMmx/X64/SetMem.nasm +++ b/MdePkg/Library/BaseMemoryLibMmx/X64/SetMem.nasm @@ -1,6 +1,6 @@ ;------------------------------------------------------------------------------ ; -; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR> +; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR> ; SPDX-License-Identifier: BSD-2-Clause-Patent ; ; Module Name: @@ -32,16 +32,16 @@ ASM_PFX(InternalMemSetMem): push rdi mov rax, r8 mov ah, al - DB 0x48, 0xf, 0x6e, 0xc0 ; movd mm0, rax + movq mm0, rax mov r8, rcx mov rdi, r8 ; rdi <- Buffer mov rcx, rdx and edx, 7 shr rcx, 3 jz @SetBytes - DB 0xf, 0x70, 0xC0, 0x0 ; pshufw mm0, mm0, 0h + pshufw mm0, mm0, 0 .0: - DB 0xf, 0xe7, 0x7 ; movntq [rdi], mm0 + movntq [rdi], mm0 add rdi, 8 loop .0 mfence diff --git a/MdePkg/Library/BaseMemoryLibMmx/X64/SetMem16.nasm b/MdePkg/Library/BaseMemoryLibMmx/X64/SetMem16.nasm index 4e1f4be2b4..7a63a1c50b 100644 --- a/MdePkg/Library/BaseMemoryLibMmx/X64/SetMem16.nasm +++ b/MdePkg/Library/BaseMemoryLibMmx/X64/SetMem16.nasm @@ -1,6 +1,6 @@ ;------------------------------------------------------------------------------ ; -; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR> +; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR> ; SPDX-License-Identifier: BSD-2-Clause-Patent ; ; Module Name: @@ -31,16 +31,16 @@ global ASM_PFX(InternalMemSetMem16) ASM_PFX(InternalMemSetMem16): push rdi mov rax, r8 - DB 0x48, 0xf, 0x6e, 0xc0 ; movd mm0, rax + movq mm0, rax mov r8, rcx mov rdi, r8 mov rcx, rdx and edx, 3 shr rcx, 2 jz @SetWords - DB 0xf, 0x70, 0xC0, 0x0 ; pshufw mm0, mm0, 0h + pshufw mm0, mm0, 0 .0: - DB 0xf, 0xe7, 0x7 ; movntq [rdi], mm0 + movntq [rdi], mm0 add rdi, 8 loop .0 mfence diff --git a/MdePkg/Library/BaseMemoryLibMmx/X64/SetMem32.nasm b/MdePkg/Library/BaseMemoryLibMmx/X64/SetMem32.nasm index b3a7385897..ab5f954826 100644 --- a/MdePkg/Library/BaseMemoryLibMmx/X64/SetMem32.nasm +++ b/MdePkg/Library/BaseMemoryLibMmx/X64/SetMem32.nasm @@ -1,6 +1,6 @@ ;------------------------------------------------------------------------------ ; -; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR> +; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR> ; SPDX-License-Identifier: BSD-2-Clause-Patent ; ; Module Name: @@ -28,20 +28,20 @@ ;------------------------------------------------------------------------------ global ASM_PFX(InternalMemSetMem32) ASM_PFX(InternalMemSetMem32): - DB 0x49, 0xf, 0x6e, 0xc0 ; movd mm0, r8 (Value) + movq mm0, r8 mov rax, rcx ; rax <- Buffer xchg rcx, rdx ; rcx <- Count rdx <- Buffer shr rcx, 1 ; rcx <- # of qwords to set jz @SetDwords - DB 0xf, 0x70, 0xC0, 0x44 ; pshufw mm0, mm0, 44h + pshufw mm0, mm0, 44h .0: - DB 0xf, 0xe7, 0x2 ; movntq [rdx], mm0 + movntq [rdx], mm0 lea rdx, [rdx + 8] ; use "lea" to avoid flag changes loop .0 mfence @SetDwords: jnc .1 - DB 0xf, 0x7e, 0x2 ; movd [rdx], mm0 + movd [rdx], mm0 .1: ret diff --git a/MdePkg/Library/BaseMemoryLibMmx/X64/SetMem64.nasm b/MdePkg/Library/BaseMemoryLibMmx/X64/SetMem64.nasm index f517e1d23a..fcc44294a8 100644 --- a/MdePkg/Library/BaseMemoryLibMmx/X64/SetMem64.nasm +++ b/MdePkg/Library/BaseMemoryLibMmx/X64/SetMem64.nasm @@ -1,6 +1,6 @@ ;------------------------------------------------------------------------------ ; -; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR> +; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR> ; SPDX-License-Identifier: BSD-2-Clause-Patent ; ; Module Name: @@ -28,11 +28,11 @@ ;------------------------------------------------------------------------------ global ASM_PFX(InternalMemSetMem64) ASM_PFX(InternalMemSetMem64): - DB 0x49, 0xf, 0x6e, 0xc0 ; movd mm0, r8 (Value) + movq mm0, r8 mov rax, rcx ; rax <- Buffer xchg rcx, rdx ; rcx <- Count .0: - DB 0xf, 0xe7, 0x2 ; movntq [rdx], mm0 + movntq [rdx], mm0 add rdx, 8 loop .0 mfence diff --git a/MdePkg/Library/BaseMemoryLibMmx/X64/ZeroMem.nasm b/MdePkg/Library/BaseMemoryLibMmx/X64/ZeroMem.nasm index 2a85f15b55..8b02eeb732 100644 --- a/MdePkg/Library/BaseMemoryLibMmx/X64/ZeroMem.nasm +++ b/MdePkg/Library/BaseMemoryLibMmx/X64/ZeroMem.nasm @@ -1,6 +1,6 @@ ;------------------------------------------------------------------------------ ; -; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR> +; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR> ; SPDX-License-Identifier: BSD-2-Clause-Patent ; ; Module Name: @@ -34,12 +34,12 @@ ASM_PFX(InternalMemZeroMem): and edx, 7 shr rcx, 3 jz @ZeroBytes - DB 0xf, 0xef, 0xc0 ; pxor mm0, mm0 + pxor mm0, mm0 .0: - DB 0xf, 0xe7, 7 ; movntq [rdi], mm0 + movntq [rdi], mm0 add rdi, 8 loop .0 - DB 0xf, 0xae, 0xf0 ; mfence + mfence @ZeroBytes: xor eax, eax mov ecx, edx -- 2.28.0.windows.1 ^ permalink raw reply related [flat|nested] 12+ messages in thread
* 回复: [edk2-devel] [PATCH v2 2/6] MdePkg: Replace Opcode with the corresponding instructions. 2022-01-10 15:12 ` [PATCH v2 2/6] MdePkg: " Jason Lou @ 2022-01-11 0:55 ` gaoliming 0 siblings, 0 replies; 12+ messages in thread From: gaoliming @ 2022-01-11 0:55 UTC (permalink / raw) To: devel, yun.lou; +Cc: 'Michael D Kinney', 'Zhiguang Liu' Jason: Thanks for your update. Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> for this patch set. Thanks Liming > -----邮件原件----- > 发件人: devel@edk2.groups.io <devel@edk2.groups.io> 代表 Jason Lou > 发送时间: 2022年1月10日 23:13 > 收件人: devel@edk2.groups.io > 抄送: Jason <yun.lou@intel.com>; Michael D Kinney > <michael.d.kinney@intel.com>; Liming Gao <gaoliming@byosoft.com.cn>; > Zhiguang Liu <zhiguang.liu@intel.com> > 主题: [edk2-devel] [PATCH v2 2/6] MdePkg: Replace Opcode with the > corresponding instructions. > > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3790 > > Replace Opcode with the corresponding instructions. > The code changes have been verified with CompareBuild.py tool, which > can be used to compare the results of two different EDK II builds to > determine if they generate the same binaries. > (tool link: https://github.com/mdkinney/edk2/tree/sandbox/CompareBuild) > > Signed-off-by: Jason Lou <yun.lou@intel.com> > Cc: Michael D Kinney <michael.d.kinney@intel.com> > Cc: Liming Gao <gaoliming@byosoft.com.cn> > Cc: Zhiguang Liu <zhiguang.liu@intel.com> > --- > MdePkg/Library/BaseLib/Ia32/EnablePaging64.nasm | 20 > ++++++++------------ > MdePkg/Library/BaseLib/Ia32/LongJump.nasm | 6 +++--- > MdePkg/Library/BaseLib/Ia32/Monitor.nasm | 4 ++-- > MdePkg/Library/BaseLib/Ia32/Mwait.nasm | 4 ++-- > MdePkg/Library/BaseLib/Ia32/RdRand.nasm | 13 +++++-------- > MdePkg/Library/BaseLib/Ia32/ReadDr4.nasm | 6 +++--- > MdePkg/Library/BaseLib/Ia32/ReadDr5.nasm | 6 +++--- > MdePkg/Library/BaseLib/Ia32/SetJump.nasm | 6 +++--- > MdePkg/Library/BaseLib/Ia32/WriteDr4.nasm | 6 +++--- > MdePkg/Library/BaseLib/Ia32/WriteDr5.nasm | 6 +++--- > MdePkg/Library/BaseLib/X64/DisablePaging64.nasm | 5 ++--- > MdePkg/Library/BaseLib/X64/LongJump.nasm | 6 +++--- > MdePkg/Library/BaseLib/X64/Monitor.nasm | 4 ++-- > MdePkg/Library/BaseLib/X64/Mwait.nasm | 4 ++-- > MdePkg/Library/BaseLib/X64/RdRand.nasm | 11 ++++------- > MdePkg/Library/BaseLib/X64/ReadDr4.nasm | 4 ++-- > MdePkg/Library/BaseLib/X64/ReadDr5.nasm | 4 ++-- > MdePkg/Library/BaseLib/X64/ReadMm0.nasm | 7 ++----- > MdePkg/Library/BaseLib/X64/ReadMm1.nasm | 7 ++----- > MdePkg/Library/BaseLib/X64/ReadMm2.nasm | 7 ++----- > MdePkg/Library/BaseLib/X64/ReadMm3.nasm | 7 ++----- > MdePkg/Library/BaseLib/X64/ReadMm4.nasm | 7 ++----- > MdePkg/Library/BaseLib/X64/ReadMm5.nasm | 7 ++----- > MdePkg/Library/BaseLib/X64/ReadMm6.nasm | 7 ++----- > MdePkg/Library/BaseLib/X64/ReadMm7.nasm | 7 ++----- > MdePkg/Library/BaseLib/X64/SetJump.nasm | 6 +++--- > MdePkg/Library/BaseLib/X64/WriteDr4.nasm | 4 ++-- > MdePkg/Library/BaseLib/X64/WriteDr5.nasm | 4 ++-- > MdePkg/Library/BaseLib/X64/WriteMm0.nasm | 7 ++----- > MdePkg/Library/BaseLib/X64/WriteMm1.nasm | 7 ++----- > MdePkg/Library/BaseLib/X64/WriteMm2.nasm | 7 ++----- > MdePkg/Library/BaseLib/X64/WriteMm3.nasm | 7 ++----- > MdePkg/Library/BaseLib/X64/WriteMm4.nasm | 7 ++----- > MdePkg/Library/BaseLib/X64/WriteMm5.nasm | 7 ++----- > MdePkg/Library/BaseLib/X64/WriteMm6.nasm | 7 ++----- > MdePkg/Library/BaseLib/X64/WriteMm7.nasm | 7 ++----- > MdePkg/Library/BaseMemoryLibMmx/X64/CopyMem.nasm | 10 > +++++----- > MdePkg/Library/BaseMemoryLibMmx/X64/SetMem.nasm | 8 ++++---- > MdePkg/Library/BaseMemoryLibMmx/X64/SetMem16.nasm | 8 ++++---- > MdePkg/Library/BaseMemoryLibMmx/X64/SetMem32.nasm | 10 > +++++----- > MdePkg/Library/BaseMemoryLibMmx/X64/SetMem64.nasm | 6 +++--- > MdePkg/Library/BaseMemoryLibMmx/X64/ZeroMem.nasm | 8 ++++---- > 42 files changed, 116 insertions(+), 175 deletions(-) > > diff --git a/MdePkg/Library/BaseLib/Ia32/EnablePaging64.nasm > b/MdePkg/Library/BaseLib/Ia32/EnablePaging64.nasm > index 544e3c3892..ef11458077 100644 > --- a/MdePkg/Library/BaseLib/Ia32/EnablePaging64.nasm > +++ b/MdePkg/Library/BaseLib/Ia32/EnablePaging64.nasm > @@ -1,6 +1,6 @@ > ;--------------------------------------------------------------------------- --- > > ; > > -; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR> > > +; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR> > > ; SPDX-License-Identifier: BSD-2-Clause-Patent > > ; > > ; Module Name: > > @@ -44,16 +44,12 @@ ASM_PFX(InternalX86EnablePaging64): > mov cr0, eax ; enable paging > > retf ; topmost 2 dwords hold the > address > > .0: > > - DB 0x67, 0x48 ; 32-bit address size, > 64-bit operand size > > - mov ebx, [esp] ; mov rbx, [esp] > > - DB 0x67, 0x48 > > - mov ecx, [esp + 8] ; mov rcx, [esp + 8] > > - DB 0x67, 0x48 > > - mov edx, [esp + 0x10] ; mov rdx, [esp + 10h] > > - DB 0x67, 0x48 > > - mov esp, [esp + 0x18] ; mov rsp, [esp + 18h] > > - DB 0x48 > > - add esp, -0x20 ; add rsp, -20h > > - call ebx ; call rbx > > +BITS 64 > > + mov rbx, [esp] > > + mov rcx, [esp + 8] > > + mov rdx, [esp + 0x10] > > + mov rsp, [esp + 0x18] > > + add rsp, -0x20 > > + call rbx > > hlt ; no one should get here > > > > diff --git a/MdePkg/Library/BaseLib/Ia32/LongJump.nasm > b/MdePkg/Library/BaseLib/Ia32/LongJump.nasm > index f94d10f806..6c13dfe307 100644 > --- a/MdePkg/Library/BaseLib/Ia32/LongJump.nasm > +++ b/MdePkg/Library/BaseLib/Ia32/LongJump.nasm > @@ -1,6 +1,6 @@ > ;--------------------------------------------------------------------------- --- > > ; > > -; Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR> > > +; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR> > > ; SPDX-License-Identifier: BSD-2-Clause-Patent > > ; > > ; Module Name: > > @@ -39,12 +39,12 @@ ASM_PFX(InternalLongJump): > > > mov edx, [esp + 4] ; edx = JumpBuffer > > mov edx, [edx + 24] ; edx = target SSP > > - READSSP_EAX > > + rdsspd eax > > sub edx, eax ; edx = delta > > mov eax, edx ; eax = delta > > > > shr eax, 2 ; eax = delta/sizeof(UINT32) > > - INCSSP_EAX > > + incsspd eax > > > > CetDone: > > > > diff --git a/MdePkg/Library/BaseLib/Ia32/Monitor.nasm > b/MdePkg/Library/BaseLib/Ia32/Monitor.nasm > index 28dc0ba70a..70dbe66e27 100644 > --- a/MdePkg/Library/BaseLib/Ia32/Monitor.nasm > +++ b/MdePkg/Library/BaseLib/Ia32/Monitor.nasm > @@ -1,6 +1,6 @@ > ;--------------------------------------------------------------------------- --- > > ; > > -; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR> > > +; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR> > > ; SPDX-License-Identifier: BSD-2-Clause-Patent > > ; > > ; Module Name: > > @@ -31,6 +31,6 @@ ASM_PFX(AsmMonitor): > mov eax, [esp + 4] > > mov ecx, [esp + 8] > > mov edx, [esp + 12] > > - DB 0xf, 1, 0xc8 ; monitor > > + monitor > > ret > > > > diff --git a/MdePkg/Library/BaseLib/Ia32/Mwait.nasm > b/MdePkg/Library/BaseLib/Ia32/Mwait.nasm > index 3956940cab..2d36a97df6 100644 > --- a/MdePkg/Library/BaseLib/Ia32/Mwait.nasm > +++ b/MdePkg/Library/BaseLib/Ia32/Mwait.nasm > @@ -1,6 +1,6 @@ > ;--------------------------------------------------------------------------- --- > > ; > > -; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR> > > +; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR> > > ; SPDX-License-Identifier: BSD-2-Clause-Patent > > ; > > ; Module Name: > > @@ -29,6 +29,6 @@ global ASM_PFX(AsmMwait) > ASM_PFX(AsmMwait): > > mov eax, [esp + 4] > > mov ecx, [esp + 8] > > - DB 0xf, 1, 0xc9 ; mwait > > + mwait > > ret > > > > diff --git a/MdePkg/Library/BaseLib/Ia32/RdRand.nasm > b/MdePkg/Library/BaseLib/Ia32/RdRand.nasm > index e12b8e9611..d818b6ef55 100644 > --- a/MdePkg/Library/BaseLib/Ia32/RdRand.nasm > +++ b/MdePkg/Library/BaseLib/Ia32/RdRand.nasm > @@ -1,6 +1,6 @@ > ;--------------------------------------------------------------------------- --- > > ; > > -; Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR> > > +; Copyright (c) 2015 - 2022, Intel Corporation. All rights reserved.<BR> > > ; SPDX-License-Identifier: BSD-2-Clause-Patent > > ; > > ; Module Name: > > @@ -25,9 +25,8 @@ SECTION .text > ;--------------------------------------------------------------------------- --- > > global ASM_PFX(InternalX86RdRand16) > > ASM_PFX(InternalX86RdRand16): > > - ; rdrand ax ; generate a 16 bit RN into ax > > + rdrand eax ; generate a 16 bit RN into ax > > ; CF=1 if RN generated ok, > otherwise CF=0 > > - db 0xf, 0xc7, 0xf0 ; rdrand r16: "0f c7 /6 > ModRM:r/m(w)" > > jc rn16_ok ; jmp if CF=1 > > xor eax, eax ; reg=0 if CF=0 > > ret ; return with failure status > > @@ -45,9 +44,8 @@ rn16_ok: > ;--------------------------------------------------------------------------- --- > > global ASM_PFX(InternalX86RdRand32) > > ASM_PFX(InternalX86RdRand32): > > - ; rdrand eax ; generate a 32 bit RN into eax > > + rdrand eax ; generate a 32 bit RN into eax > > ; CF=1 if RN generated ok, > otherwise CF=0 > > - db 0xf, 0xc7, 0xf0 ; rdrand r32: "0f c7 /6 > ModRM:r/m(w)" > > jc rn32_ok ; jmp if CF=1 > > xor eax, eax ; reg=0 if CF=0 > > ret ; return with failure status > > @@ -65,14 +63,13 @@ rn32_ok: > ;--------------------------------------------------------------------------- --- > > global ASM_PFX(InternalX86RdRand64) > > ASM_PFX(InternalX86RdRand64): > > - ; rdrand eax ; generate a 32 bit RN into eax > > + rdrand eax ; generate a 32 bit RN into eax > > ; CF=1 if RN generated ok, > otherwise CF=0 > > - db 0xf, 0xc7, 0xf0 ; rdrand r32: "0f c7 /6 > ModRM:r/m(w)" > > jnc rn64_ret ; jmp if CF=0 > > mov edx, dword [esp + 4] > > mov [edx], eax > > > > - db 0xf, 0xc7, 0xf0 ; generate another 32 bit RN > > + rdrand eax ; generate another 32 bit RN > > jnc rn64_ret ; jmp if CF=0 > > mov [edx + 4], eax > > > > diff --git a/MdePkg/Library/BaseLib/Ia32/ReadDr4.nasm > b/MdePkg/Library/BaseLib/Ia32/ReadDr4.nasm > index 81c681de34..1c312b670d 100644 > --- a/MdePkg/Library/BaseLib/Ia32/ReadDr4.nasm > +++ b/MdePkg/Library/BaseLib/Ia32/ReadDr4.nasm > @@ -1,6 +1,6 @@ > ;--------------------------------------------------------------------------- --- > > ; > > -; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR> > > +; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR> > > ; SPDX-License-Identifier: BSD-2-Clause-Patent > > ; > > ; Module Name: > > @@ -31,8 +31,8 @@ ASM_PFX(AsmReadDr4): > ; this register will cause a #UD exception. > > ; > > ; MS assembler doesn't support this instruction since no one would use > it > > - ; under normal circustances. Here opcode is used. > > + ; under normal circustances. > > ; > > - DB 0xf, 0x21, 0xe0 > > + mov eax, dr4 > > ret > > > > diff --git a/MdePkg/Library/BaseLib/Ia32/ReadDr5.nasm > b/MdePkg/Library/BaseLib/Ia32/ReadDr5.nasm > index e2deacb832..07a1b44a00 100644 > --- a/MdePkg/Library/BaseLib/Ia32/ReadDr5.nasm > +++ b/MdePkg/Library/BaseLib/Ia32/ReadDr5.nasm > @@ -1,6 +1,6 @@ > ;--------------------------------------------------------------------------- --- > > ; > > -; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR> > > +; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR> > > ; SPDX-License-Identifier: BSD-2-Clause-Patent > > ; > > ; Module Name: > > @@ -31,8 +31,8 @@ ASM_PFX(AsmReadDr5): > ; this register will cause a #UD exception. > > ; > > ; MS assembler doesn't support this instruction since no one would use > it > > - ; under normal circustances. Here opcode is used. > > + ; under normal circustances. > > ; > > - DB 0xf, 0x21, 0xe8 > > + mov eax, dr5 > > ret > > > > diff --git a/MdePkg/Library/BaseLib/Ia32/SetJump.nasm > b/MdePkg/Library/BaseLib/Ia32/SetJump.nasm > index 364613b5f9..2577373241 100644 > --- a/MdePkg/Library/BaseLib/Ia32/SetJump.nasm > +++ b/MdePkg/Library/BaseLib/Ia32/SetJump.nasm > @@ -1,6 +1,6 @@ > ;--------------------------------------------------------------------------- --- > > ; > > -; Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR> > > +; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR> > > ; SPDX-License-Identifier: BSD-2-Clause-Patent > > ; > > ; Module Name: > > @@ -46,8 +46,8 @@ ASM_PFX(SetJump): > jnc CetDone > > > > mov eax, 1 > > - INCSSP_EAX ; to read original SSP > > - READSSP_EAX > > + incsspd eax ; to read original SSP > > + rdsspd eax > > mov [edx + 0x24], eax ; save SSP > > > > CetDone: > > diff --git a/MdePkg/Library/BaseLib/Ia32/WriteDr4.nasm > b/MdePkg/Library/BaseLib/Ia32/WriteDr4.nasm > index 0d23fca111..b8479b39f7 100644 > --- a/MdePkg/Library/BaseLib/Ia32/WriteDr4.nasm > +++ b/MdePkg/Library/BaseLib/Ia32/WriteDr4.nasm > @@ -1,6 +1,6 @@ > ;--------------------------------------------------------------------------- --- > > ; > > -; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR> > > +; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR> > > ; SPDX-License-Identifier: BSD-2-Clause-Patent > > ; > > ; Module Name: > > @@ -32,8 +32,8 @@ ASM_PFX(AsmWriteDr4): > ; this register will cause a #UD exception. > > ; > > ; MS assembler doesn't support this instruction since no one would use > it > > - ; under normal circustances. Here opcode is used. > > + ; under normal circustances. > > ; > > - DB 0xf, 0x23, 0xe0 > > + mov dr4, eax > > ret > > > > diff --git a/MdePkg/Library/BaseLib/Ia32/WriteDr5.nasm > b/MdePkg/Library/BaseLib/Ia32/WriteDr5.nasm > index bc5f424b8d..3545561025 100644 > --- a/MdePkg/Library/BaseLib/Ia32/WriteDr5.nasm > +++ b/MdePkg/Library/BaseLib/Ia32/WriteDr5.nasm > @@ -1,6 +1,6 @@ > ;--------------------------------------------------------------------------- --- > > ; > > -; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR> > > +; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR> > > ; SPDX-License-Identifier: BSD-2-Clause-Patent > > ; > > ; Module Name: > > @@ -32,8 +32,8 @@ ASM_PFX(AsmWriteDr5): > ; this register will cause a #UD exception. > > ; > > ; MS assembler doesn't support this instruction since no one would use > it > > - ; under normal circustances. Here opcode is used. > > + ; under normal circustances. > > ; > > - DB 0xf, 0x23, 0xe8 > > + mov dr5, eax > > ret > > > > diff --git a/MdePkg/Library/BaseLib/X64/DisablePaging64.nasm > b/MdePkg/Library/BaseLib/X64/DisablePaging64.nasm > index c76ed1a76c..200c408d9a 100644 > --- a/MdePkg/Library/BaseLib/X64/DisablePaging64.nasm > +++ b/MdePkg/Library/BaseLib/X64/DisablePaging64.nasm > @@ -1,6 +1,6 @@ > ;--------------------------------------------------------------------------- --- > > ; > > -; Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR> > > +; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR> > > ; SPDX-License-Identifier: BSD-2-Clause-Patent > > ; > > ; Module Name: > > @@ -51,8 +51,7 @@ ASM_PFX(InternalX86DisablePaging64): > sub eax, 4 ; eax <- One slot below > transition code on the stack > > push rcx ; push Cs to stack > > push r10 ; push address of tansition > code on stack > > - DB 0x48 ; prefix to composite > "retq" with next "retf" > > - retf ; Use far return to load CS > register from stack > > + retfq > > > > ; Start of transition code > > .0: > > diff --git a/MdePkg/Library/BaseLib/X64/LongJump.nasm > b/MdePkg/Library/BaseLib/X64/LongJump.nasm > index 59f7092169..2002f65cba 100644 > --- a/MdePkg/Library/BaseLib/X64/LongJump.nasm > +++ b/MdePkg/Library/BaseLib/X64/LongJump.nasm > @@ -1,6 +1,6 @@ > ;--------------------------------------------------------------------------- --- > > ; > > -; Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR> > > +; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR> > > ; SPDX-License-Identifier: BSD-2-Clause-Patent > > ; > > ; Module Name: > > @@ -41,12 +41,12 @@ ASM_PFX(InternalLongJump): > push rdx ; save rdx > > > > mov rdx, [rcx + 0xF8] ; rdx = target SSP > > - READSSP_RAX > > + rdsspq rax > > sub rdx, rax ; rdx = delta > > mov rax, rdx ; rax = delta > > > > shr rax, 3 ; rax = delta/sizeof(UINT64) > > - INCSSP_RAX > > + incsspq rax > > > > pop rdx ; restore rdx > > CetDone: > > diff --git a/MdePkg/Library/BaseLib/X64/Monitor.nasm > b/MdePkg/Library/BaseLib/X64/Monitor.nasm > index e1ccb83a85..210037d402 100644 > --- a/MdePkg/Library/BaseLib/X64/Monitor.nasm > +++ b/MdePkg/Library/BaseLib/X64/Monitor.nasm > @@ -1,6 +1,6 @@ > ;--------------------------------------------------------------------------- --- > > ; > > -; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR> > > +; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR> > > ; SPDX-License-Identifier: BSD-2-Clause-Patent > > ; > > ; Module Name: > > @@ -32,6 +32,6 @@ ASM_PFX(AsmMonitor): > mov eax, ecx > > mov ecx, edx > > mov edx, r8d > > - DB 0xf, 1, 0xc8 ; monitor > > + monitor > > ret > > > > diff --git a/MdePkg/Library/BaseLib/X64/Mwait.nasm > b/MdePkg/Library/BaseLib/X64/Mwait.nasm > index 83fc895491..c8ad59588b 100644 > --- a/MdePkg/Library/BaseLib/X64/Mwait.nasm > +++ b/MdePkg/Library/BaseLib/X64/Mwait.nasm > @@ -1,6 +1,6 @@ > ;--------------------------------------------------------------------------- --- > > ; > > -; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR> > > +; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR> > > ; SPDX-License-Identifier: BSD-2-Clause-Patent > > ; > > ; Module Name: > > @@ -30,6 +30,6 @@ global ASM_PFX(AsmMwait) > ASM_PFX(AsmMwait): > > mov eax, ecx > > mov ecx, edx > > - DB 0xf, 1, 0xc9 ; mwait > > + mwait > > ret > > > > diff --git a/MdePkg/Library/BaseLib/X64/RdRand.nasm > b/MdePkg/Library/BaseLib/X64/RdRand.nasm > index 7e7fe99670..73479be8d3 100644 > --- a/MdePkg/Library/BaseLib/X64/RdRand.nasm > +++ b/MdePkg/Library/BaseLib/X64/RdRand.nasm > @@ -1,6 +1,6 @@ > ;--------------------------------------------------------------------------- --- > > ; > > -; Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR> > > +; Copyright (c) 2015 - 2022, Intel Corporation. All rights reserved.<BR> > > ; SPDX-License-Identifier: BSD-2-Clause-Patent > > ; > > ; Module Name: > > @@ -26,9 +26,8 @@ > ;--------------------------------------------------------------------------- --- > > global ASM_PFX(InternalX86RdRand16) > > ASM_PFX(InternalX86RdRand16): > > - ; rdrand ax ; generate a 16 bit RN into eax, > > + rdrand eax ; generate a 16 bit RN into eax, > > ; CF=1 if RN generated ok, > otherwise CF=0 > > - db 0xf, 0xc7, 0xf0 ; rdrand r16: "0f c7 /6 > ModRM:r/m(w)" > > jc rn16_ok ; jmp if CF=1 > > xor rax, rax ; reg=0 if CF=0 > > ret ; return with failure status > > @@ -45,9 +44,8 @@ rn16_ok: > ;--------------------------------------------------------------------------- --- > > global ASM_PFX(InternalX86RdRand32) > > ASM_PFX(InternalX86RdRand32): > > - ; rdrand eax ; generate a 32 bit RN into eax, > > + rdrand eax ; generate a 32 bit RN into eax, > > ; CF=1 if RN generated ok, > otherwise CF=0 > > - db 0xf, 0xc7, 0xf0 ; rdrand r32: "0f c7 /6 > ModRM:r/m(w)" > > jc rn32_ok ; jmp if CF=1 > > xor rax, rax ; reg=0 if CF=0 > > ret ; return with failure status > > @@ -64,9 +62,8 @@ rn32_ok: > ;--------------------------------------------------------------------------- --- > > global ASM_PFX(InternalX86RdRand64) > > ASM_PFX(InternalX86RdRand64): > > - ; rdrand rax ; generate a 64 bit RN into rax, > > + rdrand rax ; generate a 64 bit RN into rax, > > ; CF=1 if RN generated ok, > otherwise CF=0 > > - db 0x48, 0xf, 0xc7, 0xf0 ; rdrand r64: "REX.W + 0f c7 /6 > ModRM:r/m(w)" > > jc rn64_ok ; jmp if CF=1 > > xor rax, rax ; reg=0 if CF=0 > > ret ; return with failure status > > diff --git a/MdePkg/Library/BaseLib/X64/ReadDr4.nasm > b/MdePkg/Library/BaseLib/X64/ReadDr4.nasm > index 82c0a9a588..90b2172cee 100644 > --- a/MdePkg/Library/BaseLib/X64/ReadDr4.nasm > +++ b/MdePkg/Library/BaseLib/X64/ReadDr4.nasm > @@ -1,6 +1,6 @@ > ;--------------------------------------------------------------------------- --- > > ; > > -; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR> > > +; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR> > > ; SPDX-License-Identifier: BSD-2-Clause-Patent > > ; > > ; Module Name: > > @@ -31,6 +31,6 @@ ASM_PFX(AsmReadDr4): > ; There's no obvious reason to access this register, since it's aliased to > > ; DR7 when DE=0 or an exception generated when DE=1 > > ; > > - DB 0xf, 0x21, 0xe0 > > + mov rax, dr4 > > ret > > > > diff --git a/MdePkg/Library/BaseLib/X64/ReadDr5.nasm > b/MdePkg/Library/BaseLib/X64/ReadDr5.nasm > index c309c66dfe..c1143f4498 100644 > --- a/MdePkg/Library/BaseLib/X64/ReadDr5.nasm > +++ b/MdePkg/Library/BaseLib/X64/ReadDr5.nasm > @@ -1,6 +1,6 @@ > ;--------------------------------------------------------------------------- --- > > ; > > -; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR> > > +; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR> > > ; SPDX-License-Identifier: BSD-2-Clause-Patent > > ; > > ; Module Name: > > @@ -31,6 +31,6 @@ ASM_PFX(AsmReadDr5): > ; There's no obvious reason to access this register, since it's aliased to > > ; DR7 when DE=0 or an exception generated when DE=1 > > ; > > - DB 0xf, 0x21, 0xe8 > > + mov rax, dr5 > > ret > > > > diff --git a/MdePkg/Library/BaseLib/X64/ReadMm0.nasm > b/MdePkg/Library/BaseLib/X64/ReadMm0.nasm > index 615721b6aa..e64b2c7882 100644 > --- a/MdePkg/Library/BaseLib/X64/ReadMm0.nasm > +++ b/MdePkg/Library/BaseLib/X64/ReadMm0.nasm > @@ -1,6 +1,6 @@ > ;--------------------------------------------------------------------------- --- > > ; > > -; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR> > > +; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR> > > ; SPDX-License-Identifier: BSD-2-Clause-Patent > > ; > > ; Module Name: > > @@ -27,9 +27,6 @@ > ;--------------------------------------------------------------------------- --- > > global ASM_PFX(AsmReadMm0) > > ASM_PFX(AsmReadMm0): > > - ; > > - ; 64-bit MASM doesn't support MMX instructions, so use opcode here > > - ; > > - DB 0x48, 0xf, 0x7e, 0xc0 > > + movq rax, mm0 > > ret > > > > diff --git a/MdePkg/Library/BaseLib/X64/ReadMm1.nasm > b/MdePkg/Library/BaseLib/X64/ReadMm1.nasm > index 7b27393490..bec3c71207 100644 > --- a/MdePkg/Library/BaseLib/X64/ReadMm1.nasm > +++ b/MdePkg/Library/BaseLib/X64/ReadMm1.nasm > @@ -1,6 +1,6 @@ > ;--------------------------------------------------------------------------- --- > > ; > > -; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR> > > +; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR> > > ; SPDX-License-Identifier: BSD-2-Clause-Patent > > ; > > ; Module Name: > > @@ -27,9 +27,6 @@ > ;--------------------------------------------------------------------------- --- > > global ASM_PFX(AsmReadMm1) > > ASM_PFX(AsmReadMm1): > > - ; > > - ; 64-bit MASM doesn't support MMX instructions, so use opcode here > > - ; > > - DB 0x48, 0xf, 0x7e, 0xc8 > > + movq rax, mm1 > > ret > > > > diff --git a/MdePkg/Library/BaseLib/X64/ReadMm2.nasm > b/MdePkg/Library/BaseLib/X64/ReadMm2.nasm > index c654b91a7a..4c880697cb 100644 > --- a/MdePkg/Library/BaseLib/X64/ReadMm2.nasm > +++ b/MdePkg/Library/BaseLib/X64/ReadMm2.nasm > @@ -1,6 +1,6 @@ > ;--------------------------------------------------------------------------- --- > > ; > > -; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR> > > +; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR> > > ; SPDX-License-Identifier: BSD-2-Clause-Patent > > ; > > ; Module Name: > > @@ -27,9 +27,6 @@ > ;--------------------------------------------------------------------------- --- > > global ASM_PFX(AsmReadMm2) > > ASM_PFX(AsmReadMm2): > > - ; > > - ; 64-bit MASM doesn't support MMX instructions, so use opcode here > > - ; > > - DB 0x48, 0xf, 0x7e, 0xd0 > > + movq rax, mm2 > > ret > > > > diff --git a/MdePkg/Library/BaseLib/X64/ReadMm3.nasm > b/MdePkg/Library/BaseLib/X64/ReadMm3.nasm > index 88d51c0781..cf81e5a7ab 100644 > --- a/MdePkg/Library/BaseLib/X64/ReadMm3.nasm > +++ b/MdePkg/Library/BaseLib/X64/ReadMm3.nasm > @@ -1,6 +1,6 @@ > ;--------------------------------------------------------------------------- --- > > ; > > -; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR> > > +; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR> > > ; SPDX-License-Identifier: BSD-2-Clause-Patent > > ; > > ; Module Name: > > @@ -27,9 +27,6 @@ > ;--------------------------------------------------------------------------- --- > > global ASM_PFX(AsmReadMm3) > > ASM_PFX(AsmReadMm3): > > - ; > > - ; 64-bit MASM doesn't support MMX instructions, so use opcode here > > - ; > > - DB 0x48, 0xf, 0x7e, 0xd8 > > + movq rax, mm3 > > ret > > > > diff --git a/MdePkg/Library/BaseLib/X64/ReadMm4.nasm > b/MdePkg/Library/BaseLib/X64/ReadMm4.nasm > index 4252d20bb1..17ba364e32 100644 > --- a/MdePkg/Library/BaseLib/X64/ReadMm4.nasm > +++ b/MdePkg/Library/BaseLib/X64/ReadMm4.nasm > @@ -1,6 +1,6 @@ > ;--------------------------------------------------------------------------- --- > > ; > > -; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR> > > +; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR> > > ; SPDX-License-Identifier: BSD-2-Clause-Patent > > ; > > ; Module Name: > > @@ -27,9 +27,6 @@ > ;--------------------------------------------------------------------------- --- > > global ASM_PFX(AsmReadMm4) > > ASM_PFX(AsmReadMm4): > > - ; > > - ; 64-bit MASM doesn't support MMX instructions, so use opcode here > > - ; > > - DB 0x48, 0xf, 0x7e, 0xe0 > > + movq rax, mm4 > > ret > > > > diff --git a/MdePkg/Library/BaseLib/X64/ReadMm5.nasm > b/MdePkg/Library/BaseLib/X64/ReadMm5.nasm > index d8f530dec8..f1354dd68c 100644 > --- a/MdePkg/Library/BaseLib/X64/ReadMm5.nasm > +++ b/MdePkg/Library/BaseLib/X64/ReadMm5.nasm > @@ -1,6 +1,6 @@ > ;--------------------------------------------------------------------------- --- > > ; > > -; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR> > > +; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR> > > ; SPDX-License-Identifier: BSD-2-Clause-Patent > > ; > > ; Module Name: > > @@ -27,9 +27,6 @@ > ;--------------------------------------------------------------------------- --- > > global ASM_PFX(AsmReadMm5) > > ASM_PFX(AsmReadMm5): > > - ; > > - ; 64-bit MASM doesn't support MMX instructions, so use opcode here > > - ; > > - DB 0x48, 0xf, 0x7e, 0xe8 > > + movq rax, mm5 > > ret > > > > diff --git a/MdePkg/Library/BaseLib/X64/ReadMm6.nasm > b/MdePkg/Library/BaseLib/X64/ReadMm6.nasm > index 6f6883c2b6..9d5a287218 100644 > --- a/MdePkg/Library/BaseLib/X64/ReadMm6.nasm > +++ b/MdePkg/Library/BaseLib/X64/ReadMm6.nasm > @@ -1,6 +1,6 @@ > ;--------------------------------------------------------------------------- --- > > ; > > -; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR> > > +; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR> > > ; SPDX-License-Identifier: BSD-2-Clause-Patent > > ; > > ; Module Name: > > @@ -27,9 +27,6 @@ > ;--------------------------------------------------------------------------- --- > > global ASM_PFX(AsmReadMm6) > > ASM_PFX(AsmReadMm6): > > - ; > > - ; 64-bit MASM doesn't support MMX instructions, so use opcode here > > - ; > > - DB 0x48, 0xf, 0x7e, 0xf0 > > + movq rax, mm6 > > ret > > > > diff --git a/MdePkg/Library/BaseLib/X64/ReadMm7.nasm > b/MdePkg/Library/BaseLib/X64/ReadMm7.nasm > index 573f15dfc8..ae15f24d8b 100644 > --- a/MdePkg/Library/BaseLib/X64/ReadMm7.nasm > +++ b/MdePkg/Library/BaseLib/X64/ReadMm7.nasm > @@ -1,6 +1,6 @@ > ;--------------------------------------------------------------------------- --- > > ; > > -; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR> > > +; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR> > > ; SPDX-License-Identifier: BSD-2-Clause-Patent > > ; > > ; Module Name: > > @@ -27,9 +27,6 @@ > ;--------------------------------------------------------------------------- --- > > global ASM_PFX(AsmReadMm7) > > ASM_PFX(AsmReadMm7): > > - ; > > - ; 64-bit MASM doesn't support MMX instructions, so use opcode here > > - ; > > - DB 0x48, 0xf, 0x7e, 0xf8 > > + movq rax, mm7 > > ret > > > > diff --git a/MdePkg/Library/BaseLib/X64/SetJump.nasm > b/MdePkg/Library/BaseLib/X64/SetJump.nasm > index 5a68396eec..5943a5ebe5 100644 > --- a/MdePkg/Library/BaseLib/X64/SetJump.nasm > +++ b/MdePkg/Library/BaseLib/X64/SetJump.nasm > @@ -1,6 +1,6 @@ > ;--------------------------------------------------------------------------- --- > > ; > > -; Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR> > > +; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR> > > ; SPDX-License-Identifier: BSD-2-Clause-Patent > > ; > > ; Module Name: > > @@ -48,8 +48,8 @@ ASM_PFX(SetJump): > jnc CetDone > > > > mov rax, 1 > > - INCSSP_RAX ; to read original SSP > > - READSSP_RAX > > + incsspq rax ; to read original SSP > > + rdsspq rax > > mov [rcx + 0xF8], rax ; save SSP > > > > CetDone: > > diff --git a/MdePkg/Library/BaseLib/X64/WriteDr4.nasm > b/MdePkg/Library/BaseLib/X64/WriteDr4.nasm > index c4b12c9e92..5e4d96015e 100644 > --- a/MdePkg/Library/BaseLib/X64/WriteDr4.nasm > +++ b/MdePkg/Library/BaseLib/X64/WriteDr4.nasm > @@ -1,6 +1,6 @@ > ;--------------------------------------------------------------------------- --- > > ; > > -; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR> > > +; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR> > > ; SPDX-License-Identifier: BSD-2-Clause-Patent > > ; > > ; Module Name: > > @@ -31,7 +31,7 @@ ASM_PFX(AsmWriteDr4): > ; There's no obvious reason to access this register, since it's aliased to > > ; DR6 when DE=0 or an exception generated when DE=1 > > ; > > - DB 0xf, 0x23, 0xe1 > > + mov dr4, rcx > > mov rax, rcx > > ret > > > > diff --git a/MdePkg/Library/BaseLib/X64/WriteDr5.nasm > b/MdePkg/Library/BaseLib/X64/WriteDr5.nasm > index 986a4a95d9..d5d4e2f324 100644 > --- a/MdePkg/Library/BaseLib/X64/WriteDr5.nasm > +++ b/MdePkg/Library/BaseLib/X64/WriteDr5.nasm > @@ -1,6 +1,6 @@ > ;--------------------------------------------------------------------------- --- > > ; > > -; Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR> > > +; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR> > > ; SPDX-License-Identifier: BSD-2-Clause-Patent > > ; > > ; Module Name: > > @@ -31,7 +31,7 @@ ASM_PFX(AsmWriteDr5): > ; There's no obvious reason to access this register, since it's aliased to > > ; DR7 when DE=0 or an exception generated when DE=1 > > ; > > - DB 0xf, 0x23, 0xe9 > > + mov dr5, rcx > > mov rax, rcx > > ret > > > > diff --git a/MdePkg/Library/BaseLib/X64/WriteMm0.nasm > b/MdePkg/Library/BaseLib/X64/WriteMm0.nasm > index 3f03529edf..e6b5a0fc33 100644 > --- a/MdePkg/Library/BaseLib/X64/WriteMm0.nasm > +++ b/MdePkg/Library/BaseLib/X64/WriteMm0.nasm > @@ -1,6 +1,6 @@ > ;--------------------------------------------------------------------------- --- > > ; > > -; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR> > > +; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR> > > ; SPDX-License-Identifier: BSD-2-Clause-Patent > > ; > > ; Module Name: > > @@ -27,9 +27,6 @@ > ;--------------------------------------------------------------------------- --- > > global ASM_PFX(AsmWriteMm0) > > ASM_PFX(AsmWriteMm0): > > - ; > > - ; 64-bit MASM doesn't support MMX instructions, so use opcode here > > - ; > > - DB 0x48, 0xf, 0x6e, 0xc1 > > + movq mm0, rcx > > ret > > > > diff --git a/MdePkg/Library/BaseLib/X64/WriteMm1.nasm > b/MdePkg/Library/BaseLib/X64/WriteMm1.nasm > index f552d40716..414c6af6da 100644 > --- a/MdePkg/Library/BaseLib/X64/WriteMm1.nasm > +++ b/MdePkg/Library/BaseLib/X64/WriteMm1.nasm > @@ -1,6 +1,6 @@ > ;--------------------------------------------------------------------------- --- > > ; > > -; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR> > > +; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR> > > ; SPDX-License-Identifier: BSD-2-Clause-Patent > > ; > > ; Module Name: > > @@ -27,9 +27,6 @@ > ;--------------------------------------------------------------------------- --- > > global ASM_PFX(AsmWriteMm1) > > ASM_PFX(AsmWriteMm1): > > - ; > > - ; 64-bit MASM doesn't support MMX instructions, so use opcode here > > - ; > > - DB 0x48, 0xf, 0x6e, 0xc9 > > + movq mm1, rcx > > ret > > > > diff --git a/MdePkg/Library/BaseLib/X64/WriteMm2.nasm > b/MdePkg/Library/BaseLib/X64/WriteMm2.nasm > index 1bd176ced9..525740342a 100644 > --- a/MdePkg/Library/BaseLib/X64/WriteMm2.nasm > +++ b/MdePkg/Library/BaseLib/X64/WriteMm2.nasm > @@ -1,6 +1,6 @@ > ;--------------------------------------------------------------------------- --- > > ; > > -; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR> > > +; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR> > > ; SPDX-License-Identifier: BSD-2-Clause-Patent > > ; > > ; Module Name: > > @@ -27,9 +27,6 @@ > ;--------------------------------------------------------------------------- --- > > global ASM_PFX(AsmWriteMm2) > > ASM_PFX(AsmWriteMm2): > > - ; > > - ; 64-bit MASM doesn't support MMX instructions, so use opcode here > > - ; > > - DB 0x48, 0xf, 0x6e, 0xd1 > > + movq mm2, rcx > > ret > > > > diff --git a/MdePkg/Library/BaseLib/X64/WriteMm3.nasm > b/MdePkg/Library/BaseLib/X64/WriteMm3.nasm > index 403f140736..abf11bfb17 100644 > --- a/MdePkg/Library/BaseLib/X64/WriteMm3.nasm > +++ b/MdePkg/Library/BaseLib/X64/WriteMm3.nasm > @@ -1,6 +1,6 @@ > ;--------------------------------------------------------------------------- --- > > ; > > -; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR> > > +; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR> > > ; SPDX-License-Identifier: BSD-2-Clause-Patent > > ; > > ; Module Name: > > @@ -27,9 +27,6 @@ > ;--------------------------------------------------------------------------- --- > > global ASM_PFX(AsmWriteMm3) > > ASM_PFX(AsmWriteMm3): > > - ; > > - ; 64-bit MASM doesn't support MMX instructions, so use opcode here > > - ; > > - DB 0x48, 0xf, 0x6e, 0xd9 > > + movq mm3, rcx > > ret > > > > diff --git a/MdePkg/Library/BaseLib/X64/WriteMm4.nasm > b/MdePkg/Library/BaseLib/X64/WriteMm4.nasm > index d99709d495..7cbd25e70a 100644 > --- a/MdePkg/Library/BaseLib/X64/WriteMm4.nasm > +++ b/MdePkg/Library/BaseLib/X64/WriteMm4.nasm > @@ -1,6 +1,6 @@ > ;--------------------------------------------------------------------------- --- > > ; > > -; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR> > > +; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR> > > ; SPDX-License-Identifier: BSD-2-Clause-Patent > > ; > > ; Module Name: > > @@ -27,9 +27,6 @@ > ;--------------------------------------------------------------------------- --- > > global ASM_PFX(AsmWriteMm4) > > ASM_PFX(AsmWriteMm4): > > - ; > > - ; 64-bit MASM doesn't support MMX instructions, so use opcode here > > - ; > > - DB 0x48, 0xf, 0x6e, 0xe1 > > + movq mm4, rcx > > ret > > > > diff --git a/MdePkg/Library/BaseLib/X64/WriteMm5.nasm > b/MdePkg/Library/BaseLib/X64/WriteMm5.nasm > index 0467ac4220..9edfd0db83 100644 > --- a/MdePkg/Library/BaseLib/X64/WriteMm5.nasm > +++ b/MdePkg/Library/BaseLib/X64/WriteMm5.nasm > @@ -1,6 +1,6 @@ > ;--------------------------------------------------------------------------- --- > > ; > > -; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR> > > +; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR> > > ; SPDX-License-Identifier: BSD-2-Clause-Patent > > ; > > ; Module Name: > > @@ -27,9 +27,6 @@ > ;--------------------------------------------------------------------------- --- > > global ASM_PFX(AsmWriteMm5) > > ASM_PFX(AsmWriteMm5): > > - ; > > - ; 64-bit MASM doesn't support MMX instructions, so use opcode here > > - ; > > - DB 0x48, 0xf, 0x6e, 0xe9 > > + movq mm5, rcx > > ret > > > > diff --git a/MdePkg/Library/BaseLib/X64/WriteMm6.nasm > b/MdePkg/Library/BaseLib/X64/WriteMm6.nasm > index 6d2e5eb8fb..4555563a55 100644 > --- a/MdePkg/Library/BaseLib/X64/WriteMm6.nasm > +++ b/MdePkg/Library/BaseLib/X64/WriteMm6.nasm > @@ -1,6 +1,6 @@ > ;--------------------------------------------------------------------------- --- > > ; > > -; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR> > > +; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR> > > ; SPDX-License-Identifier: BSD-2-Clause-Patent > > ; > > ; Module Name: > > @@ -27,9 +27,6 @@ > ;--------------------------------------------------------------------------- --- > > global ASM_PFX(AsmWriteMm6) > > ASM_PFX(AsmWriteMm6): > > - ; > > - ; 64-bit MASM doesn't support MMX instructions, so use opcode here > > - ; > > - DB 0x48, 0xf, 0x6e, 0xf1 > > + movq mm6, rcx > > ret > > > > diff --git a/MdePkg/Library/BaseLib/X64/WriteMm7.nasm > b/MdePkg/Library/BaseLib/X64/WriteMm7.nasm > index de72adf685..4ef0eb5271 100644 > --- a/MdePkg/Library/BaseLib/X64/WriteMm7.nasm > +++ b/MdePkg/Library/BaseLib/X64/WriteMm7.nasm > @@ -1,6 +1,6 @@ > ;--------------------------------------------------------------------------- --- > > ; > > -; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR> > > +; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR> > > ; SPDX-License-Identifier: BSD-2-Clause-Patent > > ; > > ; Module Name: > > @@ -27,9 +27,6 @@ > ;--------------------------------------------------------------------------- --- > > global ASM_PFX(AsmWriteMm7) > > ASM_PFX(AsmWriteMm7): > > - ; > > - ; 64-bit MASM doesn't support MMX instructions, so use opcode here > > - ; > > - DB 0x48, 0xf, 0x6e, 0xf9 > > + movq mm7, rcx > > ret > > > > diff --git a/MdePkg/Library/BaseMemoryLibMmx/X64/CopyMem.nasm > b/MdePkg/Library/BaseMemoryLibMmx/X64/CopyMem.nasm > index 5769c00bf9..3b336c6bdf 100644 > --- a/MdePkg/Library/BaseMemoryLibMmx/X64/CopyMem.nasm > +++ b/MdePkg/Library/BaseMemoryLibMmx/X64/CopyMem.nasm > @@ -1,6 +1,6 @@ > ;--------------------------------------------------------------------------- --- > > ; > > -; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR> > > +; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR> > > ; SPDX-License-Identifier: BSD-2-Clause-Patent > > ; > > ; Module Name: > > @@ -44,15 +44,15 @@ ASM_PFX(InternalMemCopyMem): > and r8, 7 > > shr rcx, 3 ; rcx <- # of Qwords to copy > > jz @CopyBytes > > - DB 0x49, 0xf, 0x7e, 0xc2 ; movd r10, mm0 (Save mm0 > in r10) > > + movq r10, mm0 > > .1: > > - DB 0xf, 0x6f, 0x6 ; movd mm0, [rsi] > > - DB 0xf, 0xe7, 0x7 ; movntq [rdi], mm0 > > + movq mm0, [rsi] > > + movntq [rdi], mm0 > > add rsi, 8 > > add rdi, 8 > > loop .1 > > mfence > > - DB 0x49, 0xf, 0x6e, 0xc2 ; movd mm0, r10 (Restore > mm0) > > + movq mm0, r10 > > jmp @CopyBytes > > @CopyBackward: > > mov rsi, r9 ; rsi <- End of Source > > diff --git a/MdePkg/Library/BaseMemoryLibMmx/X64/SetMem.nasm > b/MdePkg/Library/BaseMemoryLibMmx/X64/SetMem.nasm > index 450113ba84..af584e3d34 100644 > --- a/MdePkg/Library/BaseMemoryLibMmx/X64/SetMem.nasm > +++ b/MdePkg/Library/BaseMemoryLibMmx/X64/SetMem.nasm > @@ -1,6 +1,6 @@ > ;--------------------------------------------------------------------------- --- > > ; > > -; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR> > > +; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR> > > ; SPDX-License-Identifier: BSD-2-Clause-Patent > > ; > > ; Module Name: > > @@ -32,16 +32,16 @@ ASM_PFX(InternalMemSetMem): > push rdi > > mov rax, r8 > > mov ah, al > > - DB 0x48, 0xf, 0x6e, 0xc0 ; movd mm0, rax > > + movq mm0, rax > > mov r8, rcx > > mov rdi, r8 ; rdi <- Buffer > > mov rcx, rdx > > and edx, 7 > > shr rcx, 3 > > jz @SetBytes > > - DB 0xf, 0x70, 0xC0, 0x0 ; pshufw mm0, mm0, 0h > > + pshufw mm0, mm0, 0 > > .0: > > - DB 0xf, 0xe7, 0x7 ; movntq [rdi], mm0 > > + movntq [rdi], mm0 > > add rdi, 8 > > loop .0 > > mfence > > diff --git a/MdePkg/Library/BaseMemoryLibMmx/X64/SetMem16.nasm > b/MdePkg/Library/BaseMemoryLibMmx/X64/SetMem16.nasm > index 4e1f4be2b4..7a63a1c50b 100644 > --- a/MdePkg/Library/BaseMemoryLibMmx/X64/SetMem16.nasm > +++ b/MdePkg/Library/BaseMemoryLibMmx/X64/SetMem16.nasm > @@ -1,6 +1,6 @@ > ;--------------------------------------------------------------------------- --- > > ; > > -; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR> > > +; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR> > > ; SPDX-License-Identifier: BSD-2-Clause-Patent > > ; > > ; Module Name: > > @@ -31,16 +31,16 @@ global ASM_PFX(InternalMemSetMem16) > ASM_PFX(InternalMemSetMem16): > > push rdi > > mov rax, r8 > > - DB 0x48, 0xf, 0x6e, 0xc0 ; movd mm0, rax > > + movq mm0, rax > > mov r8, rcx > > mov rdi, r8 > > mov rcx, rdx > > and edx, 3 > > shr rcx, 2 > > jz @SetWords > > - DB 0xf, 0x70, 0xC0, 0x0 ; pshufw mm0, mm0, 0h > > + pshufw mm0, mm0, 0 > > .0: > > - DB 0xf, 0xe7, 0x7 ; movntq [rdi], mm0 > > + movntq [rdi], mm0 > > add rdi, 8 > > loop .0 > > mfence > > diff --git a/MdePkg/Library/BaseMemoryLibMmx/X64/SetMem32.nasm > b/MdePkg/Library/BaseMemoryLibMmx/X64/SetMem32.nasm > index b3a7385897..ab5f954826 100644 > --- a/MdePkg/Library/BaseMemoryLibMmx/X64/SetMem32.nasm > +++ b/MdePkg/Library/BaseMemoryLibMmx/X64/SetMem32.nasm > @@ -1,6 +1,6 @@ > ;--------------------------------------------------------------------------- --- > > ; > > -; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR> > > +; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR> > > ; SPDX-License-Identifier: BSD-2-Clause-Patent > > ; > > ; Module Name: > > @@ -28,20 +28,20 @@ > ;--------------------------------------------------------------------------- --- > > global ASM_PFX(InternalMemSetMem32) > > ASM_PFX(InternalMemSetMem32): > > - DB 0x49, 0xf, 0x6e, 0xc0 ; movd mm0, r8 (Value) > > + movq mm0, r8 > > mov rax, rcx ; rax <- Buffer > > xchg rcx, rdx ; rcx <- Count rdx <- Buffer > > shr rcx, 1 ; rcx <- # of qwords to set > > jz @SetDwords > > - DB 0xf, 0x70, 0xC0, 0x44 ; pshufw mm0, mm0, 44h > > + pshufw mm0, mm0, 44h > > .0: > > - DB 0xf, 0xe7, 0x2 ; movntq [rdx], mm0 > > + movntq [rdx], mm0 > > lea rdx, [rdx + 8] ; use "lea" to avoid flag changes > > loop .0 > > mfence > > @SetDwords: > > jnc .1 > > - DB 0xf, 0x7e, 0x2 ; movd [rdx], mm0 > > + movd [rdx], mm0 > > .1: > > ret > > > > diff --git a/MdePkg/Library/BaseMemoryLibMmx/X64/SetMem64.nasm > b/MdePkg/Library/BaseMemoryLibMmx/X64/SetMem64.nasm > index f517e1d23a..fcc44294a8 100644 > --- a/MdePkg/Library/BaseMemoryLibMmx/X64/SetMem64.nasm > +++ b/MdePkg/Library/BaseMemoryLibMmx/X64/SetMem64.nasm > @@ -1,6 +1,6 @@ > ;--------------------------------------------------------------------------- --- > > ; > > -; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR> > > +; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR> > > ; SPDX-License-Identifier: BSD-2-Clause-Patent > > ; > > ; Module Name: > > @@ -28,11 +28,11 @@ > ;--------------------------------------------------------------------------- --- > > global ASM_PFX(InternalMemSetMem64) > > ASM_PFX(InternalMemSetMem64): > > - DB 0x49, 0xf, 0x6e, 0xc0 ; movd mm0, r8 (Value) > > + movq mm0, r8 > > mov rax, rcx ; rax <- Buffer > > xchg rcx, rdx ; rcx <- Count > > .0: > > - DB 0xf, 0xe7, 0x2 ; movntq [rdx], mm0 > > + movntq [rdx], mm0 > > add rdx, 8 > > loop .0 > > mfence > > diff --git a/MdePkg/Library/BaseMemoryLibMmx/X64/ZeroMem.nasm > b/MdePkg/Library/BaseMemoryLibMmx/X64/ZeroMem.nasm > index 2a85f15b55..8b02eeb732 100644 > --- a/MdePkg/Library/BaseMemoryLibMmx/X64/ZeroMem.nasm > +++ b/MdePkg/Library/BaseMemoryLibMmx/X64/ZeroMem.nasm > @@ -1,6 +1,6 @@ > ;--------------------------------------------------------------------------- --- > > ; > > -; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR> > > +; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR> > > ; SPDX-License-Identifier: BSD-2-Clause-Patent > > ; > > ; Module Name: > > @@ -34,12 +34,12 @@ ASM_PFX(InternalMemZeroMem): > and edx, 7 > > shr rcx, 3 > > jz @ZeroBytes > > - DB 0xf, 0xef, 0xc0 ; pxor mm0, mm0 > > + pxor mm0, mm0 > > .0: > > - DB 0xf, 0xe7, 7 ; movntq [rdi], mm0 > > + movntq [rdi], mm0 > > add rdi, 8 > > loop .0 > > - DB 0xf, 0xae, 0xf0 ; mfence > > + mfence > > @ZeroBytes: > > xor eax, eax > > mov ecx, edx > > -- > 2.28.0.windows.1 > > > > -=-=-=-=-=-= > Groups.io Links: You receive all messages sent to this group. > View/Reply Online (#85475): https://edk2.groups.io/g/devel/message/85475 > Mute This Topic: https://groups.io/mt/88325168/4905953 > Group Owner: devel+owner@edk2.groups.io > Unsubscribe: https://edk2.groups.io/g/devel/unsub > [gaoliming@byosoft.com.cn] > -=-=-=-=-=-= > ^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH v2 3/6] SourceLevelDebugPkg: Replace Opcode with the corresponding instructions. 2022-01-10 15:12 [PATCH v2 1/6] MdeModulePkg: Replace Opcode with the corresponding instructions Jason Lou 2022-01-10 15:12 ` [PATCH v2 2/6] MdePkg: " Jason Lou @ 2022-01-10 15:12 ` Jason Lou 2022-01-11 1:03 ` Wu, Hao A 2022-01-10 15:12 ` [PATCH v2 4/6] UefiCpuPkg: " Jason Lou ` (3 subsequent siblings) 5 siblings, 1 reply; 12+ messages in thread From: Jason Lou @ 2022-01-10 15:12 UTC (permalink / raw) To: devel; +Cc: Jason, Hao A Wu REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3790 Replace Opcode with the corresponding instructions. The code changes have been verified with CompareBuild.py tool, which can be used to compare the results of two different EDK II builds to determine if they generate the same binaries. (tool link: https://github.com/mdkinney/edk2/tree/sandbox/CompareBuild) Signed-off-by: Jason Lou <yun.lou@intel.com> Cc: Hao A Wu <hao.a.wu@intel.com> --- SourceLevelDebugPkg/Library/DebugAgent/DebugAgentCommon/Ia32/AsmFuncs.nasm | 6 +++--- SourceLevelDebugPkg/Library/DebugAgent/DebugAgentCommon/X64/AsmFuncs.nasm | 6 +++--- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/SourceLevelDebugPkg/Library/DebugAgent/DebugAgentCommon/Ia32/AsmFuncs.nasm b/SourceLevelDebugPkg/Library/DebugAgent/DebugAgentCommon/Ia32/AsmFuncs.nasm index 912256ba45..b5e5a96e34 100644 --- a/SourceLevelDebugPkg/Library/DebugAgent/DebugAgentCommon/Ia32/AsmFuncs.nasm +++ b/SourceLevelDebugPkg/Library/DebugAgent/DebugAgentCommon/Ia32/AsmFuncs.nasm @@ -1,6 +1,6 @@ ;------------------------------------------------------------------------------ ; -; Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.<BR> +; Copyright (c) 2010 - 2022, Intel Corporation. All rights reserved.<BR> ; SPDX-License-Identifier: BSD-2-Clause-Patent ; ; Module Name: @@ -321,7 +321,7 @@ NoExtrPush: test edx, BIT24 ; Test for FXSAVE/FXRESTOR support. ; edx still contains result from CPUID above jz .2 - db 0xf, 0xae, 00000111y ;fxsave [edi] + fxsave [edi] .2: ;; save the exception data @@ -342,7 +342,7 @@ NoExtrPush: cpuid ; use CPUID to determine if FXSAVE/FXRESTOR are supported test edx, BIT24 ; Test for FXSAVE/FXRESTOR support jz .3 - db 0xf, 0xae, 00001110y ; fxrstor [esi] + fxrstor [esi] .3: add esp, 512 diff --git a/SourceLevelDebugPkg/Library/DebugAgent/DebugAgentCommon/X64/AsmFuncs.nasm b/SourceLevelDebugPkg/Library/DebugAgent/DebugAgentCommon/X64/AsmFuncs.nasm index ccee120ca1..b1019e017b 100644 --- a/SourceLevelDebugPkg/Library/DebugAgent/DebugAgentCommon/X64/AsmFuncs.nasm +++ b/SourceLevelDebugPkg/Library/DebugAgent/DebugAgentCommon/X64/AsmFuncs.nasm @@ -1,6 +1,6 @@ ;------------------------------------------------------------------------------ ; -; Copyright (c) 2016, Intel Corporation. All rights reserved.<BR> +; Copyright (c) 2016 - 2022, Intel Corporation. All rights reserved.<BR> ; SPDX-License-Identifier: BSD-2-Clause-Patent ; ; Module Name: @@ -293,7 +293,7 @@ NoExtrPush: rep stosq pop rcx mov rdi, rsp - db 0xf, 0xae, 00000111y ;fxsave [rdi] + fxsave [rdi] ;; save the exception data push qword [rbp + 16] @@ -314,7 +314,7 @@ NoExtrPush: add rsp, 8 mov rsi, rsp - db 0xf, 0xae, 00001110y ; fxrstor [rsi] + fxrstor [rsi] add rsp, 512 ;; UINT64 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7; -- 2.28.0.windows.1 ^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [PATCH v2 3/6] SourceLevelDebugPkg: Replace Opcode with the corresponding instructions. 2022-01-10 15:12 ` [PATCH v2 3/6] SourceLevelDebugPkg: " Jason Lou @ 2022-01-11 1:03 ` Wu, Hao A 0 siblings, 0 replies; 12+ messages in thread From: Wu, Hao A @ 2022-01-11 1:03 UTC (permalink / raw) To: Lou, Yun, devel@edk2.groups.io Reviewed-by: Hao A Wu <hao.a.wu@intel.com> Best Regards, Hao Wu > -----Original Message----- > From: Lou, Yun <yun.lou@intel.com> > Sent: Monday, January 10, 2022 11:13 PM > To: devel@edk2.groups.io > Cc: Lou, Yun <yun.lou@intel.com>; Wu, Hao A <hao.a.wu@intel.com> > Subject: [PATCH v2 3/6] SourceLevelDebugPkg: Replace Opcode with the > corresponding instructions. > > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3790 > > Replace Opcode with the corresponding instructions. > The code changes have been verified with CompareBuild.py tool, which > can be used to compare the results of two different EDK II builds to > determine if they generate the same binaries. > (tool link: https://github.com/mdkinney/edk2/tree/sandbox/CompareBuild) > > Signed-off-by: Jason Lou <yun.lou@intel.com> > Cc: Hao A Wu <hao.a.wu@intel.com> > --- > > SourceLevelDebugPkg/Library/DebugAgent/DebugAgentCommon/Ia32/Asm > Funcs.nasm | 6 +++--- > > SourceLevelDebugPkg/Library/DebugAgent/DebugAgentCommon/X64/Asm > Funcs.nasm | 6 +++--- > 2 files changed, 6 insertions(+), 6 deletions(-) > > diff --git > a/SourceLevelDebugPkg/Library/DebugAgent/DebugAgentCommon/Ia32/As > mFuncs.nasm > b/SourceLevelDebugPkg/Library/DebugAgent/DebugAgentCommon/Ia32/A > smFuncs.nasm > index 912256ba45..b5e5a96e34 100644 > --- > a/SourceLevelDebugPkg/Library/DebugAgent/DebugAgentCommon/Ia32/As > mFuncs.nasm > +++ > b/SourceLevelDebugPkg/Library/DebugAgent/DebugAgentCommon/Ia32/A > smFuncs.nasm > @@ -1,6 +1,6 @@ > ;------------------------------------------------------------------------------ > > ; > > -; Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.<BR> > > +; Copyright (c) 2010 - 2022, Intel Corporation. All rights reserved.<BR> > > ; SPDX-License-Identifier: BSD-2-Clause-Patent > > ; > > ; Module Name: > > @@ -321,7 +321,7 @@ NoExtrPush: > test edx, BIT24 ; Test for FXSAVE/FXRESTOR support. > > ; edx still contains result from CPUID above > > jz .2 > > - db 0xf, 0xae, 00000111y ;fxsave [edi] > > + fxsave [edi] > > .2: > > > > ;; save the exception data > > @@ -342,7 +342,7 @@ NoExtrPush: > cpuid ; use CPUID to determine if FXSAVE/FXRESTOR are supported > > test edx, BIT24 ; Test for FXSAVE/FXRESTOR support > > jz .3 > > - db 0xf, 0xae, 00001110y ; fxrstor [esi] > > + fxrstor [esi] > > .3: > > add esp, 512 > > > > diff --git > a/SourceLevelDebugPkg/Library/DebugAgent/DebugAgentCommon/X64/As > mFuncs.nasm > b/SourceLevelDebugPkg/Library/DebugAgent/DebugAgentCommon/X64/As > mFuncs.nasm > index ccee120ca1..b1019e017b 100644 > --- > a/SourceLevelDebugPkg/Library/DebugAgent/DebugAgentCommon/X64/As > mFuncs.nasm > +++ > b/SourceLevelDebugPkg/Library/DebugAgent/DebugAgentCommon/X64/As > mFuncs.nasm > @@ -1,6 +1,6 @@ > ;------------------------------------------------------------------------------ > > ; > > -; Copyright (c) 2016, Intel Corporation. All rights reserved.<BR> > > +; Copyright (c) 2016 - 2022, Intel Corporation. All rights reserved.<BR> > > ; SPDX-License-Identifier: BSD-2-Clause-Patent > > ; > > ; Module Name: > > @@ -293,7 +293,7 @@ NoExtrPush: > rep stosq > > pop rcx > > mov rdi, rsp > > - db 0xf, 0xae, 00000111y ;fxsave [rdi] > > + fxsave [rdi] > > > > ;; save the exception data > > push qword [rbp + 16] > > @@ -314,7 +314,7 @@ NoExtrPush: > add rsp, 8 > > > > mov rsi, rsp > > - db 0xf, 0xae, 00001110y ; fxrstor [rsi] > > + fxrstor [rsi] > > add rsp, 512 > > > > ;; UINT64 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7; > > -- > 2.28.0.windows.1 ^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH v2 4/6] UefiCpuPkg: Replace Opcode with the corresponding instructions. 2022-01-10 15:12 [PATCH v2 1/6] MdeModulePkg: Replace Opcode with the corresponding instructions Jason Lou 2022-01-10 15:12 ` [PATCH v2 2/6] MdePkg: " Jason Lou 2022-01-10 15:12 ` [PATCH v2 3/6] SourceLevelDebugPkg: " Jason Lou @ 2022-01-10 15:12 ` Jason Lou 2022-02-10 5:35 ` Ni, Ray 2022-01-10 15:12 ` [PATCH v2 5/6] MdePkg: Remove the macro definitions regarding Opcode Jason Lou ` (2 subsequent siblings) 5 siblings, 1 reply; 12+ messages in thread From: Jason Lou @ 2022-01-10 15:12 UTC (permalink / raw) To: devel; +Cc: Jason, Ray Ni, Eric Dong, Laszlo Ersek, Rahul Kumar REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3790 Replace Opcode with the corresponding instructions. The code changes have been verified with CompareBuild.py tool, which can be used to compare the results of two different EDK II builds to determine if they generate the same binaries. (tool link: https://github.com/mdkinney/edk2/tree/sandbox/CompareBuild) Signed-off-by: Jason Lou <yun.lou@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> --- UefiCpuPkg/CpuDxe/X64/CpuAsm.nasm | 4 +-- UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionHandlerAsm.nasm | 11 +++++---- UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionTssEntryAsm.nasm | 9 +++---- UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.nasm | 14 +++++------ UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/Xcode5ExceptionHandlerAsm.nasm | 26 ++++++++++---------- UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm | 6 ++--- UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/Cet.nasm | 4 +-- UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm | 4 +-- UefiCpuPkg/PiSmmCpuDxeSmm/X64/Cet.nasm | 4 +-- UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm | 4 +-- 10 files changed, 43 insertions(+), 43 deletions(-) diff --git a/UefiCpuPkg/CpuDxe/X64/CpuAsm.nasm b/UefiCpuPkg/CpuDxe/X64/CpuAsm.nasm index 66f8857fc0..a894ff53ad 100644 --- a/UefiCpuPkg/CpuDxe/X64/CpuAsm.nasm +++ b/UefiCpuPkg/CpuDxe/X64/CpuAsm.nasm @@ -1,6 +1,6 @@ ;------------------------------------------------------------------------------ ;* -;* Copyright (c) 2016, Intel Corporation. All rights reserved.<BR> +;* Copyright (c) 2016 - 2022, Intel Corporation. All rights reserved.<BR> ;* SPDX-License-Identifier: BSD-2-Clause-Patent ;* ;* CpuAsm.nasm @@ -23,7 +23,7 @@ ASM_PFX(SetCodeSelector): push rcx lea rax, [setCodeSelectorLongJump] push rax - o64 retf + retfq setCodeSelectorLongJump: ret diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionHandlerAsm.nasm b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionHandlerAsm.nasm index 58d5312899..3fe9aed1e8 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionHandlerAsm.nasm +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionHandlerAsm.nasm @@ -1,5 +1,5 @@ ;------------------------------------------------------------------------------ ; -; Copyright (c) 2016, Intel Corporation. All rights reserved.<BR> +; Copyright (c) 2016 - 2022, Intel Corporation. All rights reserved.<BR> ; SPDX-License-Identifier: BSD-2-Clause-Patent ; ; Module Name: @@ -32,12 +32,13 @@ ALIGN 8 ; exception handler stub table ; AsmIdtVectorBegin: +%assign Vector 0 %rep 32 - db 0x6a ; push #VectorNum - db ($ - AsmIdtVectorBegin) / ((AsmIdtVectorEnd - AsmIdtVectorBegin) / 32) ; VectorNum + push byte %[Vector]; push eax mov eax, ASM_PFX(CommonInterruptEntry) jmp eax +%assign Vector Vector+1 %endrep AsmIdtVectorEnd: @@ -287,7 +288,7 @@ ErrorCodeAndVectorOnStack: test edx, BIT24 ; Test for FXSAVE/FXRESTOR support. ; edx still contains result from CPUID above jz .3 - db 0xf, 0xae, 0x7 ;fxsave [edi] + fxsave [edi] .3: ;; UEFI calling convention for IA32 requires that Direction flag in EFLAGs is clear @@ -320,7 +321,7 @@ ErrorCodeAndVectorOnStack: ; are supported test edx, BIT24 ; Test for FXSAVE/FXRESTOR support jz .4 - db 0xf, 0xae, 0xe ; fxrstor [esi] + fxrstor [esi] .4: add esp, 512 diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionTssEntryAsm.nasm b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionTssEntryAsm.nasm index dd3f74d2aa..b63cfeac6d 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionTssEntryAsm.nasm +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionTssEntryAsm.nasm @@ -1,5 +1,5 @@ ;------------------------------------------------------------------------------ ; -; Copyright (c) 2017, Intel Corporation. All rights reserved.<BR> +; Copyright (c) 2017 - 2022, Intel Corporation. All rights reserved.<BR> ; SPDX-License-Identifier: BSD-2-Clause-Patent ; ; Module Name: @@ -79,8 +79,7 @@ AsmExceptionEntryBegin: DoIret%[Vector]: iretd ASM_PFX(ExceptionTaskSwtichEntry%[Vector]): - db 0x6a ; push #VectorNum - db %[Vector] + push byte %[Vector] mov eax, ASM_PFX(CommonTaskSwtichEntryPoint) call eax mov esp, eax ; Restore stack top @@ -244,7 +243,7 @@ ASM_PFX(CommonTaskSwtichEntryPoint): clts sub esp, 512 mov edi, esp - db 0xf, 0xae, 0x7 ;fxsave [edi] + fxsave [edi] .3: ;; UINT32 ExceptionData; @@ -277,7 +276,7 @@ ASM_PFX(CommonTaskSwtichEntryPoint): test edx, BIT24 ; Test for FXSAVE/FXRESTOR support jz .4 mov esi, esp - db 0xf, 0xae, 0xe ; fxrstor [esi] + fxrstor [esi] .4: add esp, 512 diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.nasm b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.nasm index 2a5545ecfd..9a806d1f86 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.nasm +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.nasm @@ -1,5 +1,5 @@ ;------------------------------------------------------------------------------ ; -; Copyright (c) 2012 - 2018, Intel Corporation. All rights reserved.<BR> +; Copyright (c) 2012 - 2022, Intel Corporation. All rights reserved.<BR> ; SPDX-License-Identifier: BSD-2-Clause-Patent ; ; Module Name: @@ -32,12 +32,13 @@ SECTION .text ALIGN 8 AsmIdtVectorBegin: +%assign Vector 0 %rep 32 - db 0x6a ; push #VectorNum - db ($ - AsmIdtVectorBegin) / ((AsmIdtVectorEnd - AsmIdtVectorBegin) / 32) ; VectorNum + push byte %[Vector] push rax mov rax, ASM_PFX(CommonInterruptEntry) jmp rax +%assign Vector Vector+1 %endrep AsmIdtVectorEnd: @@ -257,7 +258,7 @@ DrFinish: ;; FX_SAVE_STATE_X64 FxSaveState; sub rsp, 512 mov rdi, rsp - db 0xf, 0xae, 0x7 ;fxsave [rdi] + fxsave [rdi] ;; UEFI calling convention for x64 requires that Direction flag in EFLAGs is clear cld @@ -284,7 +285,7 @@ DrFinish: ;; FX_SAVE_STATE_X64 FxSaveState; mov rsi, rsp - db 0xf, 0xae, 0xE ; fxrstor [rsi] + fxrstor [rsi] add rsp, 512 ;; UINT64 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7; @@ -371,8 +372,7 @@ DoReturn: push qword [rax + 0x18] ; save EFLAGS in new location mov rax, [rax] ; restore rax popfq ; restore EFLAGS - DB 0x48 ; prefix to composite "retq" with next "retf" - retf ; far return + retfq DoIret: iretq diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/Xcode5ExceptionHandlerAsm.nasm b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/Xcode5ExceptionHandlerAsm.nasm index 84a12ddb88..9c72fa5815 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/Xcode5ExceptionHandlerAsm.nasm +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/Xcode5ExceptionHandlerAsm.nasm @@ -1,5 +1,5 @@ ;------------------------------------------------------------------------------ ; -; Copyright (c) 2012 - 2018, Intel Corporation. All rights reserved.<BR> +; Copyright (c) 2012 - 2022, Intel Corporation. All rights reserved.<BR> ; SPDX-License-Identifier: BSD-2-Clause-Patent ; ; Module Name: @@ -54,12 +54,13 @@ SECTION .text ALIGN 8 AsmIdtVectorBegin: +%assign Vector 0 %rep 32 - db 0x6a ; push #VectorNum - db ($ - AsmIdtVectorBegin) / ((AsmIdtVectorEnd - AsmIdtVectorBegin) / 32) ; VectorNum + push byte %[Vector] push rax mov rax, strict qword 0 ; mov rax, ASM_PFX(CommonInterruptEntry) jmp rax +%assign Vector Vector+1 %endrep AsmIdtVectorEnd: @@ -280,7 +281,7 @@ DrFinish: ;; FX_SAVE_STATE_X64 FxSaveState; sub rsp, 512 mov rdi, rsp - db 0xf, 0xae, 0x7 ;fxsave [rdi] + fxsave [rdi] ;; UEFI calling convention for x64 requires that Direction flag in EFLAGs is clear cld @@ -335,15 +336,15 @@ DrFinish: jz CetDone ; SSP should be 0xFC0 at this point mov rax, 0x04 ; advance past cs:lip:prevssp;supervisor shadow stack token - INCSSP_RAX ; After this SSP should be 0xFE0 - SAVEPREVSSP ; now the shadow stack restore token will be created at 0xFB8 - READSSP_RAX ; Read new SSP, SSP should be 0xFE8 + incsspq rax ; After this SSP should be 0xFE0 + saveprevssp ; now the shadow stack restore token will be created at 0xFB8 + rdsspq rax ; Read new SSP, SSP should be 0xFE8 sub rax, 0x10 - CLRSSBSY_RAX ; Clear token at 0xFD8, SSP should be 0 after this + clrssbsy [rax] ; Clear token at 0xFD8, SSP should be 0 after this sub rax, 0x20 - RSTORSSP_RAX ; Restore to token at 0xFB8, new SSP will be 0xFB8 + rstorssp [rax] ; Restore to token at 0xFB8, new SSP will be 0xFB8 mov rax, 0x01 ; Pop off the new save token created - INCSSP_RAX ; SSP should be 0xFC0 now + incsspq rax ; SSP should be 0xFC0 now CetDone: cli @@ -353,7 +354,7 @@ CetDone: ;; FX_SAVE_STATE_X64 FxSaveState; mov rsi, rsp - db 0xf, 0xae, 0xE ; fxrstor [rsi] + fxrstor [rsi] add rsp, 512 ;; UINT64 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7; @@ -440,8 +441,7 @@ DoReturn: push qword [rax + 0x18] ; save EFLAGS in new location mov rax, [rax] ; restore rax popfq ; restore EFLAGS - DB 0x48 ; prefix to composite "retq" with next "retf" - retf ; far return + retfq DoIret: iretq diff --git a/UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm b/UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm index f7f2937faf..f1422fd30a 100644 --- a/UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm +++ b/UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm @@ -1,5 +1,5 @@ ;------------------------------------------------------------------------------ ; -; Copyright (c) 2015 - 2021, Intel Corporation. All rights reserved.<BR> +; Copyright (c) 2015 - 2022, Intel Corporation. All rights reserved.<BR> ; SPDX-License-Identifier: BSD-2-Clause-Patent ; ; Module Name: @@ -345,7 +345,7 @@ BITS 64 ; ; Far return into 32-bit mode ; -o64 retf + retfq BITS 32 CompatMode: @@ -507,7 +507,7 @@ NoSevEs: ; ; Far return into 32-bit mode ; -o64 retf + retfq BITS 32 PmEntry: diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/Cet.nasm b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/Cet.nasm index 0919d6d05f..9d66b9c5da 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/Cet.nasm +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/Cet.nasm @@ -1,5 +1,5 @@ ;------------------------------------------------------------------------------ ; -; Copyright (c) 2019, Intel Corporation. All rights reserved.<BR> +; Copyright (c) 2019 - 2022, Intel Corporation. All rights reserved.<BR> ; SPDX-License-Identifier: BSD-2-Clause-Patent ; ;------------------------------------------------------------------------------- @@ -13,7 +13,7 @@ ASM_PFX(DisableCet): ; Skip the pushed data for call mov eax, 1 - INCSSP_EAX + incsspd eax mov eax, cr4 btr eax, 23 ; clear CET diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm index 167f5e14db..19de5f614e 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm @@ -1,5 +1,5 @@ ;------------------------------------------------------------------------------ ; -; Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR> +; Copyright (c) 2016 - 2022, Intel Corporation. All rights reserved.<BR> ; Copyright (c) 2020, AMD Incorporated. All rights reserved.<BR> ; SPDX-License-Identifier: BSD-2-Clause-Patent ; @@ -252,7 +252,7 @@ CetInterruptDone: mov eax, 0x668 | CR4_CET mov cr4, eax - SETSSBSY + setssbsy CetDone: diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/Cet.nasm b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/Cet.nasm index 3240f9d974..8bbdbb31cc 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/Cet.nasm +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/Cet.nasm @@ -1,5 +1,5 @@ ;------------------------------------------------------------------------------ ; -; Copyright (c) 2019, Intel Corporation. All rights reserved.<BR> +; Copyright (c) 2019 - 2022, Intel Corporation. All rights reserved.<BR> ; SPDX-License-Identifier: BSD-2-Clause-Patent ; ;------------------------------------------------------------------------------- @@ -14,7 +14,7 @@ ASM_PFX(DisableCet): ; Skip the pushed data for call mov rax, 1 - INCSSP_RAX + incsspq rax mov rax, cr4 btr eax, 23 ; clear CET diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm index 0e154e5db9..d302ca8d01 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm @@ -1,5 +1,5 @@ ;------------------------------------------------------------------------------ ; -; Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR> +; Copyright (c) 2016 - 2022, Intel Corporation. All rights reserved.<BR> ; Copyright (c) 2020, AMD Incorporated. All rights reserved.<BR> ; SPDX-License-Identifier: BSD-2-Clause-Patent ; @@ -279,7 +279,7 @@ CetInterruptDone: mov eax, 0x668 | CR4_CET mov cr4, rax - SETSSBSY + setssbsy CetDone: -- 2.28.0.windows.1 ^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [PATCH v2 4/6] UefiCpuPkg: Replace Opcode with the corresponding instructions. 2022-01-10 15:12 ` [PATCH v2 4/6] UefiCpuPkg: " Jason Lou @ 2022-02-10 5:35 ` Ni, Ray 0 siblings, 0 replies; 12+ messages in thread From: Ni, Ray @ 2022-02-10 5:35 UTC (permalink / raw) To: Lou, Yun, devel@edk2.groups.io; +Cc: Dong, Eric, Laszlo Ersek, Kumar, Rahul1 Reviewed-by: Ray Ni <ray.ni@intel.com> -----Original Message----- From: Lou, Yun <yun.lou@intel.com> Sent: Monday, January 10, 2022 11:13 PM To: devel@edk2.groups.io Cc: Lou, Yun <yun.lou@intel.com>; Ni, Ray <ray.ni@intel.com>; Dong, Eric <eric.dong@intel.com>; Laszlo Ersek <lersek@redhat.com>; Kumar, Rahul1 <rahul1.kumar@intel.com> Subject: [PATCH v2 4/6] UefiCpuPkg: Replace Opcode with the corresponding instructions. REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3790 Replace Opcode with the corresponding instructions. The code changes have been verified with CompareBuild.py tool, which can be used to compare the results of two different EDK II builds to determine if they generate the same binaries. (tool link: https://github.com/mdkinney/edk2/tree/sandbox/CompareBuild) Signed-off-by: Jason Lou <yun.lou@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> --- UefiCpuPkg/CpuDxe/X64/CpuAsm.nasm | 4 +-- UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionHandlerAsm.nasm | 11 +++++---- UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionTssEntryAsm.nasm | 9 +++---- UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.nasm | 14 +++++------ UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/Xcode5ExceptionHandlerAsm.nasm | 26 ++++++++++---------- UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm | 6 ++--- UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/Cet.nasm | 4 +-- UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm | 4 +-- UefiCpuPkg/PiSmmCpuDxeSmm/X64/Cet.nasm | 4 +-- UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm | 4 +-- 10 files changed, 43 insertions(+), 43 deletions(-) diff --git a/UefiCpuPkg/CpuDxe/X64/CpuAsm.nasm b/UefiCpuPkg/CpuDxe/X64/CpuAsm.nasm index 66f8857fc0..a894ff53ad 100644 --- a/UefiCpuPkg/CpuDxe/X64/CpuAsm.nasm +++ b/UefiCpuPkg/CpuDxe/X64/CpuAsm.nasm @@ -1,6 +1,6 @@ ;------------------------------------------------------------------------------ ;*-;* Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>+;* Copyright (c) 2016 - 2022, Intel Corporation. All rights reserved.<BR> ;* SPDX-License-Identifier: BSD-2-Clause-Patent ;* ;* CpuAsm.nasm@@ -23,7 +23,7 @@ ASM_PFX(SetCodeSelector): push rcx lea rax, [setCodeSelectorLongJump] push rax- o64 retf+ retfq setCodeSelectorLongJump: ret diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionHandlerAsm.nasm b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionHandlerAsm.nasm index 58d5312899..3fe9aed1e8 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionHandlerAsm.nasm +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionHandlerAsm +++ .nasm @@ -1,5 +1,5 @@ ;------------------------------------------------------------------------------ ;-; Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>+; Copyright (c) 2016 - 2022, Intel Corporation. All rights reserved.<BR> ; SPDX-License-Identifier: BSD-2-Clause-Patent ; ; Module Name:@@ -32,12 +32,13 @@ ALIGN 8 ; exception handler stub table ; AsmIdtVectorBegin:+%assign Vector 0 %rep 32- db 0x6a ; push #VectorNum- db ($ - AsmIdtVectorBegin) / ((AsmIdtVectorEnd - AsmIdtVectorBegin) / 32) ; VectorNum+ push byte %[Vector]; push eax mov eax, ASM_PFX(CommonInterruptEntry) jmp eax+%assign Vector Vector+1 %endrep AsmIdtVectorEnd: @@ -287,7 +288,7 @@ ErrorCodeAndVectorOnStack: test edx, BIT24 ; Test for FXSAVE/FXRESTOR support. ; edx still contains result from CPUID above jz .3- db 0xf, 0xae, 0x7 ;fxsave [edi]+ fxsave [edi] .3: ;; UEFI calling convention for IA32 requires that Direction flag in EFLAGs is clear@@ -320,7 +321,7 @@ ErrorCodeAndVectorOnStack: ; are supported test edx, BIT24 ; Test for FXSAVE/FXRESTOR support jz .4- db 0xf, 0xae, 0xe ; fxrstor [esi]+ fxrstor [esi] .4: add esp, 512 diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionTssEntryAsm.nasm b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionTssEntryAsm.nasm index dd3f74d2aa..b63cfeac6d 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionTssEntryAsm.nasm +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionTssEntryAs +++ m.nasm @@ -1,5 +1,5 @@ ;------------------------------------------------------------------------------ ;-; Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>+; Copyright (c) 2017 - 2022, Intel Corporation. All rights reserved.<BR> ; SPDX-License-Identifier: BSD-2-Clause-Patent ; ; Module Name:@@ -79,8 +79,7 @@ AsmExceptionEntryBegin: DoIret%[Vector]: iretd ASM_PFX(ExceptionTaskSwtichEntry%[Vector]):- db 0x6a ; push #VectorNum- db %[Vector]+ push byte %[Vector] mov eax, ASM_PFX(CommonTaskSwtichEntryPoint) call eax mov esp, eax ; Restore stack top@@ -244,7 +243,7 @@ ASM_PFX(CommonTaskSwtichEntryPoint): clts sub esp, 512 mov edi, esp- db 0xf, 0xae, 0x7 ;fxsave [edi]+ fxsave [edi] .3: ;; UINT32 ExceptionData;@@ -277,7 +276,7 @@ ASM_PFX(CommonTaskSwtichEntryPoint): test edx, BIT24 ; Test for FXSAVE/FXRESTOR support jz .4 mov esi, esp- db 0xf, 0xae, 0xe ; fxrstor [esi]+ fxrstor [esi] .4: add esp, 512 diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.nasm b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.nasm index 2a5545ecfd..9a806d1f86 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.nasm +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm. +++ nasm @@ -1,5 +1,5 @@ ;------------------------------------------------------------------------------ ;-; Copyright (c) 2012 - 2018, Intel Corporation. All rights reserved.<BR>+; Copyright (c) 2012 - 2022, Intel Corporation. All rights reserved.<BR> ; SPDX-License-Identifier: BSD-2-Clause-Patent ; ; Module Name:@@ -32,12 +32,13 @@ SECTION .text ALIGN 8 AsmIdtVectorBegin:+%assign Vector 0 %rep 32- db 0x6a ; push #VectorNum- db ($ - AsmIdtVectorBegin) / ((AsmIdtVectorEnd - AsmIdtVectorBegin) / 32) ; VectorNum+ push byte %[Vector] push rax mov rax, ASM_PFX(CommonInterruptEntry) jmp rax+%assign Vector Vector+1 %endrep AsmIdtVectorEnd: @@ -257,7 +258,7 @@ DrFinish: ;; FX_SAVE_STATE_X64 FxSaveState; sub rsp, 512 mov rdi, rsp- db 0xf, 0xae, 0x7 ;fxsave [rdi]+ fxsave [rdi] ;; UEFI calling convention for x64 requires that Direction flag in EFLAGs is clear cld@@ -284,7 +285,7 @@ DrFinish: ;; FX_SAVE_STATE_X64 FxSaveState; mov rsi, rsp- db 0xf, 0xae, 0xE ; fxrstor [rsi]+ fxrstor [rsi] add rsp, 512 ;; UINT64 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;@@ -371,8 +372,7 @@ DoReturn: push qword [rax + 0x18] ; save EFLAGS in new location mov rax, [rax] ; restore rax popfq ; restore EFLAGS- DB 0x48 ; prefix to composite "retq" with next "retf"- retf ; far return+ retfq DoIret: iretq diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/Xcode5ExceptionHandlerAsm.nasm b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/Xcode5ExceptionHandlerAsm.nasm index 84a12ddb88..9c72fa5815 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/Xcode5ExceptionHandlerAsm.nasm +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/Xcode5ExceptionHandl +++ erAsm.nasm @@ -1,5 +1,5 @@ ;------------------------------------------------------------------------------ ;-; Copyright (c) 2012 - 2018, Intel Corporation. All rights reserved.<BR>+; Copyright (c) 2012 - 2022, Intel Corporation. All rights reserved.<BR> ; SPDX-License-Identifier: BSD-2-Clause-Patent ; ; Module Name:@@ -54,12 +54,13 @@ SECTION .text ALIGN 8 AsmIdtVectorBegin:+%assign Vector 0 %rep 32- db 0x6a ; push #VectorNum- db ($ - AsmIdtVectorBegin) / ((AsmIdtVectorEnd - AsmIdtVectorBegin) / 32) ; VectorNum+ push byte %[Vector] push rax mov rax, strict qword 0 ; mov rax, ASM_PFX(CommonInterruptEntry) jmp rax+%assign Vector Vector+1 %endrep AsmIdtVectorEnd: @@ -280,7 +281,7 @@ DrFinish: ;; FX_SAVE_STATE_X64 FxSaveState; sub rsp, 512 mov rdi, rsp- db 0xf, 0xae, 0x7 ;fxsave [rdi]+ fxsave [rdi] ;; UEFI calling convention for x64 requires that Direction flag in EFLAGs is clear cld@@ -335,15 +336,15 @@ DrFinish: jz CetDone ; SSP should be 0xFC0 at this point mov rax, 0x04 ; advance past cs:lip:prevssp;supervisor shadow stack token- INCSSP_RAX ; After this SSP should be 0xFE0- SAVEPREVSSP ; now the shadow stack restore token will be created at 0xFB8- READSSP_RAX ; Read new SSP, SSP should be 0xFE8+ incsspq rax ; After this SSP should be 0xFE0+ saveprevssp ; now the shadow stack restore token will be created at 0xFB8+ rdsspq rax ; Read new SSP, SSP should be 0xFE8 sub rax, 0x10- CLRSSBSY_RAX ; Clear token at 0xFD8, SSP should be 0 after this+ clrssbsy [rax] ; Clear token at 0xFD8, SSP should be 0 after this sub rax, 0x20- RSTORSSP_RAX ; Restore to token at 0xFB8, new SSP will be 0xFB8+ rstorssp [rax] ; Restore to token at 0xFB8, new SSP will be 0xFB8 mov rax, 0x01 ; Pop off the new save token created- INCSSP_RAX ; SSP should be 0xFC0 now+ incsspq rax ; SSP should be 0xFC0 now CetDone: cli@@ -353,7 +354,7 @@ CetDone: ;; FX_SAVE_STATE_X64 FxSaveState; mov rsi, rsp- db 0xf, 0xae, 0xE ; fxrstor [rsi]+ fxrstor [rsi] add rsp, 512 ;; UINT64 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;@@ -440,8 +441,7 @@ DoReturn: push qword [rax + 0x18] ; save EFLAGS in new location mov rax, [rax] ; restore rax popfq ; restore EFLAGS- DB 0x48 ; prefix to composite "retq" with next "retf"- retf ; far return+ retfq DoIret: iretq diff --git a/UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm b/UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm index f7f2937faf..f1422fd30a 100644 --- a/UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm +++ b/UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm @@ -1,5 +1,5 @@ ;------------------------------------------------------------------------------ ;-; Copyright (c) 2015 - 2021, Intel Corporation. All rights reserved.<BR>+; Copyright (c) 2015 - 2022, Intel Corporation. All rights reserved.<BR> ; SPDX-License-Identifier: BSD-2-Clause-Patent ; ; Module Name:@@ -345,7 +345,7 @@ BITS 64 ; ; Far return into 32-bit mode ;-o64 retf+ retfq BITS 32 CompatMode:@@ -507,7 +507,7 @@ NoSevEs: ; ; Far return into 32-bit mode ;-o64 retf+ retfq BITS 32 PmEntry:diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/Cet.nasm b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/Cet.nasm index 0919d6d05f..9d66b9c5da 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/Cet.nasm +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/Cet.nasm @@ -1,5 +1,5 @@ ;------------------------------------------------------------------------------ ;-; Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>+; Copyright (c) 2019 - 2022, Intel Corporation. All rights reserved.<BR> ; SPDX-License-Identifier: BSD-2-Clause-Patent ; ;-------------------------------------------------------------------------------@@ -13,7 +13,7 @@ ASM_PFX(DisableCet): ; Skip the pushed data for call mov eax, 1- INCSSP_EAX+ incsspd eax mov eax, cr4 btr eax, 23 ; clear CETdiff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm index 167f5e14db..19de5f614e 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm @@ -1,5 +1,5 @@ ;------------------------------------------------------------------------------ ;-; Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>+; Copyright (c) 2016 - 2022, Intel Corporation. All rights reserved.<BR> ; Copyright (c) 2020, AMD Incorporated. All rights reserved.<BR> ; SPDX-License-Identifier: BSD-2-Clause-Patent ;@@ -252,7 +252,7 @@ CetInterruptDone: mov eax, 0x668 | CR4_CET mov cr4, eax - SETSSBSY+ setssbsy CetDone: diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/Cet.nasm b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/Cet.nasm index 3240f9d974..8bbdbb31cc 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/Cet.nasm +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/Cet.nasm @@ -1,5 +1,5 @@ ;------------------------------------------------------------------------------ ;-; Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>+; Copyright (c) 2019 - 2022, Intel Corporation. All rights reserved.<BR> ; SPDX-License-Identifier: BSD-2-Clause-Patent ; ;-------------------------------------------------------------------------------@@ -14,7 +14,7 @@ ASM_PFX(DisableCet): ; Skip the pushed data for call mov rax, 1- INCSSP_RAX+ incsspq rax mov rax, cr4 btr eax, 23 ; clear CETdiff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm index 0e154e5db9..d302ca8d01 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm @@ -1,5 +1,5 @@ ;------------------------------------------------------------------------------ ;-; Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>+; Copyright (c) 2016 - 2022, Intel Corporation. All rights reserved.<BR> ; Copyright (c) 2020, AMD Incorporated. All rights reserved.<BR> ; SPDX-License-Identifier: BSD-2-Clause-Patent ;@@ -279,7 +279,7 @@ CetInterruptDone: mov eax, 0x668 | CR4_CET mov cr4, rax - SETSSBSY+ setssbsy CetDone: -- 2.28.0.windows.1 ^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH v2 5/6] MdePkg: Remove the macro definitions regarding Opcode. 2022-01-10 15:12 [PATCH v2 1/6] MdeModulePkg: Replace Opcode with the corresponding instructions Jason Lou ` (2 preceding siblings ...) 2022-01-10 15:12 ` [PATCH v2 4/6] UefiCpuPkg: " Jason Lou @ 2022-01-10 15:12 ` Jason Lou 2022-01-10 15:12 ` [PATCH v2 6/6] BaseTools: Upgrade the version of NASM tool Jason Lou 2022-02-10 5:36 ` [PATCH v2 1/6] MdeModulePkg: Replace Opcode with the corresponding instructions Ni, Ray 5 siblings, 0 replies; 12+ messages in thread From: Jason Lou @ 2022-01-10 15:12 UTC (permalink / raw) To: devel; +Cc: Jason, Michael D Kinney, Liming Gao, Zhiguang Liu REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3790 Remove the macro definitions regarding Opcode because new version of NASM tool(e.g. v2.15.05) supports the corresponding instructions. Note: This patch need to be merged after other NASM code change to avoid compilation errors. Signed-off-by: Jason Lou <yun.lou@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> --- MdePkg/Include/Ia32/Nasm.inc | 26 +------------------- MdePkg/Include/X64/Nasm.inc | 26 +------------------- 2 files changed, 2 insertions(+), 50 deletions(-) diff --git a/MdePkg/Include/Ia32/Nasm.inc b/MdePkg/Include/Ia32/Nasm.inc index c794d9ece3..e92c032bd8 100644 --- a/MdePkg/Include/Ia32/Nasm.inc +++ b/MdePkg/Include/Ia32/Nasm.inc @@ -1,6 +1,6 @@ ;------------------------------------------------------------------------------ ; -; Copyright (c) 2019 - 2021, Intel Corporation. All rights reserved.<BR> +; Copyright (c) 2019 - 2022, Intel Corporation. All rights reserved.<BR> ; SPDX-License-Identifier: BSD-2-Clause-Patent ; ; Abstract: @@ -9,30 +9,6 @@ ; ;------------------------------------------------------------------------------ -%macro SAVEPREVSSP 0 - DB 0xF3, 0x0F, 0x01, 0xEA -%endmacro - -%macro CLRSSBSY_EAX 0 - DB 0x67, 0xF3, 0x0F, 0xAE, 0x30 -%endmacro - -%macro RSTORSSP_EAX 0 - DB 0x67, 0xF3, 0x0F, 0x01, 0x28 -%endmacro - -%macro SETSSBSY 0 - DB 0xF3, 0x0F, 0x01, 0xE8 -%endmacro - -%macro READSSP_EAX 0 - DB 0xF3, 0x0F, 0x1E, 0xC8 -%endmacro - -%macro INCSSP_EAX 0 - DB 0xF3, 0x0F, 0xAE, 0xE8 -%endmacro - ; NASM provides built-in macros STRUC and ENDSTRUC for structure definition. ; For example, to define a structure called mytype containing a longword, ; a word, a byte and a string of bytes, you might code diff --git a/MdePkg/Include/X64/Nasm.inc b/MdePkg/Include/X64/Nasm.inc index cfb14edc94..bb77ca6c32 100644 --- a/MdePkg/Include/X64/Nasm.inc +++ b/MdePkg/Include/X64/Nasm.inc @@ -1,6 +1,6 @@ ;------------------------------------------------------------------------------ ; -; Copyright (c) 2019 - 2021, Intel Corporation. All rights reserved.<BR> +; Copyright (c) 2019 - 2022, Intel Corporation. All rights reserved.<BR> ; SPDX-License-Identifier: BSD-2-Clause-Patent ; ; Abstract: @@ -9,30 +9,6 @@ ; ;------------------------------------------------------------------------------ -%macro SAVEPREVSSP 0 - DB 0xF3, 0x0F, 0x01, 0xEA -%endmacro - -%macro CLRSSBSY_RAX 0 - DB 0xF3, 0x0F, 0xAE, 0x30 -%endmacro - -%macro RSTORSSP_RAX 0 - DB 0xF3, 0x0F, 0x01, 0x28 -%endmacro - -%macro SETSSBSY 0 - DB 0xF3, 0x0F, 0x01, 0xE8 -%endmacro - -%macro READSSP_RAX 0 - DB 0xF3, 0x48, 0x0F, 0x1E, 0xC8 -%endmacro - -%macro INCSSP_RAX 0 - DB 0xF3, 0x48, 0x0F, 0xAE, 0xE8 -%endmacro - ; ; Macro for the PVALIDATE instruction, defined in AMD APM volume 3. ; NASM feature request URL: https://bugzilla.nasm.us/show_bug.cgi?id=3392753 -- 2.28.0.windows.1 ^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH v2 6/6] BaseTools: Upgrade the version of NASM tool 2022-01-10 15:12 [PATCH v2 1/6] MdeModulePkg: Replace Opcode with the corresponding instructions Jason Lou ` (3 preceding siblings ...) 2022-01-10 15:12 ` [PATCH v2 5/6] MdePkg: Remove the macro definitions regarding Opcode Jason Lou @ 2022-01-10 15:12 ` Jason Lou 2022-01-17 0:49 ` Yuwei Chen 2022-02-10 5:36 ` [PATCH v2 1/6] MdeModulePkg: Replace Opcode with the corresponding instructions Ni, Ray 5 siblings, 1 reply; 12+ messages in thread From: Jason Lou @ 2022-01-10 15:12 UTC (permalink / raw) To: devel; +Cc: Jason, Bob Feng, Liming Gao, Yuwei Chen REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3790 Upgrade the version of NASM tool to avoid compilation errors when compiling NASM code change. Signed-off-by: Jason Lou <yun.lou@intel.com> Cc: Bob Feng <bob.c.feng@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Yuwei Chen <yuwei.chen@intel.com> --- BaseTools/Conf/tools_def.template | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/BaseTools/Conf/tools_def.template b/BaseTools/Conf/tools_def.template index 2e6b382ab6..0133860fc3 100755 --- a/BaseTools/Conf/tools_def.template +++ b/BaseTools/Conf/tools_def.template @@ -1,5 +1,5 @@ # -# Copyright (c) 2006 - 2021, Intel Corporation. All rights reserved.<BR> +# Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR> # Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> # Portions copyright (c) 2011 - 2019, ARM Ltd. All rights reserved.<BR> # Copyright (c) 2015, Hewlett-Packard Development Company, L.P.<BR> @@ -368,8 +368,8 @@ DEFINE DTC_BIN = ENV(DTC_PREFIX)dtc # Other Supported Tools # ===================== # NASM -- http://www.nasm.us/ -# - NASM 2.10 or later for use with the GCC toolchain family -# - NASM 2.12.01 or later for use with all other toolchain families +# - NASM 2.15.05 or later for use with the GCC toolchain family +# - NASM 2.15.05 or later for use with all other toolchain families # #################################################################################### #################################################################################### -- 2.28.0.windows.1 ^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [PATCH v2 6/6] BaseTools: Upgrade the version of NASM tool 2022-01-10 15:12 ` [PATCH v2 6/6] BaseTools: Upgrade the version of NASM tool Jason Lou @ 2022-01-17 0:49 ` Yuwei Chen 0 siblings, 0 replies; 12+ messages in thread From: Yuwei Chen @ 2022-01-17 0:49 UTC (permalink / raw) To: Lou, Yun, devel@edk2.groups.io; +Cc: Feng, Bob C, Gao, Liming This patch looks good to me. Reviewed-by: Yuwei Chen<yuwei.chen@intel.com> > -----Original Message----- > From: Lou, Yun <yun.lou@intel.com> > Sent: Monday, January 10, 2022 11:13 PM > To: devel@edk2.groups.io > Cc: Lou, Yun <yun.lou@intel.com>; Feng, Bob C <bob.c.feng@intel.com>; > Gao, Liming <gaoliming@byosoft.com.cn>; Chen, Christine > <yuwei.chen@intel.com> > Subject: [PATCH v2 6/6] BaseTools: Upgrade the version of NASM tool > > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3790 > > Upgrade the version of NASM tool to avoid compilation errors when > compiling NASM code change. > > Signed-off-by: Jason Lou <yun.lou@intel.com> > Cc: Bob Feng <bob.c.feng@intel.com> > Cc: Liming Gao <gaoliming@byosoft.com.cn> > Cc: Yuwei Chen <yuwei.chen@intel.com> > --- > BaseTools/Conf/tools_def.template | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) > > diff --git a/BaseTools/Conf/tools_def.template > b/BaseTools/Conf/tools_def.template > index 2e6b382ab6..0133860fc3 100755 > --- a/BaseTools/Conf/tools_def.template > +++ b/BaseTools/Conf/tools_def.template > @@ -1,5 +1,5 @@ > #-# Copyright (c) 2006 - 2021, Intel Corporation. All rights reserved.<BR>+# > Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR> # > Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> # > Portions copyright (c) 2011 - 2019, ARM Ltd. All rights reserved.<BR> # > Copyright (c) 2015, Hewlett-Packard Development Company, L.P.<BR>@@ - > 368,8 +368,8 @@ DEFINE DTC_BIN = ENV(DTC_PREFIX)dtc > # Other Supported Tools # ===================== # NASM -- > http://www.nasm.us/-# - NASM 2.10 or later for use with the GCC toolchain > family-# - NASM 2.12.01 or later for use with all other toolchain families+# > - NASM 2.15.05 or later for use with the GCC toolchain family+# - NASM > 2.15.05 or later for use with all other toolchain families # > ################################################################ > #################### > ################################################################ > ####################-- > 2.28.0.windows.1 ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v2 1/6] MdeModulePkg: Replace Opcode with the corresponding instructions. 2022-01-10 15:12 [PATCH v2 1/6] MdeModulePkg: Replace Opcode with the corresponding instructions Jason Lou ` (4 preceding siblings ...) 2022-01-10 15:12 ` [PATCH v2 6/6] BaseTools: Upgrade the version of NASM tool Jason Lou @ 2022-02-10 5:36 ` Ni, Ray 2022-02-10 7:44 ` 回复: [edk2-devel] " gaoliming 5 siblings, 1 reply; 12+ messages in thread From: Ni, Ray @ 2022-02-10 5:36 UTC (permalink / raw) To: Gao, Liming, Wang, Jian J; +Cc: Bi, Dandan, Lou, Yun, devel@edk2.groups.io Reviewed-by: Ray Ni <ray.ni@intel.com> Liming, Jian, can you give R-b as the package maintainers? -----Original Message----- From: Lou, Yun <yun.lou@intel.com> Sent: Monday, January 10, 2022 11:13 PM To: devel@edk2.groups.io Cc: Lou, Yun <yun.lou@intel.com>; Ni, Ray <ray.ni@intel.com>; Bi, Dandan <dandan.bi@intel.com>; Gao, Liming <gaoliming@byosoft.com.cn> Subject: [PATCH v2 1/6] MdeModulePkg: Replace Opcode with the corresponding instructions. REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3790 Replace Opcode with the corresponding instructions. The code changes have been verified with CompareBuild.py tool, which can be used to compare the results of two different EDK II builds to determine if they generate the same binaries. (tool link: https://github.com/mdkinney/edk2/tree/sandbox/CompareBuild) Signed-off-by: Jason Lou <yun.lou@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Dandan Bi <dandan.bi@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> --- MdeModulePkg/Universal/DebugSupportDxe/Ia32/AsmFuncs.nasm | 20 +++---------------- MdeModulePkg/Universal/DebugSupportDxe/X64/AsmFuncs.nasm | 21 +++----------------- 2 files changed, 6 insertions(+), 35 deletions(-) diff --git a/MdeModulePkg/Universal/DebugSupportDxe/Ia32/AsmFuncs.nasm b/MdeModulePkg/Universal/DebugSupportDxe/Ia32/AsmFuncs.nasm index cfb418748f..07fc912fe8 100644 --- a/MdeModulePkg/Universal/DebugSupportDxe/Ia32/AsmFuncs.nasm +++ b/MdeModulePkg/Universal/DebugSupportDxe/Ia32/AsmFuncs.nasm @@ -1,7 +1,7 @@ ;/** @file ; Low leve IA32 specific debug support functions. ; -; Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR> +; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR> ; SPDX-License-Identifier: BSD-2-Clause-Patent ; ;**/ @@ -26,20 +26,6 @@ %define FXSTOR_FLAG 0x1000000 ; bit cpuid 24 of feature flags -;; The FXSTOR and FXRSTOR commands are used for saving and restoring the x87, -;; MMX, SSE, SSE2, etc registers. The initialization of the debugsupport driver -;; MUST check the CPUID feature flags to see that these instructions are available -;; and fail to init if they are not. - -;; fxstor [edi] -%macro FXSTOR_EDI 0 - db 0xf, 0xae, 00000111y ; mod = 00, reg/op = 000, r/m = 111 = [edi] -%endmacro - -;; fxrstor [esi] -%macro FXRSTOR_ESI 0 - db 0xf, 0xae, 00001110y ; mod = 00, reg/op = 001, r/m = 110 = [esi] -%endmacro SECTION .data global ASM_PFX(OrigVector) @@ -348,7 +334,7 @@ ExtraPushDone: ; IMPORTANT!! The debug stack has been carefully constructed to ; insure that esp and edi are 16 byte aligned when we get here. ; They MUST be. If they are not, a GP fault will occur. - FXSTOR_EDI + fxsave [edi] ;; UEFI calling convention for IA32 requires that Direction flag in EFLAGs is clear cld @@ -372,7 +358,7 @@ ExtraPushDone: ;; FX_SAVE_STATE_IA32 FxSaveState; mov esi, esp - FXRSTOR_ESI + fxrstor [esi] add esp, 512 ;; UINT32 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7; diff --git a/MdeModulePkg/Universal/DebugSupportDxe/X64/AsmFuncs.nasm b/MdeModulePkg/Universal/DebugSupportDxe/X64/AsmFuncs.nasm index 9cc38a3128..c6c5e49189 100644 --- a/MdeModulePkg/Universal/DebugSupportDxe/X64/AsmFuncs.nasm +++ b/MdeModulePkg/Universal/DebugSupportDxe/X64/AsmFuncs.nasm @@ -1,7 +1,7 @@ ;/** @file ; Low level x64 routines used by the debug support driver. ; -; Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR> +; Copyright (c) 2007 - 2022, Intel Corporation. All rights reserved.<BR> ; SPDX-License-Identifier: BSD-2-Clause-Patent ; ;**/ @@ -26,21 +26,6 @@ %define FXSTOR_FLAG 0x1000000 ; bit cpuid 24 of feature flags -;; The FXSTOR and FXRSTOR commands are used for saving and restoring the x87, -;; MMX, SSE, SSE2, etc registers. The initialization of the debugsupport driver -;; MUST check the CPUID feature flags to see that these instructions are available -;; and fail to init if they are not. - -;; fxstor [rdi] -%macro FXSTOR_RDI 0 - db 0xf, 0xae, 00000111y ; mod = 00, reg/op = 000, r/m = 111 = [rdi] -%endmacro - -;; fxrstor [rsi] -%macro FXRSTOR_RSI 0 - db 0xf, 0xae, 00001110y ; mod = 00, reg/op = 001, r/m = 110 = [rsi] -%endmacro - SECTION .data global ASM_PFX(OrigVector) @@ -381,7 +366,7 @@ ExtraPushDone: ; IMPORTANT!! The debug stack has been carefully constructed to ; insure that rsp and rdi are 16 byte aligned when we get here. ; They MUST be. If they are not, a GP fault will occur. - FXSTOR_RDI + fxsave [rdi] ;; UEFI calling convention for x64 requires that Direction flag in EFLAGs is clear cld @@ -404,7 +389,7 @@ ExtraPushDone: ;; FX_SAVE_STATE_X64 FxSaveState; mov rsi, rsp - FXRSTOR_RSI + fxrstor [rsi] add rsp, 512 ;; UINT64 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7; -- 2.28.0.windows.1 ^ permalink raw reply related [flat|nested] 12+ messages in thread
* 回复: [edk2-devel] [PATCH v2 1/6] MdeModulePkg: Replace Opcode with the corresponding instructions. 2022-02-10 5:36 ` [PATCH v2 1/6] MdeModulePkg: Replace Opcode with the corresponding instructions Ni, Ray @ 2022-02-10 7:44 ` gaoliming 0 siblings, 0 replies; 12+ messages in thread From: gaoliming @ 2022-02-10 7:44 UTC (permalink / raw) To: devel, ray.ni, 'Wang, Jian J' Cc: 'Bi, Dandan', 'Lou, Yun' Ray, I have given my reviewed-by for the whole patch set. https://edk2.groups.io/g/devel/message/85499?p=%2C%2C%2C20%2C0%2C0%2C0%3A%3A created%2C0%2Ccorresponding%2C20%2C2%2C20%2C88339058 Thanks Liming > -----邮件原件----- > 发件人: devel@edk2.groups.io <devel@edk2.groups.io> 代表 Ni, Ray > 发送时间: 2022年2月10日 13:37 > 收件人: Gao, Liming <gaoliming@byosoft.com.cn>; Wang, Jian J > <jian.j.wang@intel.com> > 抄送: Bi, Dandan <dandan.bi@intel.com>; Lou, Yun <yun.lou@intel.com>; > devel@edk2.groups.io > 主题: Re: [edk2-devel] [PATCH v2 1/6] MdeModulePkg: Replace Opcode with > the corresponding instructions. > > Reviewed-by: Ray Ni <ray.ni@intel.com> > > Liming, Jian, can you give R-b as the package maintainers? > > -----Original Message----- > From: Lou, Yun <yun.lou@intel.com> > Sent: Monday, January 10, 2022 11:13 PM > To: devel@edk2.groups.io > Cc: Lou, Yun <yun.lou@intel.com>; Ni, Ray <ray.ni@intel.com>; Bi, Dandan > <dandan.bi@intel.com>; Gao, Liming <gaoliming@byosoft.com.cn> > Subject: [PATCH v2 1/6] MdeModulePkg: Replace Opcode with the > corresponding instructions. > > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3790 > > Replace Opcode with the corresponding instructions. > The code changes have been verified with CompareBuild.py tool, which > can be used to compare the results of two different EDK II builds to > determine if they generate the same binaries. > (tool link: https://github.com/mdkinney/edk2/tree/sandbox/CompareBuild) > > Signed-off-by: Jason Lou <yun.lou@intel.com> > Cc: Ray Ni <ray.ni@intel.com> > Cc: Dandan Bi <dandan.bi@intel.com> > Cc: Liming Gao <gaoliming@byosoft.com.cn> > --- > MdeModulePkg/Universal/DebugSupportDxe/Ia32/AsmFuncs.nasm | 20 > +++---------------- > MdeModulePkg/Universal/DebugSupportDxe/X64/AsmFuncs.nasm | 21 > +++----------------- > 2 files changed, 6 insertions(+), 35 deletions(-) > > diff --git > a/MdeModulePkg/Universal/DebugSupportDxe/Ia32/AsmFuncs.nasm > b/MdeModulePkg/Universal/DebugSupportDxe/Ia32/AsmFuncs.nasm > index cfb418748f..07fc912fe8 100644 > --- a/MdeModulePkg/Universal/DebugSupportDxe/Ia32/AsmFuncs.nasm > +++ b/MdeModulePkg/Universal/DebugSupportDxe/Ia32/AsmFuncs.nasm > @@ -1,7 +1,7 @@ > ;/** @file > > ; Low leve IA32 specific debug support functions. > > ; > > -; Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR> > > +; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR> > > ; SPDX-License-Identifier: BSD-2-Clause-Patent > > ; > > ;**/ > > @@ -26,20 +26,6 @@ > > > %define FXSTOR_FLAG 0x1000000 ; bit cpuid 24 of feature flags > > > > -;; The FXSTOR and FXRSTOR commands are used for saving and restoring the > x87, > > -;; MMX, SSE, SSE2, etc registers. The initialization of the debugsupport > driver > > -;; MUST check the CPUID feature flags to see that these instructions are > available > > -;; and fail to init if they are not. > > - > > -;; fxstor [edi] > > -%macro FXSTOR_EDI 0 > > - db 0xf, 0xae, 00000111y ; mod = 00, reg/op = > 000, r/m = 111 = [edi] > > -%endmacro > > - > > -;; fxrstor [esi] > > -%macro FXRSTOR_ESI 0 > > - db 0xf, 0xae, 00001110y ; mod = 00, reg/op = > 001, r/m = 110 = [esi] > > -%endmacro > > SECTION .data > > > > global ASM_PFX(OrigVector) > > @@ -348,7 +334,7 @@ ExtraPushDone: > ; IMPORTANT!! The debug stack has been carefully > constructed to > > ; insure that esp and edi are 16 byte aligned when we > get here. > > ; They MUST be. If they are not, a GP fault will occur. > > - FXSTOR_EDI > > + fxsave [edi] > > > > ;; UEFI calling convention for IA32 requires that Direction flag in EFLAGs is > clear > > cld > > @@ -372,7 +358,7 @@ ExtraPushDone: > > > ;; FX_SAVE_STATE_IA32 FxSaveState; > > mov esi, esp > > - FXRSTOR_ESI > > + fxrstor [esi] > > add esp, 512 > > > > ;; UINT32 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7; > > diff --git a/MdeModulePkg/Universal/DebugSupportDxe/X64/AsmFuncs.nasm > b/MdeModulePkg/Universal/DebugSupportDxe/X64/AsmFuncs.nasm > index 9cc38a3128..c6c5e49189 100644 > --- a/MdeModulePkg/Universal/DebugSupportDxe/X64/AsmFuncs.nasm > +++ b/MdeModulePkg/Universal/DebugSupportDxe/X64/AsmFuncs.nasm > @@ -1,7 +1,7 @@ > ;/** @file > > ; Low level x64 routines used by the debug support driver. > > ; > > -; Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR> > > +; Copyright (c) 2007 - 2022, Intel Corporation. All rights reserved.<BR> > > ; SPDX-License-Identifier: BSD-2-Clause-Patent > > ; > > ;**/ > > @@ -26,21 +26,6 @@ > > > %define FXSTOR_FLAG 0x1000000 ; bit cpuid 24 of feature flags > > > > -;; The FXSTOR and FXRSTOR commands are used for saving and restoring the > x87, > > -;; MMX, SSE, SSE2, etc registers. The initialization of the debugsupport > driver > > -;; MUST check the CPUID feature flags to see that these instructions are > available > > -;; and fail to init if they are not. > > - > > -;; fxstor [rdi] > > -%macro FXSTOR_RDI 0 > > - db 0xf, 0xae, 00000111y ; mod = 00, reg/op = > 000, r/m = 111 = [rdi] > > -%endmacro > > - > > -;; fxrstor [rsi] > > -%macro FXRSTOR_RSI 0 > > - db 0xf, 0xae, 00001110y ; mod = 00, reg/op = > 001, r/m = 110 = [rsi] > > -%endmacro > > - > > SECTION .data > > > > global ASM_PFX(OrigVector) > > @@ -381,7 +366,7 @@ ExtraPushDone: > ; IMPORTANT!! The debug stack has been carefully > constructed to > > ; insure that rsp and rdi are 16 byte aligned when we get > here. > > ; They MUST be. If they are not, a GP fault will occur. > > - FXSTOR_RDI > > + fxsave [rdi] > > > > ;; UEFI calling convention for x64 requires that Direction flag in EFLAGs is > clear > > cld > > @@ -404,7 +389,7 @@ ExtraPushDone: > > > ;; FX_SAVE_STATE_X64 FxSaveState; > > mov rsi, rsp > > - FXRSTOR_RSI > > + fxrstor [rsi] > > add rsp, 512 > > > > ;; UINT64 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7; > > -- > 2.28.0.windows.1 > > > > > ^ permalink raw reply [flat|nested] 12+ messages in thread
end of thread, other threads:[~2022-02-10 7:44 UTC | newest] Thread overview: 12+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2022-01-10 15:12 [PATCH v2 1/6] MdeModulePkg: Replace Opcode with the corresponding instructions Jason Lou 2022-01-10 15:12 ` [PATCH v2 2/6] MdePkg: " Jason Lou 2022-01-11 0:55 ` 回复: [edk2-devel] " gaoliming 2022-01-10 15:12 ` [PATCH v2 3/6] SourceLevelDebugPkg: " Jason Lou 2022-01-11 1:03 ` Wu, Hao A 2022-01-10 15:12 ` [PATCH v2 4/6] UefiCpuPkg: " Jason Lou 2022-02-10 5:35 ` Ni, Ray 2022-01-10 15:12 ` [PATCH v2 5/6] MdePkg: Remove the macro definitions regarding Opcode Jason Lou 2022-01-10 15:12 ` [PATCH v2 6/6] BaseTools: Upgrade the version of NASM tool Jason Lou 2022-01-17 0:49 ` Yuwei Chen 2022-02-10 5:36 ` [PATCH v2 1/6] MdeModulePkg: Replace Opcode with the corresponding instructions Ni, Ray 2022-02-10 7:44 ` 回复: [edk2-devel] " gaoliming
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