From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by mx.groups.io with SMTP id smtpd.web10.32920.1641827599550995785 for ; Mon, 10 Jan 2022 07:13:26 -0800 Authentication-Results: mx.groups.io; dkim=fail reason="unable to parse pub key" header.i=@intel.com header.s=intel header.b=MFVmSwSL; spf=pass (domain: intel.com, ip: 134.134.136.100, mailfrom: yun.lou@intel.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1641827606; x=1673363606; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=tcU/qCnqx6cHgPPj/HHUPuW7e3HgDNFfgSR7oXtMNFo=; b=MFVmSwSLJy0z0uDWThwn09uNdS2bfBCkWPr+MCHqgKOgWPmwhw5WazuX KMlV6mAPxfnG+6txD6Ne/pVWI+W4uNxNjH8/jpG+IqQX2t3GMYXZLam9e 2OvNEWeN6iKICV8OUjJAZrbjheKcZqQLaOOHh9tgANVpgy7Xb2RUBEQVH yrH4t47CRVdn+/9QGHQOuMDA+Xnm0ITeeEuJQzDgXqZjxCCC+4MHMuHjY 4QGWOckdCNggP/cUGZbSMQBmB3YAGvyuW2loHLKhdhEsrkJHzKnoE/Cfl 6ORkwJfG1LUgn+V/FcB6hBFd8UHoa2R+SLfh0u/yZZp5c4AHD0j+HCJ25 Q==; X-IronPort-AV: E=McAfee;i="6200,9189,10222"; a="306599956" X-IronPort-AV: E=Sophos;i="5.88,277,1635231600"; d="scan'208";a="306599956" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Jan 2022 07:13:26 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.88,277,1635231600"; d="scan'208";a="528307420" Received: from shwdeopenlab102.ccr.corp.intel.com ([10.239.183.94]) by orsmga008.jf.intel.com with ESMTP; 10 Jan 2022 07:13:24 -0800 From: "Jason Lou" To: devel@edk2.groups.io Cc: Jason , Michael D Kinney , Liming Gao , Zhiguang Liu Subject: [PATCH v2 5/6] MdePkg: Remove the macro definitions regarding Opcode. Date: Mon, 10 Jan 2022 23:12:52 +0800 Message-Id: <20220110151253.3848-5-yun.lou@intel.com> X-Mailer: git-send-email 2.31.1.windows.1 In-Reply-To: <20220110151253.3848-1-yun.lou@intel.com> References: <20220110151253.3848-1-yun.lou@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3790 Remove the macro definitions regarding Opcode because new version of NASM tool(e.g. v2.15.05) supports the corresponding instructions. Note: This patch need to be merged after other NASM code change to avoid compilation errors. Signed-off-by: Jason Lou Cc: Michael D Kinney Cc: Liming Gao Cc: Zhiguang Liu --- MdePkg/Include/Ia32/Nasm.inc | 26 +------------------- MdePkg/Include/X64/Nasm.inc | 26 +------------------- 2 files changed, 2 insertions(+), 50 deletions(-) diff --git a/MdePkg/Include/Ia32/Nasm.inc b/MdePkg/Include/Ia32/Nasm.inc index c794d9ece3..e92c032bd8 100644 --- a/MdePkg/Include/Ia32/Nasm.inc +++ b/MdePkg/Include/Ia32/Nasm.inc @@ -1,6 +1,6 @@ ;-------------------------------------------------------------------------= -----=0D ;=0D -; Copyright (c) 2019 - 2021, Intel Corporation. All rights reserved.
=0D +; Copyright (c) 2019 - 2022, Intel Corporation. All rights reserved.
=0D ; SPDX-License-Identifier: BSD-2-Clause-Patent=0D ;=0D ; Abstract:=0D @@ -9,30 +9,6 @@ ;=0D ;-------------------------------------------------------------------------= -----=0D =0D -%macro SAVEPREVSSP 0=0D - DB 0xF3, 0x0F, 0x01, 0xEA=0D -%endmacro=0D -=0D -%macro CLRSSBSY_EAX 0=0D - DB 0x67, 0xF3, 0x0F, 0xAE, 0x30=0D -%endmacro=0D -=0D -%macro RSTORSSP_EAX 0=0D - DB 0x67, 0xF3, 0x0F, 0x01, 0x28=0D -%endmacro=0D -=0D -%macro SETSSBSY 0=0D - DB 0xF3, 0x0F, 0x01, 0xE8=0D -%endmacro=0D -=0D -%macro READSSP_EAX 0=0D - DB 0xF3, 0x0F, 0x1E, 0xC8=0D -%endmacro=0D -=0D -%macro INCSSP_EAX 0=0D - DB 0xF3, 0x0F, 0xAE, 0xE8=0D -%endmacro=0D -=0D ; NASM provides built-in macros STRUC and ENDSTRUC for structure definitio= n.=0D ; For example, to define a structure called mytype containing a longword,= =0D ; a word, a byte and a string of bytes, you might code=0D diff --git a/MdePkg/Include/X64/Nasm.inc b/MdePkg/Include/X64/Nasm.inc index cfb14edc94..bb77ca6c32 100644 --- a/MdePkg/Include/X64/Nasm.inc +++ b/MdePkg/Include/X64/Nasm.inc @@ -1,6 +1,6 @@ ;-------------------------------------------------------------------------= -----=0D ;=0D -; Copyright (c) 2019 - 2021, Intel Corporation. All rights reserved.
=0D +; Copyright (c) 2019 - 2022, Intel Corporation. All rights reserved.
=0D ; SPDX-License-Identifier: BSD-2-Clause-Patent=0D ;=0D ; Abstract:=0D @@ -9,30 +9,6 @@ ;=0D ;-------------------------------------------------------------------------= -----=0D =0D -%macro SAVEPREVSSP 0=0D - DB 0xF3, 0x0F, 0x01, 0xEA=0D -%endmacro=0D -=0D -%macro CLRSSBSY_RAX 0=0D - DB 0xF3, 0x0F, 0xAE, 0x30=0D -%endmacro=0D -=0D -%macro RSTORSSP_RAX 0=0D - DB 0xF3, 0x0F, 0x01, 0x28=0D -%endmacro=0D -=0D -%macro SETSSBSY 0=0D - DB 0xF3, 0x0F, 0x01, 0xE8=0D -%endmacro=0D -=0D -%macro READSSP_RAX 0=0D - DB 0xF3, 0x48, 0x0F, 0x1E, 0xC8=0D -%endmacro=0D -=0D -%macro INCSSP_RAX 0=0D - DB 0xF3, 0x48, 0x0F, 0xAE, 0xE8=0D -%endmacro=0D -=0D ;=0D ; Macro for the PVALIDATE instruction, defined in AMD APM volume 3.=0D ; NASM feature request URL: https://bugzilla.nasm.us/show_bug.cgi?id=3D339= 2753=0D --=20 2.28.0.windows.1