From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by mx.groups.io with SMTP id smtpd.web09.3715.1642041119174450078 for ; Wed, 12 Jan 2022 18:31:59 -0800 Authentication-Results: mx.groups.io; dkim=fail reason="unable to parse pub key" header.i=@intel.com header.s=intel header.b=dZM/OV2/; spf=pass (domain: intel.com, ip: 192.55.52.43, mailfrom: yu.pu@intel.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1642041119; x=1673577119; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=UhE0nlnVqJ4Bzt7NmGlucAXFsLEUWi/ji3XMlGD3P/o=; b=dZM/OV2//bmAkp+1eWHq8KQ+4vOZ+WrUAb4ejJ9KADKxjXHWTFmqRBcA GCg1/PoGyv1W9wFBf82E3sgFcwsc5Sevv9fSTodXUiF/ygd687Dkgc2Iq I8h/Z8H8U1a1sVeOdNZ2cC2Lc4X69kvTIrvi70QZCRZNh5zXkA39lZ/aK OvUiVsC+FafSH+izIcZuddJQ1/ElxlQNEj5OkKiPMI1rlM+8sV8a+kecR bWxiARH0bT/uVSKUW8qsRKsGqEOLpKUhF/EMZGfs6bgIN8lwD+oGW2AzF Qe+B1uOIGD01HQs2A4MG1IO8XVMQQgRJQpi1JAyVomA3rSi32IEX83pIn Q==; X-IronPort-AV: E=McAfee;i="6200,9189,10225"; a="330259722" X-IronPort-AV: E=Sophos;i="5.88,284,1635231600"; d="scan'208";a="330259722" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Jan 2022 18:31:57 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.88,284,1635231600"; d="scan'208";a="490974195" Received: from shwdeopenlab704.ccr.corp.intel.com ([10.239.182.239]) by orsmga002.jf.intel.com with ESMTP; 12 Jan 2022 18:31:55 -0800 From: Yu Pu To: devel@edk2.groups.io Cc: Yu Pu , Eric Dong , Ray Ni Subject: [PATCH v1 1/1] UefiCpuPackage: Add APIs for CPU physical address mask calculation Date: Thu, 13 Jan 2022 10:31:52 +0800 Message-Id: <20220113023152.1047-1-yu.pu@intel.com> X-Mailer: git-send-email 2.30.0.windows.2 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3394 Firmware contains lots of code that deals with page table.These code need the information of cpu physical address mask which can be calculated from CPUID result.Today all these code implements directly calls CPUID and calculates the address mask. This bugzilla requests to add a new API as below so that all the duplicated code can be removed. Cc: Eric Dong Cc: Ray Ni Signed-off-by: Yu Pu --- UefiCpuPkg/CpuDxe/CpuDxe.c | 16 +------ UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.c | 47 ++++++++++++++++++= ++ UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c | 9 +--- UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c | 9 +--- UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume.c | 9 +--- UefiCpuPkg/Include/Library/UefiCpuLib.h | 17 +++++++ 6 files changed, 70 insertions(+), 37 deletions(-) diff --git a/UefiCpuPkg/CpuDxe/CpuDxe.c b/UefiCpuPkg/CpuDxe/CpuDxe.c index 00f3cb09572c..8aca1bf72b4c 100644 --- a/UefiCpuPkg/CpuDxe/CpuDxe.c +++ b/UefiCpuPkg/CpuDxe/CpuDxe.c @@ -503,21 +503,7 @@ InitializeMtrrMask ( VOID=0D )=0D {=0D - UINT32 RegEax;=0D - UINT8 PhysicalAddressBits;=0D -=0D - AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL);=0D -=0D - if (RegEax >=3D 0x80000008) {=0D - AsmCpuid (0x80000008, &RegEax, NULL, NULL, NULL);=0D -=0D - PhysicalAddressBits =3D (UINT8)RegEax;=0D - } else {=0D - PhysicalAddressBits =3D 36;=0D - }=0D -=0D - mValidMtrrBitsMask =3D LShiftU64 (1, PhysicalAddressBits) - 1;=0D - mValidMtrrAddressMask =3D mValidMtrrBitsMask & 0xfffffffffffff000ULL;=0D + GetPhysicalAddressBits(&mValidMtrrBitsMask, &mValidMtrrAddressMask);=0D }=0D =0D /**=0D diff --git a/UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.c b/UefiCpuPk= g/Library/BaseUefiCpuLib/BaseUefiCpuLib.c index 5d925bc273f8..bb1343f3cd21 100644 --- a/UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.c +++ b/UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.c @@ -79,3 +79,50 @@ GetCpuSteppingId ( =0D return (UINT8)Eax.Bits.SteppingId;=0D }=0D +=0D +/**=0D + Get the physical address width supported by the processor.=0D + @param[out] ValidAddressMask Bitmask with valid address bits se= t to=0D + one; other bits are clear. Optiona= l=0D + parameter.=0D + @param[out] ValidPageBaseAddressMask Bitmask with valid page base addre= ss=0D + bits set to one; other bits are cl= ear.=0D + Optional parameter.=0D + @return The physical address width supported by the processor.=0D +**/=0D +UINT8=0D +EFIAPI=0D +GetPhysicalAddressBits (=0D + OUT UINT64 *ValidAddressMask OPTIONAL,=0D + OUT UINT64 *ValidPageBaseAddressMask OPTIONAL=0D + )=0D +{=0D + UINT32 MaxExtendedFunction;=0D + CPUID_VIR_PHY_ADDRESS_SIZE_EAX VirPhyAddressSize;=0D + UINT64 AddressMask;=0D + UINT64 PageBaseAddressMask;=0D +=0D + AsmCpuid (CPUID_EXTENDED_FUNCTION, &MaxExtendedFunction, NULL, NULL, NUL= L);=0D + if (MaxExtendedFunction >=3D CPUID_VIR_PHY_ADDRESS_SIZE) {=0D + AsmCpuid (=0D + CPUID_VIR_PHY_ADDRESS_SIZE,=0D + &VirPhyAddressSize.Uint32,=0D + NULL,=0D + NULL,=0D + NULL=0D + );=0D + } else {=0D + VirPhyAddressSize.Bits.PhysicalAddressBits =3D 36;=0D + }=0D +=0D + AddressMask =3D LShiftU64 (1, VirPhyAddressSize.Bits.PhysicalAddressBits= ) - 1;=0D + PageBaseAddressMask =3D AddressMask & ~(UINT64)0xFFF;=0D +=0D + if (ValidAddressMask !=3D NULL) {=0D + *ValidAddressMask =3D AddressMask;=0D + }=0D + if (ValidPageBaseAddressMask !=3D NULL) {=0D + *ValidPageBaseAddressMask =3D PageBaseAddressMask;=0D + }=0D + return (UINT8)VirPhyAddressSize.Bits.PhysicalAddressBits;=0D +}=0D diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c b/UefiCpuPkg/Lib= rary/SmmCpuFeaturesLib/SmmStm.c index 4e8f897f5e9c..ec7cd4013132 100644 --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c @@ -15,6 +15,7 @@ #include =0D #include =0D #include =0D +#include =0D #include =0D #include =0D #include =0D @@ -330,13 +331,7 @@ SmmCpuFeaturesInstallSmiHandler ( if (Hob !=3D NULL) {=0D Psd->PhysicalAddressBits =3D ((EFI_HOB_CPU *)Hob)->SizeOfMemorySpace;= =0D } else {=0D - AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL);=0D - if (RegEax >=3D 0x80000008) {=0D - AsmCpuid (0x80000008, &RegEax, NULL, NULL, NULL);=0D - Psd->PhysicalAddressBits =3D (UINT8)RegEax;=0D - } else {=0D - Psd->PhysicalAddressBits =3D 36;=0D - }=0D + Psd->PhysicalAddressBits =3D GetPhysicalAddressBits (NULL, NULL);=0D }=0D =0D if (!mStmConfigurationTableInitialized) {=0D diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c b/UefiCpuPkg/PiSmmCpuD= xeSmm/X64/PageTbl.c index 538394f23910..de1385a86948 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c @@ -194,7 +194,6 @@ CalculateMaximumSupportAddress ( VOID=0D )=0D {=0D - UINT32 RegEax;=0D UINT8 PhysicalAddressBits;=0D VOID *Hob;=0D =0D @@ -205,13 +204,7 @@ CalculateMaximumSupportAddress ( if (Hob !=3D NULL) {=0D PhysicalAddressBits =3D ((EFI_HOB_CPU *)Hob)->SizeOfMemorySpace;=0D } else {=0D - AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL);=0D - if (RegEax >=3D 0x80000008) {=0D - AsmCpuid (0x80000008, &RegEax, NULL, NULL, NULL);=0D - PhysicalAddressBits =3D (UINT8)RegEax;=0D - } else {=0D - PhysicalAddressBits =3D 36;=0D - }=0D + PhysicalAddressBits =3D GetPhysicalAddressBits (NULL, NULL);=0D }=0D =0D return PhysicalAddressBits;=0D diff --git a/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume.c b/UefiCpuPkg= /Universal/Acpi/S3Resume2Pei/S3Resume.c index 8419a4e32acb..1017f0316093 100644 --- a/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume.c +++ b/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume.c @@ -42,6 +42,7 @@ #include =0D #include =0D #include =0D +#include =0D =0D /**=0D This macro aligns the address of a variable with auto storage=0D @@ -646,13 +647,7 @@ RestoreS3PageTables ( if (Hob !=3D NULL) {=0D PhysicalAddressBits =3D ((EFI_HOB_CPU *)Hob)->SizeOfMemorySpace;=0D } else {=0D - AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL);=0D - if (RegEax >=3D 0x80000008) {=0D - AsmCpuid (0x80000008, &RegEax, NULL, NULL, NULL);=0D - PhysicalAddressBits =3D (UINT8)RegEax;=0D - } else {=0D - PhysicalAddressBits =3D 36;=0D - }=0D + PhysicalAddressBits =3D GetPhysicalAddressBits (NULL, NULL);=0D }=0D =0D //=0D diff --git a/UefiCpuPkg/Include/Library/UefiCpuLib.h b/UefiCpuPkg/Include/L= ibrary/UefiCpuLib.h index 0ff4a35774c1..dabed95ab38a 100644 --- a/UefiCpuPkg/Include/Library/UefiCpuLib.h +++ b/UefiCpuPkg/Include/Library/UefiCpuLib.h @@ -62,4 +62,21 @@ GetCpuSteppingId ( VOID=0D );=0D =0D +/**=0D + Get the physical address width supported by the processor.=0D + @param[out] ValidAddressMask Bitmask with valid address bits se= t to=0D + one; other bits are clear. Optiona= l=0D + parameter.=0D + @param[out] ValidPageBaseAddressMask Bitmask with valid page base addre= ss=0D + bits set to one; other bits are cl= ear.=0D + Optional parameter.=0D + @return The physical address width supported by the processor.=0D +**/=0D +UINT8=0D +EFIAPI=0D +GetPhysicalAddressBits (=0D + OUT UINT64 *ValidAddressMask OPTIONAL,=0D + OUT UINT64 *ValidPageBaseAddressMask OPTIONAL=0D + );=0D +=0D #endif=0D --=20 2.30.0.windows.2