From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by mx.groups.io with SMTP id smtpd.web10.10057.1642493680052571638 for ; Tue, 18 Jan 2022 00:14:44 -0800 Authentication-Results: mx.groups.io; dkim=fail reason="unable to parse pub key" header.i=@intel.com header.s=intel header.b=WtQpQoU8; spf=pass (domain: intel.com, ip: 134.134.136.31, mailfrom: w.sheng@intel.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1642493683; x=1674029683; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=j/DNDM/lfJo477vosyZ/u/t5hNN6TW+F4I2f1oA4J4E=; b=WtQpQoU8IW+nnUZB2mohohwqeCviXmikq24pSKL1q8flYEUoHt5Br140 AOLorWb/bTFKXfiLo0o1c4OodCpEMnTNHJmMXkhGajQWYJ9c2nr7PFRb9 oVpHyNLeB8Q+Xx5yGGHXMhOTsPaN9Fspb46HgmJCf96cl+NT3CcyUYrZh zeFSDXOyEwsva3Ft31aY2ptoI7TdyH6hPNVz9nhWS3JIUkVM849kRR4LQ 26S+GKW4d4fV+VL7h8Ki148KmFR0yjCObRoi9/nHjfMXv4EGKPzx0BPfY zyE5L5JWLOPPJfuWN3hWlQxh55MX99HzoXcBnDFEJ1MzVwsRsIJYpqt60 Q==; X-IronPort-AV: E=McAfee;i="6200,9189,10230"; a="305496375" X-IronPort-AV: E=Sophos;i="5.88,296,1635231600"; d="scan'208";a="305496375" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Jan 2022 00:14:43 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.88,296,1635231600"; d="scan'208";a="517674501" Received: from unknown (HELO shwdeSSSDDPDWEI.ccr.corp.intel.com) ([10.239.157.43]) by orsmga007.jf.intel.com with ESMTP; 18 Jan 2022 00:14:41 -0800 From: "Sheng Wei" To: devel@edk2.groups.io Cc: Ray Ni , Rangasai V Chaganty , Jenny Huang , Robert Kowalewski Subject: [PATCH v5 2/4] IntelSiliconPkg/VTd: Update VTd register structs Date: Tue, 18 Jan 2022 16:14:31 +0800 Message-Id: <20220118081433.15620-3-w.sheng@intel.com> X-Mailer: git-send-email 2.16.2.windows.1 In-Reply-To: <20220118081433.15620-1-w.sheng@intel.com> References: <20220118081433.15620-1-w.sheng@intel.com> Update VTd register structs accroding to VTd spec ver 3.3 REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3765 Cc: Ray Ni Cc: Rangasai V Chaganty Cc: Jenny Huang Cc: Robert Kowalewski Reviewed-by: Jenny Huang Signed-off-by: Sheng Wei --- .../Feature/VTd/IntelVTdDmarPei/IntelVTdDmar.c | 3 +- .../Feature/VTd/IntelVTdDmarPei/TranslationTable.c | 23 +++++++++++---- .../Feature/VTd/IntelVTdDxe/TranslationTable.c | 22 ++++++++++++-- .../Feature/VTd/IntelVTdDxe/VtdReg.c | 7 +++-- .../IntelSiliconPkg/Include/IndustryStandard/Vtd.h | 34 +++++++++++++++++----- 5 files changed, 68 insertions(+), 21 deletions(-) diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/IntelVTdDmar.c b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/IntelVTdDmar.c index c3a939c9..87ce9716 100644 --- a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/IntelVTdDmar.c +++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/IntelVTdDmar.c @@ -631,10 +631,8 @@ DumpVtdECapRegs ( DEBUG ((DEBUG_INFO, " SC - 0x%x\n", ECapReg->Bits.SC)); DEBUG ((DEBUG_INFO, " IRO - 0x%x\n", ECapReg->Bits.IRO)); DEBUG ((DEBUG_INFO, " MHMV - 0x%x\n", ECapReg->Bits.MHMV)); - DEBUG ((DEBUG_INFO, " ECS - 0x%x\n", ECapReg->Bits.ECS)); DEBUG ((DEBUG_INFO, " MTS - 0x%x\n", ECapReg->Bits.MTS)); DEBUG ((DEBUG_INFO, " NEST - 0x%x\n", ECapReg->Bits.NEST)); - DEBUG ((DEBUG_INFO, " DIS - 0x%x\n", ECapReg->Bits.DIS)); DEBUG ((DEBUG_INFO, " PASID - 0x%x\n", ECapReg->Bits.PASID)); DEBUG ((DEBUG_INFO, " PRS - 0x%x\n", ECapReg->Bits.PRS)); DEBUG ((DEBUG_INFO, " ERS - 0x%x\n", ECapReg->Bits.ERS)); @@ -642,6 +640,7 @@ DumpVtdECapRegs ( DEBUG ((DEBUG_INFO, " NWFS - 0x%x\n", ECapReg->Bits.NWFS)); DEBUG ((DEBUG_INFO, " EAFS - 0x%x\n", ECapReg->Bits.EAFS)); DEBUG ((DEBUG_INFO, " PSS - 0x%x\n", ECapReg->Bits.PSS)); + DEBUG ((DEBUG_INFO, " ADMS - 0x%x\n", ECapReg->Bits.ADMS)); } diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/TranslationTable.c b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/TranslationTable.c index 6676b2a9..a309d566 100644 --- a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/TranslationTable.c +++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/TranslationTable.c @@ -884,13 +884,26 @@ SetupTranslationTable ( return Status; } - if (VtdUnitInfo->ECapReg.Bits.ECS) { - DEBUG ((DEBUG_INFO, "CreateExtContextEntry - %d\n", Index)); - Status = CreateExtContextEntry (VtdUnitInfo); + if (VtdUnitInfo->ECapReg.Bits.SMTS) { + if (VtdUnitInfo->ECapReg.Bits.DEP_24) { + DEBUG ((DEBUG_ERROR,"ECapReg.bit24 is not zero\n")); + ASSERT(FALSE); + Status = EFI_UNSUPPORTED; + } else { + Status = CreateExtContextEntry (VtdUnitInfo); + } } else { - DEBUG ((DEBUG_INFO, "CreateContextEntry - %d\n", Index)); - Status = CreateContextEntry (VtdUnitInfo); + if (VtdUnitInfo->ECapReg.Bits.DEP_24) { + // + // To compatible with pervious VTd engine + // It was ECS(Extended Context Support) bit. + // + Status = CreateExtContextEntry (VtdUnitInfo); + } else { + Status = CreateContextEntry (VtdUnitInfo); + } } + if (EFI_ERROR (Status)) { return Status; } diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTable.c b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTable.c index ca5f65a8..48e38d56 100644 --- a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTable.c +++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTable.c @@ -382,11 +382,27 @@ SetupTranslationTable ( for (Index = 0; Index < mVtdUnitNumber; Index++) { DEBUG((DEBUG_INFO, "CreateContextEntry - %d\n", Index)); - if (mVtdUnitInformation[Index].ECapReg.Bits.ECS) { - Status = CreateExtContextEntry (Index); + + if (mVtdUnitInformation[Index].ECapReg.Bits.SMTS) { + if (mVtdUnitInformation[Index].ECapReg.Bits.DEP_24) { + DEBUG ((DEBUG_ERROR,"ECapReg.bit24 is not zero\n")); + ASSERT(FALSE); + Status = EFI_UNSUPPORTED; + } else { + Status = CreateExtContextEntry (Index); + } } else { - Status = CreateContextEntry (Index); + if (mVtdUnitInformation[Index].ECapReg.Bits.DEP_24) { + // + // To compatible with pervious VTd engine + // It was ECS(Extended Context Support) bit. + // + Status = CreateExtContextEntry (Index); + } else { + Status = CreateContextEntry (Index); + } } + if (EFI_ERROR (Status)) { return Status; } diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/VtdReg.c b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/VtdReg.c index 1ce9c1c0..1aacd39a 100644 --- a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/VtdReg.c +++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/VtdReg.c @@ -698,10 +698,8 @@ DumpVtdECapRegs ( DEBUG((DEBUG_INFO, " SC - 0x%x\n", ECapReg->Bits.SC)); DEBUG((DEBUG_INFO, " IRO - 0x%x\n", ECapReg->Bits.IRO)); DEBUG((DEBUG_INFO, " MHMV - 0x%x\n", ECapReg->Bits.MHMV)); - DEBUG((DEBUG_INFO, " ECS - 0x%x\n", ECapReg->Bits.ECS)); DEBUG((DEBUG_INFO, " MTS - 0x%x\n", ECapReg->Bits.MTS)); DEBUG((DEBUG_INFO, " NEST - 0x%x\n", ECapReg->Bits.NEST)); - DEBUG((DEBUG_INFO, " DIS - 0x%x\n", ECapReg->Bits.DIS)); DEBUG((DEBUG_INFO, " PASID - 0x%x\n", ECapReg->Bits.PASID)); DEBUG((DEBUG_INFO, " PRS - 0x%x\n", ECapReg->Bits.PRS)); DEBUG((DEBUG_INFO, " ERS - 0x%x\n", ECapReg->Bits.ERS)); @@ -709,6 +707,8 @@ DumpVtdECapRegs ( DEBUG((DEBUG_INFO, " NWFS - 0x%x\n", ECapReg->Bits.NWFS)); DEBUG((DEBUG_INFO, " EAFS - 0x%x\n", ECapReg->Bits.EAFS)); DEBUG((DEBUG_INFO, " PSS - 0x%x\n", ECapReg->Bits.PSS)); + DEBUG((DEBUG_INFO, " SMTS - 0x%x\n", ECapReg->Bits.SMTS)); + DEBUG((DEBUG_INFO, " ADMS - 0x%x\n", ECapReg->Bits.ADMS)); } /** @@ -769,9 +769,10 @@ DumpVtdRegs ( DEBUG((DEBUG_INFO, " FRCD_REG[%d] - 0x%016lx %016lx\n", Index, FrcdReg.Uint64[1], FrcdReg.Uint64[0])); if (FrcdReg.Uint64[1] != 0 || FrcdReg.Uint64[0] != 0) { DEBUG((DEBUG_INFO, " Fault Info - 0x%016lx\n", VTD_64BITS_ADDRESS(FrcdReg.Bits.FILo, FrcdReg.Bits.FIHi))); + DEBUG((DEBUG_INFO, " Fault Bit - %d\n", FrcdReg.Bits.F)); SourceId.Uint16 = (UINT16)FrcdReg.Bits.SID; DEBUG((DEBUG_INFO, " Source - B%02x D%02x F%02x\n", SourceId.Bits.Bus, SourceId.Bits.Device, SourceId.Bits.Function)); - DEBUG((DEBUG_INFO, " Type - %x (%a)\n", FrcdReg.Bits.T, FrcdReg.Bits.T ? "read" : "write")); + DEBUG((DEBUG_INFO, " Type - 0x%02x\n", (FrcdReg.Bits.T1 << 1) | FrcdReg.Bits.T2)); DEBUG((DEBUG_INFO, " Reason - %x (Refer to VTd Spec, Appendix A)\n", FrcdReg.Bits.FR)); } } diff --git a/Silicon/Intel/IntelSiliconPkg/Include/IndustryStandard/Vtd.h b/Silicon/Intel/IntelSiliconPkg/Include/IndustryStandard/Vtd.h index a759ca10..32fbdd02 100644 --- a/Silicon/Intel/IntelSiliconPkg/Include/IndustryStandard/Vtd.h +++ b/Silicon/Intel/IntelSiliconPkg/Include/IndustryStandard/Vtd.h @@ -216,6 +216,7 @@ typedef union { #define B_GSTS_REG_RTPS BIT30 #define B_GSTS_REG_TE BIT31 #define R_RTADDR_REG 0x20 +#define V_RTADDR_REG_TTM_ADM (BIT11|BIT10) #define R_CCMD_REG 0x28 #define B_CCMD_REG_CIRG_MASK (BIT62|BIT61) #define V_CCMD_REG_CIRG_GLOBAL BIT61 @@ -334,7 +335,10 @@ typedef union { UINT8 FL1GP:1; // First Level 1-GByte Page Support UINT8 Rsvd_57:2; UINT8 PI:1; // Posted Interrupts Support - UINT8 Rsvd_60:4; + UINT8 FL5LP:1; // First Level 5-level Paging Support + UINT8 Rsvd_61:1; + UINT8 ESIRTPS:1; // Enhanced Set Interrupt Remap Table Pointer Support + UINT8 ESRTPS:1; // Enhanced Set Root Table Pointer Support } Bits; UINT64 Uint64; } VTD_CAP_REG; @@ -346,7 +350,7 @@ typedef union { UINT8 DT:1; // Device-TLB support UINT8 IR:1; // Interrupt Remapping support UINT8 EIM:1; // Extended Interrupt Mode - UINT8 Rsvd_5:1; + UINT8 DEP_5:1; UINT8 PT:1; // Pass Through UINT8 SC:1; // Snoop Control @@ -354,11 +358,11 @@ typedef union { UINT16 Rsvd_18:2; UINT16 MHMV:4; // Maximum Handle Mask Value - UINT8 ECS:1; // Extended Context Support + UINT8 DEP_24:1; UINT8 MTS:1; // Memory Type Support UINT8 NEST:1; // Nested Translation Support - UINT8 DIS:1; // Deferred Invalidate Support - UINT8 PASID:1; // Process Address Space ID Support + UINT8 Rsvd_27:1; + UINT8 DEP_28:1; UINT8 PRS:1; // Page Request Support UINT8 ERS:1; // Execute Request Support UINT8 SRS:1; // Supervisor Request Support @@ -367,7 +371,20 @@ typedef union { UINT32 NWFS:1; // No Write Flag Support UINT32 EAFS:1; // Extended Accessed Flag Support UINT32 PSS:5; // PASID Size Supported - UINT32 Rsvd_40:24; + UINT32 PASID:1; // Process Address Space ID Support + UINT32 DIT:1; // Device-TLB Invalidation Throttle + UINT32 PDS:1; // Page-request Drain Support + UINT32 SMTS:1; // Scalable Mode Translation Support + UINT32 VCS:1; // Virtual Command Support + UINT32 SLADS:1; // Second-Level Accessed Dirty Support + UINT32 SLTS:1; // Second-level Translation Support + UINT32 FLTS:1; // First-level Translation Support + UINT32 SMPWCS:1; // Scalable-Mode Page-walk Coherency Support + UINT32 RPS:1; // RID-PASID Support + UINT32 Rsvd_50:2; + UINT32 ADMS:1; // Abort DMA Mode Support + UINT32 RPRIVS:1; // RID_PRIV Support + UINT32 Rsvd_54:10; } Bits; UINT64 Uint64; } VTD_ECAP_REG; @@ -379,7 +396,8 @@ typedef union { UINT32 FIHi:32; // FaultInfo UINT32 SID:16; // Source Identifier - UINT32 Rsvd_80:13; + UINT32 Rsvd_80:12; + UINT32 T2:1; // Type bit2 (0: Write/Read, 1: Page/AtomicOp) UINT32 PRIV:1; // Privilege Mode Requested UINT32 EXE:1; // Execute Permission Requested UINT32 PP:1; // PASID Present @@ -387,7 +405,7 @@ typedef union { UINT32 FR:8; // Fault Reason UINT32 PV:20; // PASID Value UINT32 AT:2; // Address Type - UINT32 T:1; // Type (0: Write, 1: Read) + UINT32 T1:1; // Type bit1 (0: Write/Page, 1: Read/AtomicOp) UINT32 F:1; // Fault } Bits; UINT64 Uint64[2]; -- 2.16.2.windows.1