From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by mx.groups.io with SMTP id smtpd.web08.10054.1642493700408524031 for ; Tue, 18 Jan 2022 00:15:00 -0800 Authentication-Results: mx.groups.io; dkim=fail reason="unable to parse pub key" header.i=@intel.com header.s=intel header.b=lycLzrDl; spf=pass (domain: intel.com, ip: 134.134.136.65, mailfrom: w.sheng@intel.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1642493700; x=1674029700; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=JEiHzX3obrJIwd8p1w48D26ufsg2/rXrY8qvK1eIMm4=; b=lycLzrDlJoid5FKj2gvj2nYVmyjAIzyi3tbRrf5kDj5k7LyitnPZy0aF tDd1a8Abko14dMs3CrrjXYSJQmxZ4P0PFBqTrz8y7zpqqEKCa99zVl4Up vvTlWz6Yap1U8vuTEVzocFKfDPeCJhVtjnTkDglcDXb3h6uSCdjSmXhTi OASTan+7KAH4uO1mcadyEtSzS2esEk1+r4QsjWA5yavn+pjyep7TRoCBK N5qrrqDnWEtfJOYHng/Fqt/7SVxDG1bWRu2grZq5xSgnDyRST/FS3UT/A Y8YROQ14JJ8Jr9fIkS5crXoTSLCHqHzhlsNH3f+xRcwvzrLEVa3CneROr g==; X-IronPort-AV: E=McAfee;i="6200,9189,10230"; a="244721679" X-IronPort-AV: E=Sophos;i="5.88,296,1635231600"; d="scan'208";a="244721679" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Jan 2022 00:14:53 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.88,296,1635231600"; d="scan'208";a="517674512" Received: from unknown (HELO shwdeSSSDDPDWEI.ccr.corp.intel.com) ([10.239.157.43]) by orsmga007.jf.intel.com with ESMTP; 18 Jan 2022 00:14:43 -0800 From: "Sheng Wei" To: devel@edk2.groups.io Cc: Ray Ni , Rangasai V Chaganty , Jenny Huang , Robert Kowalewski Subject: [PATCH v5 3/4] IntelSiliconPkg/VTd: Support VTd Abort DMA Mode Date: Tue, 18 Jan 2022 16:14:32 +0800 Message-Id: <20220118081433.15620-4-w.sheng@intel.com> X-Mailer: git-send-email 2.16.2.windows.1 In-Reply-To: <20220118081433.15620-1-w.sheng@intel.com> References: <20220118081433.15620-1-w.sheng@intel.com> If VTd ECAP_REG.ADMS bit is set, abort DMA mode is supported. When VTd Abort DMA Mode is enabled, hardware will abort all DMA operations without the need to set up a root-table with each entry marked as not-present. REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3766 Cc: Ray Ni Cc: Rangasai V Chaganty Cc: Jenny Huang Cc: Robert Kowalewski Reviewed-by: Jenny Huang Signed-off-by: Sheng Wei --- .../Feature/VTd/IntelVTdDmarPei/IntelVTdDmar.c | 43 +++++++++++++--------- 1 file changed, 26 insertions(+), 17 deletions(-) diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/IntelVTdDmar.c b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/IntelVTdDmar.c index 87ce9716..63397a1a 100644 --- a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/IntelVTdDmar.c +++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/IntelVTdDmar.c @@ -384,7 +384,7 @@ InvalidateIOTLB ( Enable DMAR translation inpre-mem phase. @param[in] VtdUnitBaseAddress The base address of the VTd engine. - @param[in] RootEntryTable The address of the VTd RootEntryTable. + @param[in] RtaddrRegValue The value of RTADDR_REG. @retval EFI_SUCCESS DMAR translation is enabled. @retval EFI_DEVICE_ERROR DMAR translation is not enabled. @@ -392,15 +392,15 @@ InvalidateIOTLB ( EFI_STATUS EnableDmarPreMem ( IN UINTN VtdUnitBaseAddress, - IN UINTN RootEntryTable + IN UINTN RtaddrRegValue ) { UINT32 Reg32; DEBUG ((DEBUG_INFO, ">>>>>>EnableDmarPreMem() for engine [%x] \n", VtdUnitBaseAddress)); - DEBUG ((DEBUG_INFO, "RootEntryTable 0x%x \n", RootEntryTable)); - MmioWrite64 (VtdUnitBaseAddress + R_RTADDR_REG, (UINT64) (UINTN) RootEntryTable); + DEBUG ((DEBUG_INFO, "RTADDR_REG : 0x%x \n", RtaddrRegValue)); + MmioWrite64 (VtdUnitBaseAddress + R_RTADDR_REG, (UINT64) RtaddrRegValue); Reg32 = MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG); MmioWrite32 (VtdUnitBaseAddress + R_GCMD_REG, Reg32 | B_GMCD_REG_SRTP); @@ -662,18 +662,6 @@ EnableVTdTranslationProtectionAll ( DEBUG ((DEBUG_INFO, "EnableVTdTranslationProtectionAll - 0x%lx\n", EngineMask)); - Status = PeiServicesLocatePpi ( - &gEdkiiVTdNullRootEntryTableGuid, - 0, - NULL, - (VOID **)&RootEntryTable - ); - if (EFI_ERROR(Status)) { - DEBUG ((DEBUG_ERROR, "Locate Null Root Entry Table Ppi Failed : %r\n", Status)); - ASSERT (FALSE); - return; - } - for (Index = 0; Index < VTdInfo->VTdEngineCount; Index++) { if ((EngineMask & LShiftU64(1, Index)) == 0) { continue; @@ -686,7 +674,28 @@ EnableVTdTranslationProtectionAll ( VTdInfo->VtdUnitInfo[Index].ECapReg.Uint64 = MmioRead64 (VTdInfo->VtdUnitInfo[Index].VtdUnitBaseAddress + R_ECAP_REG); DumpVtdECapRegs (&VTdInfo->VtdUnitInfo[Index].ECapReg); - EnableDmarPreMem (VTdInfo->VtdUnitInfo[Index].VtdUnitBaseAddress, (UINTN) *RootEntryTable); + if (VTdInfo->VtdUnitInfo[Index].ECapReg.Bits.ADMS == 1) { + // + // Use Abort DMA Mode + // + Status = EnableDmarPreMem (VTdInfo->VtdUnitInfo[Index].VtdUnitBaseAddress, V_RTADDR_REG_TTM_ADM); + } else { + // + // Use Null Root Entry Table + // + Status = PeiServicesLocatePpi ( + &gEdkiiVTdNullRootEntryTableGuid, + 0, + NULL, + (VOID **)&RootEntryTable + ); + if (EFI_ERROR(Status)) { + DEBUG ((DEBUG_ERROR, "Locate Null Root Entry Table Ppi Failed : %r\n", Status)); + ASSERT (FALSE); + return; + } + EnableDmarPreMem (VTdInfo->VtdUnitInfo[Index].VtdUnitBaseAddress, (UINTN) *RootEntryTable); + } } return; -- 2.16.2.windows.1