From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mx0a-002e3701.pphosted.com (mx0a-002e3701.pphosted.com [148.163.147.86]) by mx.groups.io with SMTP id smtpd.web10.9949.1642758638982871271 for ; Fri, 21 Jan 2022 01:50:39 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@hpe.com header.s=pps0720 header.b=ZdUwlwoB; spf=permerror, err=parse error for token &{10 18 %{ir}.%{v}.%{d}.spf.has.pphosted.com}: invalid domain name (domain: hpe.com, ip: 148.163.147.86, mailfrom: prvs=00207f782d=abner.chang@hpe.com) Received: from pps.filterd (m0134422.ppops.net [127.0.0.1]) by mx0b-002e3701.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 20L7S06l023648; Fri, 21 Jan 2022 09:50:37 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=hpe.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : content-transfer-encoding : mime-version; s=pps0720; bh=khBUMCw2/tJ3ax0oEgUYC9zunH7FzQ2tkSEQhybpkUk=; b=ZdUwlwoBWryIbtouZxRPsWtR53OHfBe3vOfyfYG9WRijJfEpUyRQir2U07lTaIU8TyNL Y5bCcJAI0xkTZHn+PFi2GWMSsB+5XMzWomcXK9ZDS36/Rc5tNA6zXvb5v8Z+IMZ3kCsD 60VbPrDs6JNZvgc+HXikzNFl4VWrSDtmWWthVgN5Agg7zIL4ptwkkF1lZ6YP5zTz1kYW 3vyWXRP+3h8dRX0DAAkp7+RiS/IyiiwLRPT0WEsaz5K2FU/Z1PdoXPQDn9yv3OdOcMqu dkiYTbVM2xQQHtFaTIGH5LuMMGV75kHUotsSNn+9aYH6hxWn4KMWy+4L+s8pdwMgnym/ CQ== Received: from g4t3425.houston.hpe.com (g4t3425.houston.hpe.com [15.241.140.78]) by mx0b-002e3701.pphosted.com (PPS) with ESMTPS id 3dqrf5179q-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 21 Jan 2022 09:50:36 +0000 Received: from g9t2301.houston.hpecorp.net (g9t2301.houston.hpecorp.net [16.220.97.129]) by g4t3425.houston.hpe.com (Postfix) with ESMTP id B3861AA; Fri, 21 Jan 2022 09:50:35 +0000 (UTC) Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.229]) by g9t2301.houston.hpecorp.net (Postfix) with ESMTP id 9664D4C; Fri, 21 Jan 2022 09:50:34 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com, Daniel Schaefer , Sunil V L Subject: [edk2-platforms][PATCH 11/14] RISC-V/ProcessorPkg: Address Core CI Spelling errors. Date: Fri, 21 Jan 2022 16:48:45 +0800 Message-Id: <20220121084848.7695-12-abner.chang@hpe.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20220121084848.7695-1-abner.chang@hpe.com> References: <20220121084848.7695-1-abner.chang@hpe.com> X-Proofpoint-GUID: HJUAwfqr3GolaFori3l2YnLwJBlI7TA- X-Proofpoint-ORIG-GUID: HJUAwfqr3GolaFori3l2YnLwJBlI7TA- X-Proofpoint-UnRewURL: 0 URL was un-rewritten MIME-Version: 1.0 X-HPE-SCL: -1 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.816,Hydra:6.0.425,FMLib:17.11.62.513 definitions=2022-01-21_06,2022-01-20_01,2021-12-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 phishscore=0 impostorscore=0 clxscore=1015 suspectscore=0 bulkscore=0 malwarescore=0 spamscore=0 mlxlogscore=999 mlxscore=0 adultscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2201110000 definitions=main-2201210065 Content-Transfer-Encoding: quoted-printable Signed-off-by: Abner Chang Cc: Daniel Schaefer Cc: Sunil V L --- .../RISC-V/ProcessorPkg/RiscVProcessorPkg.dec | 4 ++-- .../RiscVFirmwareContextSbiLib.inf | 6 +++--- .../RiscVFirmwareContextSscratchLib.inf | 4 ++-- .../Include/Library/RiscVEdk2SbiLib.h | 16 ++++++++-------- .../RISC-V/ProcessorPkg/Include/OpensbiTypes.h | 4 ++-- .../Include/ProcessorSpecificHobData.h | 2 +- .../Include/SmbiosProcessorSpecificData.h | 4 ++-- .../Library/RiscVEdk2SbiLib/RiscVEdk2SbiLib.c | 16 ++++++++-------- .../RiscVFirmwareContextSbiLib.c | 4 ++-- .../RiscVFirmwareContextStvecLib.c | 4 ++-- 10 files changed, 32 insertions(+), 32 deletions(-) diff --git a/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec b/Silicon/RI= SC-V/ProcessorPkg/RiscVProcessorPkg.dec index 59634f4413..177c1a710d 100644 --- a/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec +++ b/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec @@ -1,7 +1,7 @@ -## @file RiscVProcesssorPkg.dec=0D +## @file RiscVProcessorPkg.dec=0D # This Package provides UEFI RISC-V processor modules and libraries.=0D #=0D -# Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All right= s reserved.
=0D +# Copyright (c) 2020-2022, Hewlett Packard Enterprise Development LP. All = rights reserved.
=0D #=0D # SPDX-License-Identifier: BSD-2-Clause-Patent=0D #=0D diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSbiLib= /RiscVFirmwareContextSbiLib.inf b/Silicon/RISC-V/ProcessorPkg/Library/RiscV= FirmwareContextSbiLib/RiscVFirmwareContextSbiLib.inf index 0edf781149..1e4f14724b 100644 --- a/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSbiLib/RiscVF= irmwareContextSbiLib.inf +++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSbiLib/RiscVF= irmwareContextSbiLib.inf @@ -1,9 +1,9 @@ ## @file=0D -# Instance of OpebSBI Firmware Conext Library=0D +# Instance of OpenSBI Firmware Context Library=0D #=0D -# This iinstance uses RISC-V OpenSBI Firmware Extension SBI.=0D +# This instance uses RISC-V OpenSBI Firmware Extension SBI.=0D #=0D -# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
=0D +# Copyright (c) 2021-2022, Hewlett Packard Enterprise Development LP. All= rights reserved.
=0D #=0D # SPDX-License-Identifier: BSD-2-Clause-Patent=0D #=0D diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSscrat= chLib/RiscVFirmwareContextSscratchLib.inf b/Silicon/RISC-V/ProcessorPkg/Lib= rary/RiscVFirmwareContextSscratchLib/RiscVFirmwareContextSscratchLib.inf index 750c1cf51f..09e635fd1d 100644 --- a/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSscratchLib/R= iscVFirmwareContextSscratchLib.inf +++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSscratchLib/R= iscVFirmwareContextSscratchLib.inf @@ -1,9 +1,9 @@ ## @file=0D -# Instance of OpebSBI Firmware Conext Library=0D +# Instance of OpenSBI Firmware Context Library=0D #=0D # This instance uses RISC-V Supervisor mode SCRATCH CSR=0D #=0D -# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
=0D +# Copyright (c) 2021-2022, Hewlett Packard Enterprise Development LP. All= rights reserved.
=0D #=0D # SPDX-License-Identifier: BSD-2-Clause-Patent=0D #=0D diff --git a/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVEdk2SbiLib.h = b/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVEdk2SbiLib.h index 88d957f002..6089137373 100644 --- a/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVEdk2SbiLib.h +++ b/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVEdk2SbiLib.h @@ -1,7 +1,7 @@ /** @file=0D Library to call the RISC-V SBI ecalls=0D =0D - Copyright (c) 2021, Hewlett Packard Development LP. All rights reserved.=
=0D + Copyright (c) 2021-2022, Hewlett Packard Development LP. All rights rese= rved.
=0D =0D SPDX-License-Identifier: BSD-2-Clause-Patent=0D =0D @@ -54,7 +54,7 @@ SbiGetSpecVersion ( /**=0D Get the SBI implementation ID=0D =0D - This ID is used to idenetify a specific SBI implementation in order to w= ork=0D + This ID is used to identify a specific SBI implementation in order to wo= rk=0D around any quirks it might have.=0D =0D @param[out] ImplId The ID of the SBI implementation.=0D @@ -275,7 +275,7 @@ SbiRemoteFenceI ( /**=0D Instructs the remote harts to execute one or more SFENCE.VMA instruction= s.=0D =0D - The SFENCE.VMA covers the range of virtual addresses between StartAaddr = and Size.=0D + The SFENCE.VMA covers the range of virtual addresses between StartAddr a= nd Size.=0D =0D The remote fence function acts as a full tlb flush if * StartAddr and si= ze=0D are both 0 * size is equal to 2^XLEN-1=0D @@ -305,7 +305,7 @@ SbiRemoteSfenceVma ( /**=0D Instructs the remote harts to execute one or more SFENCE.VMA instruction= s.=0D =0D - The SFENCE.VMA covers the range of virtual addresses between StartAaddr = and Size.=0D + The SFENCE.VMA covers the range of virtual addresses between StartAddr a= nd Size.=0D Covers only the given ASID.=0D =0D The remote fence function acts as a full tlb flush if * StartAddr and si= ze=0D @@ -337,7 +337,7 @@ SbiRemoteSfenceVmaAsid ( /**=0D Instructs the remote harts to execute one or more SFENCE.GVMA instructio= ns.=0D =0D - The SFENCE.GVMA covers the range of virtual addresses between StartAaddr= and Size.=0D + The SFENCE.GVMA covers the range of virtual addresses between StartAddr = and Size.=0D Covers only the given VMID.=0D This function call is only valid for harts implementing the hypervisor e= xtension.=0D =0D @@ -373,7 +373,7 @@ SbiRemoteHfenceGvmaVmid ( /**=0D Instructs the remote harts to execute one or more SFENCE.GVMA instructio= ns.=0D =0D - The SFENCE.GVMA covers the range of virtual addresses between StartAaddr= and Size.=0D + The SFENCE.GVMA covers the range of virtual addresses between StartAddr = and Size.=0D This function call is only valid for harts implementing the hypervisor e= xtension.=0D =0D The remote fence function acts as a full tlb flush if * StartAddr and si= ze=0D @@ -407,7 +407,7 @@ SbiRemoteHfenceGvma ( /**=0D Instructs the remote harts to execute one or more SFENCE.VVMA instructio= ns.=0D =0D - The SFENCE.GVMA covers the range of virtual addresses between StartAaddr= and Size.=0D + The SFENCE.GVMA covers the range of virtual addresses between StartAddr = and Size.=0D Covers only the given ASID.=0D This function call is only valid for harts implementing the hypervisor e= xtension.=0D =0D @@ -443,7 +443,7 @@ SbiRemoteHfenceVvmaAsid ( /**=0D Instructs the remote harts to execute one or more SFENCE.VVMA instructio= ns.=0D =0D - The SFENCE.GVMA covers the range of virtual addresses between StartAaddr= and Size.=0D + The SFENCE.GVMA covers the range of virtual addresses between StartAddr = and Size.=0D This function call is only valid for harts implementing the hypervisor e= xtension.=0D =0D The remote fence function acts as a full tlb flush if * StartAddr and si= ze=0D diff --git a/Silicon/RISC-V/ProcessorPkg/Include/OpensbiTypes.h b/Silicon/R= ISC-V/ProcessorPkg/Include/OpensbiTypes.h index 8a6ea97708..ca7fc7a4ac 100644 --- a/Silicon/RISC-V/ProcessorPkg/Include/OpensbiTypes.h +++ b/Silicon/RISC-V/ProcessorPkg/Include/OpensbiTypes.h @@ -1,7 +1,7 @@ /** @file=0D - RISC-V OpesbSBI header file reference.=0D + RISC-V OpensbiSBI header file reference.=0D =0D - Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All right= s reserved.
=0D + Copyright (c) 2020-2022, Hewlett Packard Enterprise Development LP. All = rights reserved.
=0D =0D SPDX-License-Identifier: BSD-2-Clause-Patent=0D =0D diff --git a/Silicon/RISC-V/ProcessorPkg/Include/ProcessorSpecificHobData.h= b/Silicon/RISC-V/ProcessorPkg/Include/ProcessorSpecificHobData.h index 97285289f7..4b2a92e2f2 100644 --- a/Silicon/RISC-V/ProcessorPkg/Include/ProcessorSpecificHobData.h +++ b/Silicon/RISC-V/ProcessorPkg/Include/ProcessorSpecificHobData.h @@ -29,7 +29,7 @@ typedef struct { EFI_GUID CoreGuid;=0D VOID *Context; // The additional information of this core whi= ch=0D // built in PEI phase and carried to DXE phase= .=0D - // The content is pocessor or platform specifi= c.=0D + // The content is processor or platform specif= ic.=0D SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA ProcessorSpecificData;=0D } RISC_V_PROCESSOR_SPECIFIC_HOB_DATA;=0D =0D diff --git a/Silicon/RISC-V/ProcessorPkg/Include/SmbiosProcessorSpecificDat= a.h b/Silicon/RISC-V/ProcessorPkg/Include/SmbiosProcessorSpecificData.h index 81e48cd068..85b8dcbe20 100644 --- a/Silicon/RISC-V/ProcessorPkg/Include/SmbiosProcessorSpecificData.h +++ b/Silicon/RISC-V/ProcessorPkg/Include/SmbiosProcessorSpecificData.h @@ -1,9 +1,9 @@ /** @file=0D Industry Standard Definitions of RISC-V Processor Specific data defined = in=0D - below link for complaiant with SMBIOS Table Specification v3.3.0.=0D + below link for compliant with SMBIOS Table Specification v3.3.0.=0D https://github.com/riscv/riscv-smbios=0D =0D - Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All right= s reserved.
=0D + Copyright (c) 2019-2022, Hewlett Packard Enterprise Development LP. All = rights reserved.
=0D =0D SPDX-License-Identifier: BSD-2-Clause-Patent=0D =0D diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVEdk2SbiLib/RiscVEdk2S= biLib.c b/Silicon/RISC-V/ProcessorPkg/Library/RiscVEdk2SbiLib/RiscVEdk2SbiL= ib.c index 319526ed8f..a51139542d 100644 --- a/Silicon/RISC-V/ProcessorPkg/Library/RiscVEdk2SbiLib/RiscVEdk2SbiLib.c +++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVEdk2SbiLib/RiscVEdk2SbiLib.c @@ -15,7 +15,7 @@ - SbiLegacyRemoteSfenceVmaAsid -> Use SbiRemoteSfenceVmaAsid=0D - SbiLegacyShutdown -> Wait for new System Reset extension=0D =0D - Copyright (c) 2021, Hewlett Packard Development LP. All rights reserved.=
=0D + Copyright (c) 2021-2022, Hewlett Packard Development LP. All rights rese= rved.
=0D SPDX-License-Identifier: BSD-2-Clause-Patent=0D =0D @par Revision Reference:=0D @@ -173,7 +173,7 @@ SbiGetSpecVersion ( /**=0D Get the SBI implementation ID=0D =0D - This ID is used to idenetify a specific SBI implementation in order to w= ork=0D + This ID is used to identify a specific SBI implementation in order to wo= rk=0D around any quirks it might have.=0D =0D @param[out] ImplId The ID of the SBI implementation.=0D @@ -441,7 +441,7 @@ SbiRemoteFenceI ( /**=0D Instructs the remote harts to execute one or more SFENCE.VMA instruction= s.=0D =0D - The SFENCE.VMA covers the range of virtual addresses between StartAaddr = and Size.=0D + The SFENCE.VMA covers the range of virtual addresses between StartAddr a= nd Size.=0D =0D The remote fence function acts as a full tlb flush if * StartAddr and si= ze=0D are both 0 * size is equal to 2^XLEN-1=0D @@ -483,7 +483,7 @@ SbiRemoteSfenceVma ( /**=0D Instructs the remote harts to execute one or more SFENCE.VMA instruction= s.=0D =0D - The SFENCE.VMA covers the range of virtual addresses between StartAaddr = and Size.=0D + The SFENCE.VMA covers the range of virtual addresses between StartAddr a= nd Size.=0D Covers only the given ASID.=0D =0D The remote fence function acts as a full tlb flush if * StartAddr and si= ze=0D @@ -528,7 +528,7 @@ SbiRemoteSfenceVmaAsid ( /**=0D Instructs the remote harts to execute one or more SFENCE.GVMA instructio= ns.=0D =0D - The SFENCE.GVMA covers the range of virtual addresses between StartAaddr= and Size.=0D + The SFENCE.GVMA covers the range of virtual addresses between StartAddr = and Size.=0D Covers only the given VMID.=0D This function call is only valid for harts implementing the hypervisor e= xtension.=0D =0D @@ -577,7 +577,7 @@ SbiRemoteHFenceGvmaVmid ( /**=0D Instructs the remote harts to execute one or more SFENCE.GVMA instructio= ns.=0D =0D - The SFENCE.GVMA covers the range of virtual addresses between StartAaddr= and Size.=0D + The SFENCE.GVMA covers the range of virtual addresses between StartAddr = and Size.=0D This function call is only valid for harts implementing the hypervisor e= xtension.=0D =0D The remote fence function acts as a full tlb flush if * StartAddr and si= ze=0D @@ -623,7 +623,7 @@ SbiRemoteHFenceGvma ( /**=0D Instructs the remote harts to execute one or more SFENCE.VVMA instructio= ns.=0D =0D - The SFENCE.GVMA covers the range of virtual addresses between StartAaddr= and Size.=0D + The SFENCE.GVMA covers the range of virtual addresses between StartAddr = and Size.=0D Covers only the given ASID.=0D This function call is only valid for harts implementing the hypervisor e= xtension.=0D =0D @@ -672,7 +672,7 @@ SbiRemoteHFenceVvmaAsid ( /**=0D Instructs the remote harts to execute one or more SFENCE.VVMA instructio= ns.=0D =0D - The SFENCE.GVMA covers the range of virtual addresses between StartAaddr= and Size.=0D + The SFENCE.GVMA covers the range of virtual addresses between StartAddr = and Size.=0D This function call is only valid for harts implementing the hypervisor e= xtension.=0D =0D The remote fence function acts as a full tlb flush if * StartAddr and si= ze=0D diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSbiLib= /RiscVFirmwareContextSbiLib.c b/Silicon/RISC-V/ProcessorPkg/Library/RiscVFi= rmwareContextSbiLib/RiscVFirmwareContextSbiLib.c index 6125618eaf..a2a18d3eb7 100644 --- a/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSbiLib/RiscVF= irmwareContextSbiLib.c +++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSbiLib/RiscVF= irmwareContextSbiLib.c @@ -1,8 +1,8 @@ /** @file=0D - This iinstance uses RISC-V OpenSBI Firmware Extension SBI to=0D + This instance uses RISC-V OpenSBI Firmware Extension SBI to=0D get the pointer of firmware context.=0D =0D - Copyright (c) 2021 Hewlett Packard Enterprise Development LP. All rights= reserved.
=0D + Copyright (c) 2021-2022 Hewlett Packard Enterprise Development LP. All r= ights reserved.
=0D =0D SPDX-License-Identifier: BSD-2-Clause-Patent=0D **/=0D diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextStvecL= ib/RiscVFirmwareContextStvecLib.c b/Silicon/RISC-V/ProcessorPkg/Library/Ris= cVFirmwareContextStvecLib/RiscVFirmwareContextStvecLib.c index 7d1675355a..d08b51d3d9 100644 --- a/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextStvecLib/Risc= VFirmwareContextStvecLib.c +++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextStvecLib/Risc= VFirmwareContextStvecLib.c @@ -1,8 +1,8 @@ /** @file=0D - This instance uses This iinstance Supervisor mode STVEC CSR to=0D + This instance uses This instance Supervisor mode STVEC CSR to=0D get/set the pointer of firmware context.=0D =0D - Copyright (c) 2021 Hewlett Packard Enterprise Development LP. All rights= reserved.
=0D + Copyright (c) 2021-2022 Hewlett Packard Enterprise Development LP. All r= ights reserved.
=0D =0D SPDX-License-Identifier: BSD-2-Clause-Patent=0D **/=0D --=20 2.31.1