From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mx0b-002e3701.pphosted.com (mx0b-002e3701.pphosted.com [148.163.143.35]) by mx.groups.io with SMTP id smtpd.web11.6083.1642838105899121873 for ; Fri, 21 Jan 2022 23:55:06 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@hpe.com header.s=pps0720 header.b=YhU7+Cei; spf=permerror, err=parse error for token &{10 18 %{ir}.%{v}.%{d}.spf.has.pphosted.com}: invalid domain name (domain: hpe.com, ip: 148.163.143.35, mailfrom: prvs=00215b754f=abner.chang@hpe.com) Received: from pps.filterd (m0148664.ppops.net [127.0.0.1]) by mx0b-002e3701.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 20M6WQxS019065; Sat, 22 Jan 2022 07:55:05 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=hpe.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding; s=pps0720; bh=S3duhf46wzVuY91Scs9O5Jw0Y8yBG5PC/WQAdZSeu8E=; b=YhU7+CeiiZ+Rd1cNeW5oG1csc4APIL0kPSwLdhR2zQRmYsj6FwM+/fqHSZMYdhCbBIXQ 5lyjvgwUROAkY8jFyIhCRqudzXdonpsqMLoVqOG6IKUebxegxazrVHz7leKPhv3LeSJ9 AfJtwmdxRy7kpy9k7Zi+AY5sh+eY1s5VgUwAiSKibYXG/RDKGYOMZpcuVS1YedDn22ja oCPBMSApG+oOJAdW06xE1DKotWkY36Yycc4c2WrdLfOxTClNxb5/89y+O54qASpqT/iO c1gvH9d7uBzK1dikuoG86J1KIRxTBHQLww6/mTrosdDl+I5B/a8n+E9cvPzjWzgqi/t8 4w== Received: from g9t5009.houston.hpe.com (g9t5009.houston.hpe.com [15.241.48.73]) by mx0b-002e3701.pphosted.com (PPS) with ESMTPS id 3drb2mgsxt-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Sat, 22 Jan 2022 07:55:05 +0000 Received: from g4t3433.houston.hpecorp.net (g4t3433.houston.hpecorp.net [16.208.49.245]) by g9t5009.houston.hpe.com (Postfix) with ESMTP id 5F2D055; Sat, 22 Jan 2022 07:55:04 +0000 (UTC) Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.229]) by g4t3433.houston.hpecorp.net (Postfix) with ESMTP id 4D1F245; Sat, 22 Jan 2022 07:55:03 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com, Daniel Schaefer , Sunil V L Subject: [edk2-platforms][PATCH V2 09/14] RISC-V/ProcessorPkg: Address Core CI ECC errors. Date: Sat, 22 Jan 2022 14:53:13 +0800 Message-Id: <20220122065318.21808-10-abner.chang@hpe.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20220122065318.21808-1-abner.chang@hpe.com> References: <20220122065318.21808-1-abner.chang@hpe.com> MIME-Version: 1.0 X-Proofpoint-GUID: T4IcVdGgzPgxbyDaGvWvOVml0VpyfXAe X-Proofpoint-ORIG-GUID: T4IcVdGgzPgxbyDaGvWvOVml0VpyfXAe X-HPE-SCL: -1 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.816,Hydra:6.0.425,FMLib:17.11.62.513 definitions=2022-01-22_03,2022-01-21_01,2021-12-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 suspectscore=0 lowpriorityscore=0 mlxlogscore=999 mlxscore=0 impostorscore=0 adultscore=0 priorityscore=1501 spamscore=0 clxscore=1015 phishscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2201110000 definitions=main-2201220050 Content-Transfer-Encoding: quoted-printable Signed-off-by: Abner Chang Cc: Daniel Schaefer Cc: Sunil V L --- .../RISC-V/ProcessorPkg/RiscVProcessorPkg.dec | 2 ++ .../RISC-V/ProcessorPkg/RiscVProcessorPkg.dsc | 4 ++-- .../RiscVFirmwareContextSbiLib.inf | 2 +- .../Include/Library/MachineModeTimerLib.h | 15 +++++++++++++ .../Include/Library/RiscVPlatformTimerLib.h | 21 +++++++++++++++++++ .../ProcessorPkg/Include/OpensbiTypes.h | 6 +++--- .../Include/ProcessorSpecificHobData.h | 8 +++---- .../CpuExceptionHandlerLib.h | 2 +- .../Universal/SmbiosDxe/RiscVSmbiosDxe.c | 12 +++++------ .../RISC-V/ProcessorPkg/RiscVProcessorPkg.uni | 18 +++++++++++++++- 10 files changed, 72 insertions(+), 18 deletions(-) create mode 100644 Silicon/RISC-V/ProcessorPkg/Include/Library/MachineMode= TimerLib.h create mode 100644 Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVPlatfo= rmTimerLib.h diff --git a/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec b/Silicon/RI= SC-V/ProcessorPkg/RiscVProcessorPkg.dec index 9c8b57cce3..045fc55212 100644 --- a/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec +++ b/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec @@ -26,6 +26,8 @@ RiscVCpuLib|Include/Library/RiscVCpuLib.h=0D RiscVEdk2SbiLib|Include/Library/RiscVEdk2SbiLib.h=0D RiscVFirmwareContextLib|Include/Library/RiscVFirmwareContextLib.h=0D + RiscVPlatformTimerLib|Include/Library/RiscVPlatformTimerLib.h=0D + MachineModeTimerLib|Include/Library/MachineModeTimerLib.h=0D =0D [Guids]=0D gUefiRiscVPkgTokenSpaceGuid =3D { 0x4261e9c8, 0x52c0, 0x4b34, { 0x85, 0= x3d, 0x48, 0x46, 0xea, 0xd3, 0xb7, 0x2c}}=0D diff --git a/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dsc b/Silicon/RI= SC-V/ProcessorPkg/RiscVProcessorPkg.dsc index 563b9e7088..0591cd6a6c 100644 --- a/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dsc +++ b/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dsc @@ -1,11 +1,11 @@ -#/** @file=0D +## @file=0D # RISC-V processor package.=0D #=0D # Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All right= s reserved.
=0D #=0D # SPDX-License-Identifier: BSD-2-Clause-Patent=0D #=0D -#**/=0D +#=0D =0D ##########################################################################= ######=0D #=0D diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSbiLib= /RiscVFirmwareContextSbiLib.inf b/Silicon/RISC-V/ProcessorPkg/Library/RiscV= FirmwareContextSbiLib/RiscVFirmwareContextSbiLib.inf index 168b705453..0edf781149 100644 --- a/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSbiLib/RiscVF= irmwareContextSbiLib.inf +++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSbiLib/RiscVF= irmwareContextSbiLib.inf @@ -12,7 +12,7 @@ [Defines]=0D INF_VERSION =3D 0x0001001b=0D BASE_NAME =3D RiscVFirmwareContextSbiLib=0D - FILE_GUID =3D 3709E048-6794-427A-B728-BFE3FFD6D461= =0D + FILE_GUID =3D 308117C0-400A-79C5-6ED4-AB9763A202E5= =0D MODULE_TYPE =3D PEIM=0D VERSION_STRING =3D 1.0=0D LIBRARY_CLASS =3D RiscVFirmwareContextLib|PEIM PEI_CORE= =0D diff --git a/Silicon/RISC-V/ProcessorPkg/Include/Library/MachineModeTimerLi= b.h b/Silicon/RISC-V/ProcessorPkg/Include/Library/MachineModeTimerLib.h new file mode 100644 index 0000000000..a27391cca3 --- /dev/null +++ b/Silicon/RISC-V/ProcessorPkg/Include/Library/MachineModeTimerLib.h @@ -0,0 +1,15 @@ +/** @file=0D + RISC-V Machine Mode Timer Library Definition=0D +=0D + Copyright (c) 2022, Hewlett Packard Enterprise Development LP. All right= s reserved.
=0D +=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +=0D +#ifndef MACHINE_MODE_TIMER_LIB_H_=0D +#define MACHINE_MODE_TIMER_LIB_H_=0D +=0D +UINT64=0D +RiscVReadMachineTimerInterface (VOID);=0D +=0D +#endif=0D diff --git a/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVPlatformTimer= Lib.h b/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVPlatformTimerLib.h new file mode 100644 index 0000000000..dcd8734eb5 --- /dev/null +++ b/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVPlatformTimerLib.h @@ -0,0 +1,21 @@ +/** @file=0D + RISC-V Platform Timer library definitions.=0D +=0D + Copyright (c) 2022, Hewlett Packard Enterprise Development LP. All right= s reserved.
=0D +=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +=0D +#ifndef RISCV_PLATFORM_TIMER_LIB_H_=0D +#define RISCV_PLATFORM_TIMER_LIB_H_=0D +=0D +UINT64=0D +RiscVReadMachineTimer (VOID);=0D +=0D +VOID=0D +RiscVSetMachineTimerCmp (UINT64);=0D +=0D +UINT64=0D +RiscVReadMachineTimerCmp(VOID);=0D +=0D +#endif=0D diff --git a/Silicon/RISC-V/ProcessorPkg/Include/OpensbiTypes.h b/Silicon/R= ISC-V/ProcessorPkg/Include/OpensbiTypes.h index bbf74e2a82..8a6ea97708 100644 --- a/Silicon/RISC-V/ProcessorPkg/Include/OpensbiTypes.h +++ b/Silicon/RISC-V/ProcessorPkg/Include/OpensbiTypes.h @@ -44,8 +44,8 @@ typedef UINT64 virtual_size_t; typedef UINT64 physical_addr_t;=0D typedef UINT64 physical_size_t;=0D =0D -#define true TRUE=0D -#define false FALSE=0D +#define true TRUE=0D +#define false FALSE=0D =0D #define __packed __attribute__((packed))=0D #define __noreturn __attribute__((noreturn))=0D @@ -70,7 +70,7 @@ typedef UINT64 physical_size_t; const typeof(((type *)0)->member) * __mptr =3D (ptr); \=0D (type *)((char *)__mptr - offsetof(type, member)); })=0D =0D -#define array_size(x) (sizeof(x) / sizeof((x)[0]))=0D +#define array_size(x) (sizeof(x) / sizeof((x)[0]))=0D =0D #define CLAMP(a, lo, hi) MIN(MAX(a, lo), hi)=0D #define ROUNDUP(a, b) ((((a)-1) / (b) + 1) * (b))=0D diff --git a/Silicon/RISC-V/ProcessorPkg/Include/ProcessorSpecificHobData.h= b/Silicon/RISC-V/ProcessorPkg/Include/ProcessorSpecificHobData.h index 2f5847e53e..97285289f7 100644 --- a/Silicon/RISC-V/ProcessorPkg/Include/ProcessorSpecificHobData.h +++ b/Silicon/RISC-V/ProcessorPkg/Include/ProcessorSpecificHobData.h @@ -1,7 +1,7 @@ /** @file=0D Definition of Processor Specific Data HOB.=0D =0D - Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All right= s reserved.
=0D + Copyright (c) 2019-2022, Hewlett Packard Enterprise Development LP. All = rights reserved.
=0D =0D SPDX-License-Identifier: BSD-2-Clause-Patent=0D =0D @@ -24,7 +24,7 @@ /// RISC-V processor specific data HOB=0D ///=0D typedef struct {=0D - EFI_GUID ParentPrcessorGuid;=0D + EFI_GUID ParentProcessorGuid;=0D UINTN ParentProcessorUid;=0D EFI_GUID CoreGuid;=0D VOID *Context; // The additional information of this core whi= ch=0D @@ -37,7 +37,7 @@ typedef struct { /// RISC-V SMBIOS type 4 (Processor) GUID data HOB=0D ///=0D typedef struct {=0D - EFI_GUID PrcessorGuid;=0D + EFI_GUID ProcessorGuid;=0D UINTN ProcessorUid;=0D SMBIOS_TABLE_TYPE4 SmbiosType4Processor;=0D UINT16 EndingZero;=0D @@ -75,7 +75,7 @@ typedef struct { /// RISC-V SMBIOS type 7 (Cache) GUID data HOB=0D ///=0D typedef struct {=0D - EFI_GUID PrcessorGuid;=0D + EFI_GUID ProcessorGuid;=0D UINTN ProcessorUid;=0D SMBIOS_TABLE_TYPE7 SmbiosType7Cache;=0D UINT16 EndingZero;=0D diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVExceptionLib/CpuExcep= tionHandlerLib.h b/Silicon/RISC-V/ProcessorPkg/Library/RiscVExceptionLib/Cp= uExceptionHandlerLib.h index 3e480e9b09..b316510020 100644 --- a/Silicon/RISC-V/ProcessorPkg/Library/RiscVExceptionLib/CpuExceptionHan= dlerLib.h +++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVExceptionLib/CpuExceptionHan= dlerLib.h @@ -1,4 +1,4 @@ -/**@file=0D +/** @file=0D =0D RISC-V Exception Handler library definition file.=0D =0D diff --git a/Silicon/RISC-V/ProcessorPkg/Universal/SmbiosDxe/RiscVSmbiosDxe= .c b/Silicon/RISC-V/ProcessorPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.c index b30f9d7f6a..14f62c4036 100644 --- a/Silicon/RISC-V/ProcessorPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.c +++ b/Silicon/RISC-V/ProcessorPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.c @@ -1,7 +1,7 @@ /** @file=0D RISC-V generic SMBIOS DXE driver to build up SMBIOS type 4, type 7 and t= ype 44 records.=0D =0D - Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All right= s reserved.
=0D + Copyright (c) 2019-2022, Hewlett Packard Enterprise Development LP. All = rights reserved.
=0D =0D SPDX-License-Identifier: BSD-2-Clause-Patent=0D =0D @@ -33,7 +33,7 @@ BuildSmbiosType7 ( EFI_STATUS Status;=0D SMBIOS_HANDLE Handle;=0D =0D - if (!CompareGuid (&Type4HobData->PrcessorGuid, &Type7DataHob->PrcessorGu= id) ||=0D + if (!CompareGuid (&Type4HobData->ProcessorGuid, &Type7DataHob->Processor= Guid) ||=0D Type4HobData->ProcessorUid !=3D Type7DataHob->ProcessorUid) {=0D return EFI_INVALID_PARAMETER;=0D }=0D @@ -48,7 +48,7 @@ BuildSmbiosType7 ( return Status;=0D }=0D DEBUG ((DEBUG_INFO, "SMBIOS Type 7 was added. SMBIOS Handle: 0x%x\n", Ha= ndle));=0D - DEBUG ((DEBUG_VERBOSE, " Cache belone to processor GUID: %g\n", &Typ= e7DataHob->PrcessorGuid));=0D + DEBUG ((DEBUG_VERBOSE, " Cache belone to processor GUID: %g\n", &Typ= e7DataHob->ProcessorGuid));=0D DEBUG ((DEBUG_VERBOSE, " Cache belone processor UID: %d\n", Type7Da= taHob->ProcessorUid));=0D DEBUG ((DEBUG_VERBOSE, " =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D\n"));=0D DEBUG ((DEBUG_VERBOSE, " Socket Designation: %d\n", Type7DataHob->Sm= biosType7Cache.SocketDesignation));=0D @@ -90,7 +90,7 @@ BuildSmbiosType4 ( EFI_STATUS Status;=0D =0D DEBUG ((DEBUG_INFO, "Building Type 4.\n"));=0D - DEBUG ((DEBUG_INFO, " Processor GUID: %g\n", &Type4HobData->PrcessorG= uid));=0D + DEBUG ((DEBUG_INFO, " Processor GUID: %g\n", &Type4HobData->Processor= Guid));=0D DEBUG ((DEBUG_INFO, " Processor UUID: %d\n", Type4HobData->ProcessorU= id));=0D =0D Type4HobData->SmbiosType4Processor.L1CacheHandle =3D RISC_V_CACHE_INFO_N= OT_PROVIDED;=0D @@ -193,7 +193,7 @@ BuildSmbiosType44 ( EFI_STATUS Status;=0D =0D DEBUG ((DEBUG_INFO, "Building Type 44 for...\n"));=0D - DEBUG ((DEBUG_VERBOSE, " Processor GUID: %g\n", &Type4HobData->Prces= sorGuid));=0D + DEBUG ((DEBUG_VERBOSE, " Processor GUID: %g\n", &Type4HobData->Proce= ssorGuid));=0D DEBUG ((DEBUG_VERBOSE, " Processor UUID: %d\n", Type4HobData->Proces= sorUid));=0D =0D GuidHob =3D (EFI_HOB_GUID_TYPE *)GetFirstGuidHob ((EFI_GUID *)PcdGetPtr(= PcdProcessorSpecificDataGuidHobGuid));=0D @@ -206,7 +206,7 @@ BuildSmbiosType44 ( //=0D do {=0D ProcessorSpecificData =3D (RISC_V_PROCESSOR_SPECIFIC_HOB_DATA *)GET_GU= ID_HOB_DATA (GuidHob);=0D - if (!CompareGuid (&ProcessorSpecificData->ParentPrcessorGuid, &Type4Ho= bData->PrcessorGuid) ||=0D + if (!CompareGuid (&ProcessorSpecificData->ParentProcessorGuid, &Type4H= obData->ProcessorGuid) ||=0D ProcessorSpecificData->ParentProcessorUid !=3D Type4HobData->Process= orUid) {=0D GuidHob =3D GetNextGuidHob((EFI_GUID *)PcdGetPtr(PcdProcessorSpecifi= cDataGuidHobGuid), GET_NEXT_HOB(GuidHob));=0D if (GuidHob =3D=3D NULL) {=0D diff --git a/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.uni b/Silicon/RI= SC-V/ProcessorPkg/RiscVProcessorPkg.uni index 83da92fe40..db519c42dd 100644 --- a/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.uni +++ b/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.uni @@ -8,6 +8,22 @@ // **/=0D =0D #string STR_PACKAGE_ABSTRACT #language en-US "Provides UEFI com= patible RISC-V processor modules and libraries"=0D -=0D #string STR_PACKAGE_DESCRIPTION #language en-US "This Package prov= ides UEFI compatible RISC-V processor modules and libraries."=0D =0D +#string STR_gUefiRiscVPkgTokenSpaceGuid_PcdProcessorSpecificDataGuidHobGui= d_PROMPT #language en-US "Processor Specific Data HOB GUID"=0D +#string STR_gUefiRiscVPkgTokenSpaceGuid_PcdProcessorSpecificDataGuidHobGui= d_HELP #language en-US "This is the GUID definition of HOB that passes= the "=0D + = "processor specific data to DXE phase."=0D +#string STR_gUefiRiscVPkgTokenSpaceGuid_PcdProcessorSmbiosGuidHobGuid_PROM= PT #language en-US "RISC-V SMBIOS Data HOB GUID"=0D +#string STR_gUefiRiscVPkgTokenSpaceGuid_PcdProcessorSmbiosGuidHobGuid_HELP= #language en-US "This is the GUID definition of HOB that passes= RISC-V SMBIOS "=0D + = "Data to DXE phase."=0D +#string STR_gUefiRiscVPkgTokenSpaceGuid_PcdProcessorSmbiosType4GuidHobGuid= _PROMPT #language en-US "RISC-V SMBIOS Type 4 Data HOB GUID"=0D +#string STR_gUefiRiscVPkgTokenSpaceGuid_PcdProcessorSmbiosType4GuidHobGuid= _HELP #language en-US "This is the GUID definition of HOB that passes= RISC-V SMBIOS "=0D + = "Type 4 information to DXE phase for building up SMBIOS record.= "=0D +#string STR_gUefiRiscVPkgTokenSpaceGuid_PcdProcessorSmbiosType7GuidHobGuid= _PROMPT #language en-US "RISC-V SMBIOS Type 7 Data HOB GUID"=0D +#string STR_gUefiRiscVPkgTokenSpaceGuid_PcdProcessorSmbiosType7GuidHobGuid= _HELP #language en-US "This is the GUID definition of HOB that passes= RISC-V SMBIOS "=0D + = "Type 7 information to DXE phase for building up SMBIOS record.= "=0D +#string STR_gUefiRiscVPkgTokenSpaceGuid_PcdRiscVMachineTimerTickInNanoSeco= nd_PROMPT #language en-US "RISC-V Machine Mode Timer Duration"=0D +#string STR_gUefiRiscVPkgTokenSpaceGuid_PcdRiscVMachineTimerTickInNanoSeco= nd_HELP #language en-US "RISC-V Machine Mode Timer Duration in nanoseco= nd."=0D +#string STR_gUefiRiscVPkgTokenSpaceGuid_PcdRiscVMachineTimerFrequencyInHer= z_PROMPT #language en-US "RISC-V Machine Mode Timer frequency."=0D +#string STR_gUefiRiscVPkgTokenSpaceGuid_PcdRiscVMachineTimerFrequencyInHer= z_HELP #language en-US "RISC-V Machine Mode Timer frequency in Hertz"= =0D +=0D --=20 2.31.1