* [edk2-platforms][PATCH V2 01/14] RiscVProcessorPkg: Fix build fail on RiscVProcessorPkg package
2022-01-22 6:53 [edk2-platforms][PATCH V2 00/14] Address edk2 Core CI issues Abner Chang
@ 2022-01-22 6:53 ` Abner Chang
2022-01-22 6:53 ` [edk2-platforms][PATCH V2 02/14] PlatformPkg/PlatformPei: Fix the build error Abner Chang
` (13 subsequent siblings)
14 siblings, 0 replies; 16+ messages in thread
From: Abner Chang @ 2022-01-22 6:53 UTC (permalink / raw)
To: devel; +Cc: abner.chang, Daniel Schaefer, Sunil V L
Add FdtLib to DSC file.
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Cc: Daniel Schaefer <daniel.schaefer@hpe.com>
Cc: Sunil V L <sunilvl@ventanamicro.com>
---
Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dsc | 1 +
1 file changed, 1 insertion(+)
diff --git a/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dsc b/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dsc
index 5c7425421b..563b9e7088 100644
--- a/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dsc
+++ b/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dsc
@@ -67,6 +67,7 @@
UefiLib|MdePkg/Library/UefiLib/UefiLib.inf
DevicePathLib|MdePkg/Library/UefiDevicePathLibDevicePathProtocol/UefiDevicePathLibDevicePathProtocol.inf
RiscVPlatformTimerLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVPlatformTimerLibNull/RiscVPlatformTimerLib.inf
+ FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib.inf
[LibraryClasses.common.PEI_CORE]
PeiServicesTablePointerLib|Silicon/RISC-V/ProcessorPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerLibOpenSbi.inf
--
2.31.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* [edk2-platforms][PATCH V2 02/14] PlatformPkg/PlatformPei: Fix the build error
2022-01-22 6:53 [edk2-platforms][PATCH V2 00/14] Address edk2 Core CI issues Abner Chang
2022-01-22 6:53 ` [edk2-platforms][PATCH V2 01/14] RiscVProcessorPkg: Fix build fail on RiscVProcessorPkg package Abner Chang
@ 2022-01-22 6:53 ` Abner Chang
2022-01-22 6:53 ` [edk2-platforms][PATCH V2 03/14] RISC-V/PlatformPkg: Address ECC errors Abner Chang
` (12 subsequent siblings)
14 siblings, 0 replies; 16+ messages in thread
From: Abner Chang @ 2022-01-22 6:53 UTC (permalink / raw)
To: devel; +Cc: abner.chang, Daniel Schaefer, Sunil V L
Fix the build error caused by the dependency with SiFive silicon code.
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Cc: Daniel Schaefer <daniel.schaefer@hpe.com>
Cc: Sunil V L <sunilvl@ventanamicro.com>
---
.../Universal/Pei/PlatformPei/PlatformPei.inf | 7 +------
.../Universal/Pei/PlatformPei/Platform.h | 13 ++++++++++++-
.../Universal/Pei/PlatformPei/Platform.c | 4 +---
3 files changed, 14 insertions(+), 10 deletions(-)
diff --git a/Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei/PlatformPei.inf b/Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei/PlatformPei.inf
index 0db88abba4..6368a49927 100644
--- a/Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei/PlatformPei.inf
+++ b/Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei/PlatformPei.inf
@@ -3,7 +3,7 @@
#
# This module provides platform specific function to detect boot mode.
#
-# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+# Copyright (c) 2021-2022, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -32,14 +32,11 @@
MdeModulePkg/MdeModulePkg.dec
MdePkg/MdePkg.dec
Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec
- Platform/SiFive/U5SeriesPkg/U5SeriesPkg.dec
Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec
- Silicon/SiFive/SiFive.dec
UefiCpuPkg/UefiCpuPkg.dec
[Guids]
gEfiMemoryTypeInformationGuid
- gSiFiveU5SeriesPlatformsPkgTokenSpaceGuid
[LibraryClasses]
DebugLib
@@ -64,8 +61,6 @@
gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVDxeFvSize
gUefiRiscVPlatformPkgTokenSpaceGuid.PcdTemporaryRamBase
gUefiRiscVPlatformPkgTokenSpaceGuid.PcdTemporaryRamSize
- gSiFiveU5SeriesPlatformsPkgTokenSpaceGuid.PcdNumberofU5Cores
- gSiFiveU5SeriesPlatformsPkgTokenSpaceGuid.PcdE5MCSupported
[Ppis]
gEfiPeiMasterBootModePpiGuid
diff --git a/Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei/Platform.h b/Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei/Platform.h
index c2cdd6d75b..1b6cb4f870 100644
--- a/Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei/Platform.h
+++ b/Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei/Platform.h
@@ -1,7 +1,7 @@
/** @file
Platform PEI module include file.
- Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+ Copyright (c) 2019-2022, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -83,4 +83,15 @@ InitializeXen (
VOID
);
+/**
+ Build processor and platform information for the U5 platform
+
+ @return EFI_SUCCESS Status.
+
+**/
+EFI_STATUS
+BuildRiscVSmbiosHobs (
+ VOID
+);
+
#endif // _PLATFORM_PEI_H_INCLUDED_
diff --git a/Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei/Platform.c b/Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei/Platform.c
index 8586a94b62..6deeb19655 100644
--- a/Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei/Platform.c
+++ b/Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei/Platform.c
@@ -1,7 +1,7 @@
/**@file
Platform PEI driver
- Copyright (c) 2019-2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+ Copyright (c) 2019-2022, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2011, Andrei Warkentin <andreiw@motorola.com>
@@ -30,8 +30,6 @@
#include <Ppi/MasterBootMode.h>
#include <IndustryStandard/Pci22.h>
-#include <SiFiveU5MCCoreplex.h>
-
#include "Platform.h"
EFI_MEMORY_TYPE_INFORMATION mDefaultMemoryTypeInformation[] = {
--
2.31.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* [edk2-platforms][PATCH V2 03/14] RISC-V/PlatformPkg: Address ECC errors
2022-01-22 6:53 [edk2-platforms][PATCH V2 00/14] Address edk2 Core CI issues Abner Chang
2022-01-22 6:53 ` [edk2-platforms][PATCH V2 01/14] RiscVProcessorPkg: Fix build fail on RiscVProcessorPkg package Abner Chang
2022-01-22 6:53 ` [edk2-platforms][PATCH V2 02/14] PlatformPkg/PlatformPei: Fix the build error Abner Chang
@ 2022-01-22 6:53 ` Abner Chang
2022-01-22 6:53 ` [edk2-platforms][PATCH V2 04/14] RISC-V/PlatformPkg: Address Spelling check errors Abner Chang
` (11 subsequent siblings)
14 siblings, 0 replies; 16+ messages in thread
From: Abner Chang @ 2022-01-22 6:53 UTC (permalink / raw)
To: devel; +Cc: abner.chang, Daniel Schaefer, Sunil V L
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Cc: Daniel Schaefer <daniel.schaefer@hpe.com>
Cc: Sunil V L <sunilvl@ventanamicro.com>
---
.../RISC-V/PlatformPkg/RiscVPlatformPkg.dec | 1 -
.../RISC-V/PlatformPkg/RiscVPlatformPkg.dsc | 4 +-
.../FirmwareContextProcessorSpecificLib.inf | 7 +-
.../OpensbiPlatformLib/OpensbiPlatformLib.inf | 2 +-
.../PeiCoreEntryPoint/PeiCoreEntryPoint.inf | 1 -
.../PlatformBootManagerLib.inf | 13 +---
.../PlatformMemoryTestLibNull.inf | 6 +-
.../PlatformSecPpiLibNull.inf | 8 +--
.../PlatformUpdateProgressLibNull.inf | 7 +-
.../Library/ResetSystemLib/ResetSystemLib.inf | 1 -
.../PlatformPkg/Universal/FdtPeim/FdtPeim.inf | 3 -
.../Universal/Pei/PlatformPei/PlatformPei.inf | 10 ++-
.../PlatformPkg/Universal/Sec/SecMain.inf | 1 +
.../FirmwareContextProcessorSpecificLib.h | 4 +-
.../PlatformBootManager.h | 10 +--
.../PlatformPkg/Universal/Sec/SecMain.h | 29 +++++---
.../Edk2OpensbiPlatformWrapperLib.c | 8 +--
.../FirmwareContextProcessorSpecificLib.c | 4 +-
.../{Platform.c => OpensbiPlatform.c} | 0
.../PeiCoreEntryPoint/PeiCoreEntryPoint.c | 2 +-
.../PeiCoreInfoHobLibNull/CoreInfoHob.c | 2 +-
.../PlatformBootManager.c | 7 ++
.../PlatformBootManagerLib/PlatformData.c | 2 +-
.../PlatformSecPpiLibNull/PlatformSecPpiLib.c | 2 +-
.../RiscVSpecialPlatformLib.c | 2 +-
.../PlatformPkg/Universal/FdtPeim/FdtPeim.c | 3 +-
.../Universal/Pei/PlatformPei/MemDetect.c | 6 +-
.../Universal/Pei/PlatformPei/Platform.c | 71 ++++++++++++++++++-
.../PlatformPkg/Universal/Sec/SecMain.c | 51 +++++++------
.../RISC-V/PlatformPkg/RiscVPlatformPkg.uni | 71 ++++++++++++++++++-
30 files changed, 232 insertions(+), 106 deletions(-)
rename Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/{Platform.c => OpensbiPlatform.c} (100%)
diff --git a/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec b/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec
index 19206556ce..53d424c901 100644
--- a/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec
+++ b/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec
@@ -85,7 +85,6 @@
[PcdsPatchableInModule]
[PcdsFeatureFlag]
- gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootlogoOnlyEnable|FALSE|BOOLEAN|0x00001200
[PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx]
diff --git a/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dsc b/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dsc
index 47a0fc4494..4f7b2eb282 100644
--- a/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dsc
+++ b/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dsc
@@ -1,11 +1,11 @@
-#/** @file
+## @file
# RISC-V platform package.
#
# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
-#**/
+#
################################################################################
#
diff --git a/Platform/RISC-V/PlatformPkg/Library/FirmwareContextProcessorSpecificLib/FirmwareContextProcessorSpecificLib.inf b/Platform/RISC-V/PlatformPkg/Library/FirmwareContextProcessorSpecificLib/FirmwareContextProcessorSpecificLib.inf
index 69568511ce..ea2550ce2c 100644
--- a/Platform/RISC-V/PlatformPkg/Library/FirmwareContextProcessorSpecificLib/FirmwareContextProcessorSpecificLib.inf
+++ b/Platform/RISC-V/PlatformPkg/Library/FirmwareContextProcessorSpecificLib/FirmwareContextProcessorSpecificLib.inf
@@ -1,10 +1,11 @@
-#/** @file
+## @file
+# This is the library module of RISC-V EDK2 OpenSBI Firmware Context
+# Processor Specific hwardware information.
#
-# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+# Copyright (c) 2019-2022, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
-#**/
[Defines]
INF_VERSION = 0x0001001b
diff --git a/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/OpensbiPlatformLib.inf b/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/OpensbiPlatformLib.inf
index 6661ee8204..78040d5a93 100644
--- a/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/OpensbiPlatformLib.inf
+++ b/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/OpensbiPlatformLib.inf
@@ -24,7 +24,7 @@
#
[Sources]
- Platform.c
+ OpensbiPlatform.c
[Packages]
EmbeddedPkg/EmbeddedPkg.dec
diff --git a/Platform/RISC-V/PlatformPkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.inf b/Platform/RISC-V/PlatformPkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.inf
index 4f3af27bcf..8e27011c8f 100644
--- a/Platform/RISC-V/PlatformPkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.inf
+++ b/Platform/RISC-V/PlatformPkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.inf
@@ -33,5 +33,4 @@
BaseLib
DebugLib
PlatformSecPpiLib
- RiscVFirmwareContextLib
diff --git a/Platform/RISC-V/PlatformPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf b/Platform/RISC-V/PlatformPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
index 2bf89a3c44..caefae3b2e 100644
--- a/Platform/RISC-V/PlatformPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
+++ b/Platform/RISC-V/PlatformPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
@@ -34,18 +34,11 @@
[LibraryClasses]
BaseLib
- UefiBootServicesTableLib
- UefiRuntimeServicesTableLib
- UefiLib
- UefiBootManagerLib
PcdLib
- PlatformMemoryTestLib
- PlatformUpdateProgressLib
- DxeServicesLib
MemoryAllocationLib
- DevicePathLib
- HiiLib
PrintLib
+ PlatformMemoryTestLib
+ PlatformUpdateProgressLib
[Guids]
gEfiEndOfDxeEventGroupGuid
@@ -59,4 +52,4 @@
gEfiMdeModulePkgTokenSpaceGuid.PcdConOutRow
gEfiMdeModulePkgTokenSpaceGuid.PcdConOutColumn
gEfiMdeModulePkgTokenSpaceGuid.PcdConInConnectOnDemand
- gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootlogoOnlyEnable
+
diff --git a/Platform/RISC-V/PlatformPkg/Library/PlatformMemoryTestLibNull/PlatformMemoryTestLibNull.inf b/Platform/RISC-V/PlatformPkg/Library/PlatformMemoryTestLibNull/PlatformMemoryTestLibNull.inf
index a1b503ebc2..9905448909 100644
--- a/Platform/RISC-V/PlatformPkg/Library/PlatformMemoryTestLibNull/PlatformMemoryTestLibNull.inf
+++ b/Platform/RISC-V/PlatformPkg/Library/PlatformMemoryTestLibNull/PlatformMemoryTestLibNull.inf
@@ -1,10 +1,10 @@
-#/** @file
+## @file
+# Platform NULL memory test library instance.
#
# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
-#**/
[Defines]
INF_VERSION = 0x0001001b
@@ -22,8 +22,6 @@
MdePkg/MdePkg.dec
[LibraryClasses]
- UefiLib
- DebugLib
[Pcd]
diff --git a/Platform/RISC-V/PlatformPkg/Library/PlatformSecPpiLibNull/PlatformSecPpiLibNull.inf b/Platform/RISC-V/PlatformPkg/Library/PlatformSecPpiLibNull/PlatformSecPpiLibNull.inf
index 22f5751655..c562e44c68 100644
--- a/Platform/RISC-V/PlatformPkg/Library/PlatformSecPpiLibNull/PlatformSecPpiLibNull.inf
+++ b/Platform/RISC-V/PlatformPkg/Library/PlatformSecPpiLibNull/PlatformSecPpiLibNull.inf
@@ -1,17 +1,16 @@
## @file
-# Library instance to to provide PPI before PEI Core
+# NULL library instance of PlatformSecPpiLib
#
# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
-##
[Defines]
INF_VERSION = 0x0001001b
BASE_NAME = PlatformSecPpiLib
FILE_GUID = A2CDDADC-CB65-4EED-9CAE-192B0BDD6C84
- MODULE_TYPE = PEIM
+ MODULE_TYPE = BASE
VERSION_STRING = 1.0
LIBRARY_CLASS = PlatformSecPpiLib|PEI_CORE
@@ -28,9 +27,6 @@
MdePkg/MdePkg.dec
MdeModulePkg/MdeModulePkg.dec
Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec
- #Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec
[LibraryClasses]
- #BaseLib
- #PrintLib
diff --git a/Platform/RISC-V/PlatformPkg/Library/PlatformUpdateProgressLibNull/PlatformUpdateProgressLibNull.inf b/Platform/RISC-V/PlatformPkg/Library/PlatformUpdateProgressLibNull/PlatformUpdateProgressLibNull.inf
index fdba00c053..1411015809 100644
--- a/Platform/RISC-V/PlatformPkg/Library/PlatformUpdateProgressLibNull/PlatformUpdateProgressLibNull.inf
+++ b/Platform/RISC-V/PlatformPkg/Library/PlatformUpdateProgressLibNull/PlatformUpdateProgressLibNull.inf
@@ -1,10 +1,11 @@
-#/** @file
+## @file
+# Platform Update Progress NULL library
#
# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
-#**/
+#
[Defines]
INF_VERSION = 0x0001001b
@@ -22,8 +23,6 @@
MdePkg/MdePkg.dec
[LibraryClasses]
- UefiLib
- DebugLib
[Pcd]
diff --git a/Platform/RISC-V/PlatformPkg/Library/ResetSystemLib/ResetSystemLib.inf b/Platform/RISC-V/PlatformPkg/Library/ResetSystemLib/ResetSystemLib.inf
index f876ae2056..8987adb946 100644
--- a/Platform/RISC-V/PlatformPkg/Library/ResetSystemLib/ResetSystemLib.inf
+++ b/Platform/RISC-V/PlatformPkg/Library/ResetSystemLib/ResetSystemLib.inf
@@ -4,7 +4,6 @@
# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
-##
[Defines]
INF_VERSION = 0x00010005
diff --git a/Platform/RISC-V/PlatformPkg/Universal/FdtPeim/FdtPeim.inf b/Platform/RISC-V/PlatformPkg/Universal/FdtPeim/FdtPeim.inf
index 8dc58f0a8b..dc3a685d58 100644
--- a/Platform/RISC-V/PlatformPkg/Universal/FdtPeim/FdtPeim.inf
+++ b/Platform/RISC-V/PlatformPkg/Universal/FdtPeim/FdtPeim.inf
@@ -33,14 +33,11 @@
Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec
[LibraryClasses]
- DebugLib
DebugLib
HobLib
FdtLib
PcdLib
- PeiServicesLib
PeimEntryPoint
- RiscVFirmwareContextLib
[Guids]
gFdtHobGuid ## PRODUCES
diff --git a/Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei/PlatformPei.inf b/Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei/PlatformPei.inf
index 6368a49927..8a88bbf9ce 100644
--- a/Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei/PlatformPei.inf
+++ b/Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei/PlatformPei.inf
@@ -3,7 +3,7 @@
#
# This module provides platform specific function to detect boot mode.
#
-# Copyright (c) 2021-2022, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -27,6 +27,7 @@
Fv.c
MemDetect.c
Platform.c
+ Platform.h
[Packages]
MdeModulePkg/MdeModulePkg.dec
@@ -42,12 +43,9 @@
DebugLib
HobLib
IoLib
- PciLib
- PeiResourcePublicationLib
- PeiServicesLib
- PeiServicesTablePointerLib
- PeimEntryPoint
PcdLib
+ PeimEntryPoint
+ PeiResourcePublicationLib
RiscVCoreplexInfoLib
[Pcd]
diff --git a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf
index b949b6c470..1e8d53f486 100644
--- a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf
+++ b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf
@@ -22,6 +22,7 @@
#
[Sources]
+ SecMain.h
SecMain.c
[Sources.RISCV64]
diff --git a/Platform/RISC-V/PlatformPkg/Include/Library/FirmwareContextProcessorSpecificLib.h b/Platform/RISC-V/PlatformPkg/Include/Library/FirmwareContextProcessorSpecificLib.h
index f3b096c257..3920c61155 100644
--- a/Platform/RISC-V/PlatformPkg/Include/Library/FirmwareContextProcessorSpecificLib.h
+++ b/Platform/RISC-V/PlatformPkg/Include/Library/FirmwareContextProcessorSpecificLib.h
@@ -6,8 +6,8 @@
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
-#ifndef FIRMWARE_CONTEXT_PROCESSOR_SPECIFIC_LIB_H
-#define FIRMWARE_CONTEXT_PROCESSOR_SPECIFIC_LIB_H
+#ifndef FIRMWARE_CONTEXT_PROCESSOR_SPECIFIC_LIB_H_
+#define FIRMWARE_CONTEXT_PROCESSOR_SPECIFIC_LIB_H_
#include <IndustryStandard/RiscVOpensbi.h>
#include <PiPei.h>
diff --git a/Platform/RISC-V/PlatformPkg/Library/PlatformBootManagerLib/PlatformBootManager.h b/Platform/RISC-V/PlatformPkg/Library/PlatformBootManagerLib/PlatformBootManager.h
index 58c363a48b..01c26f307e 100644
--- a/Platform/RISC-V/PlatformPkg/Library/PlatformBootManagerLib/PlatformBootManager.h
+++ b/Platform/RISC-V/PlatformPkg/Library/PlatformBootManagerLib/PlatformBootManager.h
@@ -1,4 +1,4 @@
-/**@file
+/** @file
Head file for BDS Platform specific code
Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
@@ -39,14 +39,6 @@ typedef struct {
extern PLATFORM_CONSOLE_CONNECT_ENTRY gPlatformConsole[];
-#define gEndEntire \
- { \
- END_DEVICE_PATH_TYPE,\
- END_ENTIRE_DEVICE_PATH_SUBTYPE,\
- END_DEVICE_PATH_LENGTH,\
- 0\
- }
-
#define CONSOLE_OUT BIT0
#define CONSOLE_IN BIT1
#define STD_ERROR BIT2
diff --git a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.h b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.h
index 6188778fc4..63a610fbd0 100644
--- a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.h
+++ b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.h
@@ -27,25 +27,38 @@
#include <Library/PeiServicesLib.h>
#include <Library/RiscVCpuLib.h>
-int
+/**
+ OpenSBI platform early init hook.
+
+ @param[in] ColdBoot Is cold boot path or warm boot path.
+ @retval OpenSBI error code.
+
+**/
+INT32
SecPostOpenSbiPlatformEarlylInit(
IN BOOLEAN ColdBoot
);
-int
+/**
+ OpenSBI platform final init hook.
+ We restore the next_arg1 to the pointer of EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT.
+
+ @param[in] ColdBoot Is cold boot path or warm boot path.
+ @retval OpenSBI error code.
+
+**/
+INT32
SecPostOpenSbiPlatformFinalInit (
IN BOOLEAN ColdBoot
);
+/**
+ SEC machine mode trap handler.
+
+**/
VOID
SecMachineModeTrapHandler (
IN VOID
);
-VOID
-EFIAPI
-SecStartupPhase2 (
- IN VOID *Context
- );
-
#endif // _SECMAIN_H_
diff --git a/Platform/RISC-V/PlatformPkg/Library/Edk2OpensbiPlatformWrapperLib/Edk2OpensbiPlatformWrapperLib.c b/Platform/RISC-V/PlatformPkg/Library/Edk2OpensbiPlatformWrapperLib/Edk2OpensbiPlatformWrapperLib.c
index 6c5c1a789f..2137c6c619 100644
--- a/Platform/RISC-V/PlatformPkg/Library/Edk2OpensbiPlatformWrapperLib/Edk2OpensbiPlatformWrapperLib.c
+++ b/Platform/RISC-V/PlatformPkg/Library/Edk2OpensbiPlatformWrapperLib/Edk2OpensbiPlatformWrapperLib.c
@@ -1,11 +1,11 @@
-/*
+/** @file
EDK2 OpenSBI generic platform wrapper library
Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
- */
+ **/
#include <Library/DebugAgentLib.h>
#include <Library/DebugLib.h>
@@ -189,7 +189,7 @@ Edk2OpensbiPlatformEarlyInit (
return ReturnCode;
}
}
- if (ColdBoot == TRUE) {
+ if (ColdBoot) {
return SecPostOpenSbiPlatformEarlylInit(ColdBoot);
}
return 0;
@@ -216,7 +216,7 @@ Edk2OpensbiPlatformFinalInit (
return ReturnCode;
}
}
- if (ColdBoot == TRUE) {
+ if (ColdBoot) {
return SecPostOpenSbiPlatformFinalInit(ColdBoot);
}
return 0;
diff --git a/Platform/RISC-V/PlatformPkg/Library/FirmwareContextProcessorSpecificLib/FirmwareContextProcessorSpecificLib.c b/Platform/RISC-V/PlatformPkg/Library/FirmwareContextProcessorSpecificLib/FirmwareContextProcessorSpecificLib.c
index c62f77bc49..143c18d62c 100644
--- a/Platform/RISC-V/PlatformPkg/Library/FirmwareContextProcessorSpecificLib/FirmwareContextProcessorSpecificLib.c
+++ b/Platform/RISC-V/PlatformPkg/Library/FirmwareContextProcessorSpecificLib/FirmwareContextProcessorSpecificLib.c
@@ -1,4 +1,4 @@
-/**@file
+/** @file
Common library to build upfirmware context processor-specific information
Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
@@ -93,7 +93,7 @@ CommonFirmwareContextHartSpecificInfo (
}
/**
- Print debug information of the processor specific data for a hart
+ Print debug information of the processor specific data for a hart.
@param ProcessorSpecificDataHob Pointer to RISC_V_PROCESSOR_SPECIFIC_DATA_HOB
**/
diff --git a/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/Platform.c b/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/OpensbiPlatform.c
similarity index 100%
rename from Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/Platform.c
rename to Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/OpensbiPlatform.c
diff --git a/Platform/RISC-V/PlatformPkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.c b/Platform/RISC-V/PlatformPkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.c
index 16488b7bc9..50de969947 100644
--- a/Platform/RISC-V/PlatformPkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.c
+++ b/Platform/RISC-V/PlatformPkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.c
@@ -45,7 +45,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
**/
VOID
EFIAPI
-_ModuleEntryPoint(
+_ModuleEntryPoint (
IN CONST EFI_SEC_PEI_HAND_OFF *SecCoreData,
IN CONST EFI_PEI_PPI_DESCRIPTOR *PpiList
)
diff --git a/Platform/RISC-V/PlatformPkg/Library/PeiCoreInfoHobLibNull/CoreInfoHob.c b/Platform/RISC-V/PlatformPkg/Library/PeiCoreInfoHobLibNull/CoreInfoHob.c
index 9aad7991bc..ae80b2404d 100644
--- a/Platform/RISC-V/PlatformPkg/Library/PeiCoreInfoHobLibNull/CoreInfoHob.c
+++ b/Platform/RISC-V/PlatformPkg/Library/PeiCoreInfoHobLibNull/CoreInfoHob.c
@@ -1,4 +1,4 @@
-/**@file
+/** @file
Build up platform processor information.
Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
diff --git a/Platform/RISC-V/PlatformPkg/Library/PlatformBootManagerLib/PlatformBootManager.c b/Platform/RISC-V/PlatformPkg/Library/PlatformBootManagerLib/PlatformBootManager.c
index d67f4836fc..deaad7d5a1 100644
--- a/Platform/RISC-V/PlatformPkg/Library/PlatformBootManagerLib/PlatformBootManager.c
+++ b/Platform/RISC-V/PlatformPkg/Library/PlatformBootManagerLib/PlatformBootManager.c
@@ -86,6 +86,13 @@ PlatformFindLoadOption (
return -1;
}
+/**
+ Register a boot option using a file GUID in the FV.
+
+ @param FileGuid The file GUID name in FV.
+ @param Description The boot option description.
+ @param Attributes The attributes used for the boot option loading.
+**/
VOID
PlatformRegisterFvBootOption (
EFI_GUID *FileGuid,
diff --git a/Platform/RISC-V/PlatformPkg/Library/PlatformBootManagerLib/PlatformData.c b/Platform/RISC-V/PlatformPkg/Library/PlatformBootManagerLib/PlatformData.c
index 3208051e16..c1dbbf451e 100644
--- a/Platform/RISC-V/PlatformPkg/Library/PlatformBootManagerLib/PlatformData.c
+++ b/Platform/RISC-V/PlatformPkg/Library/PlatformBootManagerLib/PlatformData.c
@@ -1,4 +1,4 @@
-/**@file
+/** @file
Defined the platform specific device path which will be filled to
ConIn/ConOut variables.
diff --git a/Platform/RISC-V/PlatformPkg/Library/PlatformSecPpiLibNull/PlatformSecPpiLib.c b/Platform/RISC-V/PlatformPkg/Library/PlatformSecPpiLibNull/PlatformSecPpiLib.c
index d5c089b02d..bcb345c4e9 100644
--- a/Platform/RISC-V/PlatformPkg/Library/PlatformSecPpiLibNull/PlatformSecPpiLib.c
+++ b/Platform/RISC-V/PlatformPkg/Library/PlatformSecPpiLibNull/PlatformSecPpiLib.c
@@ -1,4 +1,4 @@
-/**@file
+/** @file
NULL library instance of PlatformSecPpiLib
Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
diff --git a/Platform/RISC-V/PlatformPkg/Library/RiscVSpecialPlatformLibNull/RiscVSpecialPlatformLib.c b/Platform/RISC-V/PlatformPkg/Library/RiscVSpecialPlatformLibNull/RiscVSpecialPlatformLib.c
index f64bde4535..44f6ad6aed 100644
--- a/Platform/RISC-V/PlatformPkg/Library/RiscVSpecialPlatformLibNull/RiscVSpecialPlatformLib.c
+++ b/Platform/RISC-V/PlatformPkg/Library/RiscVSpecialPlatformLibNull/RiscVSpecialPlatformLib.c
@@ -1,4 +1,4 @@
-/**@file
+/** @file
Library to provide platform_override for the special
RISC-V platform. This module incorporates with
OpensbiPlatformLib and RISC-V Opensbi library.
diff --git a/Platform/RISC-V/PlatformPkg/Universal/FdtPeim/FdtPeim.c b/Platform/RISC-V/PlatformPkg/Universal/FdtPeim/FdtPeim.c
index 2cd94f291c..3487a5faf4 100644
--- a/Platform/RISC-V/PlatformPkg/Universal/FdtPeim/FdtPeim.c
+++ b/Platform/RISC-V/PlatformPkg/Universal/FdtPeim/FdtPeim.c
@@ -22,7 +22,8 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
@param FileHandle Handle of the file being invoked.
@param PeiServices Describes the list of possible PEI Services.
- @retval TODO
+ @retval EFI_SUCCESS The address of FDT is passed in HOB.
+ EFI_UNSUPPORTED Can't locate FDT.
**/
EFI_STATUS
EFIAPI
diff --git a/Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei/MemDetect.c b/Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei/MemDetect.c
index c15d6bb5d4..9b52eb5189 100644
--- a/Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei/MemDetect.c
+++ b/Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei/MemDetect.c
@@ -1,4 +1,4 @@
-/**@file
+/** @file
Memory Detection for Virtual Machines.
Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
@@ -32,7 +32,7 @@ Module Name:
/**
- Publish PEI core memory
+ Publish PEI core memory.
@return EFI_SUCCESS The PEIM initialized successfully.
@@ -65,7 +65,7 @@ PublishPeiMemory (
}
/**
- Publish system RAM and reserve memory regions
+ Publish system RAM and reserve memory regions.
**/
VOID
diff --git a/Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei/Platform.c b/Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei/Platform.c
index 6deeb19655..972a429fb9 100644
--- a/Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei/Platform.c
+++ b/Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei/Platform.c
@@ -1,4 +1,4 @@
-/**@file
+/** @file
Platform PEI driver
Copyright (c) 2019-2022, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
@@ -54,6 +54,14 @@ EFI_PEI_PPI_DESCRIPTOR mPpiBootMode[] = {
STATIC EFI_BOOT_MODE mBootMode = BOOT_WITH_FULL_CONFIGURATION;
+/**
+ Build memory map I/O range resource HOB using the
+ base address and size.
+
+ @param MemoryBase Memory map I/O base.
+ @param MemorySize Memory map I/O size.
+
+**/
VOID
AddIoMemoryBaseSizeHob (
EFI_PHYSICAL_ADDRESS MemoryBase,
@@ -71,6 +79,13 @@ AddIoMemoryBaseSizeHob (
);
}
+/**
+ Build reserved memory range resource HOB.
+
+ @param MemoryBase Reserved memory range base address.
+ @param MemorySize Reserved memory range size.
+
+**/
VOID
AddReservedMemoryBaseSizeHob (
EFI_PHYSICAL_ADDRESS MemoryBase,
@@ -88,6 +103,14 @@ AddReservedMemoryBaseSizeHob (
);
}
+/**
+ Build memory map I/O resource using the base address
+ and the top address of memory range.
+
+ @param MemoryBase Memory map I/O range base address.
+ @param MemoryLimit The top address of memory map I/O range
+
+**/
VOID
AddIoMemoryRangeHob (
EFI_PHYSICAL_ADDRESS MemoryBase,
@@ -97,7 +120,14 @@ AddIoMemoryRangeHob (
AddIoMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));
}
+/**
+ Create memory range resource HOB using the memory base
+ address and size.
+
+ @param MemoryBase Memory range base address.
+ @param MemorySize Memory range size.
+**/
VOID
AddMemoryBaseSizeHob (
EFI_PHYSICAL_ADDRESS MemoryBase,
@@ -118,7 +148,14 @@ AddMemoryBaseSizeHob (
);
}
+/**
+ Create memory range resource HOB using memory base
+ address and top address of the memory range.
+
+ @param MemoryBase Memory range base address.
+ @param MemoryLimit Memory range size.
+**/
VOID
AddMemoryRangeHob (
EFI_PHYSICAL_ADDRESS MemoryBase,
@@ -128,7 +165,14 @@ AddMemoryRangeHob (
AddMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));
}
+/**
+ Create untested memory range resource HOB using memory base
+ address and top address of the memory range.
+
+ @param MemoryBase Memory range base address.
+ @param MemorySize Memory range size.
+**/
VOID
AddUntestedMemoryBaseSizeHob (
EFI_PHYSICAL_ADDRESS MemoryBase,
@@ -148,6 +192,14 @@ AddUntestedMemoryBaseSizeHob (
);
}
+/**
+ Create untested memory range resource HOB using memory base
+ address and top address of the memory range.
+
+ @param MemoryBase Memory range base address.
+ @param MemoryLimit Memory range size.
+
+**/
VOID
AddUntestedMemoryRangeHob (
EFI_PHYSICAL_ADDRESS MemoryBase,
@@ -157,6 +209,10 @@ AddUntestedMemoryRangeHob (
AddUntestedMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));
}
+/**
+ Add PCI resource.
+
+**/
VOID
AddPciResource (
VOID
@@ -167,6 +223,10 @@ AddPciResource (
//
}
+/**
+ Platform memory map initialization.
+
+**/
VOID
MemMapInitialization (
VOID
@@ -187,6 +247,10 @@ MemMapInitialization (
AddPciResource ();
}
+/**
+ Platform misc initialization.
+
+**/
VOID
MiscInitialization (
VOID
@@ -221,7 +285,10 @@ CheckResumeFromS3 (
return FALSE;
}
+/**
+ Platform boot mode initialization.
+**/
VOID
BootModeInitialization (
VOID
@@ -229,7 +296,7 @@ BootModeInitialization (
{
EFI_STATUS Status;
- if (CheckResumeFromS3 () == TRUE) {
+ if (CheckResumeFromS3 ()) {
DEBUG ((DEBUG_INFO, "This is wake from S3\n"));
} else {
DEBUG ((DEBUG_INFO, "This is normal boot\n"));
diff --git a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c
index 05f228c44d..1fafed2799 100644
--- a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c
+++ b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c
@@ -227,10 +227,10 @@ FindFfsFileAndSection (
}
/**
- Locates the PEI Core entry point address
+ Locates the PEI Core entry point address.
@param[in] Fv The firmware volume to search
- @param[out] PeiCoreEntryPoint The entry point of the PEI Core image
+ @param[out] PeiCoreImageBase The entry point of the PEI Core image
@retval EFI_SUCCESS The file and section was found
@retval EFI_NOT_FOUND The file and section was not found
@@ -270,14 +270,10 @@ FindPeiCoreImageBaseInFv (
}
/**
- Locates the PEI Core entry point address
+ Locates the PEI Core entry point address.
- @param[in,out] Fv The firmware volume to search
- @param[out] PeiCoreEntryPoint The entry point of the PEI Core image
-
- @retval EFI_SUCCESS The file and section was found
- @retval EFI_NOT_FOUND The file and section was not found
- @retval EFI_VOLUME_CORRUPTED The firmware volume was corrupted
+ @param[in,out] BootFv The firmware volume to search
+ @param[out] PeiCoreImageBase The entry point of the PEI Core image
**/
VOID
@@ -292,12 +288,16 @@ FindPeiCoreImageBase (
FindPeiCoreImageBaseInFv (*BootFv, PeiCoreImageBase);
}
-/*
+/**
Find and return Pei Core entry point.
It also find SEC and PEI Core file debug inforamtion. It will report them if
remote debug is enabled.
+ @param[in] BootFirmwareVolumePtr The firmware volume pointer to search
+ @param[out] PeiCoreEntryPoint The entry point of the PEI Core image
+
+
**/
VOID
FindAndReportEntryPoints (
@@ -330,7 +330,7 @@ FindAndReportEntryPoints (
@param[in] ExtId The extension ID of the FW extension.
@param[in] FuncId The called function ID.
- @param[in] Args The args to the function.
+ @param[in] TrapRegs The args to the function.
@param[out] OutVal The value the function returns to the caller.
@param[out] OutTrap Trap info for trapping further, see OpenSBI code.
Is ignored if return value is not SBI_ETRAP.
@@ -339,7 +339,8 @@ FindAndReportEntryPoints (
@retval SBI_ENOTSUPP If there's no function with the given ID.
@retval SBI_ETRAP If the called SBI functions wants to trap further.
**/
-STATIC int SbiEcallFirmwareHandler (
+int
+SbiEcallFirmwareHandler (
IN unsigned long ExtId,
IN unsigned long FuncId,
IN CONST struct sbi_trap_regs *TrapRegs,
@@ -347,8 +348,9 @@ STATIC int SbiEcallFirmwareHandler (
OUT struct sbi_trap_info *OutTrap
)
{
- int Ret = SBI_OK;
+ int Ret;
+ Ret = SBI_OK;
switch (FuncId) {
case SBI_EXT_FW_MSCRATCH_FUNC:
*OutVal = (unsigned long) sbi_scratch_thishart_ptr();
@@ -408,17 +410,20 @@ RegisterFirmwareSbiExtension (
@param[in] Scratch Pointer to sbi_scratch structure.
**/
-VOID EFIAPI PeiCore (
+VOID
+EFIAPI
+PeiCore (
IN UINTN BootHartId,
IN struct sbi_scratch *Scratch
)
{
EFI_SEC_PEI_HAND_OFF SecCoreData;
EFI_PEI_CORE_ENTRY_POINT PeiCoreEntryPoint;
- EFI_FIRMWARE_VOLUME_HEADER *BootFv = (EFI_FIRMWARE_VOLUME_HEADER *)FixedPcdGet32(PcdRiscVPeiFvBase);
+ EFI_FIRMWARE_VOLUME_HEADER *BootFv;
EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT FirmwareContext;
- struct sbi_platform *ThisSbiPlatform;
+ struct sbi_platform *ThisSbiPlatform;
+ BootFv = (EFI_FIRMWARE_VOLUME_HEADER *)FixedPcdGet32(PcdRiscVPeiFvBase);
FindAndReportEntryPoints (&BootFv, &PeiCoreEntryPoint);
SecCoreData.DataSize = sizeof(EFI_SEC_PEI_HAND_OFF);
@@ -571,8 +576,6 @@ GetDeviceTreeAddress (
bootable harts other than those declared in Device Tree
@param[in] SbiPlatform Pointer to SBI platform
- @retval hart_index2id Index to ID value may be overwrote.
- @retval hart_count Index to ID value may be overwrote.
**/
VOID
@@ -626,7 +629,9 @@ Edk2PlatformHartIndex2Id (
@param[in] Scratch Pointer to sbi_scratch structure.
**/
-VOID EFIAPI SecCoreStartUpWithStack(
+VOID
+EFIAPI
+SecCoreStartUpWithStack(
IN UINTN HartId,
IN struct sbi_scratch *Scratch
)
@@ -710,11 +715,3 @@ VOID EFIAPI SecCoreStartUpWithStack(
sbi_init(Scratch);
}
-VOID OpensbiDebugPrint (CHAR8 *debugstr, ...)
-{
- VA_LIST Marker;
-
- VA_START (Marker, debugstr);
- DebugVPrint (DEBUG_INFO, debugstr, Marker);
- VA_END (Marker);
-}
diff --git a/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.uni b/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.uni
index deb91fa10c..836e02dd74 100644
--- a/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.uni
+++ b/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.uni
@@ -1,7 +1,7 @@
// /** @file
// RISC-V Package Localized Strings and Content.
//
-// Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+// Copyright (c) 2019-2022, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
//
// SPDX-License-Identifier: BSD-2-Clause-Patent
//
@@ -12,4 +12,73 @@
#string STR_PACKAGE_DESCRIPTION #language en-US "This Package provides UEFI compatible RISC-V platform modules and libraries."
+#string STR_gUefiRiscVPlatformPkgTokenSpaceGuid_PcdRiscVSecFvBase_PROMPT #language en-US "SEC FV base address"
+#string STR_gUefiRiscVPlatformPkgTokenSpaceGuid_PcdRiscVSecFvBase_HELP #language en-US "RISC-V platform SEC Firmware Volume base address."
+#string STR_gUefiRiscVPlatformPkgTokenSpaceGuid_PcdRiscVSecFvSize_PROMPT #language en-US "SEC FV Size"
+#string STR_gUefiRiscVPlatformPkgTokenSpaceGuid_PcdRiscVSecFvSize_HELP #language en-US "RISC-V platform SEC Firmware Volume size."
+#string STR_gUefiRiscVPlatformPkgTokenSpaceGuid_PcdRiscVPeiFvBase_PROMPT #language en-US "PEI FV base address"
+#string STR_gUefiRiscVPlatformPkgTokenSpaceGuid_PcdRiscVPeiFvBase_HELP #language en-US "RISC-V platform PEI Firmware Volume base address."
+#string STR_gUefiRiscVPlatformPkgTokenSpaceGuid_PcdRiscVPeiFvSize_PROMPT #language en-US "PEI FV Size"
+#string STR_gUefiRiscVPlatformPkgTokenSpaceGuid_PcdRiscVPeiFvSize_HELP #language en-US "RISC-V platform PEI Firmware Volume size.
+#string STR_gUefiRiscVPlatformPkgTokenSpaceGuid_PcdRiscVDxeFvBase_PROMPT #language en-US "DXE FV base address"
+#string STR_gUefiRiscVPlatformPkgTokenSpaceGuid_PcdRiscVDxeFvBase_HELP #language en-US "RISC-V platform DXE Firmware Volume base address."
+#string STR_gUefiRiscVPlatformPkgTokenSpaceGuid_PcdRiscVDxeFvSize_PROMPT #language en-US "DXE FV Size"
+#string STR_gUefiRiscVPlatformPkgTokenSpaceGuid_PcdRiscVDxeFvSize_HELP #language en-US "RISC-V platform DXE Firmware Volume size."
+#string STR_gUefiRiscVPlatformPkgTokenSpaceGuid_PcdRiscVDtbFvBase_PROMPT #language en-US "DBT FV base address."
+#string STR_gUefiRiscVPlatformPkgTokenSpaceGuid_PcdRiscVDtbFvBase_HELP #language en-US "RISC-V platform Device Tree Firmware Volume base address."
+#string STR_gUefiRiscVPlatformPkgTokenSpaceGuid_PcdRiscVDtbFvSize_PROMPT #language en-US "DBT FV Size".
+#string STR_gUefiRiscVPlatformPkgTokenSpaceGuid_PcdRiscVDtbFvSize_HELP #language en-US "RISC-V platform Device Tree Firmware Volume size."
+#string STR_gUefiRiscVPlatformPkgTokenSpaceGuid_PcdRootFirmwareDomainBaseAddress_PROMPT #language en-US "EDK2 OpenSBI Root Firmware Domain address"
+#string STR_gUefiRiscVPlatformPkgTokenSpaceGuid_PcdRootFirmwareDomainBaseAddress_HELP #language en-US "The base address of EDK2 OpenSBI Root Firmware Domain."
+#string STR_gUefiRiscVPlatformPkgTokenSpaceGuid_PcdRootFirmwareDomainSize_PROMPT #language en-US "EDK2 OpenSBI Root Firmware Domain size"
+#string STR_gUefiRiscVPlatformPkgTokenSpaceGuid_PcdRootFirmwareDomainSize_HELP #language en-US "This is the size of EKD2 OpenSBI Root Firmware Domain."
+#string STR_gUefiRiscVPlatformPkgTokenSpaceGuid_PcdFirmwareDomainBaseAddress_PROMPT #language en-US "EDK2 OpenSBI Firmware Domain address"
+#string STR_gUefiRiscVPlatformPkgTokenSpaceGuid_PcdFirmwareDomainBaseAddress_HELP #language en-US "This is the base address of EDK2 OpenSBI Firmware Domain."
+#string STR_gUefiRiscVPlatformPkgTokenSpaceGuid_PcdFirmwareDomainSize_PROMPT #language en-US "EDK2 OpenSBI Firmware Domain size"
+#string STR_gUefiRiscVPlatformPkgTokenSpaceGuid_PcdFirmwareDomainSize_HELP #language en-US "The size of EDK2 OpenSBI Firmware Domain."
+#string STR_gUefiRiscVPlatformPkgTokenSpaceGuid_PcdVariableFirmwareRegionBaseAddress_PROMPT #language en-US "EFI Variable FV base address"
+#string STR_gUefiRiscVPlatformPkgTokenSpaceGuid_PcdVariableFirmwareRegionBaseAddress_HELP #language en-US "The base address of EFI Variable Firmware Volume."
+#string STR_gUefiRiscVPlatformPkgTokenSpaceGuid_PcdVariableFirmwareRegionSize_PROMPT #language en-US "EFI Variable FV size"
+#string STR_gUefiRiscVPlatformPkgTokenSpaceGuid_PcdVariableFirmwareRegionSize_HELP #language en-US "The size of EFI Variable Firmware Volume."
+#string STR_gUefiRiscVPlatformPkgTokenSpaceGuid_PcdVariableFdBaseAddress_PROMPT #language en-US "FD base address"
+#string STR_gUefiRiscVPlatformPkgTokenSpaceGuid_PcdVariableFdBaseAddress_HELP #language en-US "The base address of Firmware Device."
+#string STR_gUefiRiscVPlatformPkgTokenSpaceGuid_PcdVariableFdSize_PROMPT #language en-US "FD size"
+#string STR_gUefiRiscVPlatformPkgTokenSpaceGuid_PcdVariableFdSize_HELP #language en-US "The size of Firmware Device."
+#string STR_gUefiRiscVPlatformPkgTokenSpaceGuid_PcdVariableFdBlockSize_PROMPT #language en-US "FD block size"
+#string STR_gUefiRiscVPlatformPkgTokenSpaceGuid_PcdVariableFdBlockSize_HELP #language en-US "The block size of Firmware Device"
+#string STR_gUefiRiscVPlatformPkgTokenSpaceGuid_PcdPlatformFlashNvStorageVariableBase_PROMPT #language en-US "Base address of flash NV variable range"
+#string STR_gUefiRiscVPlatformPkgTokenSpaceGuid_PcdPlatformFlashNvStorageVariableBase_HELP #language en-US "Base address of the NV variable range in flash device."
+#string STR_gUefiRiscVPlatformPkgTokenSpaceGuid_PcdPlatformFlashNvStorageFtwWorkingBase_PROMPT #language en-US "Base address of flash FTW working block range"
+#string STR_gUefiRiscVPlatformPkgTokenSpaceGuid_PcdPlatformFlashNvStorageFtwWorkingBase_HELP #language en-US "Base address of the FTW working block range in flash device. If PcdFlashNvStorageFtwWorkingSize is larger than one block size, this value should be block size aligned."
+#string STR_gUefiRiscVPlatformPkgTokenSpaceGuid_PcdPlatformFlashNvStorageFtwSpareBase_PROMPT #language en-US "Base address of flash FTW spare block range"
+#string STR_gUefiRiscVPlatformPkgTokenSpaceGuid_PcdPlatformFlashNvStorageFtwSpareBase_HELP #language en-US "Base address of the FTW spare block range in flash device. Note that this value should be block size aligned."
+#string STR_gUefiRiscVPlatformPkgTokenSpaceGuid_PcdHartCount_PROMPT #language en-US "RISC-V HART Count"
+#string STR_gUefiRiscVPlatformPkgTokenSpaceGuid_PcdHartCount_HELP #language en-US "The HART count of the RISC-V processor."
+#string STR_gUefiRiscVPlatformPkgTokenSpaceGuid_PcdBootHartId_PROMPT #language en-US "RISC-V Boot HART ID"
+#string STR_gUefiRiscVPlatformPkgTokenSpaceGuid_PcdBootHartId_HELP #language en-US "The ID number of booting HART of RISC-V processor."
+#string STR_gUefiRiscVPlatformPkgTokenSpaceGuid_PcdBootableHartNumber_PROMPT #language en-US "RISC-V Bootable HART number"
+#string STR_gUefiRiscVPlatformPkgTokenSpaceGuid_PcdBootableHartNumber_HELP #language en-US "The bootable hart core number, which incorporates with OpenSBI platform hart_index2id value.<BR>"
+ "PcdBootableHartNumber = 0 means the number of bootable hart comes from Device Tree.<BR>"
+ "Otherwise the number assigned in PcdBootableHartNumber overwrite it."
+#string STR_gUefiRiscVPlatformPkgTokenSpaceGuid_PcdBootableHartIndexToId_PROMPT #language en-US "RISC-V HARD ID to indxe tanslation"
+#string STR_gUefiRiscVPlatformPkgTokenSpaceGuid_PcdBootableHartIndexToId_HELP #language en-US "PcdBootableHartIndexToId is valid if PcdBootableHartNumber != 0.<BR>"
+ "If PcdBootableHartNumber != 0, then PcdBootableHartIndexToId is an array of<BR>"
+ "bootable hart ID.<BR>"
+ "For example,<BR>"
+ " if PcdBootableHartNumber == 3 then PcdBootableHartIndexToId could be defined<BR>"
+ " as {0x1, 0x2, 0x3}."
+#string STR_gUefiRiscVPlatformPkgTokenSpaceGuid_PcdScratchRamBase_PROMPT #language en-US "Scratch buffer base address"
+#string STR_gUefiRiscVPlatformPkgTokenSpaceGuid_PcdScratchRamBase_HELP #language en-US "The base address of scratch buffer used by OpenSBI while initializing RISC-V HARTs."
+#string STR_gUefiRiscVPlatformPkgTokenSpaceGuid_PcdScratchRamSize_PROMPT #language en-US "Scratch buffer size"
+#string STR_gUefiRiscVPlatformPkgTokenSpaceGuid_PcdScratchRamSize_HELP #language en-US "The size of scratch buffer used by OpenSBI while initializing RISC-V HARTs."
+#string STR_gUefiRiscVPlatformPkgTokenSpaceGuid_PcdOpenSbiStackSize_PROMPT #language en-US "OpenSBI stack size"
+#string STR_gUefiRiscVPlatformPkgTokenSpaceGuid_PcdOpenSbiStackSize_HELP #language en-US "The size of stack used by OpenSBI while initializing RISC-V HARTs.
+#string STR_gUefiRiscVPlatformPkgTokenSpaceGuid_PcdTemporaryRamBase_PROMPT #language en-US "Temporary RAM for PEI phase"
+#string STR_gUefiRiscVPlatformPkgTokenSpaceGuid_PcdTemporaryRamBase_HELP #language en-US "The temporary memory passed to PEI phase from SEC."
+#string STR_gUefiRiscVPlatformPkgTokenSpaceGuid_PcdTemporaryRamSize_PROMPT #language en-US "Size of Temporary RAM for PEI phase"
+#string STR_gUefiRiscVPlatformPkgTokenSpaceGuid_PcdTemporaryRamSize_HELP #language en-US "The size of temporary memory passed to PEI phase from SEC."
+#string STR_gUefiRiscVPlatformPkgTokenSpaceGuid_PcdPeiCorePrivilegeMode_PROMPT #language en-US "RISC-V Privilege mode in PEI phase "
+#string STR_gUefiRiscVPlatformPkgTokenSpaceGuid_PcdPeiCorePrivilegeMode_HELP #language en-US "The privilege mode the PEI phase is executed."
+#string STR_gUefiRiscVPlatformPkgTokenSpaceGuid_PcdDeviceTreeAddress_PROMPT #language en-US "Device Tree base address"
+#string STR_gUefiRiscVPlatformPkgTokenSpaceGuid_PcdDeviceTreeAddress_HELP #language en-US "The base address of Device Tree.<BR>"
--
2.31.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* [edk2-platforms][PATCH V2 04/14] RISC-V/PlatformPkg: Address Spelling check errors.
2022-01-22 6:53 [edk2-platforms][PATCH V2 00/14] Address edk2 Core CI issues Abner Chang
` (2 preceding siblings ...)
2022-01-22 6:53 ` [edk2-platforms][PATCH V2 03/14] RISC-V/PlatformPkg: Address ECC errors Abner Chang
@ 2022-01-22 6:53 ` Abner Chang
2022-01-22 6:53 ` [edk2-platforms][PATCH V2 05/14] RISC-V/PlatformPkg: Address Core CI package dependency " Abner Chang
` (10 subsequent siblings)
14 siblings, 0 replies; 16+ messages in thread
From: Abner Chang @ 2022-01-22 6:53 UTC (permalink / raw)
To: devel; +Cc: abner.chang, Daniel Schaefer, Sunil V L
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Cc: Daniel Schaefer <daniel.schaefer@hpe.com>
Cc: Sunil V L <sunilvl@ventanamicro.com>
---
Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec | 4 ++--
.../FirmwareContextProcessorSpecificLib.inf | 2 +-
.../PlatformPkg/Universal/FdtPeim/FdtPeim.inf | 2 +-
.../Library/FirmwareContextProcessorSpecificLib.h | 4 ++--
.../RISC-V/PlatformPkg/Universal/Sec/SecMain.h | 4 ++--
.../Edk2OpensbiPlatformWrapperLib.c | 10 +++++-----
.../FirmwareContextProcessorSpecificLib.c | 8 ++++----
.../PlatformBootManagerLib/PlatformBootManager.c | 4 ++--
.../Universal/Pei/PlatformPei/Platform.c | 4 ++--
.../RISC-V/PlatformPkg/Universal/Sec/SecMain.c | 10 +++++-----
Platform/RISC-V/PlatformPkg/Readme.md | 14 +++++++-------
.../PlatformPkg/Universal/Sec/Riscv64/SecEntry.S | 8 ++++----
12 files changed, 37 insertions(+), 37 deletions(-)
diff --git a/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec b/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec
index 53d424c901..f3217e4a05 100644
--- a/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec
+++ b/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec
@@ -1,7 +1,7 @@
## @file RiscVPlatformPkg.dec
# This Package provides UEFI RISC-V platform modules and libraries.
#
-# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+# Copyright (c) 2021-2022, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -20,7 +20,7 @@
[LibraryClasses]
FirmwareContextProcessorSpecificLib|Include/Library/FirmwareContextProcessorSpecificLib.h
RiscVPlatformTempMemoryInitLib|Include/Library/RiscVPlatformTempMemoryInitLib.h
- Edk2OpensbiPlatformiLib|Include/Library/Edk2OpensbiPlatformiWrapperLib.h
+ Edk2OpensbiPlatformWrapperLib|Include/Library/Edk2OpensbiPlatformWrapperLib.h
[Guids]
gUefiRiscVPlatformPkgTokenSpaceGuid = {0x6A67AF99, 0x4592, 0x40F8, { 0xB6, 0xBE, 0x62, 0xBC, 0xA1, 0x0D, 0xA1, 0xEC}}
diff --git a/Platform/RISC-V/PlatformPkg/Library/FirmwareContextProcessorSpecificLib/FirmwareContextProcessorSpecificLib.inf b/Platform/RISC-V/PlatformPkg/Library/FirmwareContextProcessorSpecificLib/FirmwareContextProcessorSpecificLib.inf
index ea2550ce2c..8b645e2c5c 100644
--- a/Platform/RISC-V/PlatformPkg/Library/FirmwareContextProcessorSpecificLib/FirmwareContextProcessorSpecificLib.inf
+++ b/Platform/RISC-V/PlatformPkg/Library/FirmwareContextProcessorSpecificLib/FirmwareContextProcessorSpecificLib.inf
@@ -1,6 +1,6 @@
## @file
# This is the library module of RISC-V EDK2 OpenSBI Firmware Context
-# Processor Specific hwardware information.
+# Processor Specific hardware information.
#
# Copyright (c) 2019-2022, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
#
diff --git a/Platform/RISC-V/PlatformPkg/Universal/FdtPeim/FdtPeim.inf b/Platform/RISC-V/PlatformPkg/Universal/FdtPeim/FdtPeim.inf
index dc3a685d58..2579dafe86 100644
--- a/Platform/RISC-V/PlatformPkg/Universal/FdtPeim/FdtPeim.inf
+++ b/Platform/RISC-V/PlatformPkg/Universal/FdtPeim/FdtPeim.inf
@@ -1,7 +1,7 @@
## @file
# The FDT Peim driver is used to pass the device tree to DXE phase.
#
-# Copyright (c) 2021, Hewlett Packard Enterprise Developmente LP. All rights reserved.<BR>
+# Copyright (c) 2021-2022, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
diff --git a/Platform/RISC-V/PlatformPkg/Include/Library/FirmwareContextProcessorSpecificLib.h b/Platform/RISC-V/PlatformPkg/Include/Library/FirmwareContextProcessorSpecificLib.h
index 3920c61155..0eec62033b 100644
--- a/Platform/RISC-V/PlatformPkg/Include/Library/FirmwareContextProcessorSpecificLib.h
+++ b/Platform/RISC-V/PlatformPkg/Include/Library/FirmwareContextProcessorSpecificLib.h
@@ -1,7 +1,7 @@
/** @file
Firmware Context Processor-specific common library
- Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+ Copyright (c) 2019-2022, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -18,7 +18,7 @@
@param FirmwareContextHartSpecific Pointer to EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC
@param ParentProcessorGuid Pointer to GUID of Processor which contains this core
- @param ParentProcessorUid Unique ID of pysical processor which owns this core.
+ @param ParentProcessorUid Unique ID of physical processor which owns this core.
@param CoreGuid Pointer to GUID of core
@param HartId Hart ID of this core.
@param IsBootHart This is boot hart or not
diff --git a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.h b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.h
index 63a610fbd0..4098bd7d92 100644
--- a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.h
+++ b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.h
@@ -1,7 +1,7 @@
/** @file
RISC-V SEC phase module definitions..
- Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+ Copyright (c) 2019-2022, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -35,7 +35,7 @@
**/
INT32
-SecPostOpenSbiPlatformEarlylInit(
+SecPostOpenSbiPlatformEarlyInit(
IN BOOLEAN ColdBoot
);
diff --git a/Platform/RISC-V/PlatformPkg/Library/Edk2OpensbiPlatformWrapperLib/Edk2OpensbiPlatformWrapperLib.c b/Platform/RISC-V/PlatformPkg/Library/Edk2OpensbiPlatformWrapperLib/Edk2OpensbiPlatformWrapperLib.c
index 2137c6c619..0bd1b44241 100644
--- a/Platform/RISC-V/PlatformPkg/Library/Edk2OpensbiPlatformWrapperLib/Edk2OpensbiPlatformWrapperLib.c
+++ b/Platform/RISC-V/PlatformPkg/Library/Edk2OpensbiPlatformWrapperLib/Edk2OpensbiPlatformWrapperLib.c
@@ -1,7 +1,7 @@
/** @file
EDK2 OpenSBI generic platform wrapper library
- Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+ Copyright (c) 2019-2022, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -43,7 +43,7 @@ SecSetEdk2FwMemoryRegions (
fw_memregs.flags = SBI_DOMAIN_MEMREGION_EXECUTABLE | SBI_DOMAIN_MEMREGION_READABLE;
Ret = sbi_domain_root_add_memregion ((CONST struct sbi_domain_memregion *)&fw_memregs);
if (Ret != 0) {
- DEBUG ((DEBUG_ERROR, "%a: Add firmware regiosn of FW Domain fail\n", __FUNCTION__));
+ DEBUG ((DEBUG_ERROR, "%a: Add firmware regions of FW Domain fail\n", __FUNCTION__));
}
//
@@ -54,7 +54,7 @@ SecSetEdk2FwMemoryRegions (
fw_memregs.flags = SBI_DOMAIN_MEMREGION_READABLE | SBI_DOMAIN_MEMREGION_WRITEABLE;
Ret = sbi_domain_root_add_memregion ((CONST struct sbi_domain_memregion *)&fw_memregs);
if (Ret != 0) {
- DEBUG ((DEBUG_ERROR, "%a: Add firmware regiosn of variable FW Domain fail\n", __FUNCTION__));
+ DEBUG ((DEBUG_ERROR, "%a: Add firmware regions of variable FW Domain fail\n", __FUNCTION__));
}
return Ret;
}
@@ -66,7 +66,7 @@ SecSetEdk2FwMemoryRegions (
**/
INT32
-SecPostOpenSbiPlatformEarlylInit(
+SecPostOpenSbiPlatformEarlyInit(
IN BOOLEAN ColdBoot
)
{
@@ -190,7 +190,7 @@ Edk2OpensbiPlatformEarlyInit (
}
}
if (ColdBoot) {
- return SecPostOpenSbiPlatformEarlylInit(ColdBoot);
+ return SecPostOpenSbiPlatformEarlyInit(ColdBoot);
}
return 0;
}
diff --git a/Platform/RISC-V/PlatformPkg/Library/FirmwareContextProcessorSpecificLib/FirmwareContextProcessorSpecificLib.c b/Platform/RISC-V/PlatformPkg/Library/FirmwareContextProcessorSpecificLib/FirmwareContextProcessorSpecificLib.c
index 143c18d62c..c94f7881c2 100644
--- a/Platform/RISC-V/PlatformPkg/Library/FirmwareContextProcessorSpecificLib/FirmwareContextProcessorSpecificLib.c
+++ b/Platform/RISC-V/PlatformPkg/Library/FirmwareContextProcessorSpecificLib/FirmwareContextProcessorSpecificLib.c
@@ -1,7 +1,7 @@
/** @file
- Common library to build upfirmware context processor-specific information
+ Common library to build up firmware context processor-specific information
- Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+ Copyright (c) 2019-2022, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -28,7 +28,7 @@
@param FirmwareContextHartSpecific Pointer to EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC
@param ParentProcessorGuid Pointer to GUID of Processor which contains this core
- @param ParentProcessorUid Unique ID of pysical processor which owns this core.
+ @param ParentProcessorUid Unique ID of physical processor which owns this core.
@param CoreGuid Pointer to GUID of core
@param HartId Hart ID of this core.
@param IsBootHart This is boot hart or not
@@ -52,7 +52,7 @@ CommonFirmwareContextHartSpecificInfo (
//
// Build up RISC_V_PROCESSOR_SPECIFIC_DATA_HOB.
//
- CopyGuid (&ProcessorSpecificDataHob->ParentPrcessorGuid, ParentProcessorGuid);
+ CopyGuid (&ProcessorSpecificDataHob->ParentProcessorGuid, ParentProcessorGuid);
ProcessorSpecificDataHob->ParentProcessorUid = ParentProcessorUid;
CopyGuid (&ProcessorSpecificDataHob->CoreGuid, CoreGuid);
ProcessorSpecificDataHob->Context = NULL;
diff --git a/Platform/RISC-V/PlatformPkg/Library/PlatformBootManagerLib/PlatformBootManager.c b/Platform/RISC-V/PlatformPkg/Library/PlatformBootManagerLib/PlatformBootManager.c
index deaad7d5a1..9ad4ef17db 100644
--- a/Platform/RISC-V/PlatformPkg/Library/PlatformBootManagerLib/PlatformBootManager.c
+++ b/Platform/RISC-V/PlatformPkg/Library/PlatformBootManagerLib/PlatformBootManager.c
@@ -1,7 +1,7 @@
/** @file
This file include all platform actions
-Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+Copyright (c) 2021-2022, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -215,7 +215,7 @@ PlatformBootManagerBeforeConsole (
Signal console ready platform customized event;
Run diagnostics like memory testing;
Connect certain devices;
- Dispatch aditional option roms.
+ Dispatch additional option roms.
**/
VOID
EFIAPI
diff --git a/Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei/Platform.c b/Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei/Platform.c
index 972a429fb9..c28b2ed373 100644
--- a/Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei/Platform.c
+++ b/Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei/Platform.c
@@ -296,7 +296,7 @@ BootModeInitialization (
{
EFI_STATUS Status;
- if (CheckResumeFromS3 ()) {
+ if (CheckResumeFromS3) {
DEBUG ((DEBUG_INFO, "This is wake from S3\n"));
} else {
DEBUG ((DEBUG_INFO, "This is normal boot\n"));
@@ -357,7 +357,7 @@ InitializePlatform (
MiscInitialization ();
Status = BuildCoreInformationHob ();
if (EFI_ERROR (Status)) {
- DEBUG ((DEBUG_ERROR, "Fail to build processor informstion HOB.\n"));
+ DEBUG ((DEBUG_ERROR, "Fail to build processor information HOB.\n"));
ASSERT(FALSE);
}
return EFI_SUCCESS;
diff --git a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c
index 1fafed2799..7a79eeec2d 100644
--- a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c
+++ b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c
@@ -291,7 +291,7 @@ FindPeiCoreImageBase (
/**
Find and return Pei Core entry point.
- It also find SEC and PEI Core file debug inforamtion. It will report them if
+ It also find SEC and PEI Core file debug information. It will report them if
remote debug is enabled.
@param[in] BootFirmwareVolumePtr The firmware volume pointer to search
@@ -516,7 +516,7 @@ LaunchPeiCore (
@param[in] FuncArg1 Arg1 to pass to next phase entry point address.
@param[in] NextAddr Entry point of next phase.
@param[in] NextMode Privilege mode of next phase.
- @param[in] NextVirt Next phase is in virtualiztion.
+ @param[in] NextVirt Next phase is in virtualization.
**/
VOID
@@ -600,7 +600,7 @@ Edk2PlatformHartIndex2Id (
}
/**
- This function initilizes hart specific information and SBI.
+ This function initializes hart specific information and SBI.
For the boot hart, it boots system through PEI core and initial SBI in the DXE IPL.
For others, it goes to initial SBI and halt.
@@ -658,9 +658,9 @@ SecCoreStartUpWithStack(
HartFirmwareContext->HartSwitchMode = RiscVOpenSbiHartSwitchMode;
//
- // Hook platorm_ops with EDK2 one. Thus we can have interface
+ // Hook platform_ops with EDK2 one. Thus we can have interface
// call out to OEM EDK2 platform code in M-mode before switching
- // to S-mode in opensbo init.
+ // to S-mode in opensbi init.
//
ThisSbiPlatform = (struct sbi_platform *)sbi_platform_ptr(Scratch);
ThisSbiPlatform->platform_ops_addr = (unsigned long)&Edk2OpensbiPlatformOps;
diff --git a/Platform/RISC-V/PlatformPkg/Readme.md b/Platform/RISC-V/PlatformPkg/Readme.md
index 66fba15544..5a344a864a 100644
--- a/Platform/RISC-V/PlatformPkg/Readme.md
+++ b/Platform/RISC-V/PlatformPkg/Readme.md
@@ -26,16 +26,16 @@ differently from the default settings according to the OEM platform design.
to align with OpenSBI project. As mentioned earlier, ***RiscVOpensbiLib*** provides the RISC-V SBI
implementation and initialize the OpenSBI boot flow. SEC module is also linked with below libraries,
- edk2 [OpenSbiPlatformLib](#OpenSbiPlatformLib-library) library that provides the generic RISC-V platform initialization code.
-- edk2 [RiscVSpecifialPlatformLib](#RiscVSpecifialPlatformLib-library) library which is provided by the RISC-V
+- edk2 [RiscVSpecialPlatformLib](#RiscVSpecialPlatformLib-library) library which is provided by the RISC-V
platform vendor for the platform-specific initialization. The underlying implementation of above two edk2 libraries
are from OpenSBI project. edk2 libraries are introduced as the wrapper libraries that separates and organizes OpenSBI core and platform code based on edk2 framework and the the build mechanism for edk2 RISC-V platforms. ***RiscVOpensbiLib*** library is located under [RISC-V ProcessorPkg](https://github.com/tianocore/edk2-platforms/tree/master/Silicon/RISC-V/ProcessorPkg) while the platform code (e.g. OpenSbiPlatformLib) is located under [RISC-V PlatformPkg](https://github.com/tianocore/edk2-platforms/tree/master/Platform/RISC-V/PlatformPkg).
-- edk2 [RiscVSpecifialPlatformLib](#riscvspecifialplatformlib) library is provided by the platform vendor and located under edk2 RISC-V platform-specific folder.
+- edk2 [RiscVSpecialPlatformLib](#riscvspecialplatformlib) library is provided by the platform vendor and located under edk2 RISC-V platform-specific folder.
##### OpenSbiPlatformLib Library
[Indicated as #2 in the figure](#risc-v-edk2-port-design-diagrams)
> ***OpenSbiPlatformLib*** provides the generic RISC-V platform initialization code. Platform vendor can just utilize this library if they don't have additional requirements on the platform initialization.
-##### RiscVSpecifialPlatformLib Library
+##### RiscVSpecialPlatformLib Library
[Indicated as #3 in the figure](#risc-v-edk2-port-design-diagrams)
> The major use case of this library is to facilitate the interfaces for platform vendors to provide the special
platform initialization based on the generic platform initialization library.
@@ -57,7 +57,7 @@ privilege according to the PCD.
#### PEI Phase
SEC module hands off the boot process to PEI core in the privilege configured by ***PcdPeiCorePrivilegeMode*** PCD *(TODO, currently the privilege is forced to S-mode)*. PEI and later phases are allowed to executed in M-mode
-if the platform doesn't require Hypervisor-extended Supervisor mode (HS-mode) for the virtualization. RISC-V edk2 port provides its own instance ***PeiCoreEntryPoint*** library [(indicated as #7 in the figure)](#risc-v-edk2-port-design-diagrams) and linked with [PlatformSecPpiLib](#platformsecppilib-library) in order to support the S-mode PEI phase. PEI core requires [RiscVFirmwareContextLib](#riscVfirmwarecontextlib-library) library to retrieve the information of RISC-V HARTs and platform (e.g. FDT) configurations that built up in SEC phase. ***PeiServicePointer*** is also maintained in the ***RISC-V OpenSBI FirmwareContext*** structure and the pointer is retrieved by [PeiServiceTablePointerOpensbi](#peiservicetablepointeropensbi-library) library.
+if the platform doesn't require Hypervisor-extended Supervisor mode (HS-mode) for the virtualization. RISC-V edk2 port provides its own instance ***PeiCoreEntryPoint*** library [(indicated as #7 in the figure)](#risc-v-edk2-port-design-diagrams) and linked with [PlatformSecPpiLib](#platformsecppilib-library) in order to support the S-mode PEI phase. PEI core requires [RiscVFirmwareContextLib](#riscvfirmwarecontextlib-library) library to retrieve the information of RISC-V HARTs and platform (e.g. FDT) configurations that built up in SEC phase. ***PeiServicePointer*** is also maintained in the ***RISC-V OpenSBI FirmwareContext*** structure and the pointer is retrieved by [PeiServiceTablePointerOpensbi](#peiservicetablepointeropensbi-library) library.
##### PlatformSecPpiLib Library
[Indicated as #8 in the figure](#risc-v-edk2-port-design-diagrams)
@@ -178,7 +178,7 @@ The PCD settings regard to EFI Variable
|PcdVariableFdSize| The EFI variable firmware device size|
|PcdVariableFdBlockSize| The block size of EFI variable firmware device|
|PcdPlatformFlashNvStorageVariableBase| EFI variable base address within firmware device|
-|PcdPlatformFlashNvStorageFtwWorkingBase| The base address of EFI variable fault tolerance worksapce (FTW) within firmware device|
+|PcdPlatformFlashNvStorageFtwWorkingBase| The base address of EFI variable fault tolerance workspace (FTW) within firmware device|
|PcdPlatformFlashNvStorageFtwSpareBase| The base address of EFI variable spare FTW within firmware device|
### RISC-V Physical Memory Protection (PMP) Region Settings
@@ -190,7 +190,7 @@ Below PCDs could be set in platform FDF file.
|PcdRootFirmwareDomainSize| The size of root firmware domain|-|-|
|PcdFirmwareDomainBaseAddress| The starting address of firmware domain that can be accessed and executed in S-mode|Full access|Readable and Executable|
|PcdFirmwareDomainSize| The size of firmware domain|-|-|
-|PcdVariableFirmwareRegionBaseAddress| The starting address of EFI variable region that can be accessed in S-mode|Full access|Readale and Writable|
+|PcdVariableFirmwareRegionBaseAddress| The starting address of EFI variable region that can be accessed in S-mode|Full access|Readable and Writable|
|PcdVariableFirmwareRegionSize| The size of EFI variable firmware region|-|-|
### RISC-V Processor HART Settings
@@ -198,7 +198,7 @@ Below PCDs could be set in platform FDF file.
| **PCD name** |**Usage**|
|--------------|---------|
|PcdHartCount| Number of RISC-V HARTs, the value is processor-implementation specific|
-|PcdBootHartId| The ID of RISC-V HART to execute main fimrware code and boot system to OS|
+|PcdBootHartId| The ID of RISC-V HART to execute main firmware code and boot system to OS|
|PcdBootableHartNumber|The bootable HART number, which is incorporate with RISC-V OpenSBI platform hart_index2id value|
|PcdBootableHartIndexToId| if PcdBootableHartNumber == 0, hart_index2id is built from Device Tree, otherwise this is an array of HART index to HART ID|
diff --git a/Platform/RISC-V/PlatformPkg/Universal/Sec/Riscv64/SecEntry.S b/Platform/RISC-V/PlatformPkg/Universal/Sec/Riscv64/SecEntry.S
index 0fc7817665..a96dd9474b 100644
--- a/Platform/RISC-V/PlatformPkg/Universal/Sec/Riscv64/SecEntry.S
+++ b/Platform/RISC-V/PlatformPkg/Universal/Sec/Riscv64/SecEntry.S
@@ -67,7 +67,7 @@ skip_fw_init:
* DTB for this processor. We allocate the
* scratch buffer according to this number.
*/
- la a4, _pysical_hart_count
+ la a4, _physical_hart_count
sd s7, (a4)
li s8, FixedPcdGet32 (PcdOpenSbiStackSize)
@@ -227,7 +227,7 @@ _start_warm:
csrr a0, CSR_MHARTID
j _uninitialized_hart_wait
4:
- la a5, _pysical_hart_count
+ la a5, _physical_hart_count
ld s7, (a5)
/* Find the scratch space for this hart
*
@@ -294,7 +294,7 @@ _start_warm:
.section .data, "aw"
_boot_hart_done:
RISCV_PTR 0
-_pysical_hart_count:
+_physical_hart_count:
RISCV_PTR 0
.align 3
@@ -323,7 +323,7 @@ _hartid_to_scratch:
lw s0, SBI_PLATFORM_HART_STACK_SIZE_OFFSET(s2)
#endif
- la s1, _pysical_hart_count /* total HART count */
+ la s1, _physical_hart_count /* total HART count */
ld s2, (s1)
mul s2, s2, s0
li s1, FixedPcdGet32 (PcdScratchRamBase)
--
2.31.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* [edk2-platforms][PATCH V2 05/14] RISC-V/PlatformPkg: Address Core CI package dependency check errors
2022-01-22 6:53 [edk2-platforms][PATCH V2 00/14] Address edk2 Core CI issues Abner Chang
` (3 preceding siblings ...)
2022-01-22 6:53 ` [edk2-platforms][PATCH V2 04/14] RISC-V/PlatformPkg: Address Spelling check errors Abner Chang
@ 2022-01-22 6:53 ` Abner Chang
2022-01-22 6:53 ` [edk2-platforms][PATCH V2 06/14] RISC-V/PlatformPkg: Address Core CI license " Abner Chang
` (9 subsequent siblings)
14 siblings, 0 replies; 16+ messages in thread
From: Abner Chang @ 2022-01-22 6:53 UTC (permalink / raw)
To: devel; +Cc: abner.chang, Daniel Schaefer, Sunil V L
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Cc: Daniel Schaefer <daniel.schaefer@hpe.com>
Cc: Sunil V L <sunilvl@ventanamicro.com>
---
.../RISC-V/PlatformPkg/Universal/Pei/PlatformPei/PlatformPei.inf | 1 -
1 file changed, 1 deletion(-)
diff --git a/Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei/PlatformPei.inf b/Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei/PlatformPei.inf
index 8a88bbf9ce..e99a3b9c1d 100644
--- a/Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei/PlatformPei.inf
+++ b/Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei/PlatformPei.inf
@@ -34,7 +34,6 @@
MdePkg/MdePkg.dec
Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec
Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec
- UefiCpuPkg/UefiCpuPkg.dec
[Guids]
gEfiMemoryTypeInformationGuid
--
2.31.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* [edk2-platforms][PATCH V2 06/14] RISC-V/PlatformPkg: Address Core CI license check errors.
2022-01-22 6:53 [edk2-platforms][PATCH V2 00/14] Address edk2 Core CI issues Abner Chang
` (4 preceding siblings ...)
2022-01-22 6:53 ` [edk2-platforms][PATCH V2 05/14] RISC-V/PlatformPkg: Address Core CI package dependency " Abner Chang
@ 2022-01-22 6:53 ` Abner Chang
2022-01-22 6:53 ` [edk2-platforms][PATCH V2 07/14] RISC-V/PlatformPkg: Address Core CI library header " Abner Chang
` (8 subsequent siblings)
14 siblings, 0 replies; 16+ messages in thread
From: Abner Chang @ 2022-01-22 6:53 UTC (permalink / raw)
To: devel; +Cc: abner.chang, Daniel Schaefer, Sunil V L
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Cc: Daniel Schaefer <daniel.schaefer@hpe.com>
Cc: Sunil V L <sunilvl@ventanamicro.com>
---
.../PlatformPkg/Universal/Sec/Riscv64/SecEntry.S | 11 +++++------
1 file changed, 5 insertions(+), 6 deletions(-)
diff --git a/Platform/RISC-V/PlatformPkg/Universal/Sec/Riscv64/SecEntry.S b/Platform/RISC-V/PlatformPkg/Universal/Sec/Riscv64/SecEntry.S
index a96dd9474b..8a8701f1bd 100644
--- a/Platform/RISC-V/PlatformPkg/Universal/Sec/Riscv64/SecEntry.S
+++ b/Platform/RISC-V/PlatformPkg/Universal/Sec/Riscv64/SecEntry.S
@@ -1,10 +1,9 @@
/*
- * Copyright (c) 2021 , Hewlett Packard Enterprise Development LP. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-2-Clause
- *
- * Copyright (c) 2019 Western Digital Corporation or its affiliates.
- *
+ Copyright (c) 2021-2022 , Hewlett Packard Enterprise Development LP. All rights reserved.
+ Copyright (c) 2019 Western Digital Corporation or its affiliates.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
*/
#include <IndustryStandard/RiscVOpensbi.h>
--
2.31.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* [edk2-platforms][PATCH V2 07/14] RISC-V/PlatformPkg: Address Core CI library header check errors
2022-01-22 6:53 [edk2-platforms][PATCH V2 00/14] Address edk2 Core CI issues Abner Chang
` (5 preceding siblings ...)
2022-01-22 6:53 ` [edk2-platforms][PATCH V2 06/14] RISC-V/PlatformPkg: Address Core CI license " Abner Chang
@ 2022-01-22 6:53 ` Abner Chang
2022-01-22 6:53 ` [edk2-platforms][PATCH V2 08/14] RISC-V/PlatformPkg: Address Core CI Uncrustify errors Abner Chang
` (7 subsequent siblings)
14 siblings, 0 replies; 16+ messages in thread
From: Abner Chang @ 2022-01-22 6:53 UTC (permalink / raw)
To: devel; +Cc: abner.chang, Daniel Schaefer, Sunil V L
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Cc: Daniel Schaefer <daniel.schaefer@hpe.com>
Cc: Sunil V L <sunilvl@ventanamicro.com>
---
Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec b/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec
index f3217e4a05..b45f48fdc5 100644
--- a/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec
+++ b/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec
@@ -21,6 +21,8 @@
FirmwareContextProcessorSpecificLib|Include/Library/FirmwareContextProcessorSpecificLib.h
RiscVPlatformTempMemoryInitLib|Include/Library/RiscVPlatformTempMemoryInitLib.h
Edk2OpensbiPlatformWrapperLib|Include/Library/Edk2OpensbiPlatformWrapperLib.h
+ RiscVSpecialPlatformLib|Include/Library/RiscVSpecialPlatformLib.h
+ PlatformSecPpiLib|Include/Library/PlatformSecPpiLib.h
[Guids]
gUefiRiscVPlatformPkgTokenSpaceGuid = {0x6A67AF99, 0x4592, 0x40F8, { 0xB6, 0xBE, 0x62, 0xBC, 0xA1, 0x0D, 0xA1, 0xEC}}
--
2.31.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* [edk2-platforms][PATCH V2 08/14] RISC-V/PlatformPkg: Address Core CI Uncrustify errors
2022-01-22 6:53 [edk2-platforms][PATCH V2 00/14] Address edk2 Core CI issues Abner Chang
` (6 preceding siblings ...)
2022-01-22 6:53 ` [edk2-platforms][PATCH V2 07/14] RISC-V/PlatformPkg: Address Core CI library header " Abner Chang
@ 2022-01-22 6:53 ` Abner Chang
2022-01-22 6:53 ` [edk2-platforms][PATCH V2 09/14] RISC-V/ProcessorPkg: Address Core CI ECC errors Abner Chang
` (6 subsequent siblings)
14 siblings, 0 replies; 16+ messages in thread
From: Abner Chang @ 2022-01-22 6:53 UTC (permalink / raw)
To: devel; +Cc: abner.chang, Daniel Schaefer, Sunil V L
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Cc: Daniel Schaefer <daniel.schaefer@hpe.com>
Cc: Sunil V L <sunilvl@ventanamicro.com>
---
.../Library/Edk2OpensbiPlatformWrapperLib.h | 2 +-
.../FirmwareContextProcessorSpecificLib.h | 17 +-
.../Include/Library/PlatformSecPpiLib.h | 2 +-
.../Library/RiscVPlatformTempMemoryInitLib.h | 18 +-
.../PlatformBootManager.h | 34 +-
.../Universal/Pei/PlatformPei/Platform.h | 32 +-
.../PlatformPkg/Universal/Sec/SecMain.h | 6 +-
.../Edk2OpensbiPlatformWrapperLib.c | 384 ++++++++++--------
.../FirmwareContextProcessorSpecificLib.c | 30 +-
.../OpensbiPlatformLib/OpensbiPlatform.c | 229 ++++++-----
.../PeiCoreEntryPoint/PeiCoreEntryPoint.c | 18 +-
.../PlatformBootManager.c | 68 ++--
.../PlatformBootManagerLib/PlatformData.c | 18 +-
.../PlatformMemoryTestLibNull.c | 2 +-
.../Library/ResetSystemLib/ResetSystemLib.c | 40 +-
.../RiscVSpecialPlatformLib.c | 7 +-
.../PlatformPkg/Universal/FdtPeim/FdtPeim.c | 30 +-
.../Universal/Pei/PlatformPei/Fv.c | 9 +-
.../Universal/Pei/PlatformPei/MemDetect.c | 15 +-
.../Universal/Pei/PlatformPei/Platform.c | 91 +++--
.../PlatformPkg/Universal/Sec/SecMain.c | 328 ++++++++-------
21 files changed, 745 insertions(+), 635 deletions(-)
diff --git a/Platform/RISC-V/PlatformPkg/Include/Library/Edk2OpensbiPlatformWrapperLib.h b/Platform/RISC-V/PlatformPkg/Include/Library/Edk2OpensbiPlatformWrapperLib.h
index 4da0a64a8c..cb669bd737 100644
--- a/Platform/RISC-V/PlatformPkg/Include/Library/Edk2OpensbiPlatformWrapperLib.h
+++ b/Platform/RISC-V/PlatformPkg/Include/Library/Edk2OpensbiPlatformWrapperLib.h
@@ -11,6 +11,6 @@
#include <sbi/sbi_platform.h>
-extern struct sbi_platform_operations Edk2OpensbiPlatformOps;
+extern struct sbi_platform_operations Edk2OpensbiPlatformOps;
#endif
diff --git a/Platform/RISC-V/PlatformPkg/Include/Library/FirmwareContextProcessorSpecificLib.h b/Platform/RISC-V/PlatformPkg/Include/Library/FirmwareContextProcessorSpecificLib.h
index 0eec62033b..348a644675 100644
--- a/Platform/RISC-V/PlatformPkg/Include/Library/FirmwareContextProcessorSpecificLib.h
+++ b/Platform/RISC-V/PlatformPkg/Include/Library/FirmwareContextProcessorSpecificLib.h
@@ -6,6 +6,7 @@
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
+
#ifndef FIRMWARE_CONTEXT_PROCESSOR_SPECIFIC_LIB_H_
#define FIRMWARE_CONTEXT_PROCESSOR_SPECIFIC_LIB_H_
@@ -30,13 +31,13 @@
EFI_STATUS
EFIAPI
CommonFirmwareContextHartSpecificInfo (
- EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC *FirmwareContextHartSpecific,
- EFI_GUID *ParentProcessorGuid,
- UINTN ParentProcessorUid,
- EFI_GUID *CoreGuid,
- UINTN HartId,
- BOOLEAN IsBootHart,
- RISC_V_PROCESSOR_SPECIFIC_HOB_DATA *ProcessorSpecDataHob
+ EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC *FirmwareContextHartSpecific,
+ EFI_GUID *ParentProcessorGuid,
+ UINTN ParentProcessorUid,
+ EFI_GUID *CoreGuid,
+ UINTN HartId,
+ BOOLEAN IsBootHart,
+ RISC_V_PROCESSOR_SPECIFIC_HOB_DATA *ProcessorSpecDataHob
);
/**
@@ -47,7 +48,7 @@ CommonFirmwareContextHartSpecificInfo (
VOID
EFIAPI
DebugPrintHartSpecificInfo (
- RISC_V_PROCESSOR_SPECIFIC_HOB_DATA *ProcessorSpecificDataHob
+ RISC_V_PROCESSOR_SPECIFIC_HOB_DATA *ProcessorSpecificDataHob
);
#endif
diff --git a/Platform/RISC-V/PlatformPkg/Include/Library/PlatformSecPpiLib.h b/Platform/RISC-V/PlatformPkg/Include/Library/PlatformSecPpiLib.h
index 88468e660b..e7f0b2c8ff 100644
--- a/Platform/RISC-V/PlatformPkg/Include/Library/PlatformSecPpiLib.h
+++ b/Platform/RISC-V/PlatformPkg/Include/Library/PlatformSecPpiLib.h
@@ -19,6 +19,6 @@
EFI_STATUS
GetPlatformPrePeiCorePpiDescriptor (
IN OUT EFI_PEI_PPI_DESCRIPTOR **ThisPpiList
-);
+ );
#endif
diff --git a/Platform/RISC-V/PlatformPkg/Include/Library/RiscVPlatformTempMemoryInitLib.h b/Platform/RISC-V/PlatformPkg/Include/Library/RiscVPlatformTempMemoryInitLib.h
index 4f9f7950c1..996845834c 100644
--- a/Platform/RISC-V/PlatformPkg/Include/Library/RiscVPlatformTempMemoryInitLib.h
+++ b/Platform/RISC-V/PlatformPkg/Include/Library/RiscVPlatformTempMemoryInitLib.h
@@ -11,7 +11,19 @@
#include "RiscVImpl.h"
-VOID EFIAPI RiscVPlatformTemporaryMemInit (VOID);
-UINT32 EFIAPI RiscVPlatformTemporaryMemSize (VOID);
-UINT32 EFIAPI RiscVPlatformTemporaryMemBase (VOID);
+VOID EFIAPI
+RiscVPlatformTemporaryMemInit (
+ VOID
+ );
+
+UINT32 EFIAPI
+RiscVPlatformTemporaryMemSize (
+ VOID
+ );
+
+UINT32 EFIAPI
+RiscVPlatformTemporaryMemBase (
+ VOID
+ );
+
#endif
diff --git a/Platform/RISC-V/PlatformPkg/Library/PlatformBootManagerLib/PlatformBootManager.h b/Platform/RISC-V/PlatformPkg/Library/PlatformBootManagerLib/PlatformBootManager.h
index 01c26f307e..7da15b010a 100644
--- a/Platform/RISC-V/PlatformPkg/Library/PlatformBootManagerLib/PlatformBootManager.h
+++ b/Platform/RISC-V/PlatformPkg/Library/PlatformBootManagerLib/PlatformBootManager.h
@@ -33,25 +33,25 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#include <Library/PrintLib.h>
typedef struct {
- EFI_DEVICE_PATH_PROTOCOL *DevicePath;
- UINTN ConnectType;
+ EFI_DEVICE_PATH_PROTOCOL *DevicePath;
+ UINTN ConnectType;
} PLATFORM_CONSOLE_CONNECT_ENTRY;
extern PLATFORM_CONSOLE_CONNECT_ENTRY gPlatformConsole[];
-#define CONSOLE_OUT BIT0
-#define CONSOLE_IN BIT1
-#define STD_ERROR BIT2
+#define CONSOLE_OUT BIT0
+#define CONSOLE_IN BIT1
+#define STD_ERROR BIT2
-//D3987D4B-971A-435F-8CAF-4967EB627241
+// D3987D4B-971A-435F-8CAF-4967EB627241
#define EFI_SERIAL_DXE_GUID \
{ 0xD3987D4B, 0x971A, 0x435F, { 0x8C, 0xAF, 0x49, 0x67, 0xEB, 0x62, 0x72, 0x41 } }
typedef struct {
- VENDOR_DEVICE_PATH Guid;
- UART_DEVICE_PATH Uart;
- VENDOR_DEVICE_PATH TerminalType;
- EFI_DEVICE_PATH_PROTOCOL End;
+ VENDOR_DEVICE_PATH Guid;
+ UART_DEVICE_PATH Uart;
+ VENDOR_DEVICE_PATH TerminalType;
+ EFI_DEVICE_PATH_PROTOCOL End;
} SERIAL_CONSOLE_DEVICE_PATH;
/**
@@ -78,7 +78,7 @@ PlatformBootManagerDisableQuietBoot (
**/
EFI_STATUS
PlatformBootManagerMemoryTest (
- IN EXTENDMEM_COVERAGE_LEVEL Level
+ IN EXTENDMEM_COVERAGE_LEVEL Level
);
/**
@@ -98,12 +98,12 @@ PlatformBootManagerMemoryTest (
**/
EFI_STATUS
PlatformBootManagerShowProgress (
- IN EFI_GRAPHICS_OUTPUT_BLT_PIXEL TitleForeground,
- IN EFI_GRAPHICS_OUTPUT_BLT_PIXEL TitleBackground,
- IN CHAR16 *Title,
- IN EFI_GRAPHICS_OUTPUT_BLT_PIXEL ProgressColor,
- IN UINTN Progress,
- IN UINTN PreviousValue
+ IN EFI_GRAPHICS_OUTPUT_BLT_PIXEL TitleForeground,
+ IN EFI_GRAPHICS_OUTPUT_BLT_PIXEL TitleBackground,
+ IN CHAR16 *Title,
+ IN EFI_GRAPHICS_OUTPUT_BLT_PIXEL ProgressColor,
+ IN UINTN Progress,
+ IN UINTN PreviousValue
);
#endif // _PLATFORM_BOOT_MANAGER_H
diff --git a/Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei/Platform.h b/Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei/Platform.h
index 1b6cb4f870..6c23c722a3 100644
--- a/Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei/Platform.h
+++ b/Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei/Platform.h
@@ -1,7 +1,7 @@
/** @file
Platform PEI module include file.
- Copyright (c) 2019-2022, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+ Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -13,44 +13,44 @@
VOID
AddIoMemoryBaseSizeHob (
- EFI_PHYSICAL_ADDRESS MemoryBase,
- UINT64 MemorySize
+ EFI_PHYSICAL_ADDRESS MemoryBase,
+ UINT64 MemorySize
);
VOID
AddIoMemoryRangeHob (
- EFI_PHYSICAL_ADDRESS MemoryBase,
- EFI_PHYSICAL_ADDRESS MemoryLimit
+ EFI_PHYSICAL_ADDRESS MemoryBase,
+ EFI_PHYSICAL_ADDRESS MemoryLimit
);
VOID
AddMemoryBaseSizeHob (
- EFI_PHYSICAL_ADDRESS MemoryBase,
- UINT64 MemorySize
+ EFI_PHYSICAL_ADDRESS MemoryBase,
+ UINT64 MemorySize
);
VOID
AddMemoryRangeHob (
- EFI_PHYSICAL_ADDRESS MemoryBase,
- EFI_PHYSICAL_ADDRESS MemoryLimit
+ EFI_PHYSICAL_ADDRESS MemoryBase,
+ EFI_PHYSICAL_ADDRESS MemoryLimit
);
VOID
AddUntestedMemoryBaseSizeHob (
- EFI_PHYSICAL_ADDRESS MemoryBase,
- UINT64 MemorySize
+ EFI_PHYSICAL_ADDRESS MemoryBase,
+ UINT64 MemorySize
);
VOID
AddReservedMemoryBaseSizeHob (
- EFI_PHYSICAL_ADDRESS MemoryBase,
- UINT64 MemorySize
+ EFI_PHYSICAL_ADDRESS MemoryBase,
+ UINT64 MemorySize
);
VOID
AddUntestedMemoryRangeHob (
- EFI_PHYSICAL_ADDRESS MemoryBase,
- EFI_PHYSICAL_ADDRESS MemoryLimit
+ EFI_PHYSICAL_ADDRESS MemoryBase,
+ EFI_PHYSICAL_ADDRESS MemoryLimit
);
VOID
@@ -92,6 +92,6 @@ InitializeXen (
EFI_STATUS
BuildRiscVSmbiosHobs (
VOID
-);
+ );
#endif // _PLATFORM_PEI_H_INCLUDED_
diff --git a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.h b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.h
index 4098bd7d92..8c2e6e1253 100644
--- a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.h
+++ b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.h
@@ -35,8 +35,8 @@
**/
INT32
-SecPostOpenSbiPlatformEarlyInit(
- IN BOOLEAN ColdBoot
+SecPostOpenSbiPlatformEarlyInit (
+ IN BOOLEAN ColdBoot
);
/**
@@ -49,7 +49,7 @@ SecPostOpenSbiPlatformEarlyInit(
**/
INT32
SecPostOpenSbiPlatformFinalInit (
- IN BOOLEAN ColdBoot
+ IN BOOLEAN ColdBoot
);
/**
diff --git a/Platform/RISC-V/PlatformPkg/Library/Edk2OpensbiPlatformWrapperLib/Edk2OpensbiPlatformWrapperLib.c b/Platform/RISC-V/PlatformPkg/Library/Edk2OpensbiPlatformWrapperLib/Edk2OpensbiPlatformWrapperLib.c
index 0bd1b44241..c4f9dd02b2 100644
--- a/Platform/RISC-V/PlatformPkg/Library/Edk2OpensbiPlatformWrapperLib/Edk2OpensbiPlatformWrapperLib.c
+++ b/Platform/RISC-V/PlatformPkg/Library/Edk2OpensbiPlatformWrapperLib/Edk2OpensbiPlatformWrapperLib.c
@@ -16,8 +16,8 @@
#include <sbi/sbi_domain.h>
#include <sbi/sbi_math.h>
-extern struct sbi_platform_operations platform_ops;
-extern atomic_t BootHartDone;
+extern struct sbi_platform_operations platform_ops;
+extern atomic_t BootHartDone;
/**
Add firmware memory domain.
@@ -30,18 +30,18 @@ SecSetEdk2FwMemoryRegions (
VOID
)
{
- INT32 Ret;
- struct sbi_domain_memregion fw_memregs;
+ INT32 Ret;
+ struct sbi_domain_memregion fw_memregs;
Ret = 0;
//
// EDK2 PEI domain memory region
//
- fw_memregs.order = log2roundup(FixedPcdGet32(PcdFirmwareDomainSize));
- fw_memregs.base = FixedPcdGet32(PcdFirmwareDomainBaseAddress);
+ fw_memregs.order = log2roundup (FixedPcdGet32 (PcdFirmwareDomainSize));
+ fw_memregs.base = FixedPcdGet32 (PcdFirmwareDomainBaseAddress);
fw_memregs.flags = SBI_DOMAIN_MEMREGION_EXECUTABLE | SBI_DOMAIN_MEMREGION_READABLE;
- Ret = sbi_domain_root_add_memregion ((CONST struct sbi_domain_memregion *)&fw_memregs);
+ Ret = sbi_domain_root_add_memregion ((CONST struct sbi_domain_memregion *)&fw_memregs);
if (Ret != 0) {
DEBUG ((DEBUG_ERROR, "%a: Add firmware regions of FW Domain fail\n", __FUNCTION__));
}
@@ -49,15 +49,17 @@ SecSetEdk2FwMemoryRegions (
//
// EDK2 EFI Variable domain memory region
//
- fw_memregs.order = log2roundup(FixedPcdGet32(PcdVariableFirmwareRegionSize));
- fw_memregs.base = FixedPcdGet32(PcdVariableFirmwareRegionBaseAddress);
+ fw_memregs.order = log2roundup (FixedPcdGet32 (PcdVariableFirmwareRegionSize));
+ fw_memregs.base = FixedPcdGet32 (PcdVariableFirmwareRegionBaseAddress);
fw_memregs.flags = SBI_DOMAIN_MEMREGION_READABLE | SBI_DOMAIN_MEMREGION_WRITEABLE;
- Ret = sbi_domain_root_add_memregion ((CONST struct sbi_domain_memregion *)&fw_memregs);
+ Ret = sbi_domain_root_add_memregion ((CONST struct sbi_domain_memregion *)&fw_memregs);
if (Ret != 0) {
DEBUG ((DEBUG_ERROR, "%a: Add firmware regions of variable FW Domain fail\n", __FUNCTION__));
}
+
return Ret;
}
+
/**
OpenSBI platform early init hook.
@@ -66,17 +68,18 @@ SecSetEdk2FwMemoryRegions (
**/
INT32
-SecPostOpenSbiPlatformEarlyInit(
- IN BOOLEAN ColdBoot
+SecPostOpenSbiPlatformEarlyInit (
+ IN BOOLEAN ColdBoot
)
{
- UINT32 HartId;
+ UINT32 HartId;
if (!ColdBoot) {
- HartId = current_hartid();
+ HartId = current_hartid ();
DEBUG ((DEBUG_INFO, "%a: Non boot hart %d.\n", __FUNCTION__, HartId));
return 0;
}
+
//
// Setup firmware memory region.
//
@@ -103,70 +106,75 @@ SecPostOpenSbiPlatformEarlyInit(
**/
INT32
SecPostOpenSbiPlatformFinalInit (
- IN BOOLEAN ColdBoot
+ IN BOOLEAN ColdBoot
)
{
- UINT32 HartId;
- struct sbi_scratch *SbiScratch;
- struct sbi_scratch *ScratchSpace;
- struct sbi_platform *SbiPlatform;
- EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *FirmwareContext;
+ UINT32 HartId;
+ struct sbi_scratch *SbiScratch;
+ struct sbi_scratch *ScratchSpace;
+ struct sbi_platform *SbiPlatform;
+ EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *FirmwareContext;
if (!ColdBoot) {
- HartId = current_hartid();
+ HartId = current_hartid ();
DEBUG ((DEBUG_INFO, "%a: Non boot hart %d.\n", __FUNCTION__, HartId));
return 0;
}
- DEBUG((DEBUG_INFO, "%a: Entry, preparing to jump to PEI Core\n\n", __FUNCTION__));
+ DEBUG ((DEBUG_INFO, "%a: Entry, preparing to jump to PEI Core\n\n", __FUNCTION__));
- SbiScratch = sbi_scratch_thishart_ptr();
- SbiPlatform = (struct sbi_platform *)sbi_platform_ptr(SbiScratch);
+ SbiScratch = sbi_scratch_thishart_ptr ();
+ SbiPlatform = (struct sbi_platform *)sbi_platform_ptr (SbiScratch);
FirmwareContext = (EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *)SbiPlatform->firmware_context;
//
// Print out scratch address of each hart
//
DEBUG ((DEBUG_INFO, "%a: OpenSBI scratch address for each hart:\n", __FUNCTION__));
- for (HartId = 0; HartId < SBI_HARTMASK_MAX_BITS; HartId ++) {
- if (sbi_platform_hart_invalid(SbiPlatform, HartId)) {
+ for (HartId = 0; HartId < SBI_HARTMASK_MAX_BITS; HartId++) {
+ if (sbi_platform_hart_invalid (SbiPlatform, HartId)) {
continue;
}
+
ScratchSpace = sbi_hartid_to_scratch (HartId);
- if(ScratchSpace != NULL) {
- DEBUG((DEBUG_INFO, " Hart %d: 0x%x\n", HartId, ScratchSpace));
+ if (ScratchSpace != NULL) {
+ DEBUG ((DEBUG_INFO, " Hart %d: 0x%x\n", HartId, ScratchSpace));
} else {
- DEBUG((DEBUG_INFO, " Hart %d not initialized yet\n", HartId));
+ DEBUG ((DEBUG_INFO, " Hart %d not initialized yet\n", HartId));
}
}
//
// Set firmware context Hart-specific pointer
//
- for (HartId = 0; HartId < SBI_HARTMASK_MAX_BITS; HartId ++) {
- if (sbi_platform_hart_invalid(SbiPlatform, HartId)) {
+ for (HartId = 0; HartId < SBI_HARTMASK_MAX_BITS; HartId++) {
+ if (sbi_platform_hart_invalid (SbiPlatform, HartId)) {
continue;
}
+
ScratchSpace = sbi_hartid_to_scratch (HartId);
if (ScratchSpace != NULL) {
FirmwareContext->HartSpecific[HartId] =
(EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC *)((UINT8 *)ScratchSpace - FIRMWARE_CONTEXT_HART_SPECIFIC_SIZE);
- DEBUG ((DEBUG_INFO, "%a: OpenSBI Hart %d Firmware Context Hart-specific at address: 0x%x\n",
- __FUNCTION__,
- HartId,
- FirmwareContext->HartSpecific [HartId]
- ));
+ DEBUG ((
+ DEBUG_INFO,
+ "%a: OpenSBI Hart %d Firmware Context Hart-specific at address: 0x%x\n",
+ __FUNCTION__,
+ HartId,
+ FirmwareContext->HartSpecific[HartId]
+ ));
}
}
- DEBUG((DEBUG_INFO, "%a: Will jump to PEI Core in OpenSBI with \n", __FUNCTION__));
- DEBUG((DEBUG_INFO, " sbi_scratch = %x\n", SbiScratch));
- DEBUG((DEBUG_INFO, " sbi_platform = %x\n", SbiPlatform));
- DEBUG((DEBUG_INFO, " FirmwareContext = %x\n", FirmwareContext));
+ DEBUG ((DEBUG_INFO, "%a: Will jump to PEI Core in OpenSBI with \n", __FUNCTION__));
+ DEBUG ((DEBUG_INFO, " sbi_scratch = %x\n", SbiScratch));
+ DEBUG ((DEBUG_INFO, " sbi_platform = %x\n", SbiPlatform));
+ DEBUG ((DEBUG_INFO, " FirmwareContext = %x\n", FirmwareContext));
SbiScratch->next_arg1 = (unsigned long)FirmwareContext;
return 0;
}
+
/**
OpenSBI platform early init hook.
@@ -176,24 +184,27 @@ SecPostOpenSbiPlatformFinalInit (
**/
INT32
Edk2OpensbiPlatformEarlyInit (
- IN BOOLEAN ColdBoot
+ IN BOOLEAN ColdBoot
)
{
- INT32 ReturnCode;
+ INT32 ReturnCode;
- DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));
+ DEBUG ((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));
- if (platform_ops.early_init) {
- ReturnCode = platform_ops.early_init (ColdBoot);
- if (ReturnCode) {
- return ReturnCode;
- }
- }
- if (ColdBoot) {
- return SecPostOpenSbiPlatformEarlyInit(ColdBoot);
+ if (platform_ops.early_init) {
+ ReturnCode = platform_ops.early_init (ColdBoot);
+ if (ReturnCode) {
+ return ReturnCode;
}
- return 0;
+ }
+
+ if (ColdBoot) {
+ return SecPostOpenSbiPlatformEarlyInit (ColdBoot);
+ }
+
+ return 0;
}
+
/**
OpenSBI platform final init hook.
@@ -203,24 +214,27 @@ Edk2OpensbiPlatformEarlyInit (
**/
INT32
Edk2OpensbiPlatformFinalInit (
- IN BOOLEAN ColdBoot
+ IN BOOLEAN ColdBoot
)
{
- INT32 ReturnCode;
+ INT32 ReturnCode;
- DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));
+ DEBUG ((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));
- if (platform_ops.final_init) {
- ReturnCode = platform_ops.final_init (ColdBoot);
- if (ReturnCode) {
- return ReturnCode;
- }
+ if (platform_ops.final_init) {
+ ReturnCode = platform_ops.final_init (ColdBoot);
+ if (ReturnCode) {
+ return ReturnCode;
}
- if (ColdBoot) {
- return SecPostOpenSbiPlatformFinalInit(ColdBoot);
- }
- return 0;
+ }
+
+ if (ColdBoot) {
+ return SecPostOpenSbiPlatformFinalInit (ColdBoot);
+ }
+
+ return 0;
}
+
/**
OpenSBI platform early exit hook.
@@ -228,13 +242,13 @@ Edk2OpensbiPlatformFinalInit (
VOID
Edk2OpensbiPlatformEarlyExit (
VOID
-)
+ )
{
- DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));
+ DEBUG ((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));
- if (platform_ops.early_exit) {
- return platform_ops.early_exit ();
- }
+ if (platform_ops.early_exit) {
+ return platform_ops.early_exit ();
+ }
}
/**
@@ -246,11 +260,11 @@ Edk2OpensbiPlatformFinalExit (
VOID
)
{
- DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));
+ DEBUG ((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));
- if (platform_ops.early_exit) {
- return platform_ops.early_exit ();
- }
+ if (platform_ops.early_exit) {
+ return platform_ops.early_exit ();
+ }
}
/**
@@ -263,13 +277,14 @@ Edk2OpensbiPlatformFinalExit (
**/
INT32
Edk2OpensbiPlatforMMISACheckExtension (
- IN CHAR8 Extension
+ IN CHAR8 Extension
)
{
- if (platform_ops.misa_check_extension) {
- return platform_ops.misa_check_extension (Extension);
- }
- return 0;
+ if (platform_ops.misa_check_extension) {
+ return platform_ops.misa_check_extension (Extension);
+ }
+
+ return 0;
}
/**
@@ -281,12 +296,13 @@ Edk2OpensbiPlatforMMISACheckExtension (
INT32
Edk2OpensbiPlatforMMISAGetXLEN (
VOID
-)
+ )
{
- if (platform_ops.misa_get_xlen) {
- return platform_ops.misa_get_xlen ();
- }
- return 0;
+ if (platform_ops.misa_get_xlen) {
+ return platform_ops.misa_get_xlen ();
+ }
+
+ return 0;
}
/**
@@ -298,14 +314,15 @@ Edk2OpensbiPlatforMMISAGetXLEN (
INT32
Edk2OpensbiPlatformDomainsInit (
VOID
-)
+ )
{
- DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));
+ DEBUG ((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));
- if (platform_ops.domains_init) {
- return platform_ops.domains_init ();
- }
- return 0;
+ if (platform_ops.domains_init) {
+ return platform_ops.domains_init ();
+ }
+
+ return 0;
}
/**
@@ -317,14 +334,15 @@ Edk2OpensbiPlatformDomainsInit (
INT32
Edk2OpensbiPlatformSerialInit (
VOID
-)
+ )
{
- DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));
+ DEBUG ((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));
- if (platform_ops.console_init) {
- return platform_ops.console_init ();
- }
- return 0;
+ if (platform_ops.console_init) {
+ return platform_ops.console_init ();
+ }
+
+ return 0;
}
/**
@@ -336,15 +354,16 @@ Edk2OpensbiPlatformSerialInit (
**/
INT32
Edk2OpensbiPlatformIrqchipInit (
- IN BOOLEAN ColdBoot
-)
+ IN BOOLEAN ColdBoot
+ )
{
- DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));
+ DEBUG ((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));
- if (platform_ops.irqchip_init) {
- return platform_ops.irqchip_init (ColdBoot);
- }
- return 0;
+ if (platform_ops.irqchip_init) {
+ return platform_ops.irqchip_init (ColdBoot);
+ }
+
+ return 0;
}
/**
@@ -354,13 +373,13 @@ Edk2OpensbiPlatformIrqchipInit (
VOID
Edk2OpensbiPlatformIrqchipExit (
VOID
-)
+ )
{
- DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));
+ DEBUG ((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));
- if (platform_ops.irqchip_exit) {
- return platform_ops.irqchip_exit ();
- }
+ if (platform_ops.irqchip_exit) {
+ return platform_ops.irqchip_exit ();
+ }
}
/**
@@ -372,15 +391,16 @@ Edk2OpensbiPlatformIrqchipExit (
**/
INT32
Edk2OpensbiPlatformIpiInit (
- IN BOOLEAN ColdBoot
-)
+ IN BOOLEAN ColdBoot
+ )
{
- DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));
+ DEBUG ((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));
- if (platform_ops.ipi_init) {
- return platform_ops.ipi_init (ColdBoot);
- }
- return 0;
+ if (platform_ops.ipi_init) {
+ return platform_ops.ipi_init (ColdBoot);
+ }
+
+ return 0;
}
/**
@@ -390,13 +410,13 @@ Edk2OpensbiPlatformIpiInit (
VOID
Edk2OpensbiPlatformIpiExit (
VOID
-)
+ )
{
- DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));
+ DEBUG ((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));
- if (platform_ops.ipi_exit) {
- return platform_ops.ipi_exit ();
- }
+ if (platform_ops.ipi_exit) {
+ return platform_ops.ipi_exit ();
+ }
}
/**
@@ -408,14 +428,15 @@ Edk2OpensbiPlatformIpiExit (
UINT64
Edk2OpensbiPlatformTlbrFlushLimit (
VOID
-)
+ )
{
- DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));
+ DEBUG ((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));
- if (platform_ops.get_tlbr_flush_limit) {
- return platform_ops.get_tlbr_flush_limit ();
- }
- return 0;
+ if (platform_ops.get_tlbr_flush_limit) {
+ return platform_ops.get_tlbr_flush_limit ();
+ }
+
+ return 0;
}
/**
@@ -427,15 +448,16 @@ Edk2OpensbiPlatformTlbrFlushLimit (
**/
INT32
Edk2OpensbiPlatformTimerInit (
- IN BOOLEAN ColdBoot
-)
+ IN BOOLEAN ColdBoot
+ )
{
- DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));
+ DEBUG ((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));
- if (platform_ops.timer_init) {
- return platform_ops.timer_init (ColdBoot);
- }
- return 0;
+ if (platform_ops.timer_init) {
+ return platform_ops.timer_init (ColdBoot);
+ }
+
+ return 0;
}
/**
@@ -445,13 +467,13 @@ Edk2OpensbiPlatformTimerInit (
VOID
Edk2OpensbiPlatformTimerExit (
VOID
-)
+ )
{
- DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));
+ DEBUG ((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));
- if (platform_ops.timer_exit) {
- return platform_ops.timer_exit ();
- }
+ if (platform_ops.timer_exit) {
+ return platform_ops.timer_exit ();
+ }
}
/**
@@ -463,15 +485,16 @@ Edk2OpensbiPlatformTimerExit (
**/
INT32
Edk2OpensbiPlatformVendorExtCheck (
- IN long ExtId
-)
+ IN long ExtId
+ )
{
- DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));
+ DEBUG ((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));
- if (platform_ops.vendor_ext_check) {
- return platform_ops.vendor_ext_check (ExtId);
- }
- return 0;
+ if (platform_ops.vendor_ext_check) {
+ return platform_ops.vendor_ext_check (ExtId);
+ }
+
+ return 0;
}
/**
@@ -488,43 +511,44 @@ Edk2OpensbiPlatformVendorExtCheck (
**/
INT32
Edk2OpensbiPlatformVendorExtProvider (
- IN long ExtId,
- IN long FuncId,
- IN CONST struct sbi_trap_regs *Regs,
- IN unsigned long *OutValue,
- IN struct sbi_trap_info *OutTrap
-)
+ IN long ExtId,
+ IN long FuncId,
+ IN CONST struct sbi_trap_regs *Regs,
+ IN unsigned long *OutValue,
+ IN struct sbi_trap_info *OutTrap
+ )
{
- DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));
-
- if (platform_ops.vendor_ext_provider) {
- return platform_ops.vendor_ext_provider (
- ExtId,
- FuncId,
- Regs,
- OutValue,
- OutTrap
- );
- }
- return 0;
+ DEBUG ((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));
+
+ if (platform_ops.vendor_ext_provider) {
+ return platform_ops.vendor_ext_provider (
+ ExtId,
+ FuncId,
+ Regs,
+ OutValue,
+ OutTrap
+ );
+ }
+
+ return 0;
}
-CONST struct sbi_platform_operations Edk2OpensbiPlatformOps = {
- .early_init = Edk2OpensbiPlatformEarlyInit,
- .final_init = Edk2OpensbiPlatformFinalInit,
- .early_exit = Edk2OpensbiPlatformEarlyExit,
- .final_exit = Edk2OpensbiPlatformFinalExit,
- .misa_check_extension = Edk2OpensbiPlatforMMISACheckExtension,
- .misa_get_xlen = Edk2OpensbiPlatforMMISAGetXLEN,
- .domains_init = Edk2OpensbiPlatformDomainsInit,
- .console_init = Edk2OpensbiPlatformSerialInit,
- .irqchip_init = Edk2OpensbiPlatformIrqchipInit,
- .irqchip_exit = Edk2OpensbiPlatformIrqchipExit,
- .ipi_init = Edk2OpensbiPlatformIpiInit,
- .ipi_exit = Edk2OpensbiPlatformIpiExit,
- .get_tlbr_flush_limit = Edk2OpensbiPlatformTlbrFlushLimit,
- .timer_init = Edk2OpensbiPlatformTimerInit,
- .timer_exit = Edk2OpensbiPlatformTimerExit,
- .vendor_ext_check = Edk2OpensbiPlatformVendorExtCheck,
- .vendor_ext_provider = Edk2OpensbiPlatformVendorExtProvider,
+CONST struct sbi_platform_operations Edk2OpensbiPlatformOps = {
+ .early_init = Edk2OpensbiPlatformEarlyInit,
+ .final_init = Edk2OpensbiPlatformFinalInit,
+ .early_exit = Edk2OpensbiPlatformEarlyExit,
+ .final_exit = Edk2OpensbiPlatformFinalExit,
+ .misa_check_extension = Edk2OpensbiPlatforMMISACheckExtension,
+ .misa_get_xlen = Edk2OpensbiPlatforMMISAGetXLEN,
+ .domains_init = Edk2OpensbiPlatformDomainsInit,
+ .console_init = Edk2OpensbiPlatformSerialInit,
+ .irqchip_init = Edk2OpensbiPlatformIrqchipInit,
+ .irqchip_exit = Edk2OpensbiPlatformIrqchipExit,
+ .ipi_init = Edk2OpensbiPlatformIpiInit,
+ .ipi_exit = Edk2OpensbiPlatformIpiExit,
+ .get_tlbr_flush_limit = Edk2OpensbiPlatformTlbrFlushLimit,
+ .timer_init = Edk2OpensbiPlatformTimerInit,
+ .timer_exit = Edk2OpensbiPlatformTimerExit,
+ .vendor_ext_check = Edk2OpensbiPlatformVendorExtCheck,
+ .vendor_ext_provider = Edk2OpensbiPlatformVendorExtProvider,
};
diff --git a/Platform/RISC-V/PlatformPkg/Library/FirmwareContextProcessorSpecificLib/FirmwareContextProcessorSpecificLib.c b/Platform/RISC-V/PlatformPkg/Library/FirmwareContextProcessorSpecificLib/FirmwareContextProcessorSpecificLib.c
index c94f7881c2..7f8ef28019 100644
--- a/Platform/RISC-V/PlatformPkg/Library/FirmwareContextProcessorSpecificLib/FirmwareContextProcessorSpecificLib.c
+++ b/Platform/RISC-V/PlatformPkg/Library/FirmwareContextProcessorSpecificLib/FirmwareContextProcessorSpecificLib.c
@@ -40,13 +40,13 @@
EFI_STATUS
EFIAPI
CommonFirmwareContextHartSpecificInfo (
- EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC *FirmwareContextHartSpecific,
- EFI_GUID *ParentProcessorGuid,
- UINTN ParentProcessorUid,
- EFI_GUID *CoreGuid,
- UINTN HartId,
- BOOLEAN IsBootHart,
- RISC_V_PROCESSOR_SPECIFIC_HOB_DATA *ProcessorSpecificDataHob
+ EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC *FirmwareContextHartSpecific,
+ EFI_GUID *ParentProcessorGuid,
+ UINTN ParentProcessorUid,
+ EFI_GUID *CoreGuid,
+ UINTN HartId,
+ BOOLEAN IsBootHart,
+ RISC_V_PROCESSOR_SPECIFIC_HOB_DATA *ProcessorSpecificDataHob
)
{
//
@@ -55,28 +55,32 @@ CommonFirmwareContextHartSpecificInfo (
CopyGuid (&ProcessorSpecificDataHob->ParentProcessorGuid, ParentProcessorGuid);
ProcessorSpecificDataHob->ParentProcessorUid = ParentProcessorUid;
CopyGuid (&ProcessorSpecificDataHob->CoreGuid, CoreGuid);
- ProcessorSpecificDataHob->Context = NULL;
+ ProcessorSpecificDataHob->Context = NULL;
ProcessorSpecificDataHob->ProcessorSpecificData.Revision =
SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA_REVISION;
ProcessorSpecificDataHob->ProcessorSpecificData.Length =
sizeof (SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA);
ProcessorSpecificDataHob->ProcessorSpecificData.HartId.Value64_L = (UINT64)HartId;
ProcessorSpecificDataHob->ProcessorSpecificData.HartId.Value64_H = 0;
- ProcessorSpecificDataHob->ProcessorSpecificData.BootHartId = (UINT8)IsBootHart;
+ ProcessorSpecificDataHob->ProcessorSpecificData.BootHartId = (UINT8)IsBootHart;
ProcessorSpecificDataHob->ProcessorSpecificData.InstSetSupported =
FirmwareContextHartSpecific->IsaExtensionSupported;
ProcessorSpecificDataHob->ProcessorSpecificData.PrivilegeModeSupported =
SMBIOS_RISC_V_PSD_MACHINE_MODE_SUPPORTED;
if ((ProcessorSpecificDataHob->ProcessorSpecificData.InstSetSupported &
- RISC_V_ISA_SUPERVISOR_MODE_IMPLEMENTED) != 0) {
+ RISC_V_ISA_SUPERVISOR_MODE_IMPLEMENTED) != 0)
+ {
ProcessorSpecificDataHob->ProcessorSpecificData.PrivilegeModeSupported |=
SMBIOS_RISC_V_PSD_SUPERVISOR_MODE_SUPPORTED;
}
+
if ((ProcessorSpecificDataHob->ProcessorSpecificData.InstSetSupported &
- RISC_V_ISA_USER_MODE_IMPLEMENTED) != 0) {
+ RISC_V_ISA_USER_MODE_IMPLEMENTED) != 0)
+ {
ProcessorSpecificDataHob->ProcessorSpecificData.PrivilegeModeSupported |=
SMBIOS_RISC_V_PSD_USER_MODE_SUPPORTED;
}
+
ProcessorSpecificDataHob->ProcessorSpecificData.MachineVendorId.Value64_L =
FirmwareContextHartSpecific->MachineVendorId.Value64_L;
ProcessorSpecificDataHob->ProcessorSpecificData.MachineVendorId.Value64_H =
@@ -100,7 +104,7 @@ CommonFirmwareContextHartSpecificInfo (
VOID
EFIAPI
DebugPrintHartSpecificInfo (
- RISC_V_PROCESSOR_SPECIFIC_HOB_DATA *ProcessorSpecificDataHob
+ RISC_V_PROCESSOR_SPECIFIC_HOB_DATA *ProcessorSpecificDataHob
)
{
DEBUG ((DEBUG_INFO, " *HartId = 0x%x\n", ProcessorSpecificDataHob->ProcessorSpecificData.HartId.Value64_L));
@@ -108,7 +112,7 @@ DebugPrintHartSpecificInfo (
DEBUG ((DEBUG_INFO, " *PrivilegeModeSupported = 0x%x\n", ProcessorSpecificDataHob->ProcessorSpecificData.PrivilegeModeSupported));
DEBUG ((DEBUG_INFO, " *MModeExcepDelegation = 0x%x\n", ProcessorSpecificDataHob->ProcessorSpecificData.MModeExcepDelegation.Value64_L));
DEBUG ((DEBUG_INFO, " *MModeInterruptDelegation = 0x%x\n", ProcessorSpecificDataHob->ProcessorSpecificData.MModeInterruptDelegation.Value64_L));
- DEBUG ((DEBUG_INFO, " *HartXlen = 0x%x\n", ProcessorSpecificDataHob->ProcessorSpecificData.HartXlen ));
+ DEBUG ((DEBUG_INFO, " *HartXlen = 0x%x\n", ProcessorSpecificDataHob->ProcessorSpecificData.HartXlen));
DEBUG ((DEBUG_INFO, " *MachineModeXlen = 0x%x\n", ProcessorSpecificDataHob->ProcessorSpecificData.MachineModeXlen));
DEBUG ((DEBUG_INFO, " *SupervisorModeXlen = 0x%x\n", ProcessorSpecificDataHob->ProcessorSpecificData.SupervisorModeXlen));
DEBUG ((DEBUG_INFO, " *UserModeXlen = 0x%x\n", ProcessorSpecificDataHob->ProcessorSpecificData.UserModeXlen));
diff --git a/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/OpensbiPlatform.c b/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/OpensbiPlatform.c
index c62d235333..50188d939f 100644
--- a/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/OpensbiPlatform.c
+++ b/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/OpensbiPlatform.c
@@ -34,39 +34,45 @@
// SpecialPlatformArray and NumberOfSpecialPlatform are
// provided by RiscVSpecialPlatformLib library.
//
-extern const struct platform_override *special_platforms[];
-extern INTN NumberOfPlaformsInArray;
+extern const struct platform_override *special_platforms[];
+extern INTN NumberOfPlaformsInArray;
-static const struct platform_override *generic_plat = NULL;
-static const struct fdt_match *generic_plat_match = NULL;
+static const struct platform_override *generic_plat = NULL;
+static const struct fdt_match *generic_plat_match = NULL;
-static void fw_platform_lookup_special(void *fdt, int root_offset)
+static void
+fw_platform_lookup_special (
+ void *fdt,
+ int root_offset
+ )
{
- int pos, noff;
- const struct platform_override *plat;
- const struct fdt_match *match;
+ int pos, noff;
+ const struct platform_override *plat;
+ const struct fdt_match *match;
- if (special_platforms == NULL || NumberOfPlaformsInArray == 0) {
- return;
- }
+ if ((special_platforms == NULL) || (NumberOfPlaformsInArray == 0)) {
+ return;
+ }
for (pos = 0; pos < (int)NumberOfPlaformsInArray; pos++) {
plat = special_platforms[pos];
- if (!plat->match_table)
+ if (!plat->match_table) {
continue;
+ }
- noff = fdt_find_match(fdt, -1, plat->match_table, &match);
- if (noff < 0)
+ noff = fdt_find_match (fdt, -1, plat->match_table, &match);
+ if (noff < 0) {
continue;
+ }
- generic_plat = plat;
+ generic_plat = plat;
generic_plat_match = match;
break;
}
}
-extern struct sbi_platform platform;
-static u32 generic_hart_index2id[SBI_HARTMASK_MAX_BITS] = { 0 };
+extern struct sbi_platform platform;
+static u32 generic_hart_index2id[SBI_HARTMASK_MAX_BITS] = { 0 };
/*
* The fw_platform_init() function is called very early on the boot HART
@@ -81,39 +87,50 @@ static u32 generic_hart_index2id[SBI_HARTMASK_MAX_BITS] = { 0 };
* FDT is unchanged (or FDT is modified in-place) then fw_platform_init()
* can always return the original FDT location (i.e. 'arg1') unmodified.
*/
-unsigned long fw_platform_init(unsigned long arg0, unsigned long arg1,
- unsigned long arg2, unsigned long arg3,
- unsigned long arg4)
+unsigned long
+fw_platform_init (
+ unsigned long arg0,
+ unsigned long arg1,
+ unsigned long arg2,
+ unsigned long arg3,
+ unsigned long arg4
+ )
{
- const char *model;
- void *fdt = (void *)arg1;
- u32 hartid, hart_count = 0;
- int rc, root_offset, cpus_offset, cpu_offset, len;
+ const char *model;
+ void *fdt = (void *)arg1;
+ u32 hartid, hart_count = 0;
+ int rc, root_offset, cpus_offset, cpu_offset, len;
- root_offset = fdt_path_offset(fdt, "/");
- if (root_offset < 0)
+ root_offset = fdt_path_offset (fdt, "/");
+ if (root_offset < 0) {
goto fail;
+ }
- fw_platform_lookup_special(fdt, root_offset);
+ fw_platform_lookup_special (fdt, root_offset);
- model = fdt_getprop(fdt, root_offset, "model", &len);
- if (model)
- sbi_strncpy(platform.name, model, sizeof(platform.name));
+ model = fdt_getprop (fdt, root_offset, "model", &len);
+ if (model) {
+ sbi_strncpy (platform.name, model, sizeof (platform.name));
+ }
- if (generic_plat && generic_plat->features)
- platform.features = generic_plat->features(generic_plat_match);
+ if (generic_plat && generic_plat->features) {
+ platform.features = generic_plat->features (generic_plat_match);
+ }
- cpus_offset = fdt_path_offset(fdt, "/cpus");
- if (cpus_offset < 0)
+ cpus_offset = fdt_path_offset (fdt, "/cpus");
+ if (cpus_offset < 0) {
goto fail;
+ }
- fdt_for_each_subnode(cpu_offset, fdt, cpus_offset) {
- rc = fdt_parse_hart_id(fdt, cpu_offset, &hartid);
- if (rc)
+ fdt_for_each_subnode (cpu_offset, fdt, cpus_offset) {
+ rc = fdt_parse_hart_id (fdt, cpu_offset, &hartid);
+ if (rc) {
continue;
+ }
- if (SBI_HARTMASK_MAX_BITS <= hartid)
+ if (SBI_HARTMASK_MAX_BITS <= hartid) {
continue;
+ }
generic_hart_index2id[hart_count++] = hartid;
}
@@ -124,102 +141,130 @@ unsigned long fw_platform_init(unsigned long arg0, unsigned long arg1,
return arg1;
fail:
- while (1)
- wfi();
+ while (1) {
+ wfi ();
+ }
}
-static int generic_early_init(bool cold_boot)
+static int
+generic_early_init (
+ bool cold_boot
+ )
{
- int rc;
+ int rc;
if (generic_plat && generic_plat->early_init) {
- rc = generic_plat->early_init(cold_boot, generic_plat_match);
- if (rc)
+ rc = generic_plat->early_init (cold_boot, generic_plat_match);
+ if (rc) {
return rc;
+ }
}
- if (!cold_boot)
+ if (!cold_boot) {
return 0;
+ }
- return fdt_reset_init();
+ return fdt_reset_init ();
}
-static int generic_final_init(bool cold_boot)
+static int
+generic_final_init (
+ bool cold_boot
+ )
{
- void *fdt;
- int rc;
+ void *fdt;
+ int rc;
if (generic_plat && generic_plat->final_init) {
- rc = generic_plat->final_init(cold_boot, generic_plat_match);
- if (rc)
+ rc = generic_plat->final_init (cold_boot, generic_plat_match);
+ if (rc) {
return rc;
+ }
}
- if (!cold_boot)
+ if (!cold_boot) {
return 0;
+ }
- fdt = sbi_scratch_thishart_arg1_ptr();
+ fdt = sbi_scratch_thishart_arg1_ptr ();
- fdt_cpu_fixup(fdt);
- fdt_fixups(fdt);
- fdt_domain_fixup(fdt);
+ fdt_cpu_fixup (fdt);
+ fdt_fixups (fdt);
+ fdt_domain_fixup (fdt);
if (generic_plat && generic_plat->fdt_fixup) {
- rc = generic_plat->fdt_fixup(fdt, generic_plat_match);
- if (rc)
+ rc = generic_plat->fdt_fixup (fdt, generic_plat_match);
+ if (rc) {
return rc;
+ }
}
return 0;
}
-static void generic_early_exit(void)
+static void
+generic_early_exit (
+ void
+ )
{
- if (generic_plat && generic_plat->early_exit)
- generic_plat->early_exit(generic_plat_match);
+ if (generic_plat && generic_plat->early_exit) {
+ generic_plat->early_exit (generic_plat_match);
+ }
}
-static void generic_final_exit(void)
+static void
+generic_final_exit (
+ void
+ )
{
- if (generic_plat && generic_plat->final_exit)
- generic_plat->final_exit(generic_plat_match);
+ if (generic_plat && generic_plat->final_exit) {
+ generic_plat->final_exit (generic_plat_match);
+ }
}
-static int generic_domains_init(void)
+static int
+generic_domains_init (
+ void
+ )
{
- return fdt_domains_populate(sbi_scratch_thishart_arg1_ptr());
+ return fdt_domains_populate (sbi_scratch_thishart_arg1_ptr ());
}
-static u64 generic_tlbr_flush_limit(void)
+static u64
+generic_tlbr_flush_limit (
+ void
+ )
{
- if (generic_plat && generic_plat->tlbr_flush_limit)
- return generic_plat->tlbr_flush_limit(generic_plat_match);
+ if (generic_plat && generic_plat->tlbr_flush_limit) {
+ return generic_plat->tlbr_flush_limit (generic_plat_match);
+ }
+
return SBI_PLATFORM_TLB_RANGE_FLUSH_LIMIT_DEFAULT;
}
-const struct sbi_platform_operations platform_ops = {
- .early_init = generic_early_init,
- .final_init = generic_final_init,
- .early_exit = generic_early_exit,
- .final_exit = generic_final_exit,
- .domains_init = generic_domains_init,
- .console_init = fdt_serial_init,
- .irqchip_init = fdt_irqchip_init,
- .irqchip_exit = fdt_irqchip_exit,
- .ipi_init = fdt_ipi_init,
- .ipi_exit = fdt_ipi_exit,
- .get_tlbr_flush_limit = generic_tlbr_flush_limit,
- .timer_init = fdt_timer_init,
- .timer_exit = fdt_timer_exit,
+const struct sbi_platform_operations platform_ops = {
+ .early_init = generic_early_init,
+ .final_init = generic_final_init,
+ .early_exit = generic_early_exit,
+ .final_exit = generic_final_exit,
+ .domains_init = generic_domains_init,
+ .console_init = fdt_serial_init,
+ .irqchip_init = fdt_irqchip_init,
+ .irqchip_exit = fdt_irqchip_exit,
+ .ipi_init = fdt_ipi_init,
+ .ipi_exit = fdt_ipi_exit,
+ .get_tlbr_flush_limit = generic_tlbr_flush_limit,
+ .timer_init = fdt_timer_init,
+ .timer_exit = fdt_timer_exit,
};
-struct sbi_platform platform = {
- .opensbi_version = OPENSBI_VERSION,
- .platform_version = SBI_PLATFORM_VERSION(0x0, 0x01),
- .name = "Generic",
- .features = SBI_PLATFORM_DEFAULT_FEATURES,
- .hart_count = SBI_HARTMASK_MAX_BITS,
- .hart_index2id = generic_hart_index2id,
- .hart_stack_size = FixedPcdGet32(PcdOpenSbiStackSize), // The stack given by SEC for each hart
- .platform_ops_addr = (unsigned long)&platform_ops
+struct sbi_platform platform = {
+ .opensbi_version = OPENSBI_VERSION,
+ .platform_version = SBI_PLATFORM_VERSION (0x0, 0x01),
+ .name = "Generic",
+ .features = SBI_PLATFORM_DEFAULT_FEATURES,
+ .hart_count = SBI_HARTMASK_MAX_BITS,
+ .hart_index2id = generic_hart_index2id,
+ .hart_stack_size = FixedPcdGet32 (PcdOpenSbiStackSize), // The stack given by SEC for each hart
+ .platform_ops_addr = (unsigned long)&platform_ops
};
diff --git a/Platform/RISC-V/PlatformPkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.c b/Platform/RISC-V/PlatformPkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.c
index 50de969947..f7d6fe140e 100644
--- a/Platform/RISC-V/PlatformPkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.c
+++ b/Platform/RISC-V/PlatformPkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.c
@@ -8,7 +8,6 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
**/
-
#include <PiPei.h>
#include <IndustryStandard/RiscVOpensbi.h>
//
@@ -48,19 +47,19 @@ EFIAPI
_ModuleEntryPoint (
IN CONST EFI_SEC_PEI_HAND_OFF *SecCoreData,
IN CONST EFI_PEI_PPI_DESCRIPTOR *PpiList
-)
+ )
{
- EFI_STATUS Status;
- EFI_SEC_PEI_HAND_OFF *ThisSecCoreData;
- EFI_PEI_PPI_DESCRIPTOR *ThisPpiList;
- EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *FirmwareContext;
+ EFI_STATUS Status;
+ EFI_SEC_PEI_HAND_OFF *ThisSecCoreData;
+ EFI_PEI_PPI_DESCRIPTOR *ThisPpiList;
+ EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *FirmwareContext;
FirmwareContext = (EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *)PpiList;
SetFirmwareContextPointer (FirmwareContext);
FirmwareContext->BootHartId = (UINT64)SecCoreData;
ThisSecCoreData = (EFI_SEC_PEI_HAND_OFF *)FirmwareContext->SecPeiHandOffData;
- Status = GetPlatformPrePeiCorePpiDescriptor (&ThisPpiList);
+ Status = GetPlatformPrePeiCorePpiDescriptor (&ThisPpiList);
if (EFI_ERROR (Status)) {
ThisPpiList = NULL;
}
@@ -68,16 +67,15 @@ _ModuleEntryPoint (
//
// Invoke PEI Core entry point.
//
- ProcessModuleEntryPointList(ThisSecCoreData, ThisPpiList, NULL);
+ ProcessModuleEntryPointList (ThisSecCoreData, ThisPpiList, NULL);
//
// Should never return
//
- ASSERT(FALSE);
+ ASSERT (FALSE);
CpuDeadLoop ();
}
-
/**
Required by the EBC compiler and identical in functionality to _ModuleEntryPoint().
diff --git a/Platform/RISC-V/PlatformPkg/Library/PlatformBootManagerLib/PlatformBootManager.c b/Platform/RISC-V/PlatformPkg/Library/PlatformBootManagerLib/PlatformBootManager.c
index 9ad4ef17db..21667f4225 100644
--- a/Platform/RISC-V/PlatformPkg/Library/PlatformBootManagerLib/PlatformBootManager.c
+++ b/Platform/RISC-V/PlatformPkg/Library/PlatformBootManagerLib/PlatformBootManager.c
@@ -10,8 +10,9 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#include "PlatformBootManager.h"
-
-EFI_GUID mUefiShellFileGuid = { 0x7C04A583, 0x9E3E, 0x4f1c, {0xAD, 0x65, 0xE0, 0x52, 0x68, 0xD0, 0xB4, 0xD1}};
+EFI_GUID mUefiShellFileGuid = {
+ 0x7C04A583, 0x9E3E, 0x4f1c, { 0xAD, 0x65, 0xE0, 0x52, 0x68, 0xD0, 0xB4, 0xD1 }
+};
/**
Perform the platform diagnostic, such like test memory. OEM/IBV also
@@ -23,11 +24,11 @@ EFI_GUID mUefiShellFileGuid = { 0x7C04A583, 0x9E3E, 0x4f1c, {0xAD, 0x65, 0xE0, 0
**/
VOID
PlatformBootManagerDiagnostics (
- IN EXTENDMEM_COVERAGE_LEVEL MemoryTestLevel,
- IN BOOLEAN QuietBoot
+ IN EXTENDMEM_COVERAGE_LEVEL MemoryTestLevel,
+ IN BOOLEAN QuietBoot
)
{
- EFI_STATUS Status;
+ EFI_STATUS Status;
//
// Here we can decide if we need to show
@@ -36,7 +37,6 @@ PlatformBootManagerDiagnostics (
// from the graphic lib
//
if (QuietBoot) {
-
//
// Perform system diagnostic
//
@@ -65,12 +65,12 @@ PlatformBootManagerDiagnostics (
**/
INTN
PlatformFindLoadOption (
- IN CONST EFI_BOOT_MANAGER_LOAD_OPTION *Key,
- IN CONST EFI_BOOT_MANAGER_LOAD_OPTION *Array,
- IN UINTN Count
+ IN CONST EFI_BOOT_MANAGER_LOAD_OPTION *Key,
+ IN CONST EFI_BOOT_MANAGER_LOAD_OPTION *Array,
+ IN UINTN Count
)
{
- UINTN Index;
+ UINTN Index;
for (Index = 0; Index < Count; Index++) {
if ((Key->OptionType == Array[Index].OptionType) &&
@@ -78,8 +78,9 @@ PlatformFindLoadOption (
(StrCmp (Key->Description, Array[Index].Description) == 0) &&
(CompareMem (Key->FilePath, Array[Index].FilePath, GetDevicePathSize (Key->FilePath)) == 0) &&
(Key->OptionalDataSize == Array[Index].OptionalDataSize) &&
- (CompareMem (Key->OptionalData, Array[Index].OptionalData, Key->OptionalDataSize) == 0)) {
- return (INTN) Index;
+ (CompareMem (Key->OptionalData, Array[Index].OptionalData, Key->OptionalDataSize) == 0))
+ {
+ return (INTN)Index;
}
}
@@ -95,27 +96,27 @@ PlatformFindLoadOption (
**/
VOID
PlatformRegisterFvBootOption (
- EFI_GUID *FileGuid,
- CHAR16 *Description,
- UINT32 Attributes
+ EFI_GUID *FileGuid,
+ CHAR16 *Description,
+ UINT32 Attributes
)
{
- EFI_STATUS Status;
- UINTN OptionIndex;
- EFI_BOOT_MANAGER_LOAD_OPTION NewOption;
- EFI_BOOT_MANAGER_LOAD_OPTION *BootOptions;
- UINTN BootOptionCount;
- MEDIA_FW_VOL_FILEPATH_DEVICE_PATH FileNode;
- EFI_LOADED_IMAGE_PROTOCOL *LoadedImage;
- EFI_DEVICE_PATH_PROTOCOL *DevicePath;
-
- Status = gBS->HandleProtocol (gImageHandle, &gEfiLoadedImageProtocolGuid, (VOID **) &LoadedImage);
+ EFI_STATUS Status;
+ UINTN OptionIndex;
+ EFI_BOOT_MANAGER_LOAD_OPTION NewOption;
+ EFI_BOOT_MANAGER_LOAD_OPTION *BootOptions;
+ UINTN BootOptionCount;
+ MEDIA_FW_VOL_FILEPATH_DEVICE_PATH FileNode;
+ EFI_LOADED_IMAGE_PROTOCOL *LoadedImage;
+ EFI_DEVICE_PATH_PROTOCOL *DevicePath;
+
+ Status = gBS->HandleProtocol (gImageHandle, &gEfiLoadedImageProtocolGuid, (VOID **)&LoadedImage);
ASSERT_EFI_ERROR (Status);
EfiInitializeFwVolDevicepathNode (&FileNode, FileGuid);
DevicePath = AppendDevicePathNode (
DevicePathFromHandle (LoadedImage->DeviceHandle),
- (EFI_DEVICE_PATH_PROTOCOL *) &FileNode
+ (EFI_DEVICE_PATH_PROTOCOL *)&FileNode
);
Status = EfiBootManagerInitializeLoadOption (
@@ -134,9 +135,10 @@ PlatformRegisterFvBootOption (
OptionIndex = PlatformFindLoadOption (&NewOption, BootOptions, BootOptionCount);
if (OptionIndex == -1) {
- Status = EfiBootManagerAddLoadOptionVariable (&NewOption, (UINTN) -1);
+ Status = EfiBootManagerAddLoadOptionVariable (&NewOption, (UINTN)-1);
ASSERT_EFI_ERROR (Status);
}
+
EfiBootManagerFreeLoadOption (&NewOption);
EfiBootManagerFreeLoadOptions (BootOptions, BootOptionCount);
}
@@ -156,11 +158,11 @@ PlatformBootManagerBeforeConsole (
VOID
)
{
- UINTN Index;
- EFI_STATUS Status;
- EFI_INPUT_KEY Enter;
- EFI_INPUT_KEY F2;
- EFI_BOOT_MANAGER_LOAD_OPTION BootOption;
+ UINTN Index;
+ EFI_STATUS Status;
+ EFI_INPUT_KEY Enter;
+ EFI_INPUT_KEY F2;
+ EFI_BOOT_MANAGER_LOAD_OPTION BootOption;
//
// Signal EndOfDxe PI Event
@@ -200,7 +202,7 @@ PlatformBootManagerBeforeConsole (
F2.ScanCode = SCAN_F2;
F2.UnicodeChar = CHAR_NULL;
EfiBootManagerGetBootManagerMenu (&BootOption);
- EfiBootManagerAddKeyOptionVariable (NULL, (UINT16) BootOption.OptionNumber, 0, &F2, NULL);
+ EfiBootManagerAddKeyOptionVariable (NULL, (UINT16)BootOption.OptionNumber, 0, &F2, NULL);
//
// Register UEFI Shell
//
diff --git a/Platform/RISC-V/PlatformPkg/Library/PlatformBootManagerLib/PlatformData.c b/Platform/RISC-V/PlatformPkg/Library/PlatformBootManagerLib/PlatformData.c
index c1dbbf451e..4a79c6ca71 100644
--- a/Platform/RISC-V/PlatformPkg/Library/PlatformBootManagerLib/PlatformData.c
+++ b/Platform/RISC-V/PlatformPkg/Library/PlatformBootManagerLib/PlatformData.c
@@ -14,13 +14,15 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
//
// Platform specific serial device path
//
-SERIAL_CONSOLE_DEVICE_PATH gSerialConsoleDevicePath0 = {
+SERIAL_CONSOLE_DEVICE_PATH gSerialConsoleDevicePath0 = {
{
- { HARDWARE_DEVICE_PATH, HW_VENDOR_DP, { sizeof (VENDOR_DEVICE_PATH), 0} },
+ { HARDWARE_DEVICE_PATH, HW_VENDOR_DP, { sizeof (VENDOR_DEVICE_PATH), 0 }
+ },
EFI_SERIAL_DXE_GUID // Use the driver's GUID
},
{
- { MESSAGING_DEVICE_PATH, MSG_UART_DP, { sizeof (UART_DEVICE_PATH), 0} },
+ { MESSAGING_DEVICE_PATH, MSG_UART_DP, { sizeof (UART_DEVICE_PATH), 0 }
+ },
0, // Reserved
115200, // BaudRate
8, // DataBits
@@ -28,18 +30,20 @@ SERIAL_CONSOLE_DEVICE_PATH gSerialConsoleDevicePath0 = {
1 // StopBits
},
{
- { MESSAGING_DEVICE_PATH, MSG_VENDOR_DP, { sizeof (VENDOR_DEVICE_PATH), 0} },
+ { MESSAGING_DEVICE_PATH, MSG_VENDOR_DP, { sizeof (VENDOR_DEVICE_PATH), 0 }
+ },
DEVICE_PATH_MESSAGING_PC_ANSI
},
- { END_DEVICE_PATH_TYPE, END_ENTIRE_DEVICE_PATH_SUBTYPE, { sizeof (EFI_DEVICE_PATH_PROTOCOL), 0 } }
+ { END_DEVICE_PATH_TYPE, END_ENTIRE_DEVICE_PATH_SUBTYPE, { sizeof (EFI_DEVICE_PATH_PROTOCOL), 0 }
+ }
};
//
// Predefined platform default console device path
//
-PLATFORM_CONSOLE_CONNECT_ENTRY gPlatformConsole[] = {
+PLATFORM_CONSOLE_CONNECT_ENTRY gPlatformConsole[] = {
{
- (EFI_DEVICE_PATH_PROTOCOL *) &gSerialConsoleDevicePath0,
+ (EFI_DEVICE_PATH_PROTOCOL *)&gSerialConsoleDevicePath0,
CONSOLE_OUT | CONSOLE_IN
},
{
diff --git a/Platform/RISC-V/PlatformPkg/Library/PlatformMemoryTestLibNull/PlatformMemoryTestLibNull.c b/Platform/RISC-V/PlatformPkg/Library/PlatformMemoryTestLibNull/PlatformMemoryTestLibNull.c
index 9246070787..24cc01cb18 100644
--- a/Platform/RISC-V/PlatformPkg/Library/PlatformMemoryTestLibNull/PlatformMemoryTestLibNull.c
+++ b/Platform/RISC-V/PlatformPkg/Library/PlatformMemoryTestLibNull/PlatformMemoryTestLibNull.c
@@ -22,7 +22,7 @@
**/
EFI_STATUS
PlatformBootManagerMemoryTest (
- IN EXTENDMEM_COVERAGE_LEVEL Level
+ IN EXTENDMEM_COVERAGE_LEVEL Level
)
{
return EFI_SUCCESS;
diff --git a/Platform/RISC-V/PlatformPkg/Library/ResetSystemLib/ResetSystemLib.c b/Platform/RISC-V/PlatformPkg/Library/ResetSystemLib/ResetSystemLib.c
index 67e40151d1..524b0a6353 100644
--- a/Platform/RISC-V/PlatformPkg/Library/ResetSystemLib/ResetSystemLib.c
+++ b/Platform/RISC-V/PlatformPkg/Library/ResetSystemLib/ResetSystemLib.c
@@ -74,8 +74,8 @@ ResetShutdown (
VOID
EFIAPI
ResetPlatformSpecific (
- IN UINTN DataSize,
- IN VOID *ResetData
+ IN UINTN DataSize,
+ IN VOID *ResetData
)
{
//
@@ -99,30 +99,30 @@ ResetPlatformSpecific (
VOID
EFIAPI
ResetSystem (
- IN EFI_RESET_TYPE ResetType,
- IN EFI_STATUS ResetStatus,
- IN UINTN DataSize,
- IN VOID *ResetData OPTIONAL
+ IN EFI_RESET_TYPE ResetType,
+ IN EFI_STATUS ResetStatus,
+ IN UINTN DataSize,
+ IN VOID *ResetData OPTIONAL
)
{
switch (ResetType) {
- case EfiResetWarm:
- ResetWarm ();
- break;
+ case EfiResetWarm:
+ ResetWarm ();
+ break;
- case EfiResetCold:
- ResetCold ();
- break;
+ case EfiResetCold:
+ ResetCold ();
+ break;
- case EfiResetShutdown:
- ResetShutdown ();
- return;
+ case EfiResetShutdown:
+ ResetShutdown ();
+ return;
- case EfiResetPlatformSpecific:
- ResetPlatformSpecific (DataSize, ResetData);
- return;
+ case EfiResetPlatformSpecific:
+ ResetPlatformSpecific (DataSize, ResetData);
+ return;
- default:
- return;
+ default:
+ return;
}
}
diff --git a/Platform/RISC-V/PlatformPkg/Library/RiscVSpecialPlatformLibNull/RiscVSpecialPlatformLib.c b/Platform/RISC-V/PlatformPkg/Library/RiscVSpecialPlatformLibNull/RiscVSpecialPlatformLib.c
index 44f6ad6aed..77990c7350 100644
--- a/Platform/RISC-V/PlatformPkg/Library/RiscVSpecialPlatformLibNull/RiscVSpecialPlatformLib.c
+++ b/Platform/RISC-V/PlatformPkg/Library/RiscVSpecialPlatformLibNull/RiscVSpecialPlatformLib.c
@@ -14,7 +14,6 @@
//
#include <Library/RiscVSpecialPlatformLib.h>
-const struct platform_override *special_platforms = NULL;
-const struct platform_override *SpecialPlatformArray = NULL;
-INTN NumberOfPlaformsInArray = 0;
-
+const struct platform_override *special_platforms = NULL;
+const struct platform_override *SpecialPlatformArray = NULL;
+INTN NumberOfPlaformsInArray = 0;
diff --git a/Platform/RISC-V/PlatformPkg/Universal/FdtPeim/FdtPeim.c b/Platform/RISC-V/PlatformPkg/Universal/FdtPeim/FdtPeim.c
index 3487a5faf4..c56dc4e545 100644
--- a/Platform/RISC-V/PlatformPkg/Universal/FdtPeim/FdtPeim.c
+++ b/Platform/RISC-V/PlatformPkg/Universal/FdtPeim/FdtPeim.c
@@ -28,38 +28,40 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
EFI_STATUS
EFIAPI
PeimPassFdt (
- IN EFI_PEI_FILE_HANDLE FileHandle,
- IN CONST EFI_PEI_SERVICES **PeiServices
+ IN EFI_PEI_FILE_HANDLE FileHandle,
+ IN CONST EFI_PEI_SERVICES **PeiServices
)
{
- VOID *FdtPointer;
- VOID *Base;
- VOID *NewBase;
- UINTN FdtSize;
- UINTN FdtPages;
- UINT64 *FdtHobData;
- EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *FirmwareContext;
+ VOID *FdtPointer;
+ VOID *Base;
+ VOID *NewBase;
+ UINTN FdtSize;
+ UINTN FdtPages;
+ UINT64 *FdtHobData;
+ EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *FirmwareContext;
FirmwareContext = NULL;
GetFirmwareContextPointer (&FirmwareContext);
if (FirmwareContext == NULL) {
- DEBUG((DEBUG_ERROR, "%a: OpenSBI Firmware Context is NULL\n", __FUNCTION__));
+ DEBUG ((DEBUG_ERROR, "%a: OpenSBI Firmware Context is NULL\n", __FUNCTION__));
return EFI_UNSUPPORTED;
}
+
FdtPointer = (VOID *)FirmwareContext->FlattenedDeviceTree;
if (FdtPointer == NULL) {
- DEBUG((DEBUG_ERROR, "%a: Invalid FDT pointer\n", __FUNCTION__));
+ DEBUG ((DEBUG_ERROR, "%a: Invalid FDT pointer\n", __FUNCTION__));
return EFI_UNSUPPORTED;
}
- DEBUG((DEBUG_ERROR, "%a: Build FDT HOB - FDT at address: 0x%x \n", __FUNCTION__, FdtPointer));
+
+ DEBUG ((DEBUG_ERROR, "%a: Build FDT HOB - FDT at address: 0x%x \n", __FUNCTION__, FdtPointer));
Base = FdtPointer;
ASSERT (Base != NULL);
ASSERT (fdt_check_header (Base) == 0);
- FdtSize = fdt_totalsize (Base);
+ FdtSize = fdt_totalsize (Base);
FdtPages = EFI_SIZE_TO_PAGES (FdtSize);
- NewBase = AllocatePages (FdtPages);
+ NewBase = AllocatePages (FdtPages);
ASSERT (NewBase != NULL);
fdt_open_into (Base, NewBase, EFI_PAGES_TO_SIZE (FdtPages));
diff --git a/Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei/Fv.c b/Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei/Fv.c
index 060d66238d..28a454a72c 100644
--- a/Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei/Fv.c
+++ b/Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei/Fv.c
@@ -32,16 +32,19 @@ PeiFvInitialization (
// Let DXE know about the DXE FV
//
BuildFvHob (PcdGet32 (PcdRiscVDxeFvBase), PcdGet32 (PcdRiscVDxeFvSize));
- DEBUG ((DEBUG_INFO, "Platform builds DXE FV at %x, size %x.\n",
+ DEBUG ((
+ DEBUG_INFO,
+ "Platform builds DXE FV at %x, size %x.\n",
PcdGet32 (PcdRiscVDxeFvBase),
- PcdGet32 (PcdRiscVDxeFvSize)));
+ PcdGet32 (PcdRiscVDxeFvSize)
+ ));
//
// Let PEI know about the DXE FV so it can find the DXE Core
//
PeiServicesInstallFvInfoPpi (
NULL,
- (VOID *)(UINTN) PcdGet32 (PcdRiscVDxeFvBase),
+ (VOID *)(UINTN)PcdGet32 (PcdRiscVDxeFvBase),
PcdGet32 (PcdRiscVDxeFvSize),
NULL,
NULL
diff --git a/Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei/MemDetect.c b/Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei/MemDetect.c
index 9b52eb5189..3e579bfbf5 100644
--- a/Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei/MemDetect.c
+++ b/Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei/MemDetect.c
@@ -30,7 +30,6 @@ Module Name:
#include "Platform.h"
-
/**
Publish PEI core memory.
@@ -42,23 +41,23 @@ PublishPeiMemory (
VOID
)
{
- EFI_STATUS Status;
- EFI_PHYSICAL_ADDRESS MemoryBase;
- UINT64 MemorySize;
+ EFI_STATUS Status;
+ EFI_PHYSICAL_ADDRESS MemoryBase;
+ UINT64 MemorySize;
//
// TODO: This value should come from platform
// configuration or the memory sizing code.
//
MemoryBase = 0x80000000UL + 0x1000000UL;
- MemorySize = 0x40000000UL - 0x1000000UL; //1GB - 16MB
+ MemorySize = 0x40000000UL - 0x1000000UL; // 1GB - 16MB
- DEBUG((DEBUG_INFO, "%a: MemoryBase:0x%x MemorySize:%x\n", __FUNCTION__, MemoryBase, MemorySize));
+ DEBUG ((DEBUG_INFO, "%a: MemoryBase:0x%x MemorySize:%x\n", __FUNCTION__, MemoryBase, MemorySize));
//
// Publish this memory to the PEI Core
//
- Status = PublishSystemMemory(MemoryBase, MemorySize);
+ Status = PublishSystemMemory (MemoryBase, MemorySize);
ASSERT_EFI_ERROR (Status);
return Status;
@@ -77,5 +76,5 @@ InitializeRamRegions (
// TODO: This value should come from platform
// configuration or the memory sizing code.
//
- AddMemoryRangeHob(0x81000000UL, 0x81000000UL + 0x3F000000UL);
+ AddMemoryRangeHob (0x81000000UL, 0x81000000UL + 0x3F000000UL);
}
diff --git a/Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei/Platform.c b/Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei/Platform.c
index c28b2ed373..32dcdce668 100644
--- a/Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei/Platform.c
+++ b/Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei/Platform.c
@@ -32,7 +32,7 @@
#include "Platform.h"
-EFI_MEMORY_TYPE_INFORMATION mDefaultMemoryTypeInformation[] = {
+EFI_MEMORY_TYPE_INFORMATION mDefaultMemoryTypeInformation[] = {
{ EfiACPIMemoryNVS, 0x004 },
{ EfiACPIReclaimMemory, 0x008 },
{ EfiReservedMemoryType, 0x004 },
@@ -43,8 +43,7 @@ EFI_MEMORY_TYPE_INFORMATION mDefaultMemoryTypeInformation[] = {
{ EfiMaxMemoryType, 0x000 }
};
-
-EFI_PEI_PPI_DESCRIPTOR mPpiBootMode[] = {
+EFI_PEI_PPI_DESCRIPTOR mPpiBootMode[] = {
{
EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,
&gEfiPeiMasterBootModePpiGuid,
@@ -52,7 +51,7 @@ EFI_PEI_PPI_DESCRIPTOR mPpiBootMode[] = {
}
};
-STATIC EFI_BOOT_MODE mBootMode = BOOT_WITH_FULL_CONFIGURATION;
+STATIC EFI_BOOT_MODE mBootMode = BOOT_WITH_FULL_CONFIGURATION;
/**
Build memory map I/O range resource HOB using the
@@ -64,16 +63,16 @@ STATIC EFI_BOOT_MODE mBootMode = BOOT_WITH_FULL_CONFIGURATION;
**/
VOID
AddIoMemoryBaseSizeHob (
- EFI_PHYSICAL_ADDRESS MemoryBase,
- UINT64 MemorySize
+ EFI_PHYSICAL_ADDRESS MemoryBase,
+ UINT64 MemorySize
)
{
BuildResourceDescriptorHob (
EFI_RESOURCE_MEMORY_MAPPED_IO,
- EFI_RESOURCE_ATTRIBUTE_PRESENT |
- EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
- EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
- EFI_RESOURCE_ATTRIBUTE_TESTED,
+ EFI_RESOURCE_ATTRIBUTE_PRESENT |
+ EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
+ EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
+ EFI_RESOURCE_ATTRIBUTE_TESTED,
MemoryBase,
MemorySize
);
@@ -88,16 +87,16 @@ AddIoMemoryBaseSizeHob (
**/
VOID
AddReservedMemoryBaseSizeHob (
- EFI_PHYSICAL_ADDRESS MemoryBase,
- UINT64 MemorySize
+ EFI_PHYSICAL_ADDRESS MemoryBase,
+ UINT64 MemorySize
)
{
BuildResourceDescriptorHob (
EFI_RESOURCE_MEMORY_RESERVED,
- EFI_RESOURCE_ATTRIBUTE_PRESENT |
- EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
- EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
- EFI_RESOURCE_ATTRIBUTE_TESTED,
+ EFI_RESOURCE_ATTRIBUTE_PRESENT |
+ EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
+ EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
+ EFI_RESOURCE_ATTRIBUTE_TESTED,
MemoryBase,
MemorySize
);
@@ -113,8 +112,8 @@ AddReservedMemoryBaseSizeHob (
**/
VOID
AddIoMemoryRangeHob (
- EFI_PHYSICAL_ADDRESS MemoryBase,
- EFI_PHYSICAL_ADDRESS MemoryLimit
+ EFI_PHYSICAL_ADDRESS MemoryBase,
+ EFI_PHYSICAL_ADDRESS MemoryLimit
)
{
AddIoMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));
@@ -130,19 +129,19 @@ AddIoMemoryRangeHob (
**/
VOID
AddMemoryBaseSizeHob (
- EFI_PHYSICAL_ADDRESS MemoryBase,
- UINT64 MemorySize
+ EFI_PHYSICAL_ADDRESS MemoryBase,
+ UINT64 MemorySize
)
{
BuildResourceDescriptorHob (
EFI_RESOURCE_SYSTEM_MEMORY,
- EFI_RESOURCE_ATTRIBUTE_PRESENT |
- EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
- EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
- EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
- EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
- EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |
- EFI_RESOURCE_ATTRIBUTE_TESTED,
+ EFI_RESOURCE_ATTRIBUTE_PRESENT |
+ EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
+ EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
+ EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
+ EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
+ EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |
+ EFI_RESOURCE_ATTRIBUTE_TESTED,
MemoryBase,
MemorySize
);
@@ -158,8 +157,8 @@ AddMemoryBaseSizeHob (
**/
VOID
AddMemoryRangeHob (
- EFI_PHYSICAL_ADDRESS MemoryBase,
- EFI_PHYSICAL_ADDRESS MemoryLimit
+ EFI_PHYSICAL_ADDRESS MemoryBase,
+ EFI_PHYSICAL_ADDRESS MemoryLimit
)
{
AddMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));
@@ -175,18 +174,18 @@ AddMemoryRangeHob (
**/
VOID
AddUntestedMemoryBaseSizeHob (
- EFI_PHYSICAL_ADDRESS MemoryBase,
- UINT64 MemorySize
+ EFI_PHYSICAL_ADDRESS MemoryBase,
+ UINT64 MemorySize
)
{
BuildResourceDescriptorHob (
EFI_RESOURCE_SYSTEM_MEMORY,
- EFI_RESOURCE_ATTRIBUTE_PRESENT |
- EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
- EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
- EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
- EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
- EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE,
+ EFI_RESOURCE_ATTRIBUTE_PRESENT |
+ EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
+ EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
+ EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
+ EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
+ EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE,
MemoryBase,
MemorySize
);
@@ -202,8 +201,8 @@ AddUntestedMemoryBaseSizeHob (
**/
VOID
AddUntestedMemoryRangeHob (
- EFI_PHYSICAL_ADDRESS MemoryBase,
- EFI_PHYSICAL_ADDRESS MemoryLimit
+ EFI_PHYSICAL_ADDRESS MemoryBase,
+ EFI_PHYSICAL_ADDRESS MemoryLimit
)
{
AddUntestedMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));
@@ -238,7 +237,7 @@ MemMapInitialization (
BuildGuidDataHob (
&gEfiMemoryTypeInformationGuid,
mDefaultMemoryTypeInformation,
- sizeof(mDefaultMemoryTypeInformation)
+ sizeof (mDefaultMemoryTypeInformation)
);
//
@@ -280,7 +279,7 @@ CheckResumeFromS3 (
)
{
//
- //Platform implementation-specific
+ // Platform implementation-specific
//
return FALSE;
}
@@ -294,13 +293,14 @@ BootModeInitialization (
VOID
)
{
- EFI_STATUS Status;
+ EFI_STATUS Status;
if (CheckResumeFromS3) {
DEBUG ((DEBUG_INFO, "This is wake from S3\n"));
} else {
DEBUG ((DEBUG_INFO, "This is normal boot\n"));
}
+
Status = PeiServicesSetBootMode (mBootMode);
ASSERT_EFI_ERROR (Status);
@@ -317,7 +317,7 @@ BootModeInitialization (
EFI_STATUS
BuildCoreInformationHob (
VOID
-)
+ )
{
return BuildRiscVSmbiosHobs ();
}
@@ -338,7 +338,7 @@ InitializePlatform (
IN CONST EFI_PEI_SERVICES **PeiServices
)
{
- EFI_STATUS Status;
+ EFI_STATUS Status;
DEBUG ((DEBUG_INFO, "Platform PEIM Loaded\n"));
@@ -358,7 +358,8 @@ InitializePlatform (
Status = BuildCoreInformationHob ();
if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_ERROR, "Fail to build processor information HOB.\n"));
- ASSERT(FALSE);
+ ASSERT (FALSE);
}
+
return EFI_SUCCESS;
}
diff --git a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c
index 7a79eeec2d..c488f03a6a 100644
--- a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c
+++ b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c
@@ -1,7 +1,7 @@
/** @file
RISC-V SEC phase module.
- Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+ Copyright (c) 2021-2022, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -28,8 +28,8 @@
//
// Indicates the boot hart (PcdBootHartId) OpenSBI initialization is done.
//
-atomic_t BootHartDone = ATOMIC_INITIALIZER(0);
-atomic_t NonBootHartMessageLock = ATOMIC_INITIALIZER(0);
+atomic_t BootHartDone = ATOMIC_INITIALIZER (0);
+atomic_t NonBootHartMessageLock = ATOMIC_INITIALIZER (0);
/**
Locates a section within a series of sections
@@ -51,34 +51,35 @@ atomic_t NonBootHartMessageLock = ATOMIC_INITIALIZER(0);
**/
EFI_STATUS
FindFfsSectionInstance (
- IN VOID *Sections,
- IN UINTN SizeOfSections,
- IN EFI_SECTION_TYPE SectionType,
- IN UINTN Instance,
- OUT EFI_COMMON_SECTION_HEADER **FoundSection
+ IN VOID *Sections,
+ IN UINTN SizeOfSections,
+ IN EFI_SECTION_TYPE SectionType,
+ IN UINTN Instance,
+ OUT EFI_COMMON_SECTION_HEADER **FoundSection
)
{
- EFI_PHYSICAL_ADDRESS CurrentAddress;
- UINT32 Size;
- EFI_PHYSICAL_ADDRESS EndOfSections;
- EFI_COMMON_SECTION_HEADER *Section;
- EFI_PHYSICAL_ADDRESS EndOfSection;
+ EFI_PHYSICAL_ADDRESS CurrentAddress;
+ UINT32 Size;
+ EFI_PHYSICAL_ADDRESS EndOfSections;
+ EFI_COMMON_SECTION_HEADER *Section;
+ EFI_PHYSICAL_ADDRESS EndOfSection;
//
// Loop through the FFS file sections within the PEI Core FFS file
//
- EndOfSection = (EFI_PHYSICAL_ADDRESS)(UINTN) Sections;
+ EndOfSection = (EFI_PHYSICAL_ADDRESS)(UINTN)Sections;
EndOfSections = EndOfSection + SizeOfSections;
- for (;;) {
+ for ( ; ;) {
if (EndOfSection == EndOfSections) {
break;
}
+
CurrentAddress = (EndOfSection + 3) & ~(3ULL);
if (CurrentAddress >= EndOfSections) {
return EFI_VOLUME_CORRUPTED;
}
- Section = (EFI_COMMON_SECTION_HEADER*)(UINTN) CurrentAddress;
+ Section = (EFI_COMMON_SECTION_HEADER *)(UINTN)CurrentAddress;
Size = SECTION_SIZE (Section);
if (Size < sizeof (*Section)) {
@@ -122,10 +123,10 @@ FindFfsSectionInstance (
**/
EFI_STATUS
FindFfsSectionInSections (
- IN VOID *Sections,
- IN UINTN SizeOfSections,
- IN EFI_SECTION_TYPE SectionType,
- OUT EFI_COMMON_SECTION_HEADER **FoundSection
+ IN VOID *Sections,
+ IN UINTN SizeOfSections,
+ IN EFI_SECTION_TYPE SectionType,
+ OUT EFI_COMMON_SECTION_HEADER **FoundSection
)
{
return FindFfsSectionInstance (
@@ -153,18 +154,18 @@ FindFfsSectionInSections (
**/
EFI_STATUS
FindFfsFileAndSection (
- IN EFI_FIRMWARE_VOLUME_HEADER *Fv,
- IN EFI_FV_FILETYPE FileType,
- IN EFI_SECTION_TYPE SectionType,
- OUT EFI_COMMON_SECTION_HEADER **FoundSection
+ IN EFI_FIRMWARE_VOLUME_HEADER *Fv,
+ IN EFI_FV_FILETYPE FileType,
+ IN EFI_SECTION_TYPE SectionType,
+ OUT EFI_COMMON_SECTION_HEADER **FoundSection
)
{
- EFI_STATUS Status;
- EFI_PHYSICAL_ADDRESS CurrentAddress;
- EFI_PHYSICAL_ADDRESS EndOfFirmwareVolume;
- EFI_FFS_FILE_HEADER *File;
- UINT32 Size;
- EFI_PHYSICAL_ADDRESS EndOfFile;
+ EFI_STATUS Status;
+ EFI_PHYSICAL_ADDRESS CurrentAddress;
+ EFI_PHYSICAL_ADDRESS EndOfFirmwareVolume;
+ EFI_FFS_FILE_HEADER *File;
+ UINT32 Size;
+ EFI_PHYSICAL_ADDRESS EndOfFile;
DEBUG ((DEBUG_INFO, "%a: DBT FV at 0x%x\n", __FUNCTION__, Fv));
@@ -173,22 +174,21 @@ FindFfsFileAndSection (
return EFI_VOLUME_CORRUPTED;
}
- CurrentAddress = (EFI_PHYSICAL_ADDRESS)(UINTN) Fv;
+ CurrentAddress = (EFI_PHYSICAL_ADDRESS)(UINTN)Fv;
EndOfFirmwareVolume = CurrentAddress + Fv->FvLength;
//
// Loop through the FFS files in the Boot Firmware Volume
//
for (EndOfFile = CurrentAddress + Fv->HeaderLength; ; ) {
-
CurrentAddress = (EndOfFile + 7) & ~(7ULL);
if (CurrentAddress > EndOfFirmwareVolume) {
DEBUG ((DEBUG_ERROR, "%a: FV corrupted\n", __FUNCTION__));
return EFI_VOLUME_CORRUPTED;
}
- File = (EFI_FFS_FILE_HEADER*)(UINTN) CurrentAddress;
- Size = *(UINT32*) File->Size & 0xffffff;
+ File = (EFI_FFS_FILE_HEADER *)(UINTN)CurrentAddress;
+ Size = *(UINT32 *)File->Size & 0xffffff;
if (Size < (sizeof (*File) + sizeof (EFI_COMMON_SECTION_HEADER))) {
DEBUG ((DEBUG_ERROR, "%a: FV corrupted\n", __FUNCTION__));
return EFI_VOLUME_CORRUPTED;
@@ -209,19 +209,21 @@ FindFfsFileAndSection (
}
Status = FindFfsSectionInSections (
- (VOID*) (File + 1),
- (UINTN) EndOfFile - (UINTN) (File + 1),
+ (VOID *)(File + 1),
+ (UINTN)EndOfFile - (UINTN)(File + 1),
SectionType,
FoundSection
);
- if (!EFI_ERROR(Status)) {
+ if (!EFI_ERROR (Status)) {
DEBUG ((DEBUG_INFO, "%a: Get firmware file section\n", __FUNCTION__));
return Status;
}
+
if (Status == EFI_VOLUME_CORRUPTED) {
DEBUG ((DEBUG_ERROR, "%a: FV corrupted\n", __FUNCTION__));
return Status;
}
+
DEBUG ((DEBUG_INFO, "%a: Find next FFS\n", __FUNCTION__));
}
}
@@ -239,12 +241,12 @@ FindFfsFileAndSection (
**/
EFI_STATUS
FindPeiCoreImageBaseInFv (
- IN EFI_FIRMWARE_VOLUME_HEADER *Fv,
- OUT EFI_PHYSICAL_ADDRESS *PeiCoreImageBase
+ IN EFI_FIRMWARE_VOLUME_HEADER *Fv,
+ OUT EFI_PHYSICAL_ADDRESS *PeiCoreImageBase
)
{
- EFI_STATUS Status;
- EFI_COMMON_SECTION_HEADER *Section;
+ EFI_STATUS Status;
+ EFI_COMMON_SECTION_HEADER *Section;
Status = FindFfsFileAndSection (
Fv,
@@ -264,6 +266,7 @@ FindPeiCoreImageBaseInFv (
return Status;
}
}
+
DEBUG ((DEBUG_INFO, "%a: PeiCoreImageBase found\n", __FUNCTION__));
*PeiCoreImageBase = (EFI_PHYSICAL_ADDRESS)(UINTN)(Section + 1);
return EFI_SUCCESS;
@@ -278,8 +281,8 @@ FindPeiCoreImageBaseInFv (
**/
VOID
FindPeiCoreImageBase (
- IN OUT EFI_FIRMWARE_VOLUME_HEADER **BootFv,
- OUT EFI_PHYSICAL_ADDRESS *PeiCoreImageBase
+ IN OUT EFI_FIRMWARE_VOLUME_HEADER **BootFv,
+ OUT EFI_PHYSICAL_ADDRESS *PeiCoreImageBase
)
{
*PeiCoreImageBase = 0;
@@ -301,12 +304,12 @@ FindPeiCoreImageBase (
**/
VOID
FindAndReportEntryPoints (
- IN EFI_FIRMWARE_VOLUME_HEADER **BootFirmwareVolumePtr,
- OUT EFI_PEI_CORE_ENTRY_POINT *PeiCoreEntryPoint
+ IN EFI_FIRMWARE_VOLUME_HEADER **BootFirmwareVolumePtr,
+ OUT EFI_PEI_CORE_ENTRY_POINT *PeiCoreEntryPoint
)
{
- EFI_STATUS Status;
- EFI_PHYSICAL_ADDRESS PeiCoreImageBase;
+ EFI_STATUS Status;
+ EFI_PHYSICAL_ADDRESS PeiCoreImageBase;
DEBUG ((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));
@@ -314,10 +317,11 @@ FindAndReportEntryPoints (
//
// Find PEI Core entry point
//
- Status = PeCoffLoaderGetEntryPoint ((VOID *) (UINTN) PeiCoreImageBase, (VOID**) PeiCoreEntryPoint);
- if (EFI_ERROR(Status)) {
+ Status = PeCoffLoaderGetEntryPoint ((VOID *)(UINTN)PeiCoreImageBase, (VOID **)PeiCoreEntryPoint);
+ if (EFI_ERROR (Status)) {
*PeiCoreEntryPoint = 0;
}
+
DEBUG ((DEBUG_INFO, "%a: PeCoffLoaderGetEntryPoint success: %x\n", __FUNCTION__, *PeiCoreEntryPoint));
return;
@@ -341,36 +345,36 @@ FindAndReportEntryPoints (
**/
int
SbiEcallFirmwareHandler (
- IN unsigned long ExtId,
- IN unsigned long FuncId,
- IN CONST struct sbi_trap_regs *TrapRegs,
- OUT unsigned long *OutVal,
- OUT struct sbi_trap_info *OutTrap
+ IN unsigned long ExtId,
+ IN unsigned long FuncId,
+ IN CONST struct sbi_trap_regs *TrapRegs,
+ OUT unsigned long *OutVal,
+ OUT struct sbi_trap_info *OutTrap
)
{
- int Ret;
+ int Ret;
Ret = SBI_OK;
switch (FuncId) {
case SBI_EXT_FW_MSCRATCH_FUNC:
- *OutVal = (unsigned long) sbi_scratch_thishart_ptr();
+ *OutVal = (unsigned long)sbi_scratch_thishart_ptr ();
break;
case SBI_EXT_FW_MSCRATCH_HARTID_FUNC:
- *OutVal = (unsigned long) sbi_hartid_to_scratch (TrapRegs->a0);
+ *OutVal = (unsigned long)sbi_hartid_to_scratch (TrapRegs->a0);
break;
default:
Ret = SBI_ENOTSUPP;
DEBUG ((DEBUG_ERROR, "%a: Called SBI firmware ecall with invalid function ID\n", __FUNCTION__));
ASSERT (FALSE);
- };
+ }
return Ret;
}
-struct sbi_ecall_extension FirmwareEcall = {
+struct sbi_ecall_extension FirmwareEcall = {
.extid_start = SBI_EDK2_FW_EXT,
- .extid_end = SBI_EDK2_FW_EXT,
- .handle = SbiEcallFirmwareHandler,
+ .extid_end = SBI_EDK2_FW_EXT,
+ .handle = SbiEcallFirmwareHandler,
};
/** Register EDK2's SBI extension with OpenSBI
@@ -388,20 +392,20 @@ RegisterFirmwareSbiExtension (
VOID
)
{
- UINTN Ret;
- Ret = sbi_ecall_register_extension(&FirmwareEcall);
+ UINTN Ret;
+
+ Ret = sbi_ecall_register_extension (&FirmwareEcall);
if (Ret) {
//
// Only fails if the extension ID is invalid or already is registered.
//
DEBUG ((DEBUG_ERROR, "Failed to register SBI Firmware Extension for EDK2\n"));
- ASSERT(FALSE);
+ ASSERT (FALSE);
}
return EFI_SUCCESS;
}
-
/** Transion from SEC phase to PEI phase.
This function transits to S-mode PEI phase from M-mode SEC phase.
@@ -413,24 +417,24 @@ RegisterFirmwareSbiExtension (
VOID
EFIAPI
PeiCore (
- IN UINTN BootHartId,
- IN struct sbi_scratch *Scratch
+ IN UINTN BootHartId,
+ IN struct sbi_scratch *Scratch
)
{
- EFI_SEC_PEI_HAND_OFF SecCoreData;
- EFI_PEI_CORE_ENTRY_POINT PeiCoreEntryPoint;
- EFI_FIRMWARE_VOLUME_HEADER *BootFv;
- EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT FirmwareContext;
- struct sbi_platform *ThisSbiPlatform;
+ EFI_SEC_PEI_HAND_OFF SecCoreData;
+ EFI_PEI_CORE_ENTRY_POINT PeiCoreEntryPoint;
+ EFI_FIRMWARE_VOLUME_HEADER *BootFv;
+ EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT FirmwareContext;
+ struct sbi_platform *ThisSbiPlatform;
- BootFv = (EFI_FIRMWARE_VOLUME_HEADER *)FixedPcdGet32(PcdRiscVPeiFvBase);
+ BootFv = (EFI_FIRMWARE_VOLUME_HEADER *)FixedPcdGet32 (PcdRiscVPeiFvBase);
FindAndReportEntryPoints (&BootFv, &PeiCoreEntryPoint);
- SecCoreData.DataSize = sizeof(EFI_SEC_PEI_HAND_OFF);
+ SecCoreData.DataSize = sizeof (EFI_SEC_PEI_HAND_OFF);
SecCoreData.BootFirmwareVolumeBase = BootFv;
- SecCoreData.BootFirmwareVolumeSize = (UINTN) BootFv->FvLength;
- SecCoreData.TemporaryRamBase = (VOID*)(UINT64) FixedPcdGet32(PcdTemporaryRamBase);
- SecCoreData.TemporaryRamSize = (UINTN) FixedPcdGet32(PcdTemporaryRamSize);
+ SecCoreData.BootFirmwareVolumeSize = (UINTN)BootFv->FvLength;
+ SecCoreData.TemporaryRamBase = (VOID *)(UINT64)FixedPcdGet32 (PcdTemporaryRamBase);
+ SecCoreData.TemporaryRamSize = (UINTN)FixedPcdGet32 (PcdTemporaryRamSize);
SecCoreData.PeiTemporaryRamBase = SecCoreData.TemporaryRamBase;
SecCoreData.PeiTemporaryRamSize = SecCoreData.TemporaryRamSize >> 1;
SecCoreData.StackBase = (UINT8 *)SecCoreData.TemporaryRamBase + (SecCoreData.TemporaryRamSize >> 1);
@@ -442,21 +446,26 @@ PeiCore (
// temporary RAM migration.
//
ZeroMem ((VOID *)&FirmwareContext, sizeof (EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT));
- ThisSbiPlatform = (struct sbi_platform *)sbi_platform_ptr(Scratch);
+ ThisSbiPlatform = (struct sbi_platform *)sbi_platform_ptr (Scratch);
if (ThisSbiPlatform->opensbi_version > OPENSBI_VERSION) {
- DEBUG ((DEBUG_ERROR, "%a: OpenSBI platform table version 0x%x is newer than OpenSBI version 0x%x.\n"
- "There maybe be some backward compatable issues.\n",
- __FUNCTION__,
- ThisSbiPlatform->opensbi_version,
- OPENSBI_VERSION
- ));
- ASSERT(FALSE);
+ DEBUG ((
+ DEBUG_ERROR,
+ "%a: OpenSBI platform table version 0x%x is newer than OpenSBI version 0x%x.\n"
+ "There maybe be some backward compatable issues.\n",
+ __FUNCTION__,
+ ThisSbiPlatform->opensbi_version,
+ OPENSBI_VERSION
+ ));
+ ASSERT (FALSE);
}
- DEBUG ((DEBUG_INFO, "%a: OpenSBI platform table at address: 0x%x\nFirmware Context is located at 0x%x\n",
- __FUNCTION__,
- ThisSbiPlatform,
- &FirmwareContext
- ));
+
+ DEBUG ((
+ DEBUG_INFO,
+ "%a: OpenSBI platform table at address: 0x%x\nFirmware Context is located at 0x%x\n",
+ __FUNCTION__,
+ ThisSbiPlatform,
+ &FirmwareContext
+ ));
ThisSbiPlatform->firmware_context = (unsigned long)&FirmwareContext;
//
@@ -481,7 +490,7 @@ PeiCore (
Scratch->next_addr = (UINTN)(PeiCoreEntryPoint);
Scratch->next_mode = PRV_S;
DEBUG ((DEBUG_INFO, "%a: Initializing OpenSBI library for booting hart %d\n", __FUNCTION__, BootHartId));
- sbi_init(Scratch);
+ sbi_init (Scratch);
}
/**
@@ -498,8 +507,8 @@ PeiCore (
VOID
EFIAPI
LaunchPeiCore (
- IN UINTN ThisHartId,
- IN struct sbi_scratch *Scratch
+ IN UINTN ThisHartId,
+ IN struct sbi_scratch *Scratch
)
{
RegisterFirmwareSbiExtension ();
@@ -522,14 +531,14 @@ LaunchPeiCore (
VOID
EFIAPI
RiscVOpenSbiHartSwitchMode (
- IN UINTN FuncArg0,
- IN UINTN FuncArg1,
- IN UINTN NextAddr,
- IN UINTN NextMode,
- IN BOOLEAN NextVirt
+ IN UINTN FuncArg0,
+ IN UINTN FuncArg1,
+ IN UINTN NextAddr,
+ IN UINTN NextMode,
+ IN BOOLEAN NextVirt
)
{
- sbi_hart_switch_mode(FuncArg0, FuncArg1, NextAddr, NextMode, NextVirt);
+ sbi_hart_switch_mode (FuncArg0, FuncArg1, NextAddr, NextMode, NextVirt);
}
/**
@@ -543,34 +552,37 @@ GetDeviceTreeAddress (
VOID
)
{
- EFI_STATUS Status;
- EFI_COMMON_SECTION_HEADER *FoundSection;
+ EFI_STATUS Status;
+ EFI_COMMON_SECTION_HEADER *FoundSection;
if (FixedPcdGet32 (PcdDeviceTreeAddress)) {
- DEBUG ((DEBUG_INFO, "Use fixed address of DBT from PcdDeviceTreeAddress 0x%x 0x%x.\n", FixedPcdGet32 (PcdDeviceTreeAddress), *((unsigned long *)FixedPcdGet32 (PcdDeviceTreeAddress))));
- //
- // Device tree address is pointed by PcdDeviceTreeAddress.
- //
- return (VOID *)*((unsigned long *)FixedPcdGet32 (PcdDeviceTreeAddress));
+ DEBUG ((DEBUG_INFO, "Use fixed address of DBT from PcdDeviceTreeAddress 0x%x 0x%x.\n", FixedPcdGet32 (PcdDeviceTreeAddress), *((unsigned long *)FixedPcdGet32 (PcdDeviceTreeAddress))));
+ //
+ // Device tree address is pointed by PcdDeviceTreeAddress.
+ //
+ return (VOID *)*((unsigned long *)FixedPcdGet32 (PcdDeviceTreeAddress));
} else if (FixedPcdGet32 (PcdRiscVDtbFvBase)) {
- DEBUG ((DEBUG_INFO, "Use DBT FV\n"));
- Status = FindFfsFileAndSection (
- (EFI_FIRMWARE_VOLUME_HEADER *)FixedPcdGet32 (PcdRiscVDtbFvBase),
- EFI_FV_FILETYPE_FREEFORM,
- EFI_SECTION_RAW,
- &FoundSection
- );
- if (EFI_ERROR(Status)) {
- return NULL;
- }
- FoundSection ++;
- return (VOID *)FoundSection;
+ DEBUG ((DEBUG_INFO, "Use DBT FV\n"));
+ Status = FindFfsFileAndSection (
+ (EFI_FIRMWARE_VOLUME_HEADER *)FixedPcdGet32 (PcdRiscVDtbFvBase),
+ EFI_FV_FILETYPE_FREEFORM,
+ EFI_SECTION_RAW,
+ &FoundSection
+ );
+ if (EFI_ERROR (Status)) {
+ return NULL;
+ }
+
+ FoundSection++;
+ return (VOID *)FoundSection;
} else {
- DEBUG ((DEBUG_ERROR, "Must use DTB either from memory or compiled in FW. PCDs configured incorrectly.\n"));
- ASSERT (FALSE);
+ DEBUG ((DEBUG_ERROR, "Must use DTB either from memory or compiled in FW. PCDs configured incorrectly.\n"));
+ ASSERT (FALSE);
}
+
return NULL;
}
+
/**
Overwrite hart_index2id array if platform would like to use the
bootable harts other than those declared in Device Tree
@@ -580,21 +592,22 @@ GetDeviceTreeAddress (
**/
VOID
Edk2PlatformHartIndex2Id (
- IN struct sbi_platform *SbiPlatform
+ IN struct sbi_platform *SbiPlatform
)
{
- UINT32 Index;
- UINT32 *HartIndexToId;
- UINT32 BootableHartCount;
- UINT8 *PlatformHartIndex2IdArray;
+ UINT32 Index;
+ UINT32 *HartIndexToId;
+ UINT32 BootableHartCount;
+ UINT8 *PlatformHartIndex2IdArray;
- BootableHartCount = FixedPcdGet32(PcdBootableHartNumber);
+ BootableHartCount = FixedPcdGet32 (PcdBootableHartNumber);
if (BootableHartCount != 0) {
- HartIndexToId = (UINT32 *)SbiPlatform->hart_index2id;
+ HartIndexToId = (UINT32 *)SbiPlatform->hart_index2id;
PlatformHartIndex2IdArray = (UINT8 *)FixedPcdGetPtr (PcdBootableHartIndexToId);
for (Index = 0; Index < BootableHartCount; Index++) {
*(HartIndexToId + Index) = (UINT32)(*(PlatformHartIndex2IdArray + Index));
}
+
SbiPlatform->hart_count = BootableHartCount;
}
}
@@ -631,51 +644,53 @@ Edk2PlatformHartIndex2Id (
**/
VOID
EFIAPI
-SecCoreStartUpWithStack(
- IN UINTN HartId,
- IN struct sbi_scratch *Scratch
+SecCoreStartUpWithStack (
+ IN UINTN HartId,
+ IN struct sbi_scratch *Scratch
)
{
- UINT32 HardIndex;
- UINT64 BootHartDoneSbiInit;
- UINT64 NonBootHartMessageLockValue;
- struct sbi_platform *ThisSbiPlatform;
- EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC *HartFirmwareContext;
+ UINT32 HardIndex;
+ UINT64 BootHartDoneSbiInit;
+ UINT64 NonBootHartMessageLockValue;
+ struct sbi_platform *ThisSbiPlatform;
+ EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC *HartFirmwareContext;
- //DEBUG ((DEBUG_INFO, "HART ID: 0x%x enter SecCoreStartUpWithStack\n", HartId));
+ // DEBUG ((DEBUG_INFO, "HART ID: 0x%x enter SecCoreStartUpWithStack\n", HartId));
//
// Setup EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC for each hart.
//
- HartFirmwareContext = (EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC *)((UINT8 *)Scratch - FIRMWARE_CONTEXT_HART_SPECIFIC_SIZE);
- HartFirmwareContext->IsaExtensionSupported = RiscVReadMachineIsa ();
+ HartFirmwareContext = (EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC *)((UINT8 *)Scratch - FIRMWARE_CONTEXT_HART_SPECIFIC_SIZE);
+ HartFirmwareContext->IsaExtensionSupported = RiscVReadMachineIsa ();
HartFirmwareContext->MachineVendorId.Value64_L = RiscVReadMachineVendorId ();
HartFirmwareContext->MachineVendorId.Value64_H = 0;
- HartFirmwareContext->MachineArchId.Value64_L = RiscVReadMachineArchitectureId ();
- HartFirmwareContext->MachineArchId.Value64_H = 0;
- HartFirmwareContext->MachineImplId.Value64_L = RiscVReadMachineImplementId ();
- HartFirmwareContext->MachineImplId.Value64_H = 0;
- HartFirmwareContext->HartSwitchMode = RiscVOpenSbiHartSwitchMode;
+ HartFirmwareContext->MachineArchId.Value64_L = RiscVReadMachineArchitectureId ();
+ HartFirmwareContext->MachineArchId.Value64_H = 0;
+ HartFirmwareContext->MachineImplId.Value64_L = RiscVReadMachineImplementId ();
+ HartFirmwareContext->MachineImplId.Value64_H = 0;
+ HartFirmwareContext->HartSwitchMode = RiscVOpenSbiHartSwitchMode;
//
// Hook platform_ops with EDK2 one. Thus we can have interface
// call out to OEM EDK2 platform code in M-mode before switching
// to S-mode in opensbi init.
//
- ThisSbiPlatform = (struct sbi_platform *)sbi_platform_ptr(Scratch);
+ ThisSbiPlatform = (struct sbi_platform *)sbi_platform_ptr (Scratch);
ThisSbiPlatform->platform_ops_addr = (unsigned long)&Edk2OpensbiPlatformOps;
- Scratch->next_arg1 = (unsigned long)GetDeviceTreeAddress ();
- if (HartId == FixedPcdGet32(PcdBootHartId)) {
+ Scratch->next_arg1 = (unsigned long)GetDeviceTreeAddress ();
+ if (HartId == FixedPcdGet32 (PcdBootHartId)) {
if (Scratch->next_arg1 == (unsigned long)NULL) {
DEBUG ((DEBUG_ERROR, "Platform Device Tree is not found on boot hart\n"));
ASSERT (FALSE);
}
+
DEBUG ((DEBUG_INFO, "Device Tree at 0x%x\n", Scratch->next_arg1));
DEBUG ((DEBUG_INFO, "HART number: 0x%x\n", ThisSbiPlatform->hart_count));
DEBUG ((DEBUG_INFO, "HART index to HART ID:\n"));
- for (HardIndex = 0; HardIndex < ThisSbiPlatform->hart_count; HardIndex ++) {
- DEBUG ((DEBUG_INFO, " Index: %d -> Hard ID: %x\n", HardIndex, ThisSbiPlatform->hart_index2id [HardIndex]));
+ for (HardIndex = 0; HardIndex < ThisSbiPlatform->hart_count; HardIndex++) {
+ DEBUG ((DEBUG_INFO, " Index: %d -> Hard ID: %x\n", HardIndex, ThisSbiPlatform->hart_index2id[HardIndex]));
}
+
LaunchPeiCore (HartId, Scratch);
}
@@ -693,25 +708,26 @@ SecCoreStartUpWithStack(
CpuPause ();
} while (BootHartDoneSbiInit != (UINT64)TRUE);
- NonBootHartMessageLockValue = atomic_xchg(&NonBootHartMessageLock, TRUE);
+ NonBootHartMessageLockValue = atomic_xchg (&NonBootHartMessageLock, TRUE);
while (NonBootHartMessageLockValue == TRUE) {
CpuPause ();
CpuPause ();
CpuPause ();
- NonBootHartMessageLockValue = atomic_xchg(&NonBootHartMessageLock, TRUE);
- };
- DEBUG((DEBUG_INFO, "%a: Non boot hart %d initialization.\n", __FUNCTION__, HartId));
+ NonBootHartMessageLockValue = atomic_xchg (&NonBootHartMessageLock, TRUE);
+ }
+
+ DEBUG ((DEBUG_INFO, "%a: Non boot hart %d initialization.\n", __FUNCTION__, HartId));
if (Scratch->next_arg1 == (unsigned long)NULL) {
DEBUG ((DEBUG_ERROR, "Platform Device Tree is not found\n"));
ASSERT (FALSE);
}
- DEBUG((DEBUG_INFO, "%a: Non boot hart %d DTB is at 0x%x.\n", __FUNCTION__, HartId, Scratch->next_arg1));
- NonBootHartMessageLockValue = atomic_xchg(&NonBootHartMessageLock, FALSE);
+
+ DEBUG ((DEBUG_INFO, "%a: Non boot hart %d DTB is at 0x%x.\n", __FUNCTION__, HartId, Scratch->next_arg1));
+ NonBootHartMessageLockValue = atomic_xchg (&NonBootHartMessageLock, FALSE);
//
// Non boot hart wiil be halted waiting for SBI_HART_STARTING.
// Use HSM ecall to start non boot hart (SBI_EXT_HSM_HART_START) later on,
//
Scratch->next_mode = PRV_S;
- sbi_init(Scratch);
+ sbi_init (Scratch);
}
-
--
2.31.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* [edk2-platforms][PATCH V2 09/14] RISC-V/ProcessorPkg: Address Core CI ECC errors.
2022-01-22 6:53 [edk2-platforms][PATCH V2 00/14] Address edk2 Core CI issues Abner Chang
` (7 preceding siblings ...)
2022-01-22 6:53 ` [edk2-platforms][PATCH V2 08/14] RISC-V/PlatformPkg: Address Core CI Uncrustify errors Abner Chang
@ 2022-01-22 6:53 ` Abner Chang
2022-01-22 6:53 ` [edk2-platforms][PATCH V2 10/14] RISC-V/ProcessorPkg: Address Core CI library header check errors Abner Chang
` (5 subsequent siblings)
14 siblings, 0 replies; 16+ messages in thread
From: Abner Chang @ 2022-01-22 6:53 UTC (permalink / raw)
To: devel; +Cc: abner.chang, Daniel Schaefer, Sunil V L
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Cc: Daniel Schaefer <daniel.schaefer@hpe.com>
Cc: Sunil V L <sunilvl@ventanamicro.com>
---
.../RISC-V/ProcessorPkg/RiscVProcessorPkg.dec | 2 ++
.../RISC-V/ProcessorPkg/RiscVProcessorPkg.dsc | 4 ++--
.../RiscVFirmwareContextSbiLib.inf | 2 +-
.../Include/Library/MachineModeTimerLib.h | 15 +++++++++++++
.../Include/Library/RiscVPlatformTimerLib.h | 21 +++++++++++++++++++
.../ProcessorPkg/Include/OpensbiTypes.h | 6 +++---
.../Include/ProcessorSpecificHobData.h | 8 +++----
.../CpuExceptionHandlerLib.h | 2 +-
.../Universal/SmbiosDxe/RiscVSmbiosDxe.c | 12 +++++------
.../RISC-V/ProcessorPkg/RiscVProcessorPkg.uni | 18 +++++++++++++++-
10 files changed, 72 insertions(+), 18 deletions(-)
create mode 100644 Silicon/RISC-V/ProcessorPkg/Include/Library/MachineModeTimerLib.h
create mode 100644 Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVPlatformTimerLib.h
diff --git a/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec b/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec
index 9c8b57cce3..045fc55212 100644
--- a/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec
+++ b/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec
@@ -26,6 +26,8 @@
RiscVCpuLib|Include/Library/RiscVCpuLib.h
RiscVEdk2SbiLib|Include/Library/RiscVEdk2SbiLib.h
RiscVFirmwareContextLib|Include/Library/RiscVFirmwareContextLib.h
+ RiscVPlatformTimerLib|Include/Library/RiscVPlatformTimerLib.h
+ MachineModeTimerLib|Include/Library/MachineModeTimerLib.h
[Guids]
gUefiRiscVPkgTokenSpaceGuid = { 0x4261e9c8, 0x52c0, 0x4b34, { 0x85, 0x3d, 0x48, 0x46, 0xea, 0xd3, 0xb7, 0x2c}}
diff --git a/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dsc b/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dsc
index 563b9e7088..0591cd6a6c 100644
--- a/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dsc
+++ b/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dsc
@@ -1,11 +1,11 @@
-#/** @file
+## @file
# RISC-V processor package.
#
# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
-#**/
+#
################################################################################
#
diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSbiLib/RiscVFirmwareContextSbiLib.inf b/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSbiLib/RiscVFirmwareContextSbiLib.inf
index 168b705453..0edf781149 100644
--- a/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSbiLib/RiscVFirmwareContextSbiLib.inf
+++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSbiLib/RiscVFirmwareContextSbiLib.inf
@@ -12,7 +12,7 @@
[Defines]
INF_VERSION = 0x0001001b
BASE_NAME = RiscVFirmwareContextSbiLib
- FILE_GUID = 3709E048-6794-427A-B728-BFE3FFD6D461
+ FILE_GUID = 308117C0-400A-79C5-6ED4-AB9763A202E5
MODULE_TYPE = PEIM
VERSION_STRING = 1.0
LIBRARY_CLASS = RiscVFirmwareContextLib|PEIM PEI_CORE
diff --git a/Silicon/RISC-V/ProcessorPkg/Include/Library/MachineModeTimerLib.h b/Silicon/RISC-V/ProcessorPkg/Include/Library/MachineModeTimerLib.h
new file mode 100644
index 0000000000..a27391cca3
--- /dev/null
+++ b/Silicon/RISC-V/ProcessorPkg/Include/Library/MachineModeTimerLib.h
@@ -0,0 +1,15 @@
+/** @file
+ RISC-V Machine Mode Timer Library Definition
+
+ Copyright (c) 2022, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef MACHINE_MODE_TIMER_LIB_H_
+#define MACHINE_MODE_TIMER_LIB_H_
+
+UINT64
+RiscVReadMachineTimerInterface (VOID);
+
+#endif
diff --git a/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVPlatformTimerLib.h b/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVPlatformTimerLib.h
new file mode 100644
index 0000000000..dcd8734eb5
--- /dev/null
+++ b/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVPlatformTimerLib.h
@@ -0,0 +1,21 @@
+/** @file
+ RISC-V Platform Timer library definitions.
+
+ Copyright (c) 2022, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef RISCV_PLATFORM_TIMER_LIB_H_
+#define RISCV_PLATFORM_TIMER_LIB_H_
+
+UINT64
+RiscVReadMachineTimer (VOID);
+
+VOID
+RiscVSetMachineTimerCmp (UINT64);
+
+UINT64
+RiscVReadMachineTimerCmp(VOID);
+
+#endif
diff --git a/Silicon/RISC-V/ProcessorPkg/Include/OpensbiTypes.h b/Silicon/RISC-V/ProcessorPkg/Include/OpensbiTypes.h
index bbf74e2a82..8a6ea97708 100644
--- a/Silicon/RISC-V/ProcessorPkg/Include/OpensbiTypes.h
+++ b/Silicon/RISC-V/ProcessorPkg/Include/OpensbiTypes.h
@@ -44,8 +44,8 @@ typedef UINT64 virtual_size_t;
typedef UINT64 physical_addr_t;
typedef UINT64 physical_size_t;
-#define true TRUE
-#define false FALSE
+#define true TRUE
+#define false FALSE
#define __packed __attribute__((packed))
#define __noreturn __attribute__((noreturn))
@@ -70,7 +70,7 @@ typedef UINT64 physical_size_t;
const typeof(((type *)0)->member) * __mptr = (ptr); \
(type *)((char *)__mptr - offsetof(type, member)); })
-#define array_size(x) (sizeof(x) / sizeof((x)[0]))
+#define array_size(x) (sizeof(x) / sizeof((x)[0]))
#define CLAMP(a, lo, hi) MIN(MAX(a, lo), hi)
#define ROUNDUP(a, b) ((((a)-1) / (b) + 1) * (b))
diff --git a/Silicon/RISC-V/ProcessorPkg/Include/ProcessorSpecificHobData.h b/Silicon/RISC-V/ProcessorPkg/Include/ProcessorSpecificHobData.h
index 2f5847e53e..97285289f7 100644
--- a/Silicon/RISC-V/ProcessorPkg/Include/ProcessorSpecificHobData.h
+++ b/Silicon/RISC-V/ProcessorPkg/Include/ProcessorSpecificHobData.h
@@ -1,7 +1,7 @@
/** @file
Definition of Processor Specific Data HOB.
- Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+ Copyright (c) 2019-2022, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -24,7 +24,7 @@
/// RISC-V processor specific data HOB
///
typedef struct {
- EFI_GUID ParentPrcessorGuid;
+ EFI_GUID ParentProcessorGuid;
UINTN ParentProcessorUid;
EFI_GUID CoreGuid;
VOID *Context; // The additional information of this core which
@@ -37,7 +37,7 @@ typedef struct {
/// RISC-V SMBIOS type 4 (Processor) GUID data HOB
///
typedef struct {
- EFI_GUID PrcessorGuid;
+ EFI_GUID ProcessorGuid;
UINTN ProcessorUid;
SMBIOS_TABLE_TYPE4 SmbiosType4Processor;
UINT16 EndingZero;
@@ -75,7 +75,7 @@ typedef struct {
/// RISC-V SMBIOS type 7 (Cache) GUID data HOB
///
typedef struct {
- EFI_GUID PrcessorGuid;
+ EFI_GUID ProcessorGuid;
UINTN ProcessorUid;
SMBIOS_TABLE_TYPE7 SmbiosType7Cache;
UINT16 EndingZero;
diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVExceptionLib/CpuExceptionHandlerLib.h b/Silicon/RISC-V/ProcessorPkg/Library/RiscVExceptionLib/CpuExceptionHandlerLib.h
index 3e480e9b09..b316510020 100644
--- a/Silicon/RISC-V/ProcessorPkg/Library/RiscVExceptionLib/CpuExceptionHandlerLib.h
+++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVExceptionLib/CpuExceptionHandlerLib.h
@@ -1,4 +1,4 @@
-/**@file
+/** @file
RISC-V Exception Handler library definition file.
diff --git a/Silicon/RISC-V/ProcessorPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.c b/Silicon/RISC-V/ProcessorPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.c
index b30f9d7f6a..14f62c4036 100644
--- a/Silicon/RISC-V/ProcessorPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.c
+++ b/Silicon/RISC-V/ProcessorPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.c
@@ -1,7 +1,7 @@
/** @file
RISC-V generic SMBIOS DXE driver to build up SMBIOS type 4, type 7 and type 44 records.
- Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+ Copyright (c) 2019-2022, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -33,7 +33,7 @@ BuildSmbiosType7 (
EFI_STATUS Status;
SMBIOS_HANDLE Handle;
- if (!CompareGuid (&Type4HobData->PrcessorGuid, &Type7DataHob->PrcessorGuid) ||
+ if (!CompareGuid (&Type4HobData->ProcessorGuid, &Type7DataHob->ProcessorGuid) ||
Type4HobData->ProcessorUid != Type7DataHob->ProcessorUid) {
return EFI_INVALID_PARAMETER;
}
@@ -48,7 +48,7 @@ BuildSmbiosType7 (
return Status;
}
DEBUG ((DEBUG_INFO, "SMBIOS Type 7 was added. SMBIOS Handle: 0x%x\n", Handle));
- DEBUG ((DEBUG_VERBOSE, " Cache belone to processor GUID: %g\n", &Type7DataHob->PrcessorGuid));
+ DEBUG ((DEBUG_VERBOSE, " Cache belone to processor GUID: %g\n", &Type7DataHob->ProcessorGuid));
DEBUG ((DEBUG_VERBOSE, " Cache belone processor UID: %d\n", Type7DataHob->ProcessorUid));
DEBUG ((DEBUG_VERBOSE, " ==============================\n"));
DEBUG ((DEBUG_VERBOSE, " Socket Designation: %d\n", Type7DataHob->SmbiosType7Cache.SocketDesignation));
@@ -90,7 +90,7 @@ BuildSmbiosType4 (
EFI_STATUS Status;
DEBUG ((DEBUG_INFO, "Building Type 4.\n"));
- DEBUG ((DEBUG_INFO, " Processor GUID: %g\n", &Type4HobData->PrcessorGuid));
+ DEBUG ((DEBUG_INFO, " Processor GUID: %g\n", &Type4HobData->ProcessorGuid));
DEBUG ((DEBUG_INFO, " Processor UUID: %d\n", Type4HobData->ProcessorUid));
Type4HobData->SmbiosType4Processor.L1CacheHandle = RISC_V_CACHE_INFO_NOT_PROVIDED;
@@ -193,7 +193,7 @@ BuildSmbiosType44 (
EFI_STATUS Status;
DEBUG ((DEBUG_INFO, "Building Type 44 for...\n"));
- DEBUG ((DEBUG_VERBOSE, " Processor GUID: %g\n", &Type4HobData->PrcessorGuid));
+ DEBUG ((DEBUG_VERBOSE, " Processor GUID: %g\n", &Type4HobData->ProcessorGuid));
DEBUG ((DEBUG_VERBOSE, " Processor UUID: %d\n", Type4HobData->ProcessorUid));
GuidHob = (EFI_HOB_GUID_TYPE *)GetFirstGuidHob ((EFI_GUID *)PcdGetPtr(PcdProcessorSpecificDataGuidHobGuid));
@@ -206,7 +206,7 @@ BuildSmbiosType44 (
//
do {
ProcessorSpecificData = (RISC_V_PROCESSOR_SPECIFIC_HOB_DATA *)GET_GUID_HOB_DATA (GuidHob);
- if (!CompareGuid (&ProcessorSpecificData->ParentPrcessorGuid, &Type4HobData->PrcessorGuid) ||
+ if (!CompareGuid (&ProcessorSpecificData->ParentProcessorGuid, &Type4HobData->ProcessorGuid) ||
ProcessorSpecificData->ParentProcessorUid != Type4HobData->ProcessorUid) {
GuidHob = GetNextGuidHob((EFI_GUID *)PcdGetPtr(PcdProcessorSpecificDataGuidHobGuid), GET_NEXT_HOB(GuidHob));
if (GuidHob == NULL) {
diff --git a/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.uni b/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.uni
index 83da92fe40..db519c42dd 100644
--- a/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.uni
+++ b/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.uni
@@ -8,6 +8,22 @@
// **/
#string STR_PACKAGE_ABSTRACT #language en-US "Provides UEFI compatible RISC-V processor modules and libraries"
-
#string STR_PACKAGE_DESCRIPTION #language en-US "This Package provides UEFI compatible RISC-V processor modules and libraries."
+#string STR_gUefiRiscVPkgTokenSpaceGuid_PcdProcessorSpecificDataGuidHobGuid_PROMPT #language en-US "Processor Specific Data HOB GUID"
+#string STR_gUefiRiscVPkgTokenSpaceGuid_PcdProcessorSpecificDataGuidHobGuid_HELP #language en-US "This is the GUID definition of HOB that passes the "
+ "processor specific data to DXE phase."
+#string STR_gUefiRiscVPkgTokenSpaceGuid_PcdProcessorSmbiosGuidHobGuid_PROMPT #language en-US "RISC-V SMBIOS Data HOB GUID"
+#string STR_gUefiRiscVPkgTokenSpaceGuid_PcdProcessorSmbiosGuidHobGuid_HELP #language en-US "This is the GUID definition of HOB that passes RISC-V SMBIOS "
+ "Data to DXE phase."
+#string STR_gUefiRiscVPkgTokenSpaceGuid_PcdProcessorSmbiosType4GuidHobGuid_PROMPT #language en-US "RISC-V SMBIOS Type 4 Data HOB GUID"
+#string STR_gUefiRiscVPkgTokenSpaceGuid_PcdProcessorSmbiosType4GuidHobGuid_HELP #language en-US "This is the GUID definition of HOB that passes RISC-V SMBIOS "
+ "Type 4 information to DXE phase for building up SMBIOS record."
+#string STR_gUefiRiscVPkgTokenSpaceGuid_PcdProcessorSmbiosType7GuidHobGuid_PROMPT #language en-US "RISC-V SMBIOS Type 7 Data HOB GUID"
+#string STR_gUefiRiscVPkgTokenSpaceGuid_PcdProcessorSmbiosType7GuidHobGuid_HELP #language en-US "This is the GUID definition of HOB that passes RISC-V SMBIOS "
+ "Type 7 information to DXE phase for building up SMBIOS record."
+#string STR_gUefiRiscVPkgTokenSpaceGuid_PcdRiscVMachineTimerTickInNanoSecond_PROMPT #language en-US "RISC-V Machine Mode Timer Duration"
+#string STR_gUefiRiscVPkgTokenSpaceGuid_PcdRiscVMachineTimerTickInNanoSecond_HELP #language en-US "RISC-V Machine Mode Timer Duration in nanosecond."
+#string STR_gUefiRiscVPkgTokenSpaceGuid_PcdRiscVMachineTimerFrequencyInHerz_PROMPT #language en-US "RISC-V Machine Mode Timer frequency."
+#string STR_gUefiRiscVPkgTokenSpaceGuid_PcdRiscVMachineTimerFrequencyInHerz_HELP #language en-US "RISC-V Machine Mode Timer frequency in Hertz"
+
--
2.31.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* [edk2-platforms][PATCH V2 10/14] RISC-V/ProcessorPkg: Address Core CI library header check errors
2022-01-22 6:53 [edk2-platforms][PATCH V2 00/14] Address edk2 Core CI issues Abner Chang
` (8 preceding siblings ...)
2022-01-22 6:53 ` [edk2-platforms][PATCH V2 09/14] RISC-V/ProcessorPkg: Address Core CI ECC errors Abner Chang
@ 2022-01-22 6:53 ` Abner Chang
2022-01-22 6:53 ` [edk2-platforms][PATCH V2 11/14] RISC-V/ProcessorPkg: Address Core CI Spelling errors Abner Chang
` (4 subsequent siblings)
14 siblings, 0 replies; 16+ messages in thread
From: Abner Chang @ 2022-01-22 6:53 UTC (permalink / raw)
To: devel; +Cc: abner.chang, Daniel Schaefer, Sunil V L
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Cc: Daniel Schaefer <daniel.schaefer@hpe.com>
Cc: Sunil V L <sunilvl@ventanamicro.com>
---
Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec | 1 -
1 file changed, 1 deletion(-)
diff --git a/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec b/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec
index 045fc55212..59634f4413 100644
--- a/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec
+++ b/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec
@@ -22,7 +22,6 @@
Library/RiscVOpensbiLib/opensbi/platform/generic/include # Header file reference from opensbi files, ("sbi/...")
[LibraryClasses]
- RiscVPlatformDxeIplLib|Include/Library/RiscVPlatformDxeIpl.h
RiscVCpuLib|Include/Library/RiscVCpuLib.h
RiscVEdk2SbiLib|Include/Library/RiscVEdk2SbiLib.h
RiscVFirmwareContextLib|Include/Library/RiscVFirmwareContextLib.h
--
2.31.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* [edk2-platforms][PATCH V2 11/14] RISC-V/ProcessorPkg: Address Core CI Spelling errors.
2022-01-22 6:53 [edk2-platforms][PATCH V2 00/14] Address edk2 Core CI issues Abner Chang
` (9 preceding siblings ...)
2022-01-22 6:53 ` [edk2-platforms][PATCH V2 10/14] RISC-V/ProcessorPkg: Address Core CI library header check errors Abner Chang
@ 2022-01-22 6:53 ` Abner Chang
2022-01-22 6:53 ` [edk2-platforms][PATCH V2 12/14] RISC-V/ProcessorPkg: Address Core CI Uncrustify errors Abner Chang
` (3 subsequent siblings)
14 siblings, 0 replies; 16+ messages in thread
From: Abner Chang @ 2022-01-22 6:53 UTC (permalink / raw)
To: devel; +Cc: abner.chang, Daniel Schaefer, Sunil V L
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Cc: Daniel Schaefer <daniel.schaefer@hpe.com>
Cc: Sunil V L <sunilvl@ventanamicro.com>
---
.../RISC-V/ProcessorPkg/RiscVProcessorPkg.dec | 4 ++--
.../RiscVFirmwareContextSbiLib.inf | 6 +++---
.../RiscVFirmwareContextSscratchLib.inf | 4 ++--
.../Include/Library/RiscVEdk2SbiLib.h | 16 ++++++++--------
.../RISC-V/ProcessorPkg/Include/OpensbiTypes.h | 4 ++--
.../Include/ProcessorSpecificHobData.h | 2 +-
.../Include/SmbiosProcessorSpecificData.h | 4 ++--
.../Library/RiscVEdk2SbiLib/RiscVEdk2SbiLib.c | 16 ++++++++--------
.../RiscVFirmwareContextSbiLib.c | 4 ++--
.../RiscVFirmwareContextStvecLib.c | 4 ++--
10 files changed, 32 insertions(+), 32 deletions(-)
diff --git a/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec b/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec
index 59634f4413..177c1a710d 100644
--- a/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec
+++ b/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec
@@ -1,7 +1,7 @@
-## @file RiscVProcesssorPkg.dec
+## @file RiscVProcessorPkg.dec
# This Package provides UEFI RISC-V processor modules and libraries.
#
-# Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+# Copyright (c) 2020-2022, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSbiLib/RiscVFirmwareContextSbiLib.inf b/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSbiLib/RiscVFirmwareContextSbiLib.inf
index 0edf781149..1e4f14724b 100644
--- a/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSbiLib/RiscVFirmwareContextSbiLib.inf
+++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSbiLib/RiscVFirmwareContextSbiLib.inf
@@ -1,9 +1,9 @@
## @file
-# Instance of OpebSBI Firmware Conext Library
+# Instance of OpenSBI Firmware Context Library
#
-# This iinstance uses RISC-V OpenSBI Firmware Extension SBI.
+# This instance uses RISC-V OpenSBI Firmware Extension SBI.
#
-# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+# Copyright (c) 2021-2022, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSscratchLib/RiscVFirmwareContextSscratchLib.inf b/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSscratchLib/RiscVFirmwareContextSscratchLib.inf
index 750c1cf51f..09e635fd1d 100644
--- a/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSscratchLib/RiscVFirmwareContextSscratchLib.inf
+++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSscratchLib/RiscVFirmwareContextSscratchLib.inf
@@ -1,9 +1,9 @@
## @file
-# Instance of OpebSBI Firmware Conext Library
+# Instance of OpenSBI Firmware Context Library
#
# This instance uses RISC-V Supervisor mode SCRATCH CSR
#
-# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+# Copyright (c) 2021-2022, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
diff --git a/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVEdk2SbiLib.h b/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVEdk2SbiLib.h
index 88d957f002..6089137373 100644
--- a/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVEdk2SbiLib.h
+++ b/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVEdk2SbiLib.h
@@ -1,7 +1,7 @@
/** @file
Library to call the RISC-V SBI ecalls
- Copyright (c) 2021, Hewlett Packard Development LP. All rights reserved.<BR>
+ Copyright (c) 2021-2022, Hewlett Packard Development LP. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -54,7 +54,7 @@ SbiGetSpecVersion (
/**
Get the SBI implementation ID
- This ID is used to idenetify a specific SBI implementation in order to work
+ This ID is used to identify a specific SBI implementation in order to work
around any quirks it might have.
@param[out] ImplId The ID of the SBI implementation.
@@ -275,7 +275,7 @@ SbiRemoteFenceI (
/**
Instructs the remote harts to execute one or more SFENCE.VMA instructions.
- The SFENCE.VMA covers the range of virtual addresses between StartAaddr and Size.
+ The SFENCE.VMA covers the range of virtual addresses between StartAddr and Size.
The remote fence function acts as a full tlb flush if * StartAddr and size
are both 0 * size is equal to 2^XLEN-1
@@ -305,7 +305,7 @@ SbiRemoteSfenceVma (
/**
Instructs the remote harts to execute one or more SFENCE.VMA instructions.
- The SFENCE.VMA covers the range of virtual addresses between StartAaddr and Size.
+ The SFENCE.VMA covers the range of virtual addresses between StartAddr and Size.
Covers only the given ASID.
The remote fence function acts as a full tlb flush if * StartAddr and size
@@ -337,7 +337,7 @@ SbiRemoteSfenceVmaAsid (
/**
Instructs the remote harts to execute one or more SFENCE.GVMA instructions.
- The SFENCE.GVMA covers the range of virtual addresses between StartAaddr and Size.
+ The SFENCE.GVMA covers the range of virtual addresses between StartAddr and Size.
Covers only the given VMID.
This function call is only valid for harts implementing the hypervisor extension.
@@ -373,7 +373,7 @@ SbiRemoteHfenceGvmaVmid (
/**
Instructs the remote harts to execute one or more SFENCE.GVMA instructions.
- The SFENCE.GVMA covers the range of virtual addresses between StartAaddr and Size.
+ The SFENCE.GVMA covers the range of virtual addresses between StartAddr and Size.
This function call is only valid for harts implementing the hypervisor extension.
The remote fence function acts as a full tlb flush if * StartAddr and size
@@ -407,7 +407,7 @@ SbiRemoteHfenceGvma (
/**
Instructs the remote harts to execute one or more SFENCE.VVMA instructions.
- The SFENCE.GVMA covers the range of virtual addresses between StartAaddr and Size.
+ The SFENCE.GVMA covers the range of virtual addresses between StartAddr and Size.
Covers only the given ASID.
This function call is only valid for harts implementing the hypervisor extension.
@@ -443,7 +443,7 @@ SbiRemoteHfenceVvmaAsid (
/**
Instructs the remote harts to execute one or more SFENCE.VVMA instructions.
- The SFENCE.GVMA covers the range of virtual addresses between StartAaddr and Size.
+ The SFENCE.GVMA covers the range of virtual addresses between StartAddr and Size.
This function call is only valid for harts implementing the hypervisor extension.
The remote fence function acts as a full tlb flush if * StartAddr and size
diff --git a/Silicon/RISC-V/ProcessorPkg/Include/OpensbiTypes.h b/Silicon/RISC-V/ProcessorPkg/Include/OpensbiTypes.h
index 8a6ea97708..af34e8b0ae 100644
--- a/Silicon/RISC-V/ProcessorPkg/Include/OpensbiTypes.h
+++ b/Silicon/RISC-V/ProcessorPkg/Include/OpensbiTypes.h
@@ -1,7 +1,7 @@
/** @file
- RISC-V OpesbSBI header file reference.
+ RISC-V OpenSBI header file reference.
- Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+ Copyright (c) 2020-2022, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
diff --git a/Silicon/RISC-V/ProcessorPkg/Include/ProcessorSpecificHobData.h b/Silicon/RISC-V/ProcessorPkg/Include/ProcessorSpecificHobData.h
index 97285289f7..4b2a92e2f2 100644
--- a/Silicon/RISC-V/ProcessorPkg/Include/ProcessorSpecificHobData.h
+++ b/Silicon/RISC-V/ProcessorPkg/Include/ProcessorSpecificHobData.h
@@ -29,7 +29,7 @@ typedef struct {
EFI_GUID CoreGuid;
VOID *Context; // The additional information of this core which
// built in PEI phase and carried to DXE phase.
- // The content is pocessor or platform specific.
+ // The content is processor or platform specific.
SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA ProcessorSpecificData;
} RISC_V_PROCESSOR_SPECIFIC_HOB_DATA;
diff --git a/Silicon/RISC-V/ProcessorPkg/Include/SmbiosProcessorSpecificData.h b/Silicon/RISC-V/ProcessorPkg/Include/SmbiosProcessorSpecificData.h
index 81e48cd068..85b8dcbe20 100644
--- a/Silicon/RISC-V/ProcessorPkg/Include/SmbiosProcessorSpecificData.h
+++ b/Silicon/RISC-V/ProcessorPkg/Include/SmbiosProcessorSpecificData.h
@@ -1,9 +1,9 @@
/** @file
Industry Standard Definitions of RISC-V Processor Specific data defined in
- below link for complaiant with SMBIOS Table Specification v3.3.0.
+ below link for compliant with SMBIOS Table Specification v3.3.0.
https://github.com/riscv/riscv-smbios
- Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+ Copyright (c) 2019-2022, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVEdk2SbiLib/RiscVEdk2SbiLib.c b/Silicon/RISC-V/ProcessorPkg/Library/RiscVEdk2SbiLib/RiscVEdk2SbiLib.c
index 319526ed8f..a51139542d 100644
--- a/Silicon/RISC-V/ProcessorPkg/Library/RiscVEdk2SbiLib/RiscVEdk2SbiLib.c
+++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVEdk2SbiLib/RiscVEdk2SbiLib.c
@@ -15,7 +15,7 @@
- SbiLegacyRemoteSfenceVmaAsid -> Use SbiRemoteSfenceVmaAsid
- SbiLegacyShutdown -> Wait for new System Reset extension
- Copyright (c) 2021, Hewlett Packard Development LP. All rights reserved.<BR>
+ Copyright (c) 2021-2022, Hewlett Packard Development LP. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@par Revision Reference:
@@ -173,7 +173,7 @@ SbiGetSpecVersion (
/**
Get the SBI implementation ID
- This ID is used to idenetify a specific SBI implementation in order to work
+ This ID is used to identify a specific SBI implementation in order to work
around any quirks it might have.
@param[out] ImplId The ID of the SBI implementation.
@@ -441,7 +441,7 @@ SbiRemoteFenceI (
/**
Instructs the remote harts to execute one or more SFENCE.VMA instructions.
- The SFENCE.VMA covers the range of virtual addresses between StartAaddr and Size.
+ The SFENCE.VMA covers the range of virtual addresses between StartAddr and Size.
The remote fence function acts as a full tlb flush if * StartAddr and size
are both 0 * size is equal to 2^XLEN-1
@@ -483,7 +483,7 @@ SbiRemoteSfenceVma (
/**
Instructs the remote harts to execute one or more SFENCE.VMA instructions.
- The SFENCE.VMA covers the range of virtual addresses between StartAaddr and Size.
+ The SFENCE.VMA covers the range of virtual addresses between StartAddr and Size.
Covers only the given ASID.
The remote fence function acts as a full tlb flush if * StartAddr and size
@@ -528,7 +528,7 @@ SbiRemoteSfenceVmaAsid (
/**
Instructs the remote harts to execute one or more SFENCE.GVMA instructions.
- The SFENCE.GVMA covers the range of virtual addresses between StartAaddr and Size.
+ The SFENCE.GVMA covers the range of virtual addresses between StartAddr and Size.
Covers only the given VMID.
This function call is only valid for harts implementing the hypervisor extension.
@@ -577,7 +577,7 @@ SbiRemoteHFenceGvmaVmid (
/**
Instructs the remote harts to execute one or more SFENCE.GVMA instructions.
- The SFENCE.GVMA covers the range of virtual addresses between StartAaddr and Size.
+ The SFENCE.GVMA covers the range of virtual addresses between StartAddr and Size.
This function call is only valid for harts implementing the hypervisor extension.
The remote fence function acts as a full tlb flush if * StartAddr and size
@@ -623,7 +623,7 @@ SbiRemoteHFenceGvma (
/**
Instructs the remote harts to execute one or more SFENCE.VVMA instructions.
- The SFENCE.GVMA covers the range of virtual addresses between StartAaddr and Size.
+ The SFENCE.GVMA covers the range of virtual addresses between StartAddr and Size.
Covers only the given ASID.
This function call is only valid for harts implementing the hypervisor extension.
@@ -672,7 +672,7 @@ SbiRemoteHFenceVvmaAsid (
/**
Instructs the remote harts to execute one or more SFENCE.VVMA instructions.
- The SFENCE.GVMA covers the range of virtual addresses between StartAaddr and Size.
+ The SFENCE.GVMA covers the range of virtual addresses between StartAddr and Size.
This function call is only valid for harts implementing the hypervisor extension.
The remote fence function acts as a full tlb flush if * StartAddr and size
diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSbiLib/RiscVFirmwareContextSbiLib.c b/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSbiLib/RiscVFirmwareContextSbiLib.c
index 6125618eaf..a2a18d3eb7 100644
--- a/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSbiLib/RiscVFirmwareContextSbiLib.c
+++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSbiLib/RiscVFirmwareContextSbiLib.c
@@ -1,8 +1,8 @@
/** @file
- This iinstance uses RISC-V OpenSBI Firmware Extension SBI to
+ This instance uses RISC-V OpenSBI Firmware Extension SBI to
get the pointer of firmware context.
- Copyright (c) 2021 Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+ Copyright (c) 2021-2022 Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextStvecLib/RiscVFirmwareContextStvecLib.c b/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextStvecLib/RiscVFirmwareContextStvecLib.c
index 7d1675355a..cc5a7e2ccc 100644
--- a/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextStvecLib/RiscVFirmwareContextStvecLib.c
+++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextStvecLib/RiscVFirmwareContextStvecLib.c
@@ -1,8 +1,8 @@
/** @file
- This instance uses This iinstance Supervisor mode STVEC CSR to
+ This instance uses Supervisor mode STVEC CSR to
get/set the pointer of firmware context.
- Copyright (c) 2021 Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+ Copyright (c) 2021-2022 Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
--
2.31.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* [edk2-platforms][PATCH V2 12/14] RISC-V/ProcessorPkg: Address Core CI Uncrustify errors
2022-01-22 6:53 [edk2-platforms][PATCH V2 00/14] Address edk2 Core CI issues Abner Chang
` (10 preceding siblings ...)
2022-01-22 6:53 ` [edk2-platforms][PATCH V2 11/14] RISC-V/ProcessorPkg: Address Core CI Spelling errors Abner Chang
@ 2022-01-22 6:53 ` Abner Chang
2022-01-22 6:53 ` [edk2-platforms][PATCH V2 13/14] Silicon/SiFive: Fix build error Abner Chang
` (2 subsequent siblings)
14 siblings, 0 replies; 16+ messages in thread
From: Abner Chang @ 2022-01-22 6:53 UTC (permalink / raw)
To: devel; +Cc: abner.chang, Daniel Schaefer, Sunil V L
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Cc: Daniel Schaefer <daniel.schaefer@hpe.com>
Cc: Sunil V L <sunilvl@ventanamicro.com>
---
.../Include/IndustryStandard/RiscV.h | 156 ++---
.../Include/IndustryStandard/RiscVOpensbi.h | 28 +-
.../Include/Library/MachineModeTimerLib.h | 4 +-
.../Include/Library/RiscVCpuLib.h | 76 ++-
.../Include/Library/RiscVEdk2SbiLib.h | 122 ++--
.../Include/Library/RiscVFirmwareContextLib.h | 6 +-
.../Include/Library/RiscVPlatformTimerLib.h | 10 +-
.../ProcessorPkg/Include/OpensbiTypes.h | 69 +-
.../Include/ProcessorSpecificHobData.h | 103 +--
.../RISC-V/ProcessorPkg/Include/RiscVImpl.h | 52 +-
.../Include/SmbiosProcessorSpecificData.h | 46 +-
.../CpuExceptionHandlerLib.h | 169 ++---
.../ProcessorPkg/Universal/CpuDxe/CpuDxe.h | 45 +-
.../Universal/SmbiosDxe/RiscVSmbiosDxe.h | 3 +-
.../PeiServicesTablePointerOpenSbi.c | 22 +-
.../Library/RiscVEdk2SbiLib/RiscVEdk2SbiLib.c | 601 ++++++++++--------
.../CpuExceptionHandlerLib.c | 34 +-
.../RiscVFirmwareContextSscratchLib.c | 6 +-
.../RiscVFirmwareContextStvecLib.c | 4 +-
.../Library/RiscVTimerLib/RiscVTimerLib.c | 24 +-
.../ProcessorPkg/Universal/CpuDxe/CpuDxe.c | 72 +--
.../ProcessorPkg/Universal/FdtDxe/FdtDxe.c | 66 +-
.../Universal/PciCpuIo2Dxe/PciCpuIo2Dxe.c | 47 +-
.../Universal/SmbiosDxe/RiscVSmbiosDxe.c | 153 +++--
.../PeiServicesTablePointerLibOpenSbi.uni | 15 +-
25 files changed, 1049 insertions(+), 884 deletions(-)
diff --git a/Silicon/RISC-V/ProcessorPkg/Include/IndustryStandard/RiscV.h b/Silicon/RISC-V/ProcessorPkg/Include/IndustryStandard/RiscV.h
index c9715a2ee2..8710aae677 100644
--- a/Silicon/RISC-V/ProcessorPkg/Include/IndustryStandard/RiscV.h
+++ b/Silicon/RISC-V/ProcessorPkg/Include/IndustryStandard/RiscV.h
@@ -1,7 +1,7 @@
/** @file
RISC-V package definitions.
- Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+ Copyright (c) 2021-2022, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -11,36 +11,36 @@
#define RISCV_INDUSTRY_STANDARD_H_
#if defined (MDE_CPU_RISCV64)
-#define RISC_V_XLEN_BITS 64
+#define RISC_V_XLEN_BITS 64
#else
#endif
-#define RISC_V_ISA_ATOMIC_EXTENSION (0x00000001 << 0)
-#define RISC_V_ISA_BIT_OPERATION_EXTENSION (0x00000001 << 1)
-#define RISC_V_ISA_COMPRESSED_EXTENSION (0x00000001 << 2)
-#define RISC_V_ISA_DOUBLE_PRECISION_FP_EXTENSION (0x00000001 << 3)
-#define RISC_V_ISA_RV32E_ISA (0x00000001 << 4)
-#define RISC_V_ISA_SINGLE_PRECISION_FP_EXTENSION (0x00000001 << 5)
-#define RISC_V_ISA_ADDITIONAL_STANDARD_EXTENSION (0x00000001 << 6)
-#define RISC_V_ISA_RESERVED_1 (0x00000001 << 7)
-#define RISC_V_ISA_INTEGER_ISA_EXTENSION (0x00000001 << 8)
-#define RISC_V_ISA_DYNAMICALLY_TRANSLATED_LANGUAGE_EXTENSION (0x00000001 << 9)
-#define RISC_V_ISA_RESERVED_2 (0x00000001 << 10)
-#define RISC_V_ISA_DECIMAL_FP_EXTENSION (0x00000001 << 11)
-#define RISC_V_ISA_INTEGER_MUL_DIV_EXTENSION (0x00000001 << 12)
-#define RISC_V_ISA_USER_LEVEL_INTERRUPT_SUPPORTED (0x00000001 << 13)
-#define RISC_V_ISA_RESERVED_3 (0x00000001 << 14)
-#define RISC_V_ISA_PACKED_SIMD_EXTENSION (0x00000001 << 15)
-#define RISC_V_ISA_QUAD_PRECISION_FP_EXTENSION (0x00000001 << 16)
-#define RISC_V_ISA_RESERVED_4 (0x00000001 << 17)
-#define RISC_V_ISA_SUPERVISOR_MODE_IMPLEMENTED (0x00000001 << 18)
-#define RISC_V_ISA_TRANSATIONAL_MEMORY_EXTENSION (0x00000001 << 19)
-#define RISC_V_ISA_USER_MODE_IMPLEMENTED (0x00000001 << 20)
-#define RISC_V_ISA_VECTOR_EXTENSION (0x00000001 << 21)
-#define RISC_V_ISA_RESERVED_5 (0x00000001 << 22)
-#define RISC_V_ISA_NON_STANDARD_EXTENSION (0x00000001 << 23)
-#define RISC_V_ISA_RESERVED_6 (0x00000001 << 24)
-#define RISC_V_ISA_RESERVED_7 (0x00000001 << 25)
+#define RISC_V_ISA_ATOMIC_EXTENSION (0x00000001 << 0)
+#define RISC_V_ISA_BIT_OPERATION_EXTENSION (0x00000001 << 1)
+#define RISC_V_ISA_COMPRESSED_EXTENSION (0x00000001 << 2)
+#define RISC_V_ISA_DOUBLE_PRECISION_FP_EXTENSION (0x00000001 << 3)
+#define RISC_V_ISA_RV32E_ISA (0x00000001 << 4)
+#define RISC_V_ISA_SINGLE_PRECISION_FP_EXTENSION (0x00000001 << 5)
+#define RISC_V_ISA_ADDITIONAL_STANDARD_EXTENSION (0x00000001 << 6)
+#define RISC_V_ISA_RESERVED_1 (0x00000001 << 7)
+#define RISC_V_ISA_INTEGER_ISA_EXTENSION (0x00000001 << 8)
+#define RISC_V_ISA_DYNAMICALLY_TRANSLATED_LANGUAGE_EXTENSION (0x00000001 << 9)
+#define RISC_V_ISA_RESERVED_2 (0x00000001 << 10)
+#define RISC_V_ISA_DECIMAL_FP_EXTENSION (0x00000001 << 11)
+#define RISC_V_ISA_INTEGER_MUL_DIV_EXTENSION (0x00000001 << 12)
+#define RISC_V_ISA_USER_LEVEL_INTERRUPT_SUPPORTED (0x00000001 << 13)
+#define RISC_V_ISA_RESERVED_3 (0x00000001 << 14)
+#define RISC_V_ISA_PACKED_SIMD_EXTENSION (0x00000001 << 15)
+#define RISC_V_ISA_QUAD_PRECISION_FP_EXTENSION (0x00000001 << 16)
+#define RISC_V_ISA_RESERVED_4 (0x00000001 << 17)
+#define RISC_V_ISA_SUPERVISOR_MODE_IMPLEMENTED (0x00000001 << 18)
+#define RISC_V_ISA_TRANSATIONAL_MEMORY_EXTENSION (0x00000001 << 19)
+#define RISC_V_ISA_USER_MODE_IMPLEMENTED (0x00000001 << 20)
+#define RISC_V_ISA_VECTOR_EXTENSION (0x00000001 << 21)
+#define RISC_V_ISA_RESERVED_5 (0x00000001 << 22)
+#define RISC_V_ISA_NON_STANDARD_EXTENSION (0x00000001 << 23)
+#define RISC_V_ISA_RESERVED_6 (0x00000001 << 24)
+#define RISC_V_ISA_RESERVED_7 (0x00000001 << 25)
//
// RISC-V CSR definitions.
@@ -48,81 +48,81 @@
//
// Machine information
//
-#define RISCV_CSR_MACHINE_MVENDORID 0xF11
-#define RISCV_CSR_MACHINE_MARCHID 0xF12
-#define RISCV_CSR_MACHINE_MIMPID 0xF13
-#define RISCV_CSR_MACHINE_HARRID 0xF14
+#define RISCV_CSR_MACHINE_MVENDORID 0xF11
+#define RISCV_CSR_MACHINE_MARCHID 0xF12
+#define RISCV_CSR_MACHINE_MIMPID 0xF13
+#define RISCV_CSR_MACHINE_HARRID 0xF14
//
// Machine Trap Setup.
//
-#define RISCV_CSR_MACHINE_MSTATUS 0x300
-#define RISCV_CSR_MACHINE_MISA 0x301
-#define RISCV_CSR_MACHINE_MEDELEG 0x302
-#define RISCV_CSR_MACHINE_MIDELEG 0x303
-#define RISCV_CSR_MACHINE_MIE 0x304
-#define RISCV_CSR_MACHINE_MTVEC 0x305
+#define RISCV_CSR_MACHINE_MSTATUS 0x300
+#define RISCV_CSR_MACHINE_MISA 0x301
+#define RISCV_CSR_MACHINE_MEDELEG 0x302
+#define RISCV_CSR_MACHINE_MIDELEG 0x303
+#define RISCV_CSR_MACHINE_MIE 0x304
+#define RISCV_CSR_MACHINE_MTVEC 0x305
-#define RISCV_TIMER_COMPARE_BITS 32
+#define RISCV_TIMER_COMPARE_BITS 32
//
// Machine Timer and Counter.
//
-//#define RISCV_CSR_MACHINE_MTIME 0x701
-//#define RISCV_CSR_MACHINE_MTIMEH 0x741
+// #define RISCV_CSR_MACHINE_MTIME 0x701
+// #define RISCV_CSR_MACHINE_MTIMEH 0x741
//
// Machine Trap Handling.
//
-#define RISCV_CSR_MACHINE_MSCRATCH 0x340
-#define RISCV_CSR_MACHINE_MEPC 0x341
-#define RISCV_CSR_MACHINE_MCAUSE 0x342
- #define MACHINE_MCAUSE_EXCEPTION_ MASK 0x0f
- #define MACHINE_MCAUSE_INTERRUPT (RISC_V_XLEN_BITS - 1)
-#define RISCV_CSR_MACHINE_MBADADDR 0x343
-#define RISCV_CSR_MACHINE_MIP 0x344
+#define RISCV_CSR_MACHINE_MSCRATCH 0x340
+#define RISCV_CSR_MACHINE_MEPC 0x341
+#define RISCV_CSR_MACHINE_MCAUSE 0x342
+#define MACHINE_MCAUSE_EXCEPTION_ MASK 0x0f
+#define MACHINE_MCAUSE_INTERRUPT (RISC_V_XLEN_BITS - 1)
+#define RISCV_CSR_MACHINE_MBADADDR 0x343
+#define RISCV_CSR_MACHINE_MIP 0x344
//
// Machine Protection and Translation.
//
-#define RISCV_CSR_MACHINE_MBASE 0x380
-#define RISCV_CSR_MACHINE_MBOUND 0x381
-#define RISCV_CSR_MACHINE_MIBASE 0x382
-#define RISCV_CSR_MACHINE_MIBOUND 0x383
-#define RISCV_CSR_MACHINE_MDBASE 0x384
-#define RISCV_CSR_MACHINE_MDBOUND 0x385
+#define RISCV_CSR_MACHINE_MBASE 0x380
+#define RISCV_CSR_MACHINE_MBOUND 0x381
+#define RISCV_CSR_MACHINE_MIBASE 0x382
+#define RISCV_CSR_MACHINE_MIBOUND 0x383
+#define RISCV_CSR_MACHINE_MDBASE 0x384
+#define RISCV_CSR_MACHINE_MDBOUND 0x385
//
// Supervisor mode CSR.
//
#define RISCV_CSR_SUPERVISOR_SSTATUS 0x100
- #define SSTATUS_SIE_BIT_POSITION 1
- #define SSTATUS_SPP_BIT_POSITION 8
+#define SSTATUS_SIE_BIT_POSITION 1
+#define SSTATUS_SPP_BIT_POSITION 8
#define RISCV_CSR_SUPERVISOR_SIE 0x104
#define RISCV_CSR_SUPERVISOR_STVEC 0x105
#define RISCV_CSR_SUPERVISOR_SSCRATCH 0x140
#define RISCV_CSR_SUPERVISOR_SEPC 0x141
#define RISCV_CSR_SUPERVISOR_SCAUSE 0x142
- #define SCAUSE_USER_SOFTWARE_INT 0
- #define SCAUSE_SUPERVISOR_SOFTWARE_INT 1
- #define SCAUSE_USER_TIMER_INT 4
- #define SCAUSE_SUPERVISOR_TIMER_INT 5
- #define SCAUSE_USER_EXTERNAL_INT 8
- #define SCAUSE_SUPERVISOR_EXTERNAL_INT 9
+#define SCAUSE_USER_SOFTWARE_INT 0
+#define SCAUSE_SUPERVISOR_SOFTWARE_INT 1
+#define SCAUSE_USER_TIMER_INT 4
+#define SCAUSE_SUPERVISOR_TIMER_INT 5
+#define SCAUSE_USER_EXTERNAL_INT 8
+#define SCAUSE_SUPERVISOR_EXTERNAL_INT 9
#define RISCV_CSR_SUPERVISOR_STVAL 0x143
#define RISCV_CSR_SUPERVISOR_SIP 0x144
#define RISCV_CSR_SUPERVISOR_SATP 0x180
#if defined (MDE_CPU_RISCV64)
- #define RISCV_SATP_MODE_MASK 0xF000000000000000
- #define RISCV_SATP_MODE_BIT_POSITION 60
+#define RISCV_SATP_MODE_MASK 0xF000000000000000
+#define RISCV_SATP_MODE_BIT_POSITION 60
#endif
- #define RISCV_SATP_MODE_OFF 0
- #define RISCV_SATP_MODE_SV32 1
- #define RISCV_SATP_MODE_SV39 8
- #define RISCV_SATP_MODE_SV48 9
- #define RISCV_SATP_MODE_SV57 10
- #define RISCV_SATP_MODE_SV64 11
+#define RISCV_SATP_MODE_OFF 0
+#define RISCV_SATP_MODE_SV32 1
+#define RISCV_SATP_MODE_SV39 8
+#define RISCV_SATP_MODE_SV48 9
+#define RISCV_SATP_MODE_SV57 10
+#define RISCV_SATP_MODE_SV64 11
- #define SATP64_ASID_MASK 0x0FFFF00000000000
- #define SATP64_PPN_MASK 0x00000FFFFFFFFFFF
+#define SATP64_ASID_MASK 0x0FFFF00000000000
+#define SATP64_PPN_MASK 0x00000FFFFFFFFFFF
#define RISCV_CAUSE_MISALIGNED_FETCH 0x0
#define RISCV_CAUSE_FETCH_ACCESS 0x1
@@ -146,17 +146,17 @@
//
// Machine Read-Write Shadow of Hypervisor Read-Only Registers
//
-#define RISCV_CSR_HTIMEW 0xB01
-#define RISCV_CSR_HTIMEHW 0xB81
+#define RISCV_CSR_HTIMEW 0xB01
+#define RISCV_CSR_HTIMEHW 0xB81
//
// Machine Host-Target Interface (Non-Standard Berkeley Extension)
//
-#define RISCV_CSR_MTOHOST 0x780
-#define RISCV_CSR_MFROMHOST 0x781
+#define RISCV_CSR_MTOHOST 0x780
+#define RISCV_CSR_MFROMHOST 0x781
//
// User mode CSR
//
-#define RISCV_CSR_CYCLE 0xc00
-#define RISCV_CSR_TIME 0xc01
+#define RISCV_CSR_CYCLE 0xc00
+#define RISCV_CSR_TIME 0xc01
#endif
diff --git a/Silicon/RISC-V/ProcessorPkg/Include/IndustryStandard/RiscVOpensbi.h b/Silicon/RISC-V/ProcessorPkg/Include/IndustryStandard/RiscVOpensbi.h
index d639429306..43bbf13d60 100644
--- a/Silicon/RISC-V/ProcessorPkg/Include/IndustryStandard/RiscVOpensbi.h
+++ b/Silicon/RISC-V/ProcessorPkg/Include/IndustryStandard/RiscVOpensbi.h
@@ -1,7 +1,7 @@
/** @file
SBI inline function calls.
- Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+ Copyright (c) 2021-2022, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -20,7 +20,7 @@
#include <sbi/sbi_types.h>
#include <sbi/sbi_hartmask.h>
-#define RISC_V_MAX_HART_SUPPORTED SBI_HARTMASK_MAX_BITS
+#define RISC_V_MAX_HART_SUPPORTED SBI_HARTMASK_MAX_BITS
typedef
VOID
@@ -36,27 +36,27 @@ VOID
// Keep the structure member in 64-bit alignment.
//
typedef struct {
- UINT64 IsaExtensionSupported; // The ISA extension this core supported.
- RISCV_UINT128 MachineVendorId; // Machine vendor ID
- RISCV_UINT128 MachineArchId; // Machine Architecture ID
- RISCV_UINT128 MachineImplId; // Machine Implementation ID
- RISCV_HART_SWITCH_MODE HartSwitchMode; // OpenSBI's function to switch the mode of a hart
+ UINT64 IsaExtensionSupported; // The ISA extension this core supported.
+ RISCV_UINT128 MachineVendorId; // Machine vendor ID
+ RISCV_UINT128 MachineArchId; // Machine Architecture ID
+ RISCV_UINT128 MachineImplId; // Machine Implementation ID
+ RISCV_HART_SWITCH_MODE HartSwitchMode; // OpenSBI's function to switch the mode of a hart
} EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC;
#define FIRMWARE_CONTEXT_HART_SPECIFIC_SIZE (64 * 8) // This is the size of EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC
// structure. Referred by both C code and assembly code.
typedef struct {
- UINT64 BootHartId;
- VOID *PeiServiceTable; // PEI Service table
- UINT64 FlattenedDeviceTree; // Pointer to Flattened Device tree
- UINT64 SecPeiHandOffData; // This is EFI_SEC_PEI_HAND_OFF passed to PEI Core.
- EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC *HartSpecific[RISC_V_MAX_HART_SUPPORTED];
+ UINT64 BootHartId;
+ VOID *PeiServiceTable; // PEI Service table
+ UINT64 FlattenedDeviceTree; // Pointer to Flattened Device tree
+ UINT64 SecPeiHandOffData; // This is EFI_SEC_PEI_HAND_OFF passed to PEI Core.
+ EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC *HartSpecific[RISC_V_MAX_HART_SUPPORTED];
} EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT;
//
// Typedefs of OpenSBI type to make them conform to EDK2 coding guidelines
//
-typedef struct sbi_scratch SBI_SCRATCH;
-typedef struct sbi_platform SBI_PLATFORM;
+typedef struct sbi_scratch SBI_SCRATCH;
+typedef struct sbi_platform SBI_PLATFORM;
#endif
diff --git a/Silicon/RISC-V/ProcessorPkg/Include/Library/MachineModeTimerLib.h b/Silicon/RISC-V/ProcessorPkg/Include/Library/MachineModeTimerLib.h
index a27391cca3..141d37992d 100644
--- a/Silicon/RISC-V/ProcessorPkg/Include/Library/MachineModeTimerLib.h
+++ b/Silicon/RISC-V/ProcessorPkg/Include/Library/MachineModeTimerLib.h
@@ -10,6 +10,8 @@
#define MACHINE_MODE_TIMER_LIB_H_
UINT64
-RiscVReadMachineTimerInterface (VOID);
+RiscVReadMachineTimerInterface (
+ VOID
+ );
#endif
diff --git a/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVCpuLib.h b/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVCpuLib.h
index 8d51152fa9..efe854892b 100644
--- a/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVCpuLib.h
+++ b/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVCpuLib.h
@@ -1,7 +1,7 @@
/** @file
RISC-V CPU library definitions.
- Copyright (c) 2016 - 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+ Copyright (c) 2016 - 2022, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@@ -21,66 +21,98 @@ VOID
);
VOID
-RiscVSetMachineScratch (RISCV_MACHINE_MODE_CONTEXT *RiscvContext);
+RiscVSetMachineScratch (
+ RISCV_MACHINE_MODE_CONTEXT *RiscvContext
+ );
UINT32
-RiscVGetMachineScratch (VOID);
+RiscVGetMachineScratch (
+ VOID
+ );
UINT32
-RiscVGetMachineTrapCause (VOID);
+RiscVGetMachineTrapCause (
+ VOID
+ );
UINT64
-RiscVReadMachineTimer (VOID);
+RiscVReadMachineTimer (
+ VOID
+ );
UINT64
-RiscVReadMachineTimerInterface (VOID);
+RiscVReadMachineTimerInterface (
+ VOID
+ );
VOID
-RiscVSetMachineTimerCmp (UINT64);
+ RiscVSetMachineTimerCmp (UINT64);
UINT64
-RiscVReadMachineTimerCmp(VOID);
+RiscVReadMachineTimerCmp (
+ VOID
+ );
UINT64
-RiscVReadMachineInterruptEnable(VOID);
+RiscVReadMachineInterruptEnable (
+ VOID
+ );
UINT64
-RiscVReadMachineInterruptPending(VOID);
+RiscVReadMachineInterruptPending (
+ VOID
+ );
UINT64
-RiscVReadMachineStatus(VOID);
+RiscVReadMachineStatus (
+ VOID
+ );
VOID
-RiscVWriteMachineStatus(UINT64);
+ RiscVWriteMachineStatus (UINT64);
UINT64
-RiscVReadMachineTrapVector(VOID);
+RiscVReadMachineTrapVector (
+ VOID
+ );
UINT64
-RiscVReadMachineIsa (VOID);
+RiscVReadMachineIsa (
+ VOID
+ );
UINT64
-RiscVReadMachineVendorId (VOID);
+RiscVReadMachineVendorId (
+ VOID
+ );
UINT64
-RiscVReadMachineArchitectureId (VOID);
+RiscVReadMachineArchitectureId (
+ VOID
+ );
UINT64
-RiscVReadMachineImplementId (VOID);
+RiscVReadMachineImplementId (
+ VOID
+ );
VOID
-RiscVSetSupervisorAddressTranslationRegister(UINT64);
+ RiscVSetSupervisorAddressTranslationRegister (UINT64);
VOID
-RiscVSetSupervisorScratch (UINT64);
+ RiscVSetSupervisorScratch (UINT64);
UINT64
-RiscVGetSupervisorScratch (VOID);
+RiscVGetSupervisorScratch (
+ VOID
+ );
VOID
-RiscVSetSupervisorStvec (UINT64);
+ RiscVSetSupervisorStvec (UINT64);
UINT64
-RiscVGetSupervisorStvec (VOID);
+RiscVGetSupervisorStvec (
+ VOID
+ );
#endif
diff --git a/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVEdk2SbiLib.h b/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVEdk2SbiLib.h
index 6089137373..36eb16e1cb 100644
--- a/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVEdk2SbiLib.h
+++ b/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVEdk2SbiLib.h
@@ -21,20 +21,20 @@
//
// EDK2 OpenSBI Firmware extension.
//
-#define SBI_EDK2_FW_EXT (SBI_EXT_FIRMWARE_START | SBI_OPENSBI_IMPID)
+#define SBI_EDK2_FW_EXT (SBI_EXT_FIRMWARE_START | SBI_OPENSBI_IMPID)
//
// EDK2 OpenSBI Firmware extension functions.
//
-#define SBI_EXT_FW_MSCRATCH_FUNC 0
-#define SBI_EXT_FW_MSCRATCH_HARTID_FUNC 1
+#define SBI_EXT_FW_MSCRATCH_FUNC 0
+#define SBI_EXT_FW_MSCRATCH_HARTID_FUNC 1
//
// EDK2 OpenSBI firmware extension return status.
//
typedef struct {
- UINTN Error; ///< SBI status code
- UINTN Value; ///< Value returned
-} SbiRet;
+ UINTN Error; ///< SBI status code
+ UINTN Value; ///< Value returned
+} SBI_RET;
/**
Get the implemented SBI specification version
@@ -48,7 +48,7 @@ typedef struct {
VOID
EFIAPI
SbiGetSpecVersion (
- OUT UINTN *SpecVersion
+ OUT UINTN *SpecVersion
);
/**
@@ -62,7 +62,7 @@ SbiGetSpecVersion (
VOID
EFIAPI
SbiGetImplId (
- OUT UINTN *ImplId
+ OUT UINTN *ImplId
);
/**
@@ -76,7 +76,7 @@ SbiGetImplId (
VOID
EFIAPI
SbiGetImplVersion (
- OUT UINTN *ImplVersion
+ OUT UINTN *ImplVersion
);
/**
@@ -91,8 +91,8 @@ SbiGetImplVersion (
VOID
EFIAPI
SbiProbeExtension (
- IN INTN ExtensionId,
- OUT INTN *ProbeResult
+ IN INTN ExtensionId,
+ OUT INTN *ProbeResult
);
/**
@@ -105,7 +105,7 @@ SbiProbeExtension (
VOID
EFIAPI
SbiGetMachineVendorId (
- OUT UINTN *MachineVendorId
+ OUT UINTN *MachineVendorId
);
/**
@@ -118,7 +118,7 @@ SbiGetMachineVendorId (
VOID
EFIAPI
SbiGetMachineArchId (
- OUT UINTN *MachineArchId
+ OUT UINTN *MachineArchId
);
/**
@@ -131,7 +131,7 @@ SbiGetMachineArchId (
VOID
EFIAPI
SbiGetMachineImplId (
- OUT UINTN *MachineImplId
+ OUT UINTN *MachineImplId
);
/**
@@ -160,9 +160,9 @@ SbiGetMachineImplId (
EFI_STATUS
EFIAPI
SbiHartStart (
- IN UINTN HartId,
- IN UINTN StartAddr,
- IN UINTN Priv
+ IN UINTN HartId,
+ IN UINTN StartAddr,
+ IN UINTN Priv
);
/**
@@ -199,8 +199,8 @@ SbiHartStop (
EFI_STATUS
EFIAPI
SbiHartGetStatus (
- IN UINTN HartId,
- OUT UINTN *HartStatus
+ IN UINTN HartId,
+ OUT UINTN *HartStatus
);
///
@@ -218,7 +218,7 @@ SbiHartGetStatus (
VOID
EFIAPI
SbiSetTimer (
- IN UINT64 Time
+ IN UINT64 Time
);
///
@@ -244,8 +244,8 @@ SbiSetTimer (
EFI_STATUS
EFIAPI
SbiSendIpi (
- IN UINTN *HartMask,
- IN UINTN HartMaskBase
+ IN UINTN *HartMask,
+ IN UINTN HartMaskBase
);
///
@@ -268,8 +268,8 @@ SbiSendIpi (
EFI_STATUS
EFIAPI
SbiRemoteFenceI (
- IN UINTN *HartMask,
- IN UINTN HartMaskBase
+ IN UINTN *HartMask,
+ IN UINTN HartMaskBase
);
/**
@@ -296,10 +296,10 @@ SbiRemoteFenceI (
EFI_STATUS
EFIAPI
SbiRemoteSfenceVma (
- IN UINTN *HartMask,
- IN UINTN HartMaskBase,
- IN UINTN StartAddr,
- IN UINTN Size
+ IN UINTN *HartMask,
+ IN UINTN HartMaskBase,
+ IN UINTN StartAddr,
+ IN UINTN Size
);
/**
@@ -327,11 +327,11 @@ SbiRemoteSfenceVma (
EFI_STATUS
EFIAPI
SbiRemoteSfenceVmaAsid (
- IN UINTN *HartMask,
- IN UINTN HartMaskBase,
- IN UINTN StartAddr,
- IN UINTN Size,
- IN UINTN Asid
+ IN UINTN *HartMask,
+ IN UINTN HartMaskBase,
+ IN UINTN StartAddr,
+ IN UINTN Size,
+ IN UINTN Asid
);
/**
@@ -363,11 +363,11 @@ SbiRemoteSfenceVmaAsid (
EFI_STATUS
EFIAPI
SbiRemoteHfenceGvmaVmid (
- IN UINTN *HartMask,
- IN UINTN HartMaskBase,
- IN UINTN StartAddr,
- IN UINTN Size,
- IN UINTN Vmid
+ IN UINTN *HartMask,
+ IN UINTN HartMaskBase,
+ IN UINTN StartAddr,
+ IN UINTN Size,
+ IN UINTN Vmid
);
/**
@@ -398,10 +398,10 @@ SbiRemoteHfenceGvmaVmid (
EFI_STATUS
EFIAPI
SbiRemoteHfenceGvma (
- IN UINTN *HartMask,
- IN UINTN HartMaskBase,
- IN UINTN StartAddr,
- IN UINTN Size
+ IN UINTN *HartMask,
+ IN UINTN HartMaskBase,
+ IN UINTN StartAddr,
+ IN UINTN Size
);
/**
@@ -433,11 +433,11 @@ SbiRemoteHfenceGvma (
EFI_STATUS
EFIAPI
SbiRemoteHfenceVvmaAsid (
- IN UINTN *HartMask,
- IN UINTN HartMaskBase,
- IN UINTN StartAddr,
- IN UINTN Size,
- IN UINTN Asid
+ IN UINTN *HartMask,
+ IN UINTN HartMaskBase,
+ IN UINTN StartAddr,
+ IN UINTN Size,
+ IN UINTN Asid
);
/**
@@ -468,10 +468,10 @@ SbiRemoteHfenceVvmaAsid (
EFI_STATUS
EFIAPI
SbiRemoteHfenceVvma (
- IN UINTN *HartMask,
- IN UINTN HartMaskBase,
- IN UINTN StartAddr,
- IN UINTN Size
+ IN UINTN *HartMask,
+ IN UINTN HartMaskBase,
+ IN UINTN StartAddr,
+ IN UINTN Size
);
///
@@ -506,8 +506,8 @@ SbiRemoteHfenceVvma (
EFI_STATUS
EFIAPI
SbiSystemReset (
- IN UINTN ResetType,
- IN UINTN ResetReason
+ IN UINTN ResetType,
+ IN UINTN ResetReason
);
///
@@ -531,9 +531,9 @@ SbiSystemReset (
EFI_STATUS
EFIAPI
SbiVendorCall (
- IN UINTN ExtensionId,
- IN UINTN FunctionId,
- IN UINTN NumArgs,
+ IN UINTN ExtensionId,
+ IN UINTN FunctionId,
+ IN UINTN NumArgs,
...
);
@@ -555,7 +555,7 @@ SbiVendorCall (
VOID
EFIAPI
SbiGetMscratch (
- OUT SBI_SCRATCH **ScratchSpace
+ OUT SBI_SCRATCH **ScratchSpace
);
/**
@@ -567,8 +567,8 @@ SbiGetMscratch (
VOID
EFIAPI
SbiGetMscratchHartid (
- IN UINTN HartId,
- OUT SBI_SCRATCH **ScratchSpace
+ IN UINTN HartId,
+ OUT SBI_SCRATCH **ScratchSpace
);
/**
@@ -579,7 +579,7 @@ SbiGetMscratchHartid (
VOID
EFIAPI
SbiGetFirmwareContext (
- OUT EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT **FirmwareContext
+ OUT EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT **FirmwareContext
);
/**
@@ -590,7 +590,7 @@ SbiGetFirmwareContext (
VOID
EFIAPI
SbiSetFirmwareContext (
- IN EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *FirmwareContext
+ IN EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *FirmwareContext
);
#endif
diff --git a/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVFirmwareContextLib.h b/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVFirmwareContextLib.h
index f35c4e0c51..7cf98abb99 100644
--- a/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVFirmwareContextLib.h
+++ b/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVFirmwareContextLib.h
@@ -1,7 +1,7 @@
/** @file
Library to get/set Firmware Context.
- Copyright (c) 2021, Hewlett Packard Development LP. All rights reserved.<BR>
+ Copyright (c) 2021-2022, Hewlett Packard Development LP. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -24,7 +24,7 @@
VOID
EFIAPI
GetFirmwareContextPointer (
- IN OUT EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT **FirmwareContextPtr
+ IN OUT EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT **FirmwareContextPtr
);
/**
@@ -37,7 +37,7 @@ GetFirmwareContextPointer (
VOID
EFIAPI
SetFirmwareContextPointer (
- IN EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *FirmwareContextPtr
+ IN EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *FirmwareContextPtr
);
#endif
diff --git a/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVPlatformTimerLib.h b/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVPlatformTimerLib.h
index dcd8734eb5..0ec39a15ce 100644
--- a/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVPlatformTimerLib.h
+++ b/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVPlatformTimerLib.h
@@ -10,12 +10,16 @@
#define RISCV_PLATFORM_TIMER_LIB_H_
UINT64
-RiscVReadMachineTimer (VOID);
+RiscVReadMachineTimer (
+ VOID
+ );
VOID
-RiscVSetMachineTimerCmp (UINT64);
+ RiscVSetMachineTimerCmp (UINT64);
UINT64
-RiscVReadMachineTimerCmp(VOID);
+RiscVReadMachineTimerCmp (
+ VOID
+ );
#endif
diff --git a/Silicon/RISC-V/ProcessorPkg/Include/OpensbiTypes.h b/Silicon/RISC-V/ProcessorPkg/Include/OpensbiTypes.h
index af34e8b0ae..6a62bb3aee 100644
--- a/Silicon/RISC-V/ProcessorPkg/Include/OpensbiTypes.h
+++ b/Silicon/RISC-V/ProcessorPkg/Include/OpensbiTypes.h
@@ -6,14 +6,15 @@
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
+
#ifndef EDK2_SBI_TYPES_H_
#define EDK2_SBI_TYPES_H_
#include <Base.h>
-typedef INT8 s8;
-typedef UINT8 u8;
-typedef UINT8 uint8_t;
+typedef INT8 s8;
+typedef UINT8 u8;
+typedef UINT8 uint8_t;
typedef INT16 s16;
typedef UINT16 u16;
@@ -32,49 +33,49 @@ typedef UINT64 uint64_t;
// PRILX is not used in EDK2 but we need to define it here because when
// defining our own types, this constant is not defined but used by OpenSBI.
-#define PRILX "016lx"
-
-typedef BOOLEAN bool;
-typedef unsigned long ulong;
-typedef UINT64 uintptr_t;
-typedef UINT64 size_t;
-typedef INT64 ssize_t;
-typedef UINT64 virtual_addr_t;
-typedef UINT64 virtual_size_t;
-typedef UINT64 physical_addr_t;
-typedef UINT64 physical_size_t;
-
-#define true TRUE
-#define false FALSE
-
-#define __packed __attribute__((packed))
-#define __noreturn __attribute__((noreturn))
-#define __aligned(x) __attribute__((aligned(x)))
-
-#if defined(__GNUC__) || defined(__clang__)
- #define likely(x) __builtin_expect((x), 1)
- #define unlikely(x) __builtin_expect((x), 0)
+#define PRILX "016lx"
+
+typedef BOOLEAN bool;
+typedef unsigned long ulong;
+typedef UINT64 uintptr_t;
+typedef UINT64 size_t;
+typedef INT64 ssize_t;
+typedef UINT64 virtual_addr_t;
+typedef UINT64 virtual_size_t;
+typedef UINT64 physical_addr_t;
+typedef UINT64 physical_size_t;
+
+#define true TRUE
+#define false FALSE
+
+#define __packed __attribute__((packed))
+#define __noreturn __attribute__((noreturn))
+#define __aligned(x) __attribute__((aligned(x)))
+
+#if defined (__GNUC__) || defined (__clang__)
+#define likely(x) __builtin_expect((x), 1)
+#define unlikely(x) __builtin_expect((x), 0)
#else
- #define likely(x) (x)
- #define unlikely(x) (x)
+#define likely(x) (x)
+#define unlikely(x) (x)
#endif
#undef offsetof
#ifdef __compiler_offsetof
-#define offsetof(TYPE, MEMBER) __compiler_offsetof(TYPE,MEMBER)
+#define offsetof(TYPE, MEMBER) __compiler_offsetof(TYPE,MEMBER)
#else
-#define offsetof(TYPE, MEMBER) ((size_t) &((TYPE *)0)->MEMBER)
+#define offsetof(TYPE, MEMBER) ((size_t) &((TYPE *)0)->MEMBER)
#endif
-#define container_of(ptr, type, member) ({ \
+#define container_of(ptr, type, member) ({ \
const typeof(((type *)0)->member) * __mptr = (ptr); \
(type *)((char *)__mptr - offsetof(type, member)); })
-#define array_size(x) (sizeof(x) / sizeof((x)[0]))
+#define array_size(x) (sizeof(x) / sizeof((x)[0]))
-#define CLAMP(a, lo, hi) MIN(MAX(a, lo), hi)
-#define ROUNDUP(a, b) ((((a)-1) / (b) + 1) * (b))
-#define ROUNDDOWN(a, b) ((a) / (b) * (b))
+#define CLAMP(a, lo, hi) MIN(MAX(a, lo), hi)
+#define ROUNDUP(a, b) ((((a)-1) / (b) + 1) * (b))
+#define ROUNDDOWN(a, b) ((a) / (b) * (b))
/* clang-format on */
diff --git a/Silicon/RISC-V/ProcessorPkg/Include/ProcessorSpecificHobData.h b/Silicon/RISC-V/ProcessorPkg/Include/ProcessorSpecificHobData.h
index 4b2a92e2f2..58dda7ff5b 100644
--- a/Silicon/RISC-V/ProcessorPkg/Include/ProcessorSpecificHobData.h
+++ b/Silicon/RISC-V/ProcessorPkg/Include/ProcessorSpecificHobData.h
@@ -6,6 +6,7 @@
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
+
#ifndef RISC_V_PROCESSOR_SPECIFIC_HOB_DATA_H_
#define RISC_V_PROCESSOR_SPECIFIC_HOB_DATA_H_
@@ -13,10 +14,10 @@
#include <IndustryStandard/SmBios.h>
#include <SmbiosProcessorSpecificData.h>
-#define TO_BE_FILLED 0
-#define TO_BE_FILLED_BY_VENDOR 0
-#define TO_BE_FILLED_BY_RISC_V_SMBIOS_DXE_DRIVER 0
-#define TO_BE_FILLED_BY_CODE 0
+#define TO_BE_FILLED 0
+#define TO_BE_FILLED_BY_VENDOR 0
+#define TO_BE_FILLED_BY_RISC_V_SMBIOS_DXE_DRIVER 0
+#define TO_BE_FILLED_BY_CODE 0
#pragma pack(1)
@@ -24,71 +25,71 @@
/// RISC-V processor specific data HOB
///
typedef struct {
- EFI_GUID ParentProcessorGuid;
- UINTN ParentProcessorUid;
- EFI_GUID CoreGuid;
- VOID *Context; // The additional information of this core which
- // built in PEI phase and carried to DXE phase.
- // The content is processor or platform specific.
- SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA ProcessorSpecificData;
+ EFI_GUID ParentProcessorGuid;
+ UINTN ParentProcessorUid;
+ EFI_GUID CoreGuid;
+ VOID *Context; // The additional information of this core which
+ // built in PEI phase and carried to DXE phase.
+ // The content is processor or platform specific.
+ SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA ProcessorSpecificData;
} RISC_V_PROCESSOR_SPECIFIC_HOB_DATA;
///
/// RISC-V SMBIOS type 4 (Processor) GUID data HOB
///
typedef struct {
- EFI_GUID ProcessorGuid;
- UINTN ProcessorUid;
- SMBIOS_TABLE_TYPE4 SmbiosType4Processor;
- UINT16 EndingZero;
+ EFI_GUID ProcessorGuid;
+ UINTN ProcessorUid;
+ SMBIOS_TABLE_TYPE4 SmbiosType4Processor;
+ UINT16 EndingZero;
} RISC_V_PROCESSOR_TYPE4_HOB_DATA;
-#define RISC_V_CACHE_INFO_NOT_PROVIDED 0xFFFF
-
-#define RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_MASK 0x7
- #define RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_1 0x01
- #define RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_2 0x02
- #define RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_3 0x03
-
-#define RISC_V_CACHE_CONFIGURATION_SOCKET_BIT_POSITION 3
-#define RISC_V_CACHE_CONFIGURATION_SOCKET_MASK (0x1 << RISC_V_CACHE_CONFIGURATION_SOCKET_BIT_POSITION)
- #define RISC_V_CACHE_CONFIGURATION_SOCKET_SOCKETED (0x1 << RISC_V_CACHE_CONFIGURATION_SOCKET_BIT_POSITION)
-
-#define RISC_V_CACHE_CONFIGURATION_LOCATION_BIT_POSITION 5
-#define RISC_V_CACHE_CONFIGURATION_LOCATION_MASK (0x3 << RISC_V_CACHE_CONFIGURATION_LOCATION_BIT_POSITION)
- #define RISC_V_CACHE_CONFIGURATION_LOCATION_INTERNAL (0x0 << RISC_V_CACHE_CONFIGURATION_LOCATION_BIT_POSITION)
- #define RISC_V_CACHE_CONFIGURATION_LOCATION_EXTERNAL (0x1 << RISC_V_CACHE_CONFIGURATION_LOCATION_BIT_POSITION)
- #define RISC_V_CACHE_CONFIGURATION_LOCATION_RESERVED (0x2 << RISC_V_CACHE_CONFIGURATION_LOCATION_BIT_POSITION)
- #define RISC_V_CACHE_CONFIGURATION_LOCATION_UNKNOWN (0x3 << RISC_V_CACHE_CONFIGURATION_LOCATION_BIT_POSITION)
-
-#define RISC_V_CACHE_CONFIGURATION_ENABLE_BIT_POSITION 7
-#define RISC_V_CACHE_CONFIGURATION_ENABLE_MASK (0x1 << RISC_V_CACHE_CONFIGURATION_ENABLE_BIT_POSITION)
- #define RISC_V_CACHE_CONFIGURATION_ENABLED (0x1 << RISC_V_CACHE_CONFIGURATION_ENABLE_BIT_POSITION)
-
-#define RISC_V_CACHE_CONFIGURATION_MODE_BIT_POSITION 8
-#define RISC_V_CACHE_CONFIGURATION_MODE_MASK (0x3 << RISC_V_CACHE_CONFIGURATION_MODE_BIT_POSITION)
- #define RISC_V_CACHE_CONFIGURATION_MODE_WT (0x0 << RISC_V_CACHE_CONFIGURATION_MODE_BIT_POSITION)
- #define RISC_V_CACHE_CONFIGURATION_MODE_WB (0x1 << RISC_V_CACHE_CONFIGURATION_MODE_BIT_POSITION)
- #define RISC_V_CACHE_CONFIGURATION_MODE_VARIES (0x2 << RISC_V_CACHE_CONFIGURATION_MODE_BIT_POSITION)
- #define RISC_V_CACHE_CONFIGURATION_MODE_UNKNOWN (0x3 << RISC_V_CACHE_CONFIGURATION_MODE_BIT_POSITION)
+#define RISC_V_CACHE_INFO_NOT_PROVIDED 0xFFFF
+
+#define RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_MASK 0x7
+#define RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_1 0x01
+#define RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_2 0x02
+#define RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_3 0x03
+
+#define RISC_V_CACHE_CONFIGURATION_SOCKET_BIT_POSITION 3
+#define RISC_V_CACHE_CONFIGURATION_SOCKET_MASK (0x1 << RISC_V_CACHE_CONFIGURATION_SOCKET_BIT_POSITION)
+#define RISC_V_CACHE_CONFIGURATION_SOCKET_SOCKETED (0x1 << RISC_V_CACHE_CONFIGURATION_SOCKET_BIT_POSITION)
+
+#define RISC_V_CACHE_CONFIGURATION_LOCATION_BIT_POSITION 5
+#define RISC_V_CACHE_CONFIGURATION_LOCATION_MASK (0x3 << RISC_V_CACHE_CONFIGURATION_LOCATION_BIT_POSITION)
+#define RISC_V_CACHE_CONFIGURATION_LOCATION_INTERNAL (0x0 << RISC_V_CACHE_CONFIGURATION_LOCATION_BIT_POSITION)
+#define RISC_V_CACHE_CONFIGURATION_LOCATION_EXTERNAL (0x1 << RISC_V_CACHE_CONFIGURATION_LOCATION_BIT_POSITION)
+#define RISC_V_CACHE_CONFIGURATION_LOCATION_RESERVED (0x2 << RISC_V_CACHE_CONFIGURATION_LOCATION_BIT_POSITION)
+#define RISC_V_CACHE_CONFIGURATION_LOCATION_UNKNOWN (0x3 << RISC_V_CACHE_CONFIGURATION_LOCATION_BIT_POSITION)
+
+#define RISC_V_CACHE_CONFIGURATION_ENABLE_BIT_POSITION 7
+#define RISC_V_CACHE_CONFIGURATION_ENABLE_MASK (0x1 << RISC_V_CACHE_CONFIGURATION_ENABLE_BIT_POSITION)
+#define RISC_V_CACHE_CONFIGURATION_ENABLED (0x1 << RISC_V_CACHE_CONFIGURATION_ENABLE_BIT_POSITION)
+
+#define RISC_V_CACHE_CONFIGURATION_MODE_BIT_POSITION 8
+#define RISC_V_CACHE_CONFIGURATION_MODE_MASK (0x3 << RISC_V_CACHE_CONFIGURATION_MODE_BIT_POSITION)
+#define RISC_V_CACHE_CONFIGURATION_MODE_WT (0x0 << RISC_V_CACHE_CONFIGURATION_MODE_BIT_POSITION)
+#define RISC_V_CACHE_CONFIGURATION_MODE_WB (0x1 << RISC_V_CACHE_CONFIGURATION_MODE_BIT_POSITION)
+#define RISC_V_CACHE_CONFIGURATION_MODE_VARIES (0x2 << RISC_V_CACHE_CONFIGURATION_MODE_BIT_POSITION)
+#define RISC_V_CACHE_CONFIGURATION_MODE_UNKNOWN (0x3 << RISC_V_CACHE_CONFIGURATION_MODE_BIT_POSITION)
///
/// RISC-V SMBIOS type 7 (Cache) GUID data HOB
///
typedef struct {
- EFI_GUID ProcessorGuid;
- UINTN ProcessorUid;
- SMBIOS_TABLE_TYPE7 SmbiosType7Cache;
- UINT16 EndingZero;
+ EFI_GUID ProcessorGuid;
+ UINTN ProcessorUid;
+ SMBIOS_TABLE_TYPE7 SmbiosType7Cache;
+ UINT16 EndingZero;
} RISC_V_PROCESSOR_TYPE7_HOB_DATA;
///
/// RISC-V SMBIOS type 7 (Cache) GUID data HOB
///
typedef struct {
- RISC_V_PROCESSOR_TYPE4_HOB_DATA *Processor;
- RISC_V_PROCESSOR_TYPE7_HOB_DATA *L1Cache;
- RISC_V_PROCESSOR_TYPE7_HOB_DATA *L2Cache;
- RISC_V_PROCESSOR_TYPE7_HOB_DATA *L3Cache;
+ RISC_V_PROCESSOR_TYPE4_HOB_DATA *Processor;
+ RISC_V_PROCESSOR_TYPE7_HOB_DATA *L1Cache;
+ RISC_V_PROCESSOR_TYPE7_HOB_DATA *L2Cache;
+ RISC_V_PROCESSOR_TYPE7_HOB_DATA *L3Cache;
} RISC_V_PROCESSOR_SMBIOS_HOB_DATA;
#pragma pack()
diff --git a/Silicon/RISC-V/ProcessorPkg/Include/RiscVImpl.h b/Silicon/RISC-V/ProcessorPkg/Include/RiscVImpl.h
index 14092df174..261de69869 100644
--- a/Silicon/RISC-V/ProcessorPkg/Include/RiscVImpl.h
+++ b/Silicon/RISC-V/ProcessorPkg/Include/RiscVImpl.h
@@ -1,7 +1,7 @@
/** @file
RISC-V package definitions.
- Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+ Copyright (c) 2016 - 2022, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -20,7 +20,7 @@
.p2align 2 ; \
Name:
-#define ASM_FUNC(Name) _ASM_FUNC(ASM_PFX(Name), .text. ## Name)
+#define ASM_FUNC(Name) _ASM_FUNC(ASM_PFX(Name), .text. ## Name)
#if defined (MDE_CPU_RISCV64)
typedef UINT64 RISC_V_REGS_PROTOTYPE;
@@ -31,8 +31,8 @@ typedef UINT64 RISC_V_REGS_PROTOTYPE;
// Structure for 128-bit value
//
typedef struct {
- UINT64 Value64_L;
- UINT64 Value64_H;
+ UINT64 Value64_L;
+ UINT64 Value64_H;
} RISCV_UINT128;
#define RISCV_MACHINE_CONTEXT_SIZE 0x1000
@@ -42,46 +42,46 @@ typedef struct _RISCV_MACHINE_MODE_CONTEXT RISCV_MACHINE_MODE_CONTEXT;
/// Exception handlers in context.
///
typedef struct _EXCEPTION_HANDLER_CONTEXT {
- EFI_PHYSICAL_ADDRESS InstAddressMisalignedHander;
- EFI_PHYSICAL_ADDRESS InstAccessFaultHander;
- EFI_PHYSICAL_ADDRESS IllegalInstHander;
- EFI_PHYSICAL_ADDRESS BreakpointHander;
- EFI_PHYSICAL_ADDRESS LoadAddrMisalignedHander;
- EFI_PHYSICAL_ADDRESS LoadAccessFaultHander;
- EFI_PHYSICAL_ADDRESS StoreAmoAddrMisalignedHander;
- EFI_PHYSICAL_ADDRESS StoreAmoAccessFaultHander;
- EFI_PHYSICAL_ADDRESS EnvCallFromUModeHander;
- EFI_PHYSICAL_ADDRESS EnvCallFromSModeHander;
- EFI_PHYSICAL_ADDRESS EnvCallFromHModeHander;
- EFI_PHYSICAL_ADDRESS EnvCallFromMModeHander;
+ EFI_PHYSICAL_ADDRESS InstAddressMisalignedHander;
+ EFI_PHYSICAL_ADDRESS InstAccessFaultHander;
+ EFI_PHYSICAL_ADDRESS IllegalInstHander;
+ EFI_PHYSICAL_ADDRESS BreakpointHander;
+ EFI_PHYSICAL_ADDRESS LoadAddrMisalignedHander;
+ EFI_PHYSICAL_ADDRESS LoadAccessFaultHander;
+ EFI_PHYSICAL_ADDRESS StoreAmoAddrMisalignedHander;
+ EFI_PHYSICAL_ADDRESS StoreAmoAccessFaultHander;
+ EFI_PHYSICAL_ADDRESS EnvCallFromUModeHander;
+ EFI_PHYSICAL_ADDRESS EnvCallFromSModeHander;
+ EFI_PHYSICAL_ADDRESS EnvCallFromHModeHander;
+ EFI_PHYSICAL_ADDRESS EnvCallFromMModeHander;
} EXCEPTION_HANDLER_CONTEXT;
///
/// Exception handlers in context.
///
typedef struct _INTERRUPT_HANDLER_CONTEXT {
- EFI_PHYSICAL_ADDRESS SoftwareIntHandler;
- EFI_PHYSICAL_ADDRESS TimerIntHandler;
+ EFI_PHYSICAL_ADDRESS SoftwareIntHandler;
+ EFI_PHYSICAL_ADDRESS TimerIntHandler;
} INTERRUPT_HANDLER_CONTEXT;
///
/// Interrupt handlers in context.
///
typedef struct _TRAP_HANDLER_CONTEXT {
- EXCEPTION_HANDLER_CONTEXT ExceptionHandlerContext;
- INTERRUPT_HANDLER_CONTEXT IntHandlerContext;
+ EXCEPTION_HANDLER_CONTEXT ExceptionHandlerContext;
+ INTERRUPT_HANDLER_CONTEXT IntHandlerContext;
} TRAP_HANDLER_CONTEXT;
///
/// Machine mode context used for saveing hart-local context.
///
typedef struct _RISCV_MACHINE_MODE_CONTEXT {
- EFI_PHYSICAL_ADDRESS PeiService; /// PEI service.
- EFI_PHYSICAL_ADDRESS MachineModeTrapHandler; /// Machine mode trap handler.
- EFI_PHYSICAL_ADDRESS HypervisorModeTrapHandler; /// Hypervisor mode trap handler.
- EFI_PHYSICAL_ADDRESS SupervisorModeTrapHandler; /// Supervisor mode trap handler.
- EFI_PHYSICAL_ADDRESS UserModeTrapHandler; /// USer mode trap handler.
- TRAP_HANDLER_CONTEXT MModeHandler; /// Handler for machine mode.
+ EFI_PHYSICAL_ADDRESS PeiService; /// PEI service.
+ EFI_PHYSICAL_ADDRESS MachineModeTrapHandler; /// Machine mode trap handler.
+ EFI_PHYSICAL_ADDRESS HypervisorModeTrapHandler; /// Hypervisor mode trap handler.
+ EFI_PHYSICAL_ADDRESS SupervisorModeTrapHandler; /// Supervisor mode trap handler.
+ EFI_PHYSICAL_ADDRESS UserModeTrapHandler; /// USer mode trap handler.
+ TRAP_HANDLER_CONTEXT MModeHandler; /// Handler for machine mode.
} RISCV_MACHINE_MODE_CONTEXT;
#endif
diff --git a/Silicon/RISC-V/ProcessorPkg/Include/SmbiosProcessorSpecificData.h b/Silicon/RISC-V/ProcessorPkg/Include/SmbiosProcessorSpecificData.h
index 85b8dcbe20..090c5320e0 100644
--- a/Silicon/RISC-V/ProcessorPkg/Include/SmbiosProcessorSpecificData.h
+++ b/Silicon/RISC-V/ProcessorPkg/Include/SmbiosProcessorSpecificData.h
@@ -8,6 +8,7 @@
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
+
#ifndef SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA_H_
#define SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA_H_
@@ -16,42 +17,41 @@
#pragma pack(1)
-typedef enum{
+typedef enum {
RegisterUnsupported = 0x00,
RegisterLen32 = 0x01,
RegisterLen64 = 0x02,
RegisterLen128 = 0x03
} RISC_V_REGISTER_LENGTH;
-#define SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA_REVISION 0x100
+#define SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA_REVISION 0x100
-#define SMBIOS_RISC_V_PSD_MACHINE_MODE_SUPPORTED (0x01 << 0)
-#define SMBIOS_RISC_V_PSD_SUPERVISOR_MODE_SUPPORTED (0x01 << 2)
-#define SMBIOS_RISC_V_PSD_USER_MODE_SUPPORTED (0x01 << 3)
-#define SMBIOS_RISC_V_PSD_DEBUG_MODE_SUPPORTED (0x01 << 7)
+#define SMBIOS_RISC_V_PSD_MACHINE_MODE_SUPPORTED (0x01 << 0)
+#define SMBIOS_RISC_V_PSD_SUPERVISOR_MODE_SUPPORTED (0x01 << 2)
+#define SMBIOS_RISC_V_PSD_USER_MODE_SUPPORTED (0x01 << 3)
+#define SMBIOS_RISC_V_PSD_DEBUG_MODE_SUPPORTED (0x01 << 7)
///
/// RISC-V processor specific data for SMBIOS type 44
///
typedef struct {
- UINT16 Revision;
- UINT8 Length;
- RISCV_UINT128 HartId;
- UINT8 BootHartId;
- RISCV_UINT128 MachineVendorId;
- RISCV_UINT128 MachineArchId;
- RISCV_UINT128 MachineImplId;
- UINT32 InstSetSupported;
- UINT8 PrivilegeModeSupported;
- RISCV_UINT128 MModeExcepDelegation;
- RISCV_UINT128 MModeInterruptDelegation;
- UINT8 HartXlen;
- UINT8 MachineModeXlen;
- UINT8 Reserved;
- UINT8 SupervisorModeXlen;
- UINT8 UserModeXlen;
+ UINT16 Revision;
+ UINT8 Length;
+ RISCV_UINT128 HartId;
+ UINT8 BootHartId;
+ RISCV_UINT128 MachineVendorId;
+ RISCV_UINT128 MachineArchId;
+ RISCV_UINT128 MachineImplId;
+ UINT32 InstSetSupported;
+ UINT8 PrivilegeModeSupported;
+ RISCV_UINT128 MModeExcepDelegation;
+ RISCV_UINT128 MModeInterruptDelegation;
+ UINT8 HartXlen;
+ UINT8 MachineModeXlen;
+ UINT8 Reserved;
+ UINT8 SupervisorModeXlen;
+ UINT8 UserModeXlen;
} SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA;
#pragma pack()
#endif
-
diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVExceptionLib/CpuExceptionHandlerLib.h b/Silicon/RISC-V/ProcessorPkg/Library/RiscVExceptionLib/CpuExceptionHandlerLib.h
index b316510020..350d20110a 100644
--- a/Silicon/RISC-V/ProcessorPkg/Library/RiscVExceptionLib/CpuExceptionHandlerLib.h
+++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVExceptionLib/CpuExceptionHandlerLib.h
@@ -2,7 +2,7 @@
RISC-V Exception Handler library definition file.
- Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+ Copyright (c) 2019-2022, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -11,96 +11,99 @@
#ifndef RISCV_CPU_EXECPTION_HANDLER_LIB_H_
#define RISCV_CPU_EXECPTION_HANDLER_LIB_H_
-extern void SupervisorModeTrap(void);
+extern void
+SupervisorModeTrap (
+ void
+ );
//
// Index of SMode trap register
//
-#define SMODE_TRAP_REGS_zero 0
-#define SMODE_TRAP_REGS_ra 1
-#define SMODE_TRAP_REGS_sp 2
-#define SMODE_TRAP_REGS_gp 3
-#define SMODE_TRAP_REGS_tp 4
-#define SMODE_TRAP_REGS_t0 5
-#define SMODE_TRAP_REGS_t1 6
-#define SMODE_TRAP_REGS_t2 7
-#define SMODE_TRAP_REGS_s0 8
-#define SMODE_TRAP_REGS_s1 9
-#define SMODE_TRAP_REGS_a0 10
-#define SMODE_TRAP_REGS_a1 11
-#define SMODE_TRAP_REGS_a2 12
-#define SMODE_TRAP_REGS_a3 13
-#define SMODE_TRAP_REGS_a4 14
-#define SMODE_TRAP_REGS_a5 15
-#define SMODE_TRAP_REGS_a6 16
-#define SMODE_TRAP_REGS_a7 17
-#define SMODE_TRAP_REGS_s2 18
-#define SMODE_TRAP_REGS_s3 19
-#define SMODE_TRAP_REGS_s4 20
-#define SMODE_TRAP_REGS_s5 21
-#define SMODE_TRAP_REGS_s6 22
-#define SMODE_TRAP_REGS_s7 23
-#define SMODE_TRAP_REGS_s8 24
-#define SMODE_TRAP_REGS_s9 25
-#define SMODE_TRAP_REGS_s10 26
-#define SMODE_TRAP_REGS_s11 27
-#define SMODE_TRAP_REGS_t3 28
-#define SMODE_TRAP_REGS_t4 29
-#define SMODE_TRAP_REGS_t5 30
-#define SMODE_TRAP_REGS_t6 31
-#define SMODE_TRAP_REGS_sepc 32
-#define SMODE_TRAP_REGS_sstatus 33
-#define SMODE_TRAP_REGS_sie 34
-#define SMODE_TRAP_REGS_last 35
+#define SMODE_TRAP_REGS_zero 0
+#define SMODE_TRAP_REGS_ra 1
+#define SMODE_TRAP_REGS_sp 2
+#define SMODE_TRAP_REGS_gp 3
+#define SMODE_TRAP_REGS_tp 4
+#define SMODE_TRAP_REGS_t0 5
+#define SMODE_TRAP_REGS_t1 6
+#define SMODE_TRAP_REGS_t2 7
+#define SMODE_TRAP_REGS_s0 8
+#define SMODE_TRAP_REGS_s1 9
+#define SMODE_TRAP_REGS_a0 10
+#define SMODE_TRAP_REGS_a1 11
+#define SMODE_TRAP_REGS_a2 12
+#define SMODE_TRAP_REGS_a3 13
+#define SMODE_TRAP_REGS_a4 14
+#define SMODE_TRAP_REGS_a5 15
+#define SMODE_TRAP_REGS_a6 16
+#define SMODE_TRAP_REGS_a7 17
+#define SMODE_TRAP_REGS_s2 18
+#define SMODE_TRAP_REGS_s3 19
+#define SMODE_TRAP_REGS_s4 20
+#define SMODE_TRAP_REGS_s5 21
+#define SMODE_TRAP_REGS_s6 22
+#define SMODE_TRAP_REGS_s7 23
+#define SMODE_TRAP_REGS_s8 24
+#define SMODE_TRAP_REGS_s9 25
+#define SMODE_TRAP_REGS_s10 26
+#define SMODE_TRAP_REGS_s11 27
+#define SMODE_TRAP_REGS_t3 28
+#define SMODE_TRAP_REGS_t4 29
+#define SMODE_TRAP_REGS_t5 30
+#define SMODE_TRAP_REGS_t6 31
+#define SMODE_TRAP_REGS_sepc 32
+#define SMODE_TRAP_REGS_sstatus 33
+#define SMODE_TRAP_REGS_sie 34
+#define SMODE_TRAP_REGS_last 35
-#define SMODE_TRAP_REGS_OFFSET(x) ((SMODE_TRAP_REGS_##x) * __SIZEOF_POINTER__)
-#define SMODE_TRAP_REGS_SIZE SMODE_TRAP_REGS_OFFSET(last)
+#define SMODE_TRAP_REGS_OFFSET(x) ((SMODE_TRAP_REGS_##x) * __SIZEOF_POINTER__)
+#define SMODE_TRAP_REGS_SIZE SMODE_TRAP_REGS_OFFSET(last)
#pragma pack(1)
typedef struct {
-//
-// Below are follow the format of EFI_SYSTEM_CONTEXT
-//
- RISC_V_REGS_PROTOTYPE zero;
- RISC_V_REGS_PROTOTYPE ra;
- RISC_V_REGS_PROTOTYPE sp;
- RISC_V_REGS_PROTOTYPE gp;
- RISC_V_REGS_PROTOTYPE tp;
- RISC_V_REGS_PROTOTYPE t0;
- RISC_V_REGS_PROTOTYPE t1;
- RISC_V_REGS_PROTOTYPE t2;
- RISC_V_REGS_PROTOTYPE s0;
- RISC_V_REGS_PROTOTYPE s1;
- RISC_V_REGS_PROTOTYPE a0;
- RISC_V_REGS_PROTOTYPE a1;
- RISC_V_REGS_PROTOTYPE a2;
- RISC_V_REGS_PROTOTYPE a3;
- RISC_V_REGS_PROTOTYPE a4;
- RISC_V_REGS_PROTOTYPE a5;
- RISC_V_REGS_PROTOTYPE a6;
- RISC_V_REGS_PROTOTYPE a7;
- RISC_V_REGS_PROTOTYPE s2;
- RISC_V_REGS_PROTOTYPE s3;
- RISC_V_REGS_PROTOTYPE s4;
- RISC_V_REGS_PROTOTYPE s5;
- RISC_V_REGS_PROTOTYPE s6;
- RISC_V_REGS_PROTOTYPE s7;
- RISC_V_REGS_PROTOTYPE s8;
- RISC_V_REGS_PROTOTYPE s9;
- RISC_V_REGS_PROTOTYPE s10;
- RISC_V_REGS_PROTOTYPE s11;
- RISC_V_REGS_PROTOTYPE t3;
- RISC_V_REGS_PROTOTYPE t4;
- RISC_V_REGS_PROTOTYPE t5;
- RISC_V_REGS_PROTOTYPE t6;
-//
-// Below are the additional information to
-// EFI_SYSTEM_CONTEXT, private to supervisor mode trap
-// and not public to EFI environment.
-//
- RISC_V_REGS_PROTOTYPE sepc;
- RISC_V_REGS_PROTOTYPE sstatus;
- RISC_V_REGS_PROTOTYPE sie;
+ //
+ // Below are follow the format of EFI_SYSTEM_CONTEXT
+ //
+ RISC_V_REGS_PROTOTYPE zero;
+ RISC_V_REGS_PROTOTYPE ra;
+ RISC_V_REGS_PROTOTYPE sp;
+ RISC_V_REGS_PROTOTYPE gp;
+ RISC_V_REGS_PROTOTYPE tp;
+ RISC_V_REGS_PROTOTYPE t0;
+ RISC_V_REGS_PROTOTYPE t1;
+ RISC_V_REGS_PROTOTYPE t2;
+ RISC_V_REGS_PROTOTYPE s0;
+ RISC_V_REGS_PROTOTYPE s1;
+ RISC_V_REGS_PROTOTYPE a0;
+ RISC_V_REGS_PROTOTYPE a1;
+ RISC_V_REGS_PROTOTYPE a2;
+ RISC_V_REGS_PROTOTYPE a3;
+ RISC_V_REGS_PROTOTYPE a4;
+ RISC_V_REGS_PROTOTYPE a5;
+ RISC_V_REGS_PROTOTYPE a6;
+ RISC_V_REGS_PROTOTYPE a7;
+ RISC_V_REGS_PROTOTYPE s2;
+ RISC_V_REGS_PROTOTYPE s3;
+ RISC_V_REGS_PROTOTYPE s4;
+ RISC_V_REGS_PROTOTYPE s5;
+ RISC_V_REGS_PROTOTYPE s6;
+ RISC_V_REGS_PROTOTYPE s7;
+ RISC_V_REGS_PROTOTYPE s8;
+ RISC_V_REGS_PROTOTYPE s9;
+ RISC_V_REGS_PROTOTYPE s10;
+ RISC_V_REGS_PROTOTYPE s11;
+ RISC_V_REGS_PROTOTYPE t3;
+ RISC_V_REGS_PROTOTYPE t4;
+ RISC_V_REGS_PROTOTYPE t5;
+ RISC_V_REGS_PROTOTYPE t6;
+ //
+ // Below are the additional information to
+ // EFI_SYSTEM_CONTEXT, private to supervisor mode trap
+ // and not public to EFI environment.
+ //
+ RISC_V_REGS_PROTOTYPE sepc;
+ RISC_V_REGS_PROTOTYPE sstatus;
+ RISC_V_REGS_PROTOTYPE sie;
} SMODE_TRAP_REGISTERS;
#pragma pack()
diff --git a/Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxe.h b/Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxe.h
index c2c2739434..9d70d7b6e8 100644
--- a/Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxe.h
+++ b/Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxe.h
@@ -1,7 +1,7 @@
/** @file
RISC-V CPU DXE module header file.
- Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+ Copyright (c) 2016 - 2022, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -38,10 +38,10 @@
EFI_STATUS
EFIAPI
CpuFlushCpuDataCache (
- IN EFI_CPU_ARCH_PROTOCOL *This,
- IN EFI_PHYSICAL_ADDRESS Start,
- IN UINT64 Length,
- IN EFI_CPU_FLUSH_TYPE FlushType
+ IN EFI_CPU_ARCH_PROTOCOL *This,
+ IN EFI_PHYSICAL_ADDRESS Start,
+ IN UINT64 Length,
+ IN EFI_CPU_FLUSH_TYPE FlushType
);
/**
@@ -56,7 +56,7 @@ CpuFlushCpuDataCache (
EFI_STATUS
EFIAPI
CpuEnableInterrupt (
- IN EFI_CPU_ARCH_PROTOCOL *This
+ IN EFI_CPU_ARCH_PROTOCOL *This
);
/**
@@ -71,7 +71,7 @@ CpuEnableInterrupt (
EFI_STATUS
EFIAPI
CpuDisableInterrupt (
- IN EFI_CPU_ARCH_PROTOCOL *This
+ IN EFI_CPU_ARCH_PROTOCOL *This
);
/**
@@ -87,8 +87,8 @@ CpuDisableInterrupt (
EFI_STATUS
EFIAPI
CpuGetInterruptState (
- IN EFI_CPU_ARCH_PROTOCOL *This,
- OUT BOOLEAN *State
+ IN EFI_CPU_ARCH_PROTOCOL *This,
+ OUT BOOLEAN *State
);
/**
@@ -106,8 +106,8 @@ CpuGetInterruptState (
EFI_STATUS
EFIAPI
CpuInit (
- IN EFI_CPU_ARCH_PROTOCOL *This,
- IN EFI_CPU_INIT_TYPE InitType
+ IN EFI_CPU_ARCH_PROTOCOL *This,
+ IN EFI_CPU_INIT_TYPE InitType
);
/**
@@ -133,9 +133,9 @@ CpuInit (
EFI_STATUS
EFIAPI
CpuRegisterInterruptHandler (
- IN EFI_CPU_ARCH_PROTOCOL *This,
- IN EFI_EXCEPTION_TYPE InterruptType,
- IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler
+ IN EFI_CPU_ARCH_PROTOCOL *This,
+ IN EFI_EXCEPTION_TYPE InterruptType,
+ IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler
);
/**
@@ -164,10 +164,10 @@ CpuRegisterInterruptHandler (
EFI_STATUS
EFIAPI
CpuGetTimerValue (
- IN EFI_CPU_ARCH_PROTOCOL *This,
- IN UINT32 TimerIndex,
- OUT UINT64 *TimerValue,
- OUT UINT64 *TimerPeriod OPTIONAL
+ IN EFI_CPU_ARCH_PROTOCOL *This,
+ IN UINT32 TimerIndex,
+ OUT UINT64 *TimerValue,
+ OUT UINT64 *TimerPeriod OPTIONAL
);
/**
@@ -189,11 +189,10 @@ CpuGetTimerValue (
EFI_STATUS
EFIAPI
CpuSetMemoryAttributes (
- IN EFI_CPU_ARCH_PROTOCOL *This,
- IN EFI_PHYSICAL_ADDRESS BaseAddress,
- IN UINT64 Length,
- IN UINT64 Attributes
+ IN EFI_CPU_ARCH_PROTOCOL *This,
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ IN UINT64 Length,
+ IN UINT64 Attributes
);
#endif
-
diff --git a/Silicon/RISC-V/ProcessorPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.h b/Silicon/RISC-V/ProcessorPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.h
index 1072877ad8..cbeb5ec37d 100644
--- a/Silicon/RISC-V/ProcessorPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.h
+++ b/Silicon/RISC-V/ProcessorPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.h
@@ -1,7 +1,7 @@
/** @file
RISC-V SMBIOS Builder DXE module header file.
- Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+ Copyright (c) 2019-2022, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -20,4 +20,3 @@
#include <ProcessorSpecificHobData.h>
#include <SmbiosProcessorSpecificData.h>
#endif
-
diff --git a/Silicon/RISC-V/ProcessorPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerOpenSbi.c b/Silicon/RISC-V/ProcessorPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerOpenSbi.c
index 9aa74b4f9f..23607a4eba 100644
--- a/Silicon/RISC-V/ProcessorPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerOpenSbi.c
+++ b/Silicon/RISC-V/ProcessorPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerOpenSbi.c
@@ -1,7 +1,7 @@
/** @file
PEI Services Table Pointer Library.
- Copyright (c) 2019 - 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+ Copyright (c) 2019 - 2022, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@@ -28,18 +28,20 @@
VOID
EFIAPI
SetPeiServicesTablePointer (
- IN CONST EFI_PEI_SERVICES ** PeiServicesTablePointer
+ IN CONST EFI_PEI_SERVICES **PeiServicesTablePointer
)
{
- EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *FirmwareContext;
+ EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *FirmwareContext;
GetFirmwareContextPointer (&FirmwareContext);
FirmwareContext->PeiServiceTable = (VOID *)(UINTN)PeiServicesTablePointer;
- DEBUG ((DEBUG_INFO, "Set PEI Service 0x%x at OpenSBI Firmware Context at 0x%x\n",
- PeiServicesTablePointer,
- FirmwareContext
- ));
+ DEBUG ((
+ DEBUG_INFO,
+ "Set PEI Service 0x%x at OpenSBI Firmware Context at 0x%x\n",
+ PeiServicesTablePointer,
+ FirmwareContext
+ ));
}
/**
@@ -60,7 +62,7 @@ GetPeiServicesTablePointer (
VOID
)
{
- EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *FirmwareContext;
+ EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *FirmwareContext;
GetFirmwareContextPointer (&FirmwareContext);
return (CONST EFI_PEI_SERVICES **)FirmwareContext->PeiServiceTable;
@@ -81,8 +83,8 @@ GetPeiServicesTablePointer (
EFI_STATUS
EFIAPI
PeiServicesTablePointerLibOpenSbiConstructor (
- IN EFI_PEI_FILE_HANDLE FileHandle,
- IN CONST EFI_PEI_SERVICES **PeiServices
+ IN EFI_PEI_FILE_HANDLE FileHandle,
+ IN CONST EFI_PEI_SERVICES **PeiServices
)
{
SetPeiServicesTablePointer (PeiServices);
diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVEdk2SbiLib/RiscVEdk2SbiLib.c b/Silicon/RISC-V/ProcessorPkg/Library/RiscVEdk2SbiLib/RiscVEdk2SbiLib.c
index a51139542d..a25e16ab34 100644
--- a/Silicon/RISC-V/ProcessorPkg/Library/RiscVEdk2SbiLib/RiscVEdk2SbiLib.c
+++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVEdk2SbiLib/RiscVEdk2SbiLib.c
@@ -31,14 +31,13 @@
#include <sbi/sbi_types.h>
#include <sbi/sbi_init.h>
-
//
// Maximum arguments for SBI ecall
// It's possible to pass more but no SBI call uses more as of SBI 0.2.
// The additional arguments would have to be passed on the stack instead of as
// registers, like it's done now.
//
-#define SBI_CALL_MAX_ARGS 6
+#define SBI_CALL_MAX_ARGS 6
/**
Call SBI call using ecall instruction.
@@ -50,53 +49,55 @@
@param[in] NumArgs Number of arguments to pass to the ecall.
@param[in] ... Argument list for the ecall.
- @retval Returns SbiRet structure with value and error code.
+ @retval Returns SBI_RET structure with value and error code.
**/
STATIC
-SbiRet
+SBI_RET
EFIAPI
-SbiCall(
- IN UINTN ExtId,
- IN UINTN FuncId,
- IN UINTN NumArgs,
+SbiCall (
+ IN UINTN ExtId,
+ IN UINTN FuncId,
+ IN UINTN NumArgs,
...
)
{
- UINTN I;
- SbiRet Ret;
- UINTN Args[SBI_CALL_MAX_ARGS];
- VA_LIST ArgList;
- VA_START (ArgList, NumArgs);
-
- ASSERT (NumArgs <= SBI_CALL_MAX_ARGS);
-
- for (I = 0; I < SBI_CALL_MAX_ARGS; I++) {
- if (I < NumArgs) {
- Args[I] = VA_ARG (ArgList, UINTN);
- } else {
- // Default to 0 for all arguments that are not given
- Args[I] = 0;
- }
+ UINTN I;
+ SBI_RET Ret;
+ UINTN Args[SBI_CALL_MAX_ARGS];
+ VA_LIST ArgList;
+
+ VA_START (ArgList, NumArgs);
+
+ ASSERT (NumArgs <= SBI_CALL_MAX_ARGS);
+
+ for (I = 0; I < SBI_CALL_MAX_ARGS; I++) {
+ if (I < NumArgs) {
+ Args[I] = VA_ARG (ArgList, UINTN);
+ } else {
+ // Default to 0 for all arguments that are not given
+ Args[I] = 0;
}
+ }
- VA_END(ArgList);
-
- register UINTN a0 asm ("a0") = Args[0];
- register UINTN a1 asm ("a1") = Args[1];
- register UINTN a2 asm ("a2") = Args[2];
- register UINTN a3 asm ("a3") = Args[3];
- register UINTN a4 asm ("a4") = Args[4];
- register UINTN a5 asm ("a5") = Args[5];
- register UINTN a6 asm ("a6") = (UINTN)(FuncId);
- register UINTN a7 asm ("a7") = (UINTN)(ExtId);
- asm volatile ("ecall" \
- : "+r" (a0), "+r" (a1) \
- : "r" (a2), "r" (a3), "r" (a4), "r" (a5), "r" (a6), "r" (a7) \
- : "memory"); \
- Ret.Error = a0;
- Ret.Value = a1;
- return Ret;
+ VA_END (ArgList);
+
+ register UINTN a0 asm ("a0") = Args[0];
+ register UINTN a1 asm ("a1") = Args[1];
+ register UINTN a2 asm ("a2") = Args[2];
+ register UINTN a3 asm ("a3") = Args[3];
+ register UINTN a4 asm ("a4") = Args[4];
+ register UINTN a5 asm ("a5") = Args[5];
+ register UINTN a6 asm ("a6") = (UINTN)(FuncId);
+ register UINTN a7 asm ("a7") = (UINTN)(ExtId);
+
+ asm volatile ("ecall" \
+ : "+r" (a0), "+r" (a1) \
+ : "r" (a2), "r" (a3), "r" (a4), "r" (a5), "r" (a6), "r" (a7) \
+ : "memory"); \
+ Ret.Error = a0;
+ Ret.Value = a1;
+ return Ret;
}
/**
@@ -105,12 +106,11 @@ SbiCall(
@param[in] SbiError SBI error code
@retval EFI_STATUS
**/
-
STATIC
EFI_STATUS
EFIAPI
-TranslateError(
- IN UINTN SbiError
+TranslateError (
+ IN UINTN SbiError
)
{
switch (SbiError) {
@@ -160,10 +160,12 @@ TranslateError(
VOID
EFIAPI
SbiGetSpecVersion (
- OUT UINTN *SpecVersion
+ OUT UINTN *SpecVersion
)
{
- SbiRet Ret = SbiCall (SBI_EXT_BASE, SBI_EXT_BASE_GET_SPEC_VERSION, 0);
+ SBI_RET Ret;
+
+ Ret = SbiCall (SBI_EXT_BASE, SBI_EXT_BASE_GET_SPEC_VERSION, 0);
if (!Ret.Error) {
*SpecVersion = (UINTN)Ret.Value;
@@ -181,10 +183,13 @@ SbiGetSpecVersion (
VOID
EFIAPI
SbiGetImplId (
- OUT UINTN *ImplId
+ OUT UINTN *ImplId
)
{
- SbiRet Ret = SbiCall (SBI_EXT_BASE, SBI_EXT_BASE_GET_IMP_ID, 0);
+ SBI_RET Ret;
+
+ Ret = SbiCall (SBI_EXT_BASE, SBI_EXT_BASE_GET_IMP_ID, 0);
+
*ImplId = (UINTN)Ret.Value;
}
@@ -199,10 +204,13 @@ SbiGetImplId (
VOID
EFIAPI
SbiGetImplVersion (
- OUT UINTN *ImplVersion
+ OUT UINTN *ImplVersion
)
{
- SbiRet Ret = SbiCall (SBI_EXT_BASE, SBI_EXT_BASE_GET_IMP_VERSION, 0);
+ SBI_RET Ret;
+
+ Ret = SbiCall (SBI_EXT_BASE, SBI_EXT_BASE_GET_IMP_VERSION, 0);
+
*ImplVersion = (UINTN)Ret.Value;
}
@@ -218,11 +226,14 @@ SbiGetImplVersion (
VOID
EFIAPI
SbiProbeExtension (
- IN INTN ExtensionId,
- OUT INTN *ProbeResult
+ IN INTN ExtensionId,
+ OUT INTN *ProbeResult
)
{
- SbiRet Ret = SbiCall (SBI_EXT_BASE, SBI_EXT_BASE_PROBE_EXT, 0);
+ SBI_RET Ret;
+
+ Ret = SbiCall (SBI_EXT_BASE, SBI_EXT_BASE_PROBE_EXT, 0);
+
*ProbeResult = (UINTN)Ret.Value;
}
@@ -236,10 +247,13 @@ SbiProbeExtension (
VOID
EFIAPI
SbiGetMachineVendorId (
- OUT UINTN *MachineVendorId
+ OUT UINTN *MachineVendorId
)
{
- SbiRet Ret = SbiCall (SBI_EXT_BASE, SBI_EXT_BASE_GET_MVENDORID, 0);
+ SBI_RET Ret;
+
+ Ret = SbiCall (SBI_EXT_BASE, SBI_EXT_BASE_GET_MVENDORID, 0);
+
*MachineVendorId = (UINTN)Ret.Value;
}
@@ -253,10 +267,13 @@ SbiGetMachineVendorId (
VOID
EFIAPI
SbiGetMachineArchId (
- OUT UINTN *MachineArchId
+ OUT UINTN *MachineArchId
)
{
- SbiRet Ret = SbiCall (SBI_EXT_BASE, SBI_EXT_BASE_GET_MARCHID, 0);
+ SBI_RET Ret;
+
+ Ret = SbiCall (SBI_EXT_BASE, SBI_EXT_BASE_GET_MARCHID, 0);
+
*MachineArchId = (UINTN)Ret.Value;
}
@@ -270,10 +287,13 @@ SbiGetMachineArchId (
VOID
EFIAPI
SbiGetMachineImplId (
- OUT UINTN *MachineImplId
+ OUT UINTN *MachineImplId
)
{
- SbiRet Ret = SbiCall (SBI_EXT_BASE, SBI_EXT_BASE_GET_MIMPID, 0);
+ SBI_RET Ret;
+
+ Ret = SbiCall (SBI_EXT_BASE, SBI_EXT_BASE_GET_MIMPID, 0);
+
*MachineImplId = (UINTN)Ret.Value;
}
@@ -307,19 +327,22 @@ SbiGetMachineImplId (
EFI_STATUS
EFIAPI
SbiHartStart (
- IN UINTN HartId,
- IN UINTN StartAddr,
- IN UINTN Priv
+ IN UINTN HartId,
+ IN UINTN StartAddr,
+ IN UINTN Priv
)
{
- SbiRet Ret = SbiCall (
- SBI_EXT_HSM,
- SBI_EXT_HSM_HART_START,
- 3,
- HartId,
- StartAddr,
- Priv
- );
+ SBI_RET Ret;
+
+ Ret = SbiCall (
+ SBI_EXT_HSM,
+ SBI_EXT_HSM_HART_START,
+ 3,
+ HartId,
+ StartAddr,
+ Priv
+ );
+
return TranslateError (Ret.Error);
}
@@ -337,7 +360,10 @@ EFIAPI
SbiHartStop (
)
{
- SbiRet Ret = SbiCall (SBI_EXT_HSM, SBI_EXT_HSM_HART_STOP, 0);
+ SBI_RET Ret;
+
+ Ret = SbiCall (SBI_EXT_HSM, SBI_EXT_HSM_HART_STOP, 0);
+
return TranslateError (Ret.Error);
}
@@ -361,11 +387,13 @@ SbiHartStop (
EFI_STATUS
EFIAPI
SbiHartGetStatus (
- IN UINTN HartId,
- OUT UINTN *HartStatus
+ IN UINTN HartId,
+ OUT UINTN *HartStatus
)
{
- SbiRet Ret = SbiCall (SBI_EXT_HSM, SBI_EXT_HSM_HART_GET_STATUS, 1, HartId);
+ SBI_RET Ret;
+
+ Ret = SbiCall (SBI_EXT_HSM, SBI_EXT_HSM_HART_GET_STATUS, 1, HartId);
if (!Ret.Error) {
*HartStatus = (UINTN)Ret.Value;
@@ -385,7 +413,7 @@ SbiHartGetStatus (
VOID
EFIAPI
SbiSetTimer (
- IN UINT64 Time
+ IN UINT64 Time
)
{
SbiCall (SBI_EXT_TIME, SBI_EXT_TIME_SET_TIMER, 1, Time);
@@ -394,17 +422,20 @@ SbiSetTimer (
EFI_STATUS
EFIAPI
SbiSendIpi (
- IN UINTN *HartMask,
- IN UINTN HartMaskBase
+ IN UINTN *HartMask,
+ IN UINTN HartMaskBase
)
{
- SbiRet Ret = SbiCall (
- SBI_EXT_IPI,
- SBI_EXT_IPI_SEND_IPI,
- 2,
- (UINTN)HartMask,
- HartMaskBase
- );
+ SBI_RET Ret;
+
+ Ret = SbiCall (
+ SBI_EXT_IPI,
+ SBI_EXT_IPI_SEND_IPI,
+ 2,
+ (UINTN)HartMask,
+ HartMaskBase
+ );
+
return TranslateError (Ret.Error);
}
@@ -424,17 +455,20 @@ SbiSendIpi (
EFI_STATUS
EFIAPI
SbiRemoteFenceI (
- IN UINTN *HartMask,
- IN UINTN HartMaskBase
+ IN UINTN *HartMask,
+ IN UINTN HartMaskBase
)
{
- SbiRet Ret = SbiCall (
- SBI_EXT_RFENCE,
- SBI_EXT_RFENCE_REMOTE_FENCE_I,
- 2,
- (UINTN)HartMask,
- HartMaskBase
- );
+ SBI_RET Ret;
+
+ Ret = SbiCall (
+ SBI_EXT_RFENCE,
+ SBI_EXT_RFENCE_REMOTE_FENCE_I,
+ 2,
+ (UINTN)HartMask,
+ HartMaskBase
+ );
+
return TranslateError (Ret.Error);
}
@@ -462,21 +496,24 @@ SbiRemoteFenceI (
EFI_STATUS
EFIAPI
SbiRemoteSfenceVma (
- IN UINTN *HartMask,
- IN UINTN HartMaskBase,
- IN UINTN StartAddr,
- IN UINTN Size
+ IN UINTN *HartMask,
+ IN UINTN HartMaskBase,
+ IN UINTN StartAddr,
+ IN UINTN Size
)
{
- SbiRet Ret = SbiCall (
- SBI_EXT_RFENCE,
- SBI_EXT_RFENCE_REMOTE_SFENCE_VMA,
- 4,
- (UINTN)HartMask,
- HartMaskBase,
- StartAddr,
- Size
- );
+ SBI_RET Ret;
+
+ Ret = SbiCall (
+ SBI_EXT_RFENCE,
+ SBI_EXT_RFENCE_REMOTE_SFENCE_VMA,
+ 4,
+ (UINTN)HartMask,
+ HartMaskBase,
+ StartAddr,
+ Size
+ );
+
return TranslateError (Ret.Error);
}
@@ -505,23 +542,26 @@ SbiRemoteSfenceVma (
EFI_STATUS
EFIAPI
SbiRemoteSfenceVmaAsid (
- IN UINTN *HartMask,
- IN UINTN HartMaskBase,
- IN UINTN StartAddr,
- IN UINTN Size,
- IN UINTN Asid
+ IN UINTN *HartMask,
+ IN UINTN HartMaskBase,
+ IN UINTN StartAddr,
+ IN UINTN Size,
+ IN UINTN Asid
)
{
- SbiRet Ret = SbiCall (
- SBI_EXT_RFENCE,
- SBI_EXT_RFENCE_REMOTE_SFENCE_VMA_ASID,
- 5,
- (UINTN)HartMask,
- HartMaskBase,
- StartAddr,
- Size,
- Asid
- );
+ SBI_RET Ret;
+
+ Ret = SbiCall (
+ SBI_EXT_RFENCE,
+ SBI_EXT_RFENCE_REMOTE_SFENCE_VMA_ASID,
+ 5,
+ (UINTN)HartMask,
+ HartMaskBase,
+ StartAddr,
+ Size,
+ Asid
+ );
+
return TranslateError (Ret.Error);
}
@@ -554,23 +594,26 @@ SbiRemoteSfenceVmaAsid (
EFI_STATUS
EFIAPI
SbiRemoteHFenceGvmaVmid (
- IN UINTN *HartMask,
- IN UINTN HartMaskBase,
- IN UINTN StartAddr,
- IN UINTN Size,
- IN UINTN Vmid
+ IN UINTN *HartMask,
+ IN UINTN HartMaskBase,
+ IN UINTN StartAddr,
+ IN UINTN Size,
+ IN UINTN Vmid
)
{
- SbiRet Ret = SbiCall (
- SBI_EXT_RFENCE,
- SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA,
- 5,
- (UINTN)HartMask,
- HartMaskBase,
- StartAddr,
- Size,
- Vmid
- );
+ SBI_RET Ret;
+
+ Ret = SbiCall (
+ SBI_EXT_RFENCE,
+ SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA,
+ 5,
+ (UINTN)HartMask,
+ HartMaskBase,
+ StartAddr,
+ Size,
+ Vmid
+ );
+
return TranslateError (Ret.Error);
}
@@ -602,21 +645,24 @@ SbiRemoteHFenceGvmaVmid (
EFI_STATUS
EFIAPI
SbiRemoteHFenceGvma (
- IN UINTN *HartMask,
- IN UINTN HartMaskBase,
- IN UINTN StartAddr,
- IN UINTN Size
+ IN UINTN *HartMask,
+ IN UINTN HartMaskBase,
+ IN UINTN StartAddr,
+ IN UINTN Size
)
{
- SbiRet Ret = SbiCall (
- SBI_EXT_RFENCE,
- SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA_VMID,
- 4,
- (UINTN)HartMask,
- HartMaskBase,
- StartAddr,
- Size
- );
+ SBI_RET Ret;
+
+ Ret = SbiCall (
+ SBI_EXT_RFENCE,
+ SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA_VMID,
+ 4,
+ (UINTN)HartMask,
+ HartMaskBase,
+ StartAddr,
+ Size
+ );
+
return TranslateError (Ret.Error);
}
@@ -649,23 +695,26 @@ SbiRemoteHFenceGvma (
EFI_STATUS
EFIAPI
SbiRemoteHFenceVvmaAsid (
- IN UINTN *HartMask,
- IN UINTN HartMaskBase,
- IN UINTN StartAddr,
- IN UINTN Size,
- IN UINTN Asid
+ IN UINTN *HartMask,
+ IN UINTN HartMaskBase,
+ IN UINTN StartAddr,
+ IN UINTN Size,
+ IN UINTN Asid
)
{
- SbiRet Ret = SbiCall (
- SBI_EXT_RFENCE,
- SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA,
- 5,
- (UINTN)HartMask,
- HartMaskBase,
- StartAddr,
- Size,
- Asid
- );
+ SBI_RET Ret;
+
+ Ret = SbiCall (
+ SBI_EXT_RFENCE,
+ SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA,
+ 5,
+ (UINTN)HartMask,
+ HartMaskBase,
+ StartAddr,
+ Size,
+ Asid
+ );
+
return TranslateError (Ret.Error);
}
@@ -697,21 +746,24 @@ SbiRemoteHFenceVvmaAsid (
EFI_STATUS
EFIAPI
SbiRemoteHFenceVvma (
- IN UINTN *HartMask,
- IN UINTN HartMaskBase,
- IN UINTN StartAddr,
- IN UINTN Size
+ IN UINTN *HartMask,
+ IN UINTN HartMaskBase,
+ IN UINTN StartAddr,
+ IN UINTN Size
)
{
- SbiRet Ret = SbiCall (
- SBI_EXT_RFENCE,
- SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA_ASID,
- 4,
- (UINTN)HartMask,
- HartMaskBase,
- StartAddr,
- Size
- );
+ SBI_RET Ret;
+
+ Ret = SbiCall (
+ SBI_EXT_RFENCE,
+ SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA_ASID,
+ 4,
+ (UINTN)HartMask,
+ HartMaskBase,
+ StartAddr,
+ Size
+ );
+
return TranslateError (Ret.Error);
}
@@ -743,17 +795,20 @@ SbiRemoteHFenceVvma (
EFI_STATUS
EFIAPI
SbiSystemReset (
- IN UINTN ResetType,
- IN UINTN ResetReason
+ IN UINTN ResetType,
+ IN UINTN ResetReason
)
{
- SbiRet Ret = SbiCall (
- SBI_EXT_SRST,
- SBI_EXT_SRST_RESET,
- 2,
- ResetType,
- ResetReason
- );
+ SBI_RET Ret;
+
+ Ret = SbiCall (
+ SBI_EXT_SRST,
+ SBI_EXT_SRST_RESET,
+ 2,
+ ResetType,
+ ResetReason
+ );
+
return TranslateError (Ret.Error);
}
@@ -777,59 +832,91 @@ SbiSystemReset (
EFI_STATUS
EFIAPI
SbiVendorCall (
- IN UINTN ExtensionId,
- IN UINTN FunctionId,
- IN UINTN NumArgs,
+ IN UINTN ExtensionId,
+ IN UINTN FunctionId,
+ IN UINTN NumArgs,
...
)
{
- SbiRet Ret;
- VA_LIST Args;
- VA_START (Args, NumArgs);
-
- ASSERT (ExtensionId >= SBI_EXT_VENDOR_START && ExtensionId <= SBI_EXT_VENDOR_END);
- ASSERT (NumArgs <= SBI_CALL_MAX_ARGS);
-
- switch (NumArgs) {
- case 0:
- Ret = SbiCall (ExtensionId, FunctionId, NumArgs);
- break;
- case 1:
- Ret = SbiCall (ExtensionId, FunctionId, NumArgs, VA_ARG (Args, UINTN));
- break;
- case 2:
- Ret = SbiCall (ExtensionId, FunctionId, NumArgs, VA_ARG (Args, UINTN),
- VA_ARG (Args, UINTN));
- break;
- case 3:
- Ret = SbiCall (ExtensionId, FunctionId, NumArgs, VA_ARG (Args, UINTN),
- VA_ARG (Args, UINTN), VA_ARG (Args, UINTN));
- break;
- case 4:
- Ret = SbiCall (ExtensionId, FunctionId, NumArgs, VA_ARG (Args, UINTN),
- VA_ARG (Args, UINTN), VA_ARG (Args, UINTN),
- VA_ARG (Args, UINTN));
- break;
- case 5:
- Ret = SbiCall (ExtensionId, FunctionId, NumArgs, VA_ARG (Args, UINTN),
- VA_ARG (Args, UINTN), VA_ARG (Args, UINTN),
- VA_ARG (Args, UINTN), VA_ARG (Args, UINTN));
- break;
- case 6:
- Ret = SbiCall (ExtensionId, FunctionId, NumArgs, VA_ARG (Args, UINTN),
- VA_ARG (Args, UINTN), VA_ARG (Args, UINTN),
- VA_ARG (Args, UINTN), VA_ARG (Args, UINTN),
- VA_ARG (Args, UINTN));
- break;
- default:
- // Too many args. In theory SBI can handle more arguments when they are
- // passed on the stack but no SBI extension uses this, therefore it's
- // not yet implemented here.
- return EFI_INVALID_PARAMETER;
- }
-
- VA_END(Args);
- return TranslateError (Ret.Error);
+ SBI_RET Ret;
+ VA_LIST Args;
+
+ VA_START (Args, NumArgs);
+
+ ASSERT (ExtensionId >= SBI_EXT_VENDOR_START && ExtensionId <= SBI_EXT_VENDOR_END);
+ ASSERT (NumArgs <= SBI_CALL_MAX_ARGS);
+
+ switch (NumArgs) {
+ case 0:
+ Ret = SbiCall (ExtensionId, FunctionId, NumArgs);
+ break;
+ case 1:
+ Ret = SbiCall (ExtensionId, FunctionId, NumArgs, VA_ARG (Args, UINTN));
+ break;
+ case 2:
+ Ret = SbiCall (
+ ExtensionId,
+ FunctionId,
+ NumArgs,
+ VA_ARG (Args, UINTN),
+ VA_ARG (Args, UINTN)
+ );
+ break;
+ case 3:
+ Ret = SbiCall (
+ ExtensionId,
+ FunctionId,
+ NumArgs,
+ VA_ARG (Args, UINTN),
+ VA_ARG (Args, UINTN),
+ VA_ARG (Args, UINTN)
+ );
+ break;
+ case 4:
+ Ret = SbiCall (
+ ExtensionId,
+ FunctionId,
+ NumArgs,
+ VA_ARG (Args, UINTN),
+ VA_ARG (Args, UINTN),
+ VA_ARG (Args, UINTN),
+ VA_ARG (Args, UINTN)
+ );
+ break;
+ case 5:
+ Ret = SbiCall (
+ ExtensionId,
+ FunctionId,
+ NumArgs,
+ VA_ARG (Args, UINTN),
+ VA_ARG (Args, UINTN),
+ VA_ARG (Args, UINTN),
+ VA_ARG (Args, UINTN),
+ VA_ARG (Args, UINTN)
+ );
+ break;
+ case 6:
+ Ret = SbiCall (
+ ExtensionId,
+ FunctionId,
+ NumArgs,
+ VA_ARG (Args, UINTN),
+ VA_ARG (Args, UINTN),
+ VA_ARG (Args, UINTN),
+ VA_ARG (Args, UINTN),
+ VA_ARG (Args, UINTN),
+ VA_ARG (Args, UINTN)
+ );
+ break;
+ default:
+ // Too many args. In theory SBI can handle more arguments when they are
+ // passed on the stack but no SBI extension uses this, therefore it's
+ // not yet implemented here.
+ return EFI_INVALID_PARAMETER;
+ }
+
+ VA_END (Args);
+ return TranslateError (Ret.Error);
}
//
@@ -847,10 +934,12 @@ SbiVendorCall (
VOID
EFIAPI
SbiGetMscratch (
- OUT SBI_SCRATCH **ScratchSpace
+ OUT SBI_SCRATCH **ScratchSpace
)
{
- SbiRet Ret = SbiCall (SBI_EDK2_FW_EXT, SBI_EXT_FW_MSCRATCH_FUNC, 0);
+ SBI_RET Ret;
+
+ Ret = SbiCall (SBI_EDK2_FW_EXT, SBI_EXT_FW_MSCRATCH_FUNC, 0);
// Our ecall handler never returns an error, only when the func id is invalid
ASSERT (Ret.Error == SBI_OK);
@@ -867,16 +956,18 @@ SbiGetMscratch (
VOID
EFIAPI
SbiGetMscratchHartid (
- IN UINTN HartId,
- OUT SBI_SCRATCH **ScratchSpace
+ IN UINTN HartId,
+ OUT SBI_SCRATCH **ScratchSpace
)
{
- SbiRet Ret = SbiCall (
- SBI_EDK2_FW_EXT,
- SBI_EXT_FW_MSCRATCH_HARTID_FUNC,
- 1,
- HartId
- );
+ SBI_RET Ret;
+
+ Ret = SbiCall (
+ SBI_EDK2_FW_EXT,
+ SBI_EXT_FW_MSCRATCH_HARTID_FUNC,
+ 1,
+ HartId
+ );
// Our ecall handler never returns an error, only when the func id is invalid
ASSERT (Ret.Error == SBI_OK);
@@ -893,14 +984,14 @@ SbiGetMscratchHartid (
VOID
EFIAPI
SbiGetFirmwareContext (
- OUT EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT **FirmwareContext
+ OUT EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT **FirmwareContext
)
{
- SBI_SCRATCH *ScratchSpace;
- SBI_PLATFORM *SbiPlatform;
+ SBI_SCRATCH *ScratchSpace;
+ SBI_PLATFORM *SbiPlatform;
- SbiGetMscratch(&ScratchSpace);
- SbiPlatform = (SBI_PLATFORM *)sbi_platform_ptr(ScratchSpace);
+ SbiGetMscratch (&ScratchSpace);
+ SbiPlatform = (SBI_PLATFORM *)sbi_platform_ptr (ScratchSpace);
*FirmwareContext = (EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *)SbiPlatform->firmware_context;
}
@@ -912,14 +1003,14 @@ SbiGetFirmwareContext (
VOID
EFIAPI
SbiSetFirmwareContext (
- IN EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *FirmwareContext
+ IN EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *FirmwareContext
)
{
- SBI_SCRATCH *ScratchSpace;
- SBI_PLATFORM *SbiPlatform;
+ SBI_SCRATCH *ScratchSpace;
+ SBI_PLATFORM *SbiPlatform;
- SbiGetMscratch(&ScratchSpace);
+ SbiGetMscratch (&ScratchSpace);
- SbiPlatform = (SBI_PLATFORM *)sbi_platform_ptr (ScratchSpace);
+ SbiPlatform = (SBI_PLATFORM *)sbi_platform_ptr (ScratchSpace);
SbiPlatform->firmware_context = (UINTN)FirmwareContext;
}
diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVExceptionLib/CpuExceptionHandlerLib.c b/Silicon/RISC-V/ProcessorPkg/Library/RiscVExceptionLib/CpuExceptionHandlerLib.c
index a9316ae758..93fbde619f 100644
--- a/Silicon/RISC-V/ProcessorPkg/Library/RiscVExceptionLib/CpuExceptionHandlerLib.c
+++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVExceptionLib/CpuExceptionHandlerLib.c
@@ -1,7 +1,7 @@
/** @file
- RISC-V Exception Handler library implementition.
+ RISC-V Exception Handler library implementation.
- Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+ Copyright (c) 2016 - 2022, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -17,7 +17,7 @@
#include "CpuExceptionHandlerLib.h"
-STATIC EFI_CPU_INTERRUPT_HANDLER mInterruptHandlers[2];
+STATIC EFI_CPU_INTERRUPT_HANDLER mInterruptHandlers[2];
/**
Initializes all CPU exceptions entries and provides the default exception handlers.
@@ -38,7 +38,7 @@ STATIC EFI_CPU_INTERRUPT_HANDLER mInterruptHandlers[2];
EFI_STATUS
EFIAPI
InitializeCpuExceptionHandlers (
- IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL
+ IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL
)
{
return EFI_SUCCESS;
@@ -63,7 +63,7 @@ InitializeCpuExceptionHandlers (
EFI_STATUS
EFIAPI
InitializeCpuInterruptHandlers (
- IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL
+ IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL
)
{
return EFI_SUCCESS;
@@ -95,15 +95,15 @@ InitializeCpuInterruptHandlers (
EFI_STATUS
EFIAPI
RegisterCpuInterruptHandler (
- IN EFI_EXCEPTION_TYPE InterruptType,
- IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler
+ IN EFI_EXCEPTION_TYPE InterruptType,
+ IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler
)
{
-
DEBUG ((DEBUG_INFO, "%a: Type:%x Handler: %x\n", __FUNCTION__, InterruptType, InterruptHandler));
mInterruptHandlers[InterruptType] = InterruptHandler;
return EFI_SUCCESS;
}
+
/**
Machine mode trap handler.
@@ -112,23 +112,23 @@ RegisterCpuInterruptHandler (
**/
VOID
RiscVSupervisorModeTrapHandler (
- SMODE_TRAP_REGISTERS *SmodeTrapReg
+ SMODE_TRAP_REGISTERS *SmodeTrapReg
)
{
- UINTN SCause;
- EFI_SYSTEM_CONTEXT RiscVSystemContext;
+ UINTN SCause;
+ EFI_SYSTEM_CONTEXT RiscVSystemContext;
RiscVSystemContext.SystemContextRiscV64 = (EFI_SYSTEM_CONTEXT_RISCV64 *)SmodeTrapReg;
//
// Check scasue register.
//
- SCause = (UINTN)csr_read(RISCV_CSR_SUPERVISOR_SCAUSE);
+ SCause = (UINTN)csr_read (RISCV_CSR_SUPERVISOR_SCAUSE);
if ((SCause & (1UL << (sizeof (UINTN) * 8- 1))) != 0) {
//
// This is interrupt event.
//
SCause &= ~(1UL << (sizeof (UINTN) * 8- 1));
- if((SCause == SCAUSE_SUPERVISOR_TIMER_INT) && (mInterruptHandlers[EXCEPT_RISCV_TIMER_INT] != NULL)) {
+ if ((SCause == SCAUSE_SUPERVISOR_TIMER_INT) && (mInterruptHandlers[EXCEPT_RISCV_TIMER_INT] != NULL)) {
mInterruptHandlers[EXCEPT_RISCV_TIMER_INT](EXCEPT_RISCV_TIMER_INT, RiscVSystemContext);
}
}
@@ -160,8 +160,8 @@ RiscVSupervisorModeTrapHandler (
EFI_STATUS
EFIAPI
InitializeCpuExceptionHandlersEx (
- IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL,
- IN CPU_EXCEPTION_INIT_DATA *InitData OPTIONAL
+ IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL,
+ IN CPU_EXCEPTION_INIT_DATA *InitData OPTIONAL
)
{
return InitializeCpuExceptionHandlers (VectorInfo);
@@ -186,9 +186,9 @@ CpuExceptionHandlerLibConstructor (
)
{
//
- // Set Superviosr mode trap handler.
+ // Set Supervisor mode trap handler.
//
- csr_write(CSR_STVEC, SupervisorModeTrap);
+ csr_write (CSR_STVEC, SupervisorModeTrap);
return EFI_SUCCESS;
}
diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSscratchLib/RiscVFirmwareContextSscratchLib.c b/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSscratchLib/RiscVFirmwareContextSscratchLib.c
index 2504e17132..1b1db65f60 100644
--- a/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSscratchLib/RiscVFirmwareContextSscratchLib.c
+++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSscratchLib/RiscVFirmwareContextSscratchLib.c
@@ -2,7 +2,7 @@
This instance uses Supervisor mode SCRATCH CSR to get/set the
pointer of firmware context.
- Copyright (c) 2021 Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+ Copyright (c) 2021-2022 Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@@ -25,7 +25,7 @@
VOID
EFIAPI
GetFirmwareContextPointer (
- IN OUT EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT **FirmwareContextPtr
+ IN OUT EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT **FirmwareContextPtr
)
{
*FirmwareContextPtr = (EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *)RiscVGetSupervisorScratch ();
@@ -41,7 +41,7 @@ GetFirmwareContextPointer (
VOID
EFIAPI
SetFirmwareContextPointer (
- IN EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *FirmwareContextPtr
+ IN EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *FirmwareContextPtr
)
{
RiscVSetSupervisorScratch ((UINT64)FirmwareContextPtr);
diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextStvecLib/RiscVFirmwareContextStvecLib.c b/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextStvecLib/RiscVFirmwareContextStvecLib.c
index cc5a7e2ccc..7198944af6 100644
--- a/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextStvecLib/RiscVFirmwareContextStvecLib.c
+++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextStvecLib/RiscVFirmwareContextStvecLib.c
@@ -25,7 +25,7 @@
VOID
EFIAPI
GetFirmwareContextPointer (
- IN OUT EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT **FirmwareContextPtr
+ IN OUT EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT **FirmwareContextPtr
)
{
*FirmwareContextPtr = (EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *)RiscVGetSupervisorStvec ();
@@ -41,7 +41,7 @@ GetFirmwareContextPointer (
VOID
EFIAPI
SetFirmwareContextPointer (
- IN EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *FirmwareContextPtr
+ IN EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *FirmwareContextPtr
)
{
RiscVSetSupervisorStvec ((UINT64)FirmwareContextPtr);
diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVTimerLib/RiscVTimerLib.c b/Silicon/RISC-V/ProcessorPkg/Library/RiscVTimerLib/RiscVTimerLib.c
index 54ca99787e..85cd93c5e6 100644
--- a/Silicon/RISC-V/ProcessorPkg/Library/RiscVTimerLib/RiscVTimerLib.c
+++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVTimerLib/RiscVTimerLib.c
@@ -1,7 +1,7 @@
/** @file
RISC-V instance of Timer Library.
- Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+ Copyright (c) 2016 - 2022, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -24,21 +24,21 @@
**/
VOID
InternalRiscVTimerDelay (
- IN UINT32 Delay
+ IN UINT32 Delay
)
{
- UINT32 Ticks;
- UINT32 Times;
+ UINT32 Ticks;
+ UINT32 Times;
- Times = Delay >> (RISCV_TIMER_COMPARE_BITS - 2);
- Delay &= (( 1 << (RISCV_TIMER_COMPARE_BITS - 2)) - 1);
+ Times = Delay >> (RISCV_TIMER_COMPARE_BITS - 2);
+ Delay &= ((1 << (RISCV_TIMER_COMPARE_BITS - 2)) - 1);
do {
//
// The target timer count is calculated here
//
Ticks = RiscVReadMachineTimerInterface () + Delay;
Delay = 1 << (RISCV_TIMER_COMPARE_BITS - 2);
- while (((Ticks - RiscVReadMachineTimerInterface ()) & ( 1 << (RISCV_TIMER_COMPARE_BITS - 1))) == 0) {
+ while (((Ticks - RiscVReadMachineTimerInterface ()) & (1 << (RISCV_TIMER_COMPARE_BITS - 1))) == 0) {
CpuPause ();
}
} while (Times-- > 0);
@@ -57,7 +57,7 @@ InternalRiscVTimerDelay (
UINTN
EFIAPI
MicroSecondDelay (
- IN UINTN MicroSeconds
+ IN UINTN MicroSeconds
)
{
InternalRiscVTimerDelay (
@@ -85,7 +85,7 @@ MicroSecondDelay (
UINTN
EFIAPI
NanoSecondDelay (
- IN UINTN NanoSeconds
+ IN UINTN NanoSeconds
)
{
InternalRiscVTimerDelay (
@@ -147,7 +147,7 @@ GetPerformanceCounter (
UINT64
EFIAPI
GetPerformanceCounterProperties (
- OUT UINT64 *StartValue, OPTIONAL
+ OUT UINT64 *StartValue, OPTIONAL
OUT UINT64 *EndValue OPTIONAL
)
{
@@ -176,7 +176,7 @@ GetPerformanceCounterProperties (
UINT64
EFIAPI
GetTimeInNanoSecond (
- IN UINT64 Ticks
+ IN UINT64 Ticks
)
{
UINT64 NanoSeconds;
@@ -193,7 +193,7 @@ GetTimeInNanoSecond (
// Frequency < 0x100000000, so Remainder < 0x100000000, then (Remainder * 1,000,000,000)
// will not overflow 64-bit.
//
- NanoSeconds += DivU64x32 (MultU64x32 ((UINT64) Remainder, 1000000000u), PcdGet64 (PcdRiscVMachineTimerFrequencyInHerz));
+ NanoSeconds += DivU64x32 (MultU64x32 ((UINT64)Remainder, 1000000000u), PcdGet64 (PcdRiscVMachineTimerFrequencyInHerz));
return NanoSeconds;
}
diff --git a/Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxe.c b/Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxe.c
index 3104c6d2de..8d4d406edf 100644
--- a/Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxe.c
+++ b/Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxe.c
@@ -1,7 +1,7 @@
/** @file
RISC-V CPU DXE driver.
- Copyright (c) 2016 - 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+ Copyright (c) 2016 - 2022, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -12,8 +12,8 @@
//
// Global Variables
//
-STATIC BOOLEAN mInterruptState = FALSE;
-STATIC EFI_HANDLE mCpuHandle = NULL;
+STATIC BOOLEAN mInterruptState = FALSE;
+STATIC EFI_HANDLE mCpuHandle = NULL;
EFI_CPU_ARCH_PROTOCOL gCpu = {
CpuFlushCpuDataCache,
@@ -50,16 +50,15 @@ EFI_CPU_ARCH_PROTOCOL gCpu = {
EFI_STATUS
EFIAPI
CpuFlushCpuDataCache (
- IN EFI_CPU_ARCH_PROTOCOL *This,
- IN EFI_PHYSICAL_ADDRESS Start,
- IN UINT64 Length,
- IN EFI_CPU_FLUSH_TYPE FlushType
+ IN EFI_CPU_ARCH_PROTOCOL *This,
+ IN EFI_PHYSICAL_ADDRESS Start,
+ IN UINT64 Length,
+ IN EFI_CPU_FLUSH_TYPE FlushType
)
{
return EFI_SUCCESS;
}
-
/**
Enables CPU interrupts.
@@ -72,7 +71,7 @@ CpuFlushCpuDataCache (
EFI_STATUS
EFIAPI
CpuEnableInterrupt (
- IN EFI_CPU_ARCH_PROTOCOL *This
+ IN EFI_CPU_ARCH_PROTOCOL *This
)
{
EnableInterrupts ();
@@ -80,7 +79,6 @@ CpuEnableInterrupt (
return EFI_SUCCESS;
}
-
/**
Disables CPU interrupts.
@@ -93,7 +91,7 @@ CpuEnableInterrupt (
EFI_STATUS
EFIAPI
CpuDisableInterrupt (
- IN EFI_CPU_ARCH_PROTOCOL *This
+ IN EFI_CPU_ARCH_PROTOCOL *This
)
{
DisableInterrupts ();
@@ -101,7 +99,6 @@ CpuDisableInterrupt (
return EFI_SUCCESS;
}
-
/**
Return the state of interrupts.
@@ -115,8 +112,8 @@ CpuDisableInterrupt (
EFI_STATUS
EFIAPI
CpuGetInterruptState (
- IN EFI_CPU_ARCH_PROTOCOL *This,
- OUT BOOLEAN *State
+ IN EFI_CPU_ARCH_PROTOCOL *This,
+ OUT BOOLEAN *State
)
{
if (State == NULL) {
@@ -127,7 +124,6 @@ CpuGetInterruptState (
return EFI_SUCCESS;
}
-
/**
Generates an INIT to the CPU.
@@ -143,14 +139,13 @@ CpuGetInterruptState (
EFI_STATUS
EFIAPI
CpuInit (
- IN EFI_CPU_ARCH_PROTOCOL *This,
- IN EFI_CPU_INIT_TYPE InitType
+ IN EFI_CPU_ARCH_PROTOCOL *This,
+ IN EFI_CPU_INIT_TYPE InitType
)
{
return EFI_UNSUPPORTED;
}
-
/**
Registers a function to be called from the CPU interrupt handler.
@@ -174,15 +169,14 @@ CpuInit (
EFI_STATUS
EFIAPI
CpuRegisterInterruptHandler (
- IN EFI_CPU_ARCH_PROTOCOL *This,
- IN EFI_EXCEPTION_TYPE InterruptType,
- IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler
+ IN EFI_CPU_ARCH_PROTOCOL *This,
+ IN EFI_EXCEPTION_TYPE InterruptType,
+ IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler
)
{
return RegisterCpuInterruptHandler (InterruptType, InterruptHandler);
}
-
/**
Returns a timer value from one of the CPU's internal timers. There is no
inherent time interval between ticks but is a function of the CPU frequency.
@@ -209,10 +203,10 @@ CpuRegisterInterruptHandler (
EFI_STATUS
EFIAPI
CpuGetTimerValue (
- IN EFI_CPU_ARCH_PROTOCOL *This,
- IN UINT32 TimerIndex,
- OUT UINT64 *TimerValue,
- OUT UINT64 *TimerPeriod OPTIONAL
+ IN EFI_CPU_ARCH_PROTOCOL *This,
+ IN UINT32 TimerIndex,
+ OUT UINT64 *TimerValue,
+ OUT UINT64 *TimerPeriod OPTIONAL
)
{
if (TimerValue == NULL) {
@@ -225,15 +219,15 @@ CpuGetTimerValue (
*TimerValue = (UINT64)RiscVReadMachineTimerInterface ();
if (TimerPeriod != NULL) {
- *TimerPeriod = DivU64x32 (
- 1000000000000000u,
- PcdGet64 (PcdRiscVMachineTimerFrequencyInHerz)
- );
+ *TimerPeriod = DivU64x32 (
+ 1000000000000000u,
+ PcdGet64 (PcdRiscVMachineTimerFrequencyInHerz)
+ );
}
+
return EFI_SUCCESS;
}
-
/**
Implementation of SetMemoryAttributes() service of CPU Architecture Protocol.
@@ -262,10 +256,10 @@ CpuGetTimerValue (
EFI_STATUS
EFIAPI
CpuSetMemoryAttributes (
- IN EFI_CPU_ARCH_PROTOCOL *This,
- IN EFI_PHYSICAL_ADDRESS BaseAddress,
- IN UINT64 Length,
- IN UINT64 Attributes
+ IN EFI_CPU_ARCH_PROTOCOL *This,
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ IN UINT64 Length,
+ IN UINT64 Attributes
)
{
DEBUG ((DEBUG_INFO, "%a: Set memory attributes not supported yet\n", __FUNCTION__));
@@ -286,8 +280,8 @@ CpuSetMemoryAttributes (
EFI_STATUS
EFIAPI
InitializeCpu (
- IN EFI_HANDLE ImageHandle,
- IN EFI_SYSTEM_TABLE *SystemTable
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
)
{
EFI_STATUS Status;
@@ -307,10 +301,10 @@ InitializeCpu (
//
Status = gBS->InstallMultipleProtocolInterfaces (
&mCpuHandle,
- &gEfiCpuArchProtocolGuid, &gCpu,
+ &gEfiCpuArchProtocolGuid,
+ &gCpu,
NULL
);
ASSERT_EFI_ERROR (Status);
return Status;
}
-
diff --git a/Silicon/RISC-V/ProcessorPkg/Universal/FdtDxe/FdtDxe.c b/Silicon/RISC-V/ProcessorPkg/Universal/FdtDxe/FdtDxe.c
index 22b12027d3..1e76249237 100644
--- a/Silicon/RISC-V/ProcessorPkg/Universal/FdtDxe/FdtDxe.c
+++ b/Silicon/RISC-V/ProcessorPkg/Universal/FdtDxe/FdtDxe.c
@@ -6,7 +6,7 @@
it runs in S-Mode, it cannot get this information from mhartid. Instead we
insert the id into the device tree, that the EFIFSTUB can read from the config table.
- Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+ Copyright (c) 2021-2022, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@@ -21,7 +21,8 @@
/**
Fix up the device tree with booting hartid for the kernel
- @param DtbBlob The device tree. Is extended to fit the hart id.
+ @param DtbBlob The device tree. Is extended to fit the hart id.
+ @param BootingHartId The boot hart ID.
@retval EFI_SUCCESS The device tree was success fixed up with the hart id.
@retval EFI_OUT_OF_RESOURCES There is not enough memory available to complete the operation.
@@ -29,25 +30,32 @@
EFI_STATUS
EFIAPI
FixDtb (
- IN OUT VOID *DtbBlob,
+ IN OUT VOID *DtbBlob,
IN UINTN BootingHartId
)
{
- fdt32_t Size;
- UINT32 ChosenOffset, Err;
+ fdt32_t Size;
+ UINT32 ChosenOffset, Err;
- DEBUG ((DEBUG_INFO, "Fixing up device tree with boot hart id: %d\n",
- BootingHartId));
+ DEBUG ((
+ DEBUG_INFO,
+ "Fixing up device tree with boot hart id: %d\n",
+ BootingHartId
+ ));
- Size = fdt_totalsize(DtbBlob);
- Err = fdt_open_into(DtbBlob, DtbBlob, Size + 32);
+ Size = fdt_totalsize (DtbBlob);
+ Err = fdt_open_into (DtbBlob, DtbBlob, Size + 32);
if (Err < 0) {
- DEBUG ((DEBUG_ERROR,
- "Device Tree can't be expanded to accommodate new node\n", __FUNCTION__));
+ DEBUG ((
+ DEBUG_ERROR,
+ "Device Tree can't be expanded to accommodate new node\n",
+ __FUNCTION__
+ ));
return EFI_OUT_OF_RESOURCES;
}
- ChosenOffset = fdt_path_offset(DtbBlob, "/chosen");
- fdt_setprop_u32(DtbBlob, ChosenOffset, "boot-hartid", BootingHartId);
+
+ ChosenOffset = fdt_path_offset (DtbBlob, "/chosen");
+ fdt_setprop_u32 (DtbBlob, ChosenOffset, "boot-hartid", BootingHartId);
return EFI_SUCCESS;
}
@@ -61,32 +69,42 @@ FixDtb (
**/
EFI_STATUS
EFIAPI
-InstallFdtFromHob (VOID)
+InstallFdtFromHob (
+ VOID
+ )
{
EFI_STATUS Status;
- EFI_HOB_GUID_TYPE *GuidHob;
- VOID *DataInHob;
+ EFI_HOB_GUID_TYPE *GuidHob;
+ VOID *DataInHob;
UINTN DataSize;
GuidHob = GetFirstGuidHob (&gFdtHobGuid);
if (GuidHob == NULL) {
- DEBUG ((DEBUG_ERROR, "Failed to find RISC-V DTB Hob\n",
- __FUNCTION__));
+ DEBUG ((
+ DEBUG_ERROR,
+ "Failed to find RISC-V DTB Hob\n",
+ __FUNCTION__
+ ));
return EFI_NOT_FOUND;
}
- DataInHob = (VOID *) *((UINTN *) GET_GUID_HOB_DATA (GuidHob));
+
+ DataInHob = (VOID *)*((UINTN *)GET_GUID_HOB_DATA (GuidHob));
DataSize = GET_GUID_HOB_DATA_SIZE (GuidHob);
- Status = FixDtb (DataInHob, PcdGet32(PcdBootHartId));
+ Status = FixDtb (DataInHob, PcdGet32 (PcdBootHartId));
if (EFI_ERROR (Status)) {
return Status;
}
Status = gBS->InstallConfigurationTable (&gFdtTableGuid, DataInHob);
if (EFI_ERROR (Status)) {
- DEBUG ((DEBUG_ERROR, "%a: failed to install FDT configuration table\n",
- __FUNCTION__));
+ DEBUG ((
+ DEBUG_ERROR,
+ "%a: failed to install FDT configuration table\n",
+ __FUNCTION__
+ ));
}
+
return Status;
}
@@ -104,8 +122,8 @@ InstallFdtFromHob (VOID)
EFI_STATUS
EFIAPI
InstallFdt (
- IN EFI_HANDLE ImageHandle,
- IN EFI_SYSTEM_TABLE *SystemTable
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
)
{
EFI_STATUS Status;
diff --git a/Silicon/RISC-V/ProcessorPkg/Universal/PciCpuIo2Dxe/PciCpuIo2Dxe.c b/Silicon/RISC-V/ProcessorPkg/Universal/PciCpuIo2Dxe/PciCpuIo2Dxe.c
index 03e3070682..c0a79ef321 100644
--- a/Silicon/RISC-V/ProcessorPkg/Universal/PciCpuIo2Dxe/PciCpuIo2Dxe.c
+++ b/Silicon/RISC-V/ProcessorPkg/Universal/PciCpuIo2Dxe/PciCpuIo2Dxe.c
@@ -3,7 +3,7 @@
Copyright (c) 2009 - 2012, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2016, Linaro Ltd. All rights reserved.<BR>
-(C) Copyright 2021 Hewlett Packard Enterprise Development LP<BR>
+(C) Copyright 2021-2022 Hewlett Packard Enterprise Development LP<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -19,7 +19,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#include <Library/PcdLib.h>
#include <Library/UefiBootServicesTableLib.h>
-#define MAX_IO_PORT_ADDRESS 0xFFFF
+#define MAX_IO_PORT_ADDRESS 0xFFFF
//
// Handle for the CPU I/O 2 Protocol
@@ -29,7 +29,7 @@ STATIC EFI_HANDLE mHandle = NULL;
//
// Lookup table for increment values based on transfer widths
//
-STATIC CONST UINT8 mInStride[] = {
+STATIC CONST UINT8 mInStride[] = {
1, // EfiCpuIoWidthUint8
2, // EfiCpuIoWidthUint16
4, // EfiCpuIoWidthUint32
@@ -47,7 +47,7 @@ STATIC CONST UINT8 mInStride[] = {
//
// Lookup table for increment values based on transfer widths
//
-STATIC CONST UINT8 mOutStride[] = {
+STATIC CONST UINT8 mOutStride[] = {
1, // EfiCpuIoWidthUint8
2, // EfiCpuIoWidthUint16
4, // EfiCpuIoWidthUint32
@@ -118,14 +118,14 @@ CpuIoCheckParameter (
// For FIFO type, the target address won't increase during the access,
// so treat Count as 1
//
- if (Width >= EfiCpuIoWidthFifoUint8 && Width <= EfiCpuIoWidthFifoUint64) {
+ if ((Width >= EfiCpuIoWidthFifoUint8) && (Width <= EfiCpuIoWidthFifoUint64)) {
Count = 1;
}
//
// Check to see if Width is in the valid range for I/O Port operations
//
- Width = (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03);
+ Width = (EFI_CPU_IO_PROTOCOL_WIDTH)(Width & 0x03);
if (!MmioOperation && (Width == EfiCpuIoWidthUint64)) {
return EFI_INVALID_PARAMETER;
}
@@ -162,6 +162,7 @@ CpuIoCheckParameter (
if (MaxCount < (Count - 1)) {
return EFI_UNSUPPORTED;
}
+
if (Address > LShiftU64 (MaxCount - Count + 1, Width)) {
return EFI_UNSUPPORTED;
}
@@ -241,9 +242,9 @@ CpuMemoryServiceRead (
//
// Select loop based on the width of the transfer
//
- InStride = mInStride[Width];
- OutStride = mOutStride[Width];
- OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03);
+ InStride = mInStride[Width];
+ OutStride = mOutStride[Width];
+ OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH)(Width & 0x03);
for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) {
if (OperationWidth == EfiCpuIoWidthUint8) {
*Uint8Buffer = MmioRead8 ((UINTN)Address);
@@ -255,6 +256,7 @@ CpuMemoryServiceRead (
*((UINT64 *)Uint8Buffer) = MmioRead64 ((UINTN)Address);
}
}
+
return EFI_SUCCESS;
}
@@ -322,9 +324,9 @@ CpuMemoryServiceWrite (
//
// Select loop based on the width of the transfer
//
- InStride = mInStride[Width];
- OutStride = mOutStride[Width];
- OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03);
+ InStride = mInStride[Width];
+ OutStride = mOutStride[Width];
+ OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH)(Width & 0x03);
for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) {
if (OperationWidth == EfiCpuIoWidthUint8) {
MmioWrite8 ((UINTN)Address, *Uint8Buffer);
@@ -336,6 +338,7 @@ CpuMemoryServiceWrite (
MmioWrite64 ((UINTN)Address, *((UINT64 *)Uint8Buffer));
}
}
+
return EFI_SUCCESS;
}
@@ -405,9 +408,9 @@ CpuIoServiceRead (
//
// Select loop based on the width of the transfer
//
- InStride = mInStride[Width];
- OutStride = mOutStride[Width];
- OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03);
+ InStride = mInStride[Width];
+ OutStride = mOutStride[Width];
+ OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH)(Width & 0x03);
for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) {
if (OperationWidth == EfiCpuIoWidthUint8) {
@@ -491,9 +494,9 @@ CpuIoServiceWrite (
//
// Select loop based on the width of the transfer
//
- InStride = mInStride[Width];
- OutStride = mOutStride[Width];
- OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03);
+ InStride = mInStride[Width];
+ OutStride = mOutStride[Width];
+ OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH)(Width & 0x03);
for (Uint8Buffer = (UINT8 *)Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) {
if (OperationWidth == EfiCpuIoWidthUint8) {
@@ -511,7 +514,7 @@ CpuIoServiceWrite (
//
// CPU I/O 2 Protocol instance
//
-STATIC EFI_CPU_IO2_PROTOCOL mCpuIo2 = {
+STATIC EFI_CPU_IO2_PROTOCOL mCpuIo2 = {
{
CpuMemoryServiceRead,
CpuMemoryServiceWrite
@@ -522,7 +525,6 @@ STATIC EFI_CPU_IO2_PROTOCOL mCpuIo2 = {
}
};
-
/**
The user Entry Point for module CpuIo2Dxe. The user code starts with this function.
@@ -540,12 +542,13 @@ PciCpuIo2Initialize (
IN EFI_SYSTEM_TABLE *SystemTable
)
{
- EFI_STATUS Status;
+ EFI_STATUS Status;
ASSERT_PROTOCOL_ALREADY_INSTALLED (NULL, &gEfiCpuIo2ProtocolGuid);
Status = gBS->InstallMultipleProtocolInterfaces (
&mHandle,
- &gEfiCpuIo2ProtocolGuid, &mCpuIo2,
+ &gEfiCpuIo2ProtocolGuid,
+ &mCpuIo2,
NULL
);
ASSERT_EFI_ERROR (Status);
diff --git a/Silicon/RISC-V/ProcessorPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.c b/Silicon/RISC-V/ProcessorPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.c
index 14f62c4036..1375bb0afc 100644
--- a/Silicon/RISC-V/ProcessorPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.c
+++ b/Silicon/RISC-V/ProcessorPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.c
@@ -9,7 +9,7 @@
#include "RiscVSmbiosDxe.h"
-STATIC EFI_SMBIOS_PROTOCOL *mSmbios;
+STATIC EFI_SMBIOS_PROTOCOL *mSmbios;
/**
This function builds SMBIOS type 7 record according to
@@ -25,28 +25,31 @@ STATIC EFI_SMBIOS_PROTOCOL *mSmbios;
STATIC
EFI_STATUS
BuildSmbiosType7 (
- IN RISC_V_PROCESSOR_TYPE4_HOB_DATA *Type4HobData,
- IN RISC_V_PROCESSOR_TYPE7_HOB_DATA *Type7DataHob,
- OUT SMBIOS_HANDLE *SmbiosHandle
-)
+ IN RISC_V_PROCESSOR_TYPE4_HOB_DATA *Type4HobData,
+ IN RISC_V_PROCESSOR_TYPE7_HOB_DATA *Type7DataHob,
+ OUT SMBIOS_HANDLE *SmbiosHandle
+ )
{
- EFI_STATUS Status;
- SMBIOS_HANDLE Handle;
+ EFI_STATUS Status;
+ SMBIOS_HANDLE Handle;
if (!CompareGuid (&Type4HobData->ProcessorGuid, &Type7DataHob->ProcessorGuid) ||
- Type4HobData->ProcessorUid != Type7DataHob->ProcessorUid) {
+ (Type4HobData->ProcessorUid != Type7DataHob->ProcessorUid))
+ {
return EFI_INVALID_PARAMETER;
}
- Handle = SMBIOS_HANDLE_PI_RESERVED;
- Type7DataHob->SmbiosType7Cache.Hdr.Type = SMBIOS_TYPE_CACHE_INFORMATION;
- Type7DataHob->SmbiosType7Cache.Hdr.Length = sizeof(SMBIOS_TABLE_TYPE7);
+
+ Handle = SMBIOS_HANDLE_PI_RESERVED;
+ Type7DataHob->SmbiosType7Cache.Hdr.Type = SMBIOS_TYPE_CACHE_INFORMATION;
+ Type7DataHob->SmbiosType7Cache.Hdr.Length = sizeof (SMBIOS_TABLE_TYPE7);
Type7DataHob->SmbiosType7Cache.Hdr.Handle = 0;
- Type7DataHob->EndingZero = 0;
- Status = mSmbios->Add (mSmbios, NULL, &Handle, &Type7DataHob->SmbiosType7Cache.Hdr);
- if (EFI_ERROR(Status)) {
+ Type7DataHob->EndingZero = 0;
+ Status = mSmbios->Add (mSmbios, NULL, &Handle, &Type7DataHob->SmbiosType7Cache.Hdr);
+ if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_ERROR, "%a: Fail to add SMBIOS Type 7\n", __FUNCTION__));
return Status;
}
+
DEBUG ((DEBUG_INFO, "SMBIOS Type 7 was added. SMBIOS Handle: 0x%x\n", Handle));
DEBUG ((DEBUG_VERBOSE, " Cache belone to processor GUID: %g\n", &Type7DataHob->ProcessorGuid));
DEBUG ((DEBUG_VERBOSE, " Cache belone processor UID: %d\n", Type7DataHob->ProcessorUid));
@@ -79,15 +82,15 @@ BuildSmbiosType7 (
STATIC
EFI_STATUS
BuildSmbiosType4 (
- IN RISC_V_PROCESSOR_TYPE4_HOB_DATA *Type4HobData,
- OUT SMBIOS_HANDLE *SmbiosHandle
+ IN RISC_V_PROCESSOR_TYPE4_HOB_DATA *Type4HobData,
+ OUT SMBIOS_HANDLE *SmbiosHandle
)
{
- EFI_HOB_GUID_TYPE *GuidHob;
- RISC_V_PROCESSOR_TYPE7_HOB_DATA *Type7HobData;
- SMBIOS_HANDLE Cache;
- SMBIOS_HANDLE Processor;
- EFI_STATUS Status;
+ EFI_HOB_GUID_TYPE *GuidHob;
+ RISC_V_PROCESSOR_TYPE7_HOB_DATA *Type7HobData;
+ SMBIOS_HANDLE Cache;
+ SMBIOS_HANDLE Processor;
+ EFI_STATUS Status;
DEBUG ((DEBUG_INFO, "Building Type 4.\n"));
DEBUG ((DEBUG_INFO, " Processor GUID: %g\n", &Type4HobData->ProcessorGuid));
@@ -96,55 +99,66 @@ BuildSmbiosType4 (
Type4HobData->SmbiosType4Processor.L1CacheHandle = RISC_V_CACHE_INFO_NOT_PROVIDED;
Type4HobData->SmbiosType4Processor.L2CacheHandle = RISC_V_CACHE_INFO_NOT_PROVIDED;
Type4HobData->SmbiosType4Processor.L3CacheHandle = RISC_V_CACHE_INFO_NOT_PROVIDED;
- GuidHob = (EFI_HOB_GUID_TYPE *)GetFirstGuidHob ((EFI_GUID *)PcdGetPtr(PcdProcessorSmbiosType7GuidHobGuid));
+ GuidHob = (EFI_HOB_GUID_TYPE *)GetFirstGuidHob ((EFI_GUID *)PcdGetPtr (PcdProcessorSmbiosType7GuidHobGuid));
if (GuidHob == NULL) {
DEBUG ((DEBUG_ERROR, "No RISC-V SMBIOS Type7 data HOB found.\n"));
return EFI_NOT_FOUND;
}
+
//
// Go through each RISC_V_PROCESSOR_TYPE4_HOB_DATA for multiple processors.
//
do {
Type7HobData = (RISC_V_PROCESSOR_TYPE7_HOB_DATA *)GET_GUID_HOB_DATA (GuidHob);
- Status = BuildSmbiosType7 (Type4HobData, Type7HobData, &Cache);
+ Status = BuildSmbiosType7 (Type4HobData, Type7HobData, &Cache);
if (EFI_ERROR (Status)) {
return Status;
}
+
if ((Type7HobData->SmbiosType7Cache.SystemCacheType & RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_MASK) ==
- RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_1) {
+ RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_1)
+ {
Type4HobData->SmbiosType4Processor.L1CacheHandle = Cache;
} else if ((Type7HobData->SmbiosType7Cache.SystemCacheType & RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_MASK) ==
- RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_2) {
+ RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_2)
+ {
Type4HobData->SmbiosType4Processor.L2CacheHandle = Cache;
} else if ((Type7HobData->SmbiosType7Cache.SystemCacheType & RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_MASK) ==
- RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_3) {
+ RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_3)
+ {
Type4HobData->SmbiosType4Processor.L3CacheHandle = Cache;
} else {
DEBUG ((DEBUG_ERROR, "Improper cache level of SMBIOS handle %d\n", Cache));
}
- GuidHob = GetNextGuidHob((EFI_GUID *)PcdGetPtr(PcdProcessorSmbiosType7GuidHobGuid), GET_NEXT_HOB(GuidHob));
+
+ GuidHob = GetNextGuidHob ((EFI_GUID *)PcdGetPtr (PcdProcessorSmbiosType7GuidHobGuid), GET_NEXT_HOB (GuidHob));
} while (GuidHob != NULL);
//
// Build SMBIOS Type 4 record
//
- Processor = SMBIOS_HANDLE_PI_RESERVED;
- Type4HobData->SmbiosType4Processor.Hdr.Type = SMBIOS_TYPE_PROCESSOR_INFORMATION;
- Type4HobData->SmbiosType4Processor.Hdr.Length = sizeof(SMBIOS_TABLE_TYPE4);
+ Processor = SMBIOS_HANDLE_PI_RESERVED;
+ Type4HobData->SmbiosType4Processor.Hdr.Type = SMBIOS_TYPE_PROCESSOR_INFORMATION;
+ Type4HobData->SmbiosType4Processor.Hdr.Length = sizeof (SMBIOS_TABLE_TYPE4);
Type4HobData->SmbiosType4Processor.Hdr.Handle = 0;
- Type4HobData->EndingZero = 0;
- Status = mSmbios->Add (mSmbios, NULL, &Processor, &Type4HobData->SmbiosType4Processor.Hdr);
- if (EFI_ERROR(Status)) {
+ Type4HobData->EndingZero = 0;
+ Status = mSmbios->Add (mSmbios, NULL, &Processor, &Type4HobData->SmbiosType4Processor.Hdr);
+ if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_ERROR, "Fail to add SMBIOS Type 4\n"));
return Status;
}
+
DEBUG ((DEBUG_INFO, "SMBIOS Type 4 was added. SMBIOS Handle: 0x%x\n", Processor));
DEBUG ((DEBUG_VERBOSE, " Socket StringID: %d\n", Type4HobData->SmbiosType4Processor.Socket));
DEBUG ((DEBUG_VERBOSE, " Processor Type: 0x%x\n", Type4HobData->SmbiosType4Processor.ProcessorType));
DEBUG ((DEBUG_VERBOSE, " Processor Family: 0x%x\n", Type4HobData->SmbiosType4Processor.ProcessorFamily));
DEBUG ((DEBUG_VERBOSE, " Processor Manufacture StringID: %d\n", Type4HobData->SmbiosType4Processor.ProcessorManufacturer));
- DEBUG ((DEBUG_VERBOSE, " Processor Id: 0x%x:0x%x\n", \
- Type4HobData->SmbiosType4Processor.ProcessorId.Signature, Type4HobData->SmbiosType4Processor.ProcessorId.FeatureFlags));
+ DEBUG ((
+ DEBUG_VERBOSE,
+ " Processor Id: 0x%x:0x%x\n", \
+ Type4HobData->SmbiosType4Processor.ProcessorId.Signature,
+ Type4HobData->SmbiosType4Processor.ProcessorId.FeatureFlags
+ ));
DEBUG ((DEBUG_VERBOSE, " Processor Version StringID: %d\n", Type4HobData->SmbiosType4Processor.ProcessorVersion));
DEBUG ((DEBUG_VERBOSE, " Voltage: 0x%x\n", Type4HobData->SmbiosType4Processor.Voltage));
DEBUG ((DEBUG_VERBOSE, " External Clock: 0x%x\n", Type4HobData->SmbiosType4Processor.ExternalClock));
@@ -153,7 +167,7 @@ BuildSmbiosType4 (
DEBUG ((DEBUG_VERBOSE, " Status: 0x%x\n", Type4HobData->SmbiosType4Processor.Status));
DEBUG ((DEBUG_VERBOSE, " ProcessorUpgrade: 0x%x\n", Type4HobData->SmbiosType4Processor.ProcessorUpgrade));
DEBUG ((DEBUG_VERBOSE, " L1 Cache Handle: 0x%x\n", Type4HobData->SmbiosType4Processor.L1CacheHandle));
- DEBUG ((DEBUG_VERBOSE, " L2 Cache Handle: 0x%x\n",Type4HobData->SmbiosType4Processor.L2CacheHandle));
+ DEBUG ((DEBUG_VERBOSE, " L2 Cache Handle: 0x%x\n", Type4HobData->SmbiosType4Processor.L2CacheHandle));
DEBUG ((DEBUG_VERBOSE, " L3 Cache Handle: 0x%x\n", Type4HobData->SmbiosType4Processor.L3CacheHandle));
DEBUG ((DEBUG_VERBOSE, " Serial Number StringID: %d\n", Type4HobData->SmbiosType4Processor.SerialNumber));
DEBUG ((DEBUG_VERBOSE, " Asset Tag StringID: %d\n", Type4HobData->SmbiosType4Processor.AssetTag));
@@ -182,51 +196,55 @@ BuildSmbiosType4 (
**/
EFI_STATUS
BuildSmbiosType44 (
- IN RISC_V_PROCESSOR_TYPE4_HOB_DATA *Type4HobData,
- IN SMBIOS_HANDLE Type4Handle
+ IN RISC_V_PROCESSOR_TYPE4_HOB_DATA *Type4HobData,
+ IN SMBIOS_HANDLE Type4Handle
)
{
- EFI_HOB_GUID_TYPE *GuidHob;
- RISC_V_PROCESSOR_SPECIFIC_HOB_DATA *ProcessorSpecificData;
- SMBIOS_HANDLE RiscVType44;
- SMBIOS_TABLE_TYPE44 *Type44Ptr;
- EFI_STATUS Status;
+ EFI_HOB_GUID_TYPE *GuidHob;
+ RISC_V_PROCESSOR_SPECIFIC_HOB_DATA *ProcessorSpecificData;
+ SMBIOS_HANDLE RiscVType44;
+ SMBIOS_TABLE_TYPE44 *Type44Ptr;
+ EFI_STATUS Status;
DEBUG ((DEBUG_INFO, "Building Type 44 for...\n"));
DEBUG ((DEBUG_VERBOSE, " Processor GUID: %g\n", &Type4HobData->ProcessorGuid));
DEBUG ((DEBUG_VERBOSE, " Processor UUID: %d\n", Type4HobData->ProcessorUid));
- GuidHob = (EFI_HOB_GUID_TYPE *)GetFirstGuidHob ((EFI_GUID *)PcdGetPtr(PcdProcessorSpecificDataGuidHobGuid));
+ GuidHob = (EFI_HOB_GUID_TYPE *)GetFirstGuidHob ((EFI_GUID *)PcdGetPtr (PcdProcessorSpecificDataGuidHobGuid));
if (GuidHob == NULL) {
DEBUG ((DEBUG_ERROR, "No RISC_V_PROCESSOR_SPECIFIC_HOB_DATA found.\n"));
return EFI_NOT_FOUND;
}
+
//
// Go through each RISC_V_PROCESSOR_SPECIFIC_HOB_DATA for multiple cores.
//
do {
ProcessorSpecificData = (RISC_V_PROCESSOR_SPECIFIC_HOB_DATA *)GET_GUID_HOB_DATA (GuidHob);
if (!CompareGuid (&ProcessorSpecificData->ParentProcessorGuid, &Type4HobData->ProcessorGuid) ||
- ProcessorSpecificData->ParentProcessorUid != Type4HobData->ProcessorUid) {
- GuidHob = GetNextGuidHob((EFI_GUID *)PcdGetPtr(PcdProcessorSpecificDataGuidHobGuid), GET_NEXT_HOB(GuidHob));
+ (ProcessorSpecificData->ParentProcessorUid != Type4HobData->ProcessorUid))
+ {
+ GuidHob = GetNextGuidHob ((EFI_GUID *)PcdGetPtr (PcdProcessorSpecificDataGuidHobGuid), GET_NEXT_HOB (GuidHob));
if (GuidHob == NULL) {
break;
}
+
continue;
}
DEBUG ((DEBUG_VERBOSE, "================================\n"));
DEBUG ((DEBUG_VERBOSE, "Core GUID: %g\n", &ProcessorSpecificData->CoreGuid));
- Type44Ptr = AllocateZeroPool(sizeof(SMBIOS_TABLE_TYPE44) + sizeof(SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA) + 2); // Two ending zero.
+ Type44Ptr = AllocateZeroPool (sizeof (SMBIOS_TABLE_TYPE44) + sizeof (SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA) + 2); // Two ending zero.
if (Type44Ptr == NULL) {
return EFI_NOT_FOUND;
}
- Type44Ptr->Hdr.Type = SMBIOS_TYPE_PROCESSOR_ADDITIONAL_INFORMATION;
- Type44Ptr->Hdr.Handle = 0;
- Type44Ptr->Hdr.Length = sizeof(SMBIOS_TABLE_TYPE44) + sizeof(SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA);
- Type44Ptr->RefHandle = Type4Handle;
- Type44Ptr->ProcessorSpecificBlock.Length = sizeof(SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA);
+
+ Type44Ptr->Hdr.Type = SMBIOS_TYPE_PROCESSOR_ADDITIONAL_INFORMATION;
+ Type44Ptr->Hdr.Handle = 0;
+ Type44Ptr->Hdr.Length = sizeof (SMBIOS_TABLE_TYPE44) + sizeof (SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA);
+ Type44Ptr->RefHandle = Type4Handle;
+ Type44Ptr->ProcessorSpecificBlock.Length = sizeof (SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA);
Type44Ptr->ProcessorSpecificBlock.ProcessorArchType = Type4HobData->SmbiosType4Processor.ProcessorFamily2 -
ProcessorFamilyRiscvRV32 + \
ProcessorSpecificBlockArchTypeRiscVRV32;
@@ -251,15 +269,17 @@ BuildSmbiosType44 (
// Add to SMBIOS table.
//
RiscVType44 = SMBIOS_HANDLE_PI_RESERVED;
- Status = mSmbios->Add (mSmbios, NULL, &RiscVType44, &Type44Ptr->Hdr);
- if (EFI_ERROR(Status)) {
+ Status = mSmbios->Add (mSmbios, NULL, &RiscVType44, &Type44Ptr->Hdr);
+ if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_ERROR, "Fail to add SMBIOS Type 44\n"));
return Status;
}
+
DEBUG ((DEBUG_INFO, "SMBIOS Type 44 was added. SMBIOS Handle: 0x%x\n", RiscVType44));
- GuidHob = GetNextGuidHob((EFI_GUID *)PcdGetPtr(PcdProcessorSpecificDataGuidHobGuid), GET_NEXT_HOB(GuidHob));
+ GuidHob = GetNextGuidHob ((EFI_GUID *)PcdGetPtr (PcdProcessorSpecificDataGuidHobGuid), GET_NEXT_HOB (GuidHob));
} while (GuidHob != NULL);
+
return EFI_SUCCESS;
}
@@ -277,14 +297,14 @@ BuildSmbiosType44 (
EFI_STATUS
EFIAPI
RiscVSmbiosBuilderEntry (
- IN EFI_HANDLE ImageHandle,
- IN EFI_SYSTEM_TABLE *SystemTable
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
)
{
- EFI_STATUS Status;
- EFI_HOB_GUID_TYPE *GuidHob;
- RISC_V_PROCESSOR_TYPE4_HOB_DATA *Type4HobData;
- SMBIOS_HANDLE Processor;
+ EFI_STATUS Status;
+ EFI_HOB_GUID_TYPE *GuidHob;
+ RISC_V_PROCESSOR_TYPE4_HOB_DATA *Type4HobData;
+ SMBIOS_HANDLE Processor;
DEBUG ((DEBUG_INFO, "%a: entry\n", __FUNCTION__));
@@ -297,13 +317,15 @@ RiscVSmbiosBuilderEntry (
DEBUG ((DEBUG_ERROR, "Locate SMBIOS Protocol fail\n"));
return Status;
}
- GuidHob = (EFI_HOB_GUID_TYPE *)GetFirstGuidHob ((EFI_GUID *)PcdGetPtr(PcdProcessorSmbiosType4GuidHobGuid));
+
+ GuidHob = (EFI_HOB_GUID_TYPE *)GetFirstGuidHob ((EFI_GUID *)PcdGetPtr (PcdProcessorSmbiosType4GuidHobGuid));
if (GuidHob == NULL) {
DEBUG ((DEBUG_ERROR, "No RISC-V SMBIOS information found.\n"));
return EFI_NOT_FOUND;
}
+
Type4HobData = (RISC_V_PROCESSOR_TYPE4_HOB_DATA *)GET_GUID_HOB_DATA (GuidHob);
- Status = EFI_NOT_FOUND;
+ Status = EFI_NOT_FOUND;
//
// Go through each RISC_V_PROCESSOR_TYPE4_HOB_DATA for multiple processors.
//
@@ -313,15 +335,16 @@ RiscVSmbiosBuilderEntry (
DEBUG ((DEBUG_ERROR, "No RISC-V SMBIOS type 4 created.\n"));
ASSERT (FALSE);
}
+
Status = BuildSmbiosType44 (Type4HobData, Processor);
if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_ERROR, "No RISC-V SMBIOS type 44 found.\n"));
ASSERT (FALSE);
}
- GuidHob = GetNextGuidHob((EFI_GUID *)PcdGetPtr(PcdProcessorSmbiosType4GuidHobGuid), GET_NEXT_HOB(GuidHob));
+ GuidHob = GetNextGuidHob ((EFI_GUID *)PcdGetPtr (PcdProcessorSmbiosType4GuidHobGuid), GET_NEXT_HOB (GuidHob));
} while (GuidHob != NULL);
+
DEBUG ((DEBUG_INFO, "%a: exit\n", __FUNCTION__));
return Status;
}
-
diff --git a/Silicon/RISC-V/ProcessorPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerLibOpenSbi.uni b/Silicon/RISC-V/ProcessorPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerLibOpenSbi.uni
index f6fad8bcb5..9472496fb2 100644
--- a/Silicon/RISC-V/ProcessorPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerLibOpenSbi.uni
+++ b/Silicon/RISC-V/ProcessorPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerLibOpenSbi.uni
@@ -1,23 +1,16 @@
// /** @file
//
// Instance of PEI Services Table Pointer Library using RISC-V OpenSBI FirmwareContext.
-//
// PEI Services Table Pointer Library implementation that retrieves a pointer to the
// PEI Services Table from a RISC-V OpenSBI sbi_platform firmware context structure.
//
-// Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+// Copyright (c) 2029-2022, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
//
-// This program and the accompanying materials
-// are licensed and made available under the terms and conditions of the BSD License
-// which accompanies this distribution. The full text of the license may be found at
-// http://opensource.org/licenses/bsd-license.php.
-// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+// SPDX-License-Identifier: BSD-2-Clause-Patent
//
// **/
-
#string STR_MODULE_ABSTRACT #language en-US "Instance of PEI Services Table Pointer Library using global variable for the table pointer"
-
-#string STR_MODULE_DESCRIPTION #language en-US "The PEI Services Table Pointer Library implementation that retrieves a pointer to the PEI Services Table from a global variable. Not available to modules that execute from read-only memory."
+#string STR_MODULE_DESCRIPTION #language en-US "The PEI Services Table Pointer Library implementation that retrieves a pointer to the PEI Services Table from a global variable."
+ "Not available to modules that execute from read-only memory."
--
2.31.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* [edk2-platforms][PATCH V2 13/14] Silicon/SiFive: Fix build error
2022-01-22 6:53 [edk2-platforms][PATCH V2 00/14] Address edk2 Core CI issues Abner Chang
` (11 preceding siblings ...)
2022-01-22 6:53 ` [edk2-platforms][PATCH V2 12/14] RISC-V/ProcessorPkg: Address Core CI Uncrustify errors Abner Chang
@ 2022-01-22 6:53 ` Abner Chang
2022-01-22 6:53 ` [edk2-platforms][PATCH V2 14/14] Platform/U5Series: " Abner Chang
2022-01-22 10:19 ` [edk2-platforms][PATCH V2 00/14] Address edk2 Core CI issues Sunil V L
14 siblings, 0 replies; 16+ messages in thread
From: Abner Chang @ 2022-01-22 6:53 UTC (permalink / raw)
To: devel; +Cc: abner.chang, Daniel Schaefer, Sunil V L
Fix the build error caused by the spelling correction.
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Cc: Daniel Schaefer <daniel.schaefer@hpe.com>
Cc: Sunil V L <sunilvl@ventanamicro.com>
---
Silicon/SiFive/U54/Library/PeiCoreInfoHobLib/CoreInfoHob.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/Silicon/SiFive/U54/Library/PeiCoreInfoHobLib/CoreInfoHob.c b/Silicon/SiFive/U54/Library/PeiCoreInfoHobLib/CoreInfoHob.c
index 37363a0028..aed00b2bd7 100644
--- a/Silicon/SiFive/U54/Library/PeiCoreInfoHobLib/CoreInfoHob.c
+++ b/Silicon/SiFive/U54/Library/PeiCoreInfoHobLib/CoreInfoHob.c
@@ -145,7 +145,7 @@ CreateU54SmbiosType7L1DataHob (
// Build up SMBIOS type 7 L1 cache record.
//
ZeroMem((VOID *)&L1CacheDataHob, sizeof (RISC_V_PROCESSOR_TYPE7_HOB_DATA));
- L1CacheDataHob.PrcessorGuid = *((EFI_GUID *)PcdGetPtr (PcdSiFiveU5MCCoreplexGuid));
+ L1CacheDataHob.ProcessorGuid = *((EFI_GUID *)PcdGetPtr (PcdSiFiveU5MCCoreplexGuid));
L1CacheDataHob.ProcessorUid = ProcessorUid;
L1CacheDataHob.SmbiosType7Cache.SocketDesignation = TO_BE_FILLED_BY_VENDOR;
L1CacheDataHob.SmbiosType7Cache.CacheConfiguration = RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_1 | \
@@ -193,7 +193,7 @@ CreateU54SmbiosType4DataHob (
// Build up SMBIOS type 4 record.
//
ZeroMem((VOID *)&ProcessorDataHob, sizeof (RISC_V_PROCESSOR_TYPE4_HOB_DATA));
- ProcessorDataHob.PrcessorGuid = *((EFI_GUID *)PcdGetPtr (PcdSiFiveU5MCCoreplexGuid));
+ ProcessorDataHob.ProcessorGuid = *((EFI_GUID *)PcdGetPtr (PcdSiFiveU5MCCoreplexGuid));
ProcessorDataHob.ProcessorUid = ProcessorUid;
ProcessorDataHob.SmbiosType4Processor.Socket = TO_BE_FILLED_BY_VENDOR;
ProcessorDataHob.SmbiosType4Processor.ProcessorType = CentralProcessor;
--
2.31.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* [edk2-platforms][PATCH V2 14/14] Platform/U5Series: Fix build error
2022-01-22 6:53 [edk2-platforms][PATCH V2 00/14] Address edk2 Core CI issues Abner Chang
` (12 preceding siblings ...)
2022-01-22 6:53 ` [edk2-platforms][PATCH V2 13/14] Silicon/SiFive: Fix build error Abner Chang
@ 2022-01-22 6:53 ` Abner Chang
2022-01-22 10:19 ` [edk2-platforms][PATCH V2 00/14] Address edk2 Core CI issues Sunil V L
14 siblings, 0 replies; 16+ messages in thread
From: Abner Chang @ 2022-01-22 6:53 UTC (permalink / raw)
To: devel; +Cc: abner.chang, Daniel Schaefer, Sunil V L
Fix the build error caused by the spelling correction.
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Cc: Daniel Schaefer <daniel.schaefer@hpe.com>
Cc: Sunil V L <sunilvl@ventanamicro.com>
---
.../SiFive/U5SeriesPkg/Library/PeiCoreInfoHobLib/CoreInfoHob.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Platform/SiFive/U5SeriesPkg/Library/PeiCoreInfoHobLib/CoreInfoHob.c b/Platform/SiFive/U5SeriesPkg/Library/PeiCoreInfoHobLib/CoreInfoHob.c
index c147028add..5e66a98380 100644
--- a/Platform/SiFive/U5SeriesPkg/Library/PeiCoreInfoHobLib/CoreInfoHob.c
+++ b/Platform/SiFive/U5SeriesPkg/Library/PeiCoreInfoHobLib/CoreInfoHob.c
@@ -119,7 +119,7 @@ CreateU5MCProcessorSmbiosDataHob (
// Build up SMBIOS type 7 L2 cache record.
//
ZeroMem((VOID *)&L2CacheDataHob, sizeof (RISC_V_PROCESSOR_TYPE7_HOB_DATA));
- L2CacheDataHob.PrcessorGuid = *((EFI_GUID *)PcdGetPtr (PcdSiFiveU5MCCoreplexGuid));
+ L2CacheDataHob.ProcessorGuid = *((EFI_GUID *)PcdGetPtr (PcdSiFiveU5MCCoreplexGuid));
L2CacheDataHob.ProcessorUid = ProcessorUid;
L2CacheDataHob.SmbiosType7Cache.SocketDesignation = TO_BE_FILLED_BY_VENDOR;
L2CacheDataHob.SmbiosType7Cache.CacheConfiguration = RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_2 | \
--
2.31.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* Re: [edk2-platforms][PATCH V2 00/14] Address edk2 Core CI issues
2022-01-22 6:53 [edk2-platforms][PATCH V2 00/14] Address edk2 Core CI issues Abner Chang
` (13 preceding siblings ...)
2022-01-22 6:53 ` [edk2-platforms][PATCH V2 14/14] Platform/U5Series: " Abner Chang
@ 2022-01-22 10:19 ` Sunil V L
14 siblings, 0 replies; 16+ messages in thread
From: Sunil V L @ 2022-01-22 10:19 UTC (permalink / raw)
To: Abner Chang; +Cc: devel, Daniel Schaefer
The series looks good to me.
Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
Regards
Sunil
On Sat, Jan 22, 2022 at 02:53:04PM +0800, Abner Chang wrote:
> This patch set addresses edk2 Core CI on RISC-V ProcessorPkg
> and PlatformPkg.
>
>
> V2: Address comments to V1.
>
> Signed-off-by: Abner Chang <abner.chang@hpe.com>
> Cc: Daniel Schaefer <daniel.schaefer@hpe.com>
> Cc: Sunil V L <sunilvl@ventanamicro.com>
>
> Abner Chang (14):
> RiscVProcessorPkg: Fix build fail on RiscVProcessorPkg package
> PlatformPkg/PlatformPei: Fix the build error
> RISC-V/PlatformPkg: Address ECC errors
> RISC-V/PlatformPkg: Address Spelling check errors.
> RISC-V/PlatformPkg: Address Core CI package dependency check errors
> RISC-V/PlatformPkg: Address Core CI license check errors.
> RISC-V/PlatformPkg: Address Core CI library header check errors
> RISC-V/PlatformPkg: Address Core CI Uncrustify errors
> RISC-V/ProcessorPkg: Address Core CI ECC errors.
> RISC-V/ProcessorPkg: Address Core CI library header check errors
> RISC-V/ProcessorPkg: Address Core CI Spelling errors.
> RISC-V/ProcessorPkg: Address Core CI Uncrustify errors
> Silicon/SiFive: Fix build error
> Platform/U5Series: Fix build error
>
> .../RISC-V/PlatformPkg/RiscVPlatformPkg.dec | 7 +-
> .../RISC-V/ProcessorPkg/RiscVProcessorPkg.dec | 7 +-
> .../RISC-V/PlatformPkg/RiscVPlatformPkg.dsc | 4 +-
> .../RISC-V/ProcessorPkg/RiscVProcessorPkg.dsc | 5 +-
> .../FirmwareContextProcessorSpecificLib.inf | 7 +-
> .../OpensbiPlatformLib/OpensbiPlatformLib.inf | 2 +-
> .../PeiCoreEntryPoint/PeiCoreEntryPoint.inf | 1 -
> .../PlatformBootManagerLib.inf | 13 +-
> .../PlatformMemoryTestLibNull.inf | 6 +-
> .../PlatformSecPpiLibNull.inf | 8 +-
> .../PlatformUpdateProgressLibNull.inf | 7 +-
> .../Library/ResetSystemLib/ResetSystemLib.inf | 1 -
> .../PlatformPkg/Universal/FdtPeim/FdtPeim.inf | 5 +-
> .../Universal/Pei/PlatformPei/PlatformPei.inf | 14 +-
> .../PlatformPkg/Universal/Sec/SecMain.inf | 1 +
> .../RiscVFirmwareContextSbiLib.inf | 8 +-
> .../RiscVFirmwareContextSscratchLib.inf | 4 +-
> .../Library/Edk2OpensbiPlatformWrapperLib.h | 2 +-
> .../FirmwareContextProcessorSpecificLib.h | 25 +-
> .../Include/Library/PlatformSecPpiLib.h | 2 +-
> .../Library/RiscVPlatformTempMemoryInitLib.h | 18 +-
> .../PlatformBootManager.h | 44 +-
> .../Universal/Pei/PlatformPei/Platform.h | 39 +-
> .../PlatformPkg/Universal/Sec/SecMain.h | 37 +-
> .../Include/IndustryStandard/RiscV.h | 156 ++---
> .../Include/IndustryStandard/RiscVOpensbi.h | 28 +-
> .../Include/Library/MachineModeTimerLib.h | 17 +
> .../Include/Library/RiscVCpuLib.h | 76 ++-
> .../Include/Library/RiscVEdk2SbiLib.h | 138 ++--
> .../Include/Library/RiscVFirmwareContextLib.h | 6 +-
> .../Include/Library/RiscVPlatformTimerLib.h | 25 +
> .../ProcessorPkg/Include/OpensbiTypes.h | 73 ++-
> .../Include/ProcessorSpecificHobData.h | 105 +--
> .../RISC-V/ProcessorPkg/Include/RiscVImpl.h | 52 +-
> .../Include/SmbiosProcessorSpecificData.h | 50 +-
> .../CpuExceptionHandlerLib.h | 171 ++---
> .../ProcessorPkg/Universal/CpuDxe/CpuDxe.h | 45 +-
> .../Universal/SmbiosDxe/RiscVSmbiosDxe.h | 3 +-
> .../Edk2OpensbiPlatformWrapperLib.c | 394 +++++------
> .../FirmwareContextProcessorSpecificLib.c | 42 +-
> .../OpensbiPlatformLib/OpensbiPlatform.c | 270 ++++++++
> .../Library/OpensbiPlatformLib/Platform.c | 225 -------
> .../PeiCoreEntryPoint/PeiCoreEntryPoint.c | 20 +-
> .../PeiCoreInfoHobLibNull/CoreInfoHob.c | 2 +-
> .../PlatformBootManager.c | 79 ++-
> .../PlatformBootManagerLib/PlatformData.c | 20 +-
> .../PlatformMemoryTestLibNull.c | 2 +-
> .../PlatformSecPpiLibNull/PlatformSecPpiLib.c | 2 +-
> .../Library/ResetSystemLib/ResetSystemLib.c | 40 +-
> .../RiscVSpecialPlatformLib.c | 9 +-
> .../PlatformPkg/Universal/FdtPeim/FdtPeim.c | 33 +-
> .../Universal/Pei/PlatformPei/Fv.c | 9 +-
> .../Universal/Pei/PlatformPei/MemDetect.c | 21 +-
> .../Universal/Pei/PlatformPei/Platform.c | 168 +++--
> .../PlatformPkg/Universal/Sec/SecMain.c | 379 +++++------
> .../Library/PeiCoreInfoHobLib/CoreInfoHob.c | 2 +-
> .../PeiServicesTablePointerOpenSbi.c | 22 +-
> .../Library/RiscVEdk2SbiLib/RiscVEdk2SbiLib.c | 617 ++++++++++--------
> .../CpuExceptionHandlerLib.c | 34 +-
> .../RiscVFirmwareContextSbiLib.c | 4 +-
> .../RiscVFirmwareContextSscratchLib.c | 6 +-
> .../RiscVFirmwareContextStvecLib.c | 8 +-
> .../Library/RiscVTimerLib/RiscVTimerLib.c | 24 +-
> .../ProcessorPkg/Universal/CpuDxe/CpuDxe.c | 72 +-
> .../ProcessorPkg/Universal/FdtDxe/FdtDxe.c | 66 +-
> .../Universal/PciCpuIo2Dxe/PciCpuIo2Dxe.c | 47 +-
> .../Universal/SmbiosDxe/RiscVSmbiosDxe.c | 165 +++--
> .../Library/PeiCoreInfoHobLib/CoreInfoHob.c | 4 +-
> Platform/RISC-V/PlatformPkg/Readme.md | 14 +-
> .../RISC-V/PlatformPkg/RiscVPlatformPkg.uni | 71 +-
> .../Universal/Sec/Riscv64/SecEntry.S | 19 +-
> .../PeiServicesTablePointerLibOpenSbi.uni | 15 +-
> .../RISC-V/ProcessorPkg/RiscVProcessorPkg.uni | 18 +-
> 73 files changed, 2297 insertions(+), 1838 deletions(-)
> create mode 100644 Silicon/RISC-V/ProcessorPkg/Include/Library/MachineModeTimerLib.h
> create mode 100644 Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVPlatformTimerLib.h
> create mode 100644 Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/OpensbiPlatform.c
> delete mode 100644 Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/Platform.c
>
> --
> 2.31.1
>
^ permalink raw reply [flat|nested] 16+ messages in thread