From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mx0a-002e3701.pphosted.com (mx0a-002e3701.pphosted.com [148.163.147.86]) by mx.groups.io with SMTP id smtpd.web11.6086.1642838110567461905 for ; Fri, 21 Jan 2022 23:55:10 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@hpe.com header.s=pps0720 header.b=JzACyRiN; spf=permerror, err=parse error for token &{10 18 %{ir}.%{v}.%{d}.spf.has.pphosted.com}: invalid domain name (domain: hpe.com, ip: 148.163.147.86, mailfrom: prvs=00215b754f=abner.chang@hpe.com) Received: from pps.filterd (m0150241.ppops.net [127.0.0.1]) by mx0a-002e3701.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 20M4grPr022979; Sat, 22 Jan 2022 07:55:10 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=hpe.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : content-transfer-encoding : mime-version; s=pps0720; bh=CTuHqR/wMYlK+7QNbMjkNwBPEc/m/ffHFqTkdxxM54M=; b=JzACyRiN3pZyzD0PEyHu6hFyg+W6yJBedlSr4xEQV7s1dQ6dzqfGocJgdYF0cwzqo5VJ 4mtOLzYLqndtoXKnpGS2agzCjXGLSOWVJQ90vEw4bEIpGnsA7c+NBhSjdik/bCCd0ARr UIsMD2UkUNH3V7NoDvWFQ6K0nJcoSbvHkNMb0c2JTrYOPZ7at4RgARRanPxXFZ8fkhAO J1PYsH0zmF+nBkJAwPqiwKhxqqQHgUlETXCRhLZntpDDPJyU0d+OuVIbMiIG9UVGOVFe 3XX5tVgcQioauDUFhx027S0Dqzk7YFv3BuO0/09UazdSd3HuP00OuCo48B6FsSKrAflQ aQ== Received: from g9t5008.houston.hpe.com (g9t5008.houston.hpe.com [15.241.48.72]) by mx0a-002e3701.pphosted.com (PPS) with ESMTPS id 3drb4n0rab-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Sat, 22 Jan 2022 07:55:09 +0000 Received: from g4t3433.houston.hpecorp.net (g4t3433.houston.hpecorp.net [16.208.49.245]) by g9t5008.houston.hpe.com (Postfix) with ESMTP id CF50956; Sat, 22 Jan 2022 07:55:08 +0000 (UTC) Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.229]) by g4t3433.houston.hpecorp.net (Postfix) with ESMTP id 8F5E045; Sat, 22 Jan 2022 07:55:07 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com, Daniel Schaefer , Sunil V L Subject: [edk2-platforms][PATCH V2 12/14] RISC-V/ProcessorPkg: Address Core CI Uncrustify errors Date: Sat, 22 Jan 2022 14:53:16 +0800 Message-Id: <20220122065318.21808-13-abner.chang@hpe.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20220122065318.21808-1-abner.chang@hpe.com> References: <20220122065318.21808-1-abner.chang@hpe.com> X-Proofpoint-GUID: d5DoQWmtQYx3J8VqKPIVkxsFwDiH_Kxh X-Proofpoint-ORIG-GUID: d5DoQWmtQYx3J8VqKPIVkxsFwDiH_Kxh X-Proofpoint-UnRewURL: 0 URL was un-rewritten MIME-Version: 1.0 X-HPE-SCL: -1 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.816,Hydra:6.0.425,FMLib:17.11.62.513 definitions=2022-01-22_03,2022-01-21_01,2021-12-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=999 adultscore=0 spamscore=0 clxscore=1015 impostorscore=0 phishscore=0 bulkscore=0 suspectscore=0 priorityscore=1501 malwarescore=0 lowpriorityscore=0 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2201110000 definitions=main-2201220050 Content-Transfer-Encoding: quoted-printable Signed-off-by: Abner Chang Cc: Daniel Schaefer Cc: Sunil V L --- .../Include/IndustryStandard/RiscV.h | 156 ++--- .../Include/IndustryStandard/RiscVOpensbi.h | 28 +- .../Include/Library/MachineModeTimerLib.h | 4 +- .../Include/Library/RiscVCpuLib.h | 76 ++- .../Include/Library/RiscVEdk2SbiLib.h | 122 ++-- .../Include/Library/RiscVFirmwareContextLib.h | 6 +- .../Include/Library/RiscVPlatformTimerLib.h | 10 +- .../ProcessorPkg/Include/OpensbiTypes.h | 69 +- .../Include/ProcessorSpecificHobData.h | 103 +-- .../RISC-V/ProcessorPkg/Include/RiscVImpl.h | 52 +- .../Include/SmbiosProcessorSpecificData.h | 46 +- .../CpuExceptionHandlerLib.h | 169 ++--- .../ProcessorPkg/Universal/CpuDxe/CpuDxe.h | 45 +- .../Universal/SmbiosDxe/RiscVSmbiosDxe.h | 3 +- .../PeiServicesTablePointerOpenSbi.c | 22 +- .../Library/RiscVEdk2SbiLib/RiscVEdk2SbiLib.c | 601 ++++++++++-------- .../CpuExceptionHandlerLib.c | 34 +- .../RiscVFirmwareContextSscratchLib.c | 6 +- .../RiscVFirmwareContextStvecLib.c | 4 +- .../Library/RiscVTimerLib/RiscVTimerLib.c | 24 +- .../ProcessorPkg/Universal/CpuDxe/CpuDxe.c | 72 +-- .../ProcessorPkg/Universal/FdtDxe/FdtDxe.c | 66 +- .../Universal/PciCpuIo2Dxe/PciCpuIo2Dxe.c | 47 +- .../Universal/SmbiosDxe/RiscVSmbiosDxe.c | 153 +++-- .../PeiServicesTablePointerLibOpenSbi.uni | 15 +- 25 files changed, 1049 insertions(+), 884 deletions(-) diff --git a/Silicon/RISC-V/ProcessorPkg/Include/IndustryStandard/RiscV.h b= /Silicon/RISC-V/ProcessorPkg/Include/IndustryStandard/RiscV.h index c9715a2ee2..8710aae677 100644 --- a/Silicon/RISC-V/ProcessorPkg/Include/IndustryStandard/RiscV.h +++ b/Silicon/RISC-V/ProcessorPkg/Include/IndustryStandard/RiscV.h @@ -1,7 +1,7 @@ /** @file=0D RISC-V package definitions.=0D =0D - Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All right= s reserved.
=0D + Copyright (c) 2021-2022, Hewlett Packard Enterprise Development LP. All = rights reserved.
=0D =0D SPDX-License-Identifier: BSD-2-Clause-Patent=0D =0D @@ -11,36 +11,36 @@ #define RISCV_INDUSTRY_STANDARD_H_=0D =0D #if defined (MDE_CPU_RISCV64)=0D -#define RISC_V_XLEN_BITS 64=0D +#define RISC_V_XLEN_BITS 64=0D #else=0D #endif=0D =0D -#define RISC_V_ISA_ATOMIC_EXTENSION (0x00000001 << 0)=0D -#define RISC_V_ISA_BIT_OPERATION_EXTENSION (0x00000001 << 1)=0D -#define RISC_V_ISA_COMPRESSED_EXTENSION (0x00000001 << 2)=0D -#define RISC_V_ISA_DOUBLE_PRECISION_FP_EXTENSION (0x00000001 << 3)=0D -#define RISC_V_ISA_RV32E_ISA (0x00000001 << 4)=0D -#define RISC_V_ISA_SINGLE_PRECISION_FP_EXTENSION (0x00000001 << 5)=0D -#define RISC_V_ISA_ADDITIONAL_STANDARD_EXTENSION (0x00000001 << 6)=0D -#define RISC_V_ISA_RESERVED_1 (0x00000001 << 7)=0D -#define RISC_V_ISA_INTEGER_ISA_EXTENSION (0x00000001 << 8)=0D -#define RISC_V_ISA_DYNAMICALLY_TRANSLATED_LANGUAGE_EXTENSION (0x0000000= 1 << 9)=0D -#define RISC_V_ISA_RESERVED_2 (0x00000001 << 10)=0D -#define RISC_V_ISA_DECIMAL_FP_EXTENSION (0x00000001 << 11)=0D -#define RISC_V_ISA_INTEGER_MUL_DIV_EXTENSION (0x00000001 << 12)=0D -#define RISC_V_ISA_USER_LEVEL_INTERRUPT_SUPPORTED (0x00000001 << 13)=0D -#define RISC_V_ISA_RESERVED_3 (0x00000001 << 14)=0D -#define RISC_V_ISA_PACKED_SIMD_EXTENSION (0x00000001 << 15)=0D -#define RISC_V_ISA_QUAD_PRECISION_FP_EXTENSION (0x00000001 << 16)=0D -#define RISC_V_ISA_RESERVED_4 (0x00000001 << 17)=0D -#define RISC_V_ISA_SUPERVISOR_MODE_IMPLEMENTED (0x00000001 << 18)=0D -#define RISC_V_ISA_TRANSATIONAL_MEMORY_EXTENSION (0x00000001 << 19)=0D -#define RISC_V_ISA_USER_MODE_IMPLEMENTED (0x00000001 << 20)=0D -#define RISC_V_ISA_VECTOR_EXTENSION (0x00000001 << 21)=0D -#define RISC_V_ISA_RESERVED_5 (0x00000001 << 22)=0D -#define RISC_V_ISA_NON_STANDARD_EXTENSION (0x00000001 << 23)=0D -#define RISC_V_ISA_RESERVED_6 (0x00000001 << 24)=0D -#define RISC_V_ISA_RESERVED_7 (0x00000001 << 25)=0D +#define RISC_V_ISA_ATOMIC_EXTENSION (0x00000001 = << 0)=0D +#define RISC_V_ISA_BIT_OPERATION_EXTENSION (0x00000001 = << 1)=0D +#define RISC_V_ISA_COMPRESSED_EXTENSION (0x00000001 = << 2)=0D +#define RISC_V_ISA_DOUBLE_PRECISION_FP_EXTENSION (0x00000001 = << 3)=0D +#define RISC_V_ISA_RV32E_ISA (0x00000001 = << 4)=0D +#define RISC_V_ISA_SINGLE_PRECISION_FP_EXTENSION (0x00000001 = << 5)=0D +#define RISC_V_ISA_ADDITIONAL_STANDARD_EXTENSION (0x00000001 = << 6)=0D +#define RISC_V_ISA_RESERVED_1 (0x00000001 = << 7)=0D +#define RISC_V_ISA_INTEGER_ISA_EXTENSION (0x00000001 = << 8)=0D +#define RISC_V_ISA_DYNAMICALLY_TRANSLATED_LANGUAGE_EXTENSION (0x00000001 = << 9)=0D +#define RISC_V_ISA_RESERVED_2 (0x00000001 = << 10)=0D +#define RISC_V_ISA_DECIMAL_FP_EXTENSION (0x00000001 = << 11)=0D +#define RISC_V_ISA_INTEGER_MUL_DIV_EXTENSION (0x00000001 = << 12)=0D +#define RISC_V_ISA_USER_LEVEL_INTERRUPT_SUPPORTED (0x00000001 = << 13)=0D +#define RISC_V_ISA_RESERVED_3 (0x00000001 = << 14)=0D +#define RISC_V_ISA_PACKED_SIMD_EXTENSION (0x00000001 = << 15)=0D +#define RISC_V_ISA_QUAD_PRECISION_FP_EXTENSION (0x00000001 = << 16)=0D +#define RISC_V_ISA_RESERVED_4 (0x00000001 = << 17)=0D +#define RISC_V_ISA_SUPERVISOR_MODE_IMPLEMENTED (0x00000001 = << 18)=0D +#define RISC_V_ISA_TRANSATIONAL_MEMORY_EXTENSION (0x00000001 = << 19)=0D +#define RISC_V_ISA_USER_MODE_IMPLEMENTED (0x00000001 = << 20)=0D +#define RISC_V_ISA_VECTOR_EXTENSION (0x00000001 = << 21)=0D +#define RISC_V_ISA_RESERVED_5 (0x00000001 = << 22)=0D +#define RISC_V_ISA_NON_STANDARD_EXTENSION (0x00000001 = << 23)=0D +#define RISC_V_ISA_RESERVED_6 (0x00000001 = << 24)=0D +#define RISC_V_ISA_RESERVED_7 (0x00000001 = << 25)=0D =0D //=0D // RISC-V CSR definitions.=0D @@ -48,81 +48,81 @@ //=0D // Machine information=0D //=0D -#define RISCV_CSR_MACHINE_MVENDORID 0xF11=0D -#define RISCV_CSR_MACHINE_MARCHID 0xF12=0D -#define RISCV_CSR_MACHINE_MIMPID 0xF13=0D -#define RISCV_CSR_MACHINE_HARRID 0xF14=0D +#define RISCV_CSR_MACHINE_MVENDORID 0xF11=0D +#define RISCV_CSR_MACHINE_MARCHID 0xF12=0D +#define RISCV_CSR_MACHINE_MIMPID 0xF13=0D +#define RISCV_CSR_MACHINE_HARRID 0xF14=0D //=0D // Machine Trap Setup.=0D //=0D -#define RISCV_CSR_MACHINE_MSTATUS 0x300=0D -#define RISCV_CSR_MACHINE_MISA 0x301=0D -#define RISCV_CSR_MACHINE_MEDELEG 0x302=0D -#define RISCV_CSR_MACHINE_MIDELEG 0x303=0D -#define RISCV_CSR_MACHINE_MIE 0x304=0D -#define RISCV_CSR_MACHINE_MTVEC 0x305=0D +#define RISCV_CSR_MACHINE_MSTATUS 0x300=0D +#define RISCV_CSR_MACHINE_MISA 0x301=0D +#define RISCV_CSR_MACHINE_MEDELEG 0x302=0D +#define RISCV_CSR_MACHINE_MIDELEG 0x303=0D +#define RISCV_CSR_MACHINE_MIE 0x304=0D +#define RISCV_CSR_MACHINE_MTVEC 0x305=0D =0D -#define RISCV_TIMER_COMPARE_BITS 32=0D +#define RISCV_TIMER_COMPARE_BITS 32=0D //=0D // Machine Timer and Counter.=0D //=0D -//#define RISCV_CSR_MACHINE_MTIME 0x701=0D -//#define RISCV_CSR_MACHINE_MTIMEH 0x741=0D +// #define RISCV_CSR_MACHINE_MTIME 0x701=0D +// #define RISCV_CSR_MACHINE_MTIMEH 0x741=0D //=0D // Machine Trap Handling.=0D //=0D -#define RISCV_CSR_MACHINE_MSCRATCH 0x340=0D -#define RISCV_CSR_MACHINE_MEPC 0x341=0D -#define RISCV_CSR_MACHINE_MCAUSE 0x342=0D - #define MACHINE_MCAUSE_EXCEPTION_ MASK 0x0f=0D - #define MACHINE_MCAUSE_INTERRUPT (RISC_V_XLEN_BITS - 1)=0D -#define RISCV_CSR_MACHINE_MBADADDR 0x343=0D -#define RISCV_CSR_MACHINE_MIP 0x344=0D +#define RISCV_CSR_MACHINE_MSCRATCH 0x340=0D +#define RISCV_CSR_MACHINE_MEPC 0x341=0D +#define RISCV_CSR_MACHINE_MCAUSE 0x342=0D +#define MACHINE_MCAUSE_EXCEPTION_ MASK 0x0f=0D +#define MACHINE_MCAUSE_INTERRUPT (RISC_V_XLEN_BITS - 1)=0D +#define RISCV_CSR_MACHINE_MBADADDR 0x343=0D +#define RISCV_CSR_MACHINE_MIP 0x344=0D =0D //=0D // Machine Protection and Translation.=0D //=0D -#define RISCV_CSR_MACHINE_MBASE 0x380=0D -#define RISCV_CSR_MACHINE_MBOUND 0x381=0D -#define RISCV_CSR_MACHINE_MIBASE 0x382=0D -#define RISCV_CSR_MACHINE_MIBOUND 0x383=0D -#define RISCV_CSR_MACHINE_MDBASE 0x384=0D -#define RISCV_CSR_MACHINE_MDBOUND 0x385=0D +#define RISCV_CSR_MACHINE_MBASE 0x380=0D +#define RISCV_CSR_MACHINE_MBOUND 0x381=0D +#define RISCV_CSR_MACHINE_MIBASE 0x382=0D +#define RISCV_CSR_MACHINE_MIBOUND 0x383=0D +#define RISCV_CSR_MACHINE_MDBASE 0x384=0D +#define RISCV_CSR_MACHINE_MDBOUND 0x385=0D =0D //=0D // Supervisor mode CSR.=0D //=0D #define RISCV_CSR_SUPERVISOR_SSTATUS 0x100=0D - #define SSTATUS_SIE_BIT_POSITION 1=0D - #define SSTATUS_SPP_BIT_POSITION 8=0D +#define SSTATUS_SIE_BIT_POSITION 1=0D +#define SSTATUS_SPP_BIT_POSITION 8=0D #define RISCV_CSR_SUPERVISOR_SIE 0x104=0D #define RISCV_CSR_SUPERVISOR_STVEC 0x105=0D #define RISCV_CSR_SUPERVISOR_SSCRATCH 0x140=0D #define RISCV_CSR_SUPERVISOR_SEPC 0x141=0D #define RISCV_CSR_SUPERVISOR_SCAUSE 0x142=0D - #define SCAUSE_USER_SOFTWARE_INT 0=0D - #define SCAUSE_SUPERVISOR_SOFTWARE_INT 1=0D - #define SCAUSE_USER_TIMER_INT 4=0D - #define SCAUSE_SUPERVISOR_TIMER_INT 5=0D - #define SCAUSE_USER_EXTERNAL_INT 8=0D - #define SCAUSE_SUPERVISOR_EXTERNAL_INT 9=0D +#define SCAUSE_USER_SOFTWARE_INT 0=0D +#define SCAUSE_SUPERVISOR_SOFTWARE_INT 1=0D +#define SCAUSE_USER_TIMER_INT 4=0D +#define SCAUSE_SUPERVISOR_TIMER_INT 5=0D +#define SCAUSE_USER_EXTERNAL_INT 8=0D +#define SCAUSE_SUPERVISOR_EXTERNAL_INT 9=0D #define RISCV_CSR_SUPERVISOR_STVAL 0x143=0D #define RISCV_CSR_SUPERVISOR_SIP 0x144=0D #define RISCV_CSR_SUPERVISOR_SATP 0x180=0D =0D #if defined (MDE_CPU_RISCV64)=0D - #define RISCV_SATP_MODE_MASK 0xF000000000000000=0D - #define RISCV_SATP_MODE_BIT_POSITION 60=0D +#define RISCV_SATP_MODE_MASK 0xF000000000000000=0D +#define RISCV_SATP_MODE_BIT_POSITION 60=0D #endif=0D - #define RISCV_SATP_MODE_OFF 0=0D - #define RISCV_SATP_MODE_SV32 1=0D - #define RISCV_SATP_MODE_SV39 8=0D - #define RISCV_SATP_MODE_SV48 9=0D - #define RISCV_SATP_MODE_SV57 10=0D - #define RISCV_SATP_MODE_SV64 11=0D +#define RISCV_SATP_MODE_OFF 0=0D +#define RISCV_SATP_MODE_SV32 1=0D +#define RISCV_SATP_MODE_SV39 8=0D +#define RISCV_SATP_MODE_SV48 9=0D +#define RISCV_SATP_MODE_SV57 10=0D +#define RISCV_SATP_MODE_SV64 11=0D =0D - #define SATP64_ASID_MASK 0x0FFFF00000000000=0D - #define SATP64_PPN_MASK 0x00000FFFFFFFFFFF=0D +#define SATP64_ASID_MASK 0x0FFFF00000000000=0D +#define SATP64_PPN_MASK 0x00000FFFFFFFFFFF=0D =0D #define RISCV_CAUSE_MISALIGNED_FETCH 0x0=0D #define RISCV_CAUSE_FETCH_ACCESS 0x1=0D @@ -146,17 +146,17 @@ //=0D // Machine Read-Write Shadow of Hypervisor Read-Only Registers=0D //=0D -#define RISCV_CSR_HTIMEW 0xB01=0D -#define RISCV_CSR_HTIMEHW 0xB81=0D +#define RISCV_CSR_HTIMEW 0xB01=0D +#define RISCV_CSR_HTIMEHW 0xB81=0D //=0D // Machine Host-Target Interface (Non-Standard Berkeley Extension)=0D //=0D -#define RISCV_CSR_MTOHOST 0x780=0D -#define RISCV_CSR_MFROMHOST 0x781=0D +#define RISCV_CSR_MTOHOST 0x780=0D +#define RISCV_CSR_MFROMHOST 0x781=0D =0D //=0D // User mode CSR=0D //=0D -#define RISCV_CSR_CYCLE 0xc00=0D -#define RISCV_CSR_TIME 0xc01=0D +#define RISCV_CSR_CYCLE 0xc00=0D +#define RISCV_CSR_TIME 0xc01=0D #endif=0D diff --git a/Silicon/RISC-V/ProcessorPkg/Include/IndustryStandard/RiscVOpen= sbi.h b/Silicon/RISC-V/ProcessorPkg/Include/IndustryStandard/RiscVOpensbi.h index d639429306..43bbf13d60 100644 --- a/Silicon/RISC-V/ProcessorPkg/Include/IndustryStandard/RiscVOpensbi.h +++ b/Silicon/RISC-V/ProcessorPkg/Include/IndustryStandard/RiscVOpensbi.h @@ -1,7 +1,7 @@ /** @file=0D SBI inline function calls.=0D =0D - Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All right= s reserved.
=0D + Copyright (c) 2021-2022, Hewlett Packard Enterprise Development LP. All = rights reserved.
=0D =0D SPDX-License-Identifier: BSD-2-Clause-Patent=0D =0D @@ -20,7 +20,7 @@ #include =0D #include =0D =0D -#define RISC_V_MAX_HART_SUPPORTED SBI_HARTMASK_MAX_BITS=0D +#define RISC_V_MAX_HART_SUPPORTED SBI_HARTMASK_MAX_BITS=0D =0D typedef=0D VOID=0D @@ -36,27 +36,27 @@ VOID // Keep the structure member in 64-bit alignment.=0D //=0D typedef struct {=0D - UINT64 IsaExtensionSupported; // The ISA extension th= is core supported.=0D - RISCV_UINT128 MachineVendorId; // Machine vendor ID=0D - RISCV_UINT128 MachineArchId; // Machine Architecture= ID=0D - RISCV_UINT128 MachineImplId; // Machine Implementati= on ID=0D - RISCV_HART_SWITCH_MODE HartSwitchMode; // OpenSBI's function t= o switch the mode of a hart=0D + UINT64 IsaExtensionSupported; // The ISA extension th= is core supported.=0D + RISCV_UINT128 MachineVendorId; // Machine vendor ID=0D + RISCV_UINT128 MachineArchId; // Machine Architecture= ID=0D + RISCV_UINT128 MachineImplId; // Machine Implementati= on ID=0D + RISCV_HART_SWITCH_MODE HartSwitchMode; // OpenSBI's function t= o switch the mode of a hart=0D } EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC;=0D #define FIRMWARE_CONTEXT_HART_SPECIFIC_SIZE (64 * 8) // This is the size = of EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC=0D // structure. Referr= ed by both C code and assembly code.=0D =0D typedef struct {=0D - UINT64 BootHartId;=0D - VOID *PeiServiceTable; // PEI Service table=0D - UINT64 FlattenedDeviceTree; // Pointer to Flattened Devic= e tree=0D - UINT64 SecPeiHandOffData; // This is EFI_SEC_PEI_HAND_O= FF passed to PEI Core.=0D - EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC *HartSpecific[RISC_V_MAX_HART_= SUPPORTED];=0D + UINT64 BootHartId;=0D + VOID *PeiServiceTable; // PEI = Service table=0D + UINT64 FlattenedDeviceTree; // Poin= ter to Flattened Device tree=0D + UINT64 SecPeiHandOffData; // This= is EFI_SEC_PEI_HAND_OFF passed to PEI Core.=0D + EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC *HartSpecific[RISC_V_MAX_HAR= T_SUPPORTED];=0D } EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT;=0D =0D //=0D // Typedefs of OpenSBI type to make them conform to EDK2 coding guidelines= =0D //=0D -typedef struct sbi_scratch SBI_SCRATCH;=0D -typedef struct sbi_platform SBI_PLATFORM;=0D +typedef struct sbi_scratch SBI_SCRATCH;=0D +typedef struct sbi_platform SBI_PLATFORM;=0D =0D #endif=0D diff --git a/Silicon/RISC-V/ProcessorPkg/Include/Library/MachineModeTimerLi= b.h b/Silicon/RISC-V/ProcessorPkg/Include/Library/MachineModeTimerLib.h index a27391cca3..141d37992d 100644 --- a/Silicon/RISC-V/ProcessorPkg/Include/Library/MachineModeTimerLib.h +++ b/Silicon/RISC-V/ProcessorPkg/Include/Library/MachineModeTimerLib.h @@ -10,6 +10,8 @@ #define MACHINE_MODE_TIMER_LIB_H_=0D =0D UINT64=0D -RiscVReadMachineTimerInterface (VOID);=0D +RiscVReadMachineTimerInterface (=0D + VOID=0D + );=0D =0D #endif=0D diff --git a/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVCpuLib.h b/Si= licon/RISC-V/ProcessorPkg/Include/Library/RiscVCpuLib.h index 8d51152fa9..efe854892b 100644 --- a/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVCpuLib.h +++ b/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVCpuLib.h @@ -1,7 +1,7 @@ /** @file=0D RISC-V CPU library definitions.=0D =0D - Copyright (c) 2016 - 2021, Hewlett Packard Enterprise Development LP. Al= l rights reserved.
=0D + Copyright (c) 2016 - 2022, Hewlett Packard Enterprise Development LP. Al= l rights reserved.
=0D =0D SPDX-License-Identifier: BSD-2-Clause-Patent=0D **/=0D @@ -21,66 +21,98 @@ VOID );=0D =0D VOID=0D -RiscVSetMachineScratch (RISCV_MACHINE_MODE_CONTEXT *RiscvContext);=0D +RiscVSetMachineScratch (=0D + RISCV_MACHINE_MODE_CONTEXT *RiscvContext=0D + );=0D =0D UINT32=0D -RiscVGetMachineScratch (VOID);=0D +RiscVGetMachineScratch (=0D + VOID=0D + );=0D =0D UINT32=0D -RiscVGetMachineTrapCause (VOID);=0D +RiscVGetMachineTrapCause (=0D + VOID=0D + );=0D =0D UINT64=0D -RiscVReadMachineTimer (VOID);=0D +RiscVReadMachineTimer (=0D + VOID=0D + );=0D =0D UINT64=0D -RiscVReadMachineTimerInterface (VOID);=0D +RiscVReadMachineTimerInterface (=0D + VOID=0D + );=0D =0D VOID=0D -RiscVSetMachineTimerCmp (UINT64);=0D + RiscVSetMachineTimerCmp (UINT64);=0D =0D UINT64=0D -RiscVReadMachineTimerCmp(VOID);=0D +RiscVReadMachineTimerCmp (=0D + VOID=0D + );=0D =0D UINT64=0D -RiscVReadMachineInterruptEnable(VOID);=0D +RiscVReadMachineInterruptEnable (=0D + VOID=0D + );=0D =0D UINT64=0D -RiscVReadMachineInterruptPending(VOID);=0D +RiscVReadMachineInterruptPending (=0D + VOID=0D + );=0D =0D UINT64=0D -RiscVReadMachineStatus(VOID);=0D +RiscVReadMachineStatus (=0D + VOID=0D + );=0D =0D VOID=0D -RiscVWriteMachineStatus(UINT64);=0D + RiscVWriteMachineStatus (UINT64);=0D =0D UINT64=0D -RiscVReadMachineTrapVector(VOID);=0D +RiscVReadMachineTrapVector (=0D + VOID=0D + );=0D =0D UINT64=0D -RiscVReadMachineIsa (VOID);=0D +RiscVReadMachineIsa (=0D + VOID=0D + );=0D =0D UINT64=0D -RiscVReadMachineVendorId (VOID);=0D +RiscVReadMachineVendorId (=0D + VOID=0D + );=0D =0D UINT64=0D -RiscVReadMachineArchitectureId (VOID);=0D +RiscVReadMachineArchitectureId (=0D + VOID=0D + );=0D =0D UINT64=0D -RiscVReadMachineImplementId (VOID);=0D +RiscVReadMachineImplementId (=0D + VOID=0D + );=0D =0D VOID=0D -RiscVSetSupervisorAddressTranslationRegister(UINT64);=0D + RiscVSetSupervisorAddressTranslationRegister (UINT64);=0D =0D VOID=0D -RiscVSetSupervisorScratch (UINT64);=0D + RiscVSetSupervisorScratch (UINT64);=0D =0D UINT64=0D -RiscVGetSupervisorScratch (VOID);=0D +RiscVGetSupervisorScratch (=0D + VOID=0D + );=0D =0D VOID=0D -RiscVSetSupervisorStvec (UINT64);=0D + RiscVSetSupervisorStvec (UINT64);=0D =0D UINT64=0D -RiscVGetSupervisorStvec (VOID);=0D +RiscVGetSupervisorStvec (=0D + VOID=0D + );=0D =0D #endif=0D diff --git a/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVEdk2SbiLib.h = b/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVEdk2SbiLib.h index 6089137373..36eb16e1cb 100644 --- a/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVEdk2SbiLib.h +++ b/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVEdk2SbiLib.h @@ -21,20 +21,20 @@ //=0D // EDK2 OpenSBI Firmware extension.=0D //=0D -#define SBI_EDK2_FW_EXT (SBI_EXT_FIRMWARE_START | SBI_OPENSBI_IMPID)=0D +#define SBI_EDK2_FW_EXT (SBI_EXT_FIRMWARE_START | SBI_OPENSBI_IMPID)=0D //=0D // EDK2 OpenSBI Firmware extension functions.=0D //=0D -#define SBI_EXT_FW_MSCRATCH_FUNC 0=0D -#define SBI_EXT_FW_MSCRATCH_HARTID_FUNC 1=0D +#define SBI_EXT_FW_MSCRATCH_FUNC 0=0D +#define SBI_EXT_FW_MSCRATCH_HARTID_FUNC 1=0D =0D //=0D // EDK2 OpenSBI firmware extension return status.=0D //=0D typedef struct {=0D - UINTN Error; ///< SBI status code=0D - UINTN Value; ///< Value returned=0D -} SbiRet;=0D + UINTN Error; ///< SBI status code=0D + UINTN Value; ///< Value returned=0D +} SBI_RET;=0D =0D /**=0D Get the implemented SBI specification version=0D @@ -48,7 +48,7 @@ typedef struct { VOID=0D EFIAPI=0D SbiGetSpecVersion (=0D - OUT UINTN *SpecVersion=0D + OUT UINTN *SpecVersion=0D );=0D =0D /**=0D @@ -62,7 +62,7 @@ SbiGetSpecVersion ( VOID=0D EFIAPI=0D SbiGetImplId (=0D - OUT UINTN *ImplId=0D + OUT UINTN *ImplId=0D );=0D =0D /**=0D @@ -76,7 +76,7 @@ SbiGetImplId ( VOID=0D EFIAPI=0D SbiGetImplVersion (=0D - OUT UINTN *ImplVersion=0D + OUT UINTN *ImplVersion=0D );=0D =0D /**=0D @@ -91,8 +91,8 @@ SbiGetImplVersion ( VOID=0D EFIAPI=0D SbiProbeExtension (=0D - IN INTN ExtensionId,=0D - OUT INTN *ProbeResult=0D + IN INTN ExtensionId,=0D + OUT INTN *ProbeResult=0D );=0D =0D /**=0D @@ -105,7 +105,7 @@ SbiProbeExtension ( VOID=0D EFIAPI=0D SbiGetMachineVendorId (=0D - OUT UINTN *MachineVendorId=0D + OUT UINTN *MachineVendorId=0D );=0D =0D /**=0D @@ -118,7 +118,7 @@ SbiGetMachineVendorId ( VOID=0D EFIAPI=0D SbiGetMachineArchId (=0D - OUT UINTN *MachineArchId=0D + OUT UINTN *MachineArchId=0D );=0D =0D /**=0D @@ -131,7 +131,7 @@ SbiGetMachineArchId ( VOID=0D EFIAPI=0D SbiGetMachineImplId (=0D - OUT UINTN *MachineImplId=0D + OUT UINTN *MachineImplId=0D );=0D =0D /**=0D @@ -160,9 +160,9 @@ SbiGetMachineImplId ( EFI_STATUS=0D EFIAPI=0D SbiHartStart (=0D - IN UINTN HartId,=0D - IN UINTN StartAddr,=0D - IN UINTN Priv=0D + IN UINTN HartId,=0D + IN UINTN StartAddr,=0D + IN UINTN Priv=0D );=0D =0D /**=0D @@ -199,8 +199,8 @@ SbiHartStop ( EFI_STATUS=0D EFIAPI=0D SbiHartGetStatus (=0D - IN UINTN HartId,=0D - OUT UINTN *HartStatus=0D + IN UINTN HartId,=0D + OUT UINTN *HartStatus=0D );=0D =0D ///=0D @@ -218,7 +218,7 @@ SbiHartGetStatus ( VOID=0D EFIAPI=0D SbiSetTimer (=0D - IN UINT64 Time=0D + IN UINT64 Time=0D );=0D =0D ///=0D @@ -244,8 +244,8 @@ SbiSetTimer ( EFI_STATUS=0D EFIAPI=0D SbiSendIpi (=0D - IN UINTN *HartMask,=0D - IN UINTN HartMaskBase=0D + IN UINTN *HartMask,=0D + IN UINTN HartMaskBase=0D );=0D =0D ///=0D @@ -268,8 +268,8 @@ SbiSendIpi ( EFI_STATUS=0D EFIAPI=0D SbiRemoteFenceI (=0D - IN UINTN *HartMask,=0D - IN UINTN HartMaskBase=0D + IN UINTN *HartMask,=0D + IN UINTN HartMaskBase=0D );=0D =0D /**=0D @@ -296,10 +296,10 @@ SbiRemoteFenceI ( EFI_STATUS=0D EFIAPI=0D SbiRemoteSfenceVma (=0D - IN UINTN *HartMask,=0D - IN UINTN HartMaskBase,=0D - IN UINTN StartAddr,=0D - IN UINTN Size=0D + IN UINTN *HartMask,=0D + IN UINTN HartMaskBase,=0D + IN UINTN StartAddr,=0D + IN UINTN Size=0D );=0D =0D /**=0D @@ -327,11 +327,11 @@ SbiRemoteSfenceVma ( EFI_STATUS=0D EFIAPI=0D SbiRemoteSfenceVmaAsid (=0D - IN UINTN *HartMask,=0D - IN UINTN HartMaskBase,=0D - IN UINTN StartAddr,=0D - IN UINTN Size,=0D - IN UINTN Asid=0D + IN UINTN *HartMask,=0D + IN UINTN HartMaskBase,=0D + IN UINTN StartAddr,=0D + IN UINTN Size,=0D + IN UINTN Asid=0D );=0D =0D /**=0D @@ -363,11 +363,11 @@ SbiRemoteSfenceVmaAsid ( EFI_STATUS=0D EFIAPI=0D SbiRemoteHfenceGvmaVmid (=0D - IN UINTN *HartMask,=0D - IN UINTN HartMaskBase,=0D - IN UINTN StartAddr,=0D - IN UINTN Size,=0D - IN UINTN Vmid=0D + IN UINTN *HartMask,=0D + IN UINTN HartMaskBase,=0D + IN UINTN StartAddr,=0D + IN UINTN Size,=0D + IN UINTN Vmid=0D );=0D =0D /**=0D @@ -398,10 +398,10 @@ SbiRemoteHfenceGvmaVmid ( EFI_STATUS=0D EFIAPI=0D SbiRemoteHfenceGvma (=0D - IN UINTN *HartMask,=0D - IN UINTN HartMaskBase,=0D - IN UINTN StartAddr,=0D - IN UINTN Size=0D + IN UINTN *HartMask,=0D + IN UINTN HartMaskBase,=0D + IN UINTN StartAddr,=0D + IN UINTN Size=0D );=0D =0D /**=0D @@ -433,11 +433,11 @@ SbiRemoteHfenceGvma ( EFI_STATUS=0D EFIAPI=0D SbiRemoteHfenceVvmaAsid (=0D - IN UINTN *HartMask,=0D - IN UINTN HartMaskBase,=0D - IN UINTN StartAddr,=0D - IN UINTN Size,=0D - IN UINTN Asid=0D + IN UINTN *HartMask,=0D + IN UINTN HartMaskBase,=0D + IN UINTN StartAddr,=0D + IN UINTN Size,=0D + IN UINTN Asid=0D );=0D =0D /**=0D @@ -468,10 +468,10 @@ SbiRemoteHfenceVvmaAsid ( EFI_STATUS=0D EFIAPI=0D SbiRemoteHfenceVvma (=0D - IN UINTN *HartMask,=0D - IN UINTN HartMaskBase,=0D - IN UINTN StartAddr,=0D - IN UINTN Size=0D + IN UINTN *HartMask,=0D + IN UINTN HartMaskBase,=0D + IN UINTN StartAddr,=0D + IN UINTN Size=0D );=0D =0D ///=0D @@ -506,8 +506,8 @@ SbiRemoteHfenceVvma ( EFI_STATUS=0D EFIAPI=0D SbiSystemReset (=0D - IN UINTN ResetType,=0D - IN UINTN ResetReason=0D + IN UINTN ResetType,=0D + IN UINTN ResetReason=0D );=0D =0D ///=0D @@ -531,9 +531,9 @@ SbiSystemReset ( EFI_STATUS=0D EFIAPI=0D SbiVendorCall (=0D - IN UINTN ExtensionId,=0D - IN UINTN FunctionId,=0D - IN UINTN NumArgs,=0D + IN UINTN ExtensionId,=0D + IN UINTN FunctionId,=0D + IN UINTN NumArgs,=0D ...=0D );=0D =0D @@ -555,7 +555,7 @@ SbiVendorCall ( VOID=0D EFIAPI=0D SbiGetMscratch (=0D - OUT SBI_SCRATCH **ScratchSpace=0D + OUT SBI_SCRATCH **ScratchSpace=0D );=0D =0D /**=0D @@ -567,8 +567,8 @@ SbiGetMscratch ( VOID=0D EFIAPI=0D SbiGetMscratchHartid (=0D - IN UINTN HartId,=0D - OUT SBI_SCRATCH **ScratchSpace=0D + IN UINTN HartId,=0D + OUT SBI_SCRATCH **ScratchSpace=0D );=0D =0D /**=0D @@ -579,7 +579,7 @@ SbiGetMscratchHartid ( VOID=0D EFIAPI=0D SbiGetFirmwareContext (=0D - OUT EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT **FirmwareContext=0D + OUT EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT **FirmwareContext=0D );=0D =0D /**=0D @@ -590,7 +590,7 @@ SbiGetFirmwareContext ( VOID=0D EFIAPI=0D SbiSetFirmwareContext (=0D - IN EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *FirmwareContext=0D + IN EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *FirmwareContext=0D );=0D =0D #endif=0D diff --git a/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVFirmwareConte= xtLib.h b/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVFirmwareContextL= ib.h index f35c4e0c51..7cf98abb99 100644 --- a/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVFirmwareContextLib.h +++ b/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVFirmwareContextLib.h @@ -1,7 +1,7 @@ /** @file=0D Library to get/set Firmware Context.=0D =0D - Copyright (c) 2021, Hewlett Packard Development LP. All rights reserved.=
=0D + Copyright (c) 2021-2022, Hewlett Packard Development LP. All rights rese= rved.
=0D =0D SPDX-License-Identifier: BSD-2-Clause-Patent=0D =0D @@ -24,7 +24,7 @@ VOID=0D EFIAPI=0D GetFirmwareContextPointer (=0D - IN OUT EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT **FirmwareContextPtr=0D + IN OUT EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT **FirmwareContextPtr=0D );=0D =0D /**=0D @@ -37,7 +37,7 @@ GetFirmwareContextPointer ( VOID=0D EFIAPI=0D SetFirmwareContextPointer (=0D - IN EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *FirmwareContextPtr=0D + IN EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *FirmwareContextPtr=0D );=0D =0D #endif=0D diff --git a/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVPlatformTimer= Lib.h b/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVPlatformTimerLib.h index dcd8734eb5..0ec39a15ce 100644 --- a/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVPlatformTimerLib.h +++ b/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVPlatformTimerLib.h @@ -10,12 +10,16 @@ #define RISCV_PLATFORM_TIMER_LIB_H_=0D =0D UINT64=0D -RiscVReadMachineTimer (VOID);=0D +RiscVReadMachineTimer (=0D + VOID=0D + );=0D =0D VOID=0D -RiscVSetMachineTimerCmp (UINT64);=0D + RiscVSetMachineTimerCmp (UINT64);=0D =0D UINT64=0D -RiscVReadMachineTimerCmp(VOID);=0D +RiscVReadMachineTimerCmp (=0D + VOID=0D + );=0D =0D #endif=0D diff --git a/Silicon/RISC-V/ProcessorPkg/Include/OpensbiTypes.h b/Silicon/R= ISC-V/ProcessorPkg/Include/OpensbiTypes.h index af34e8b0ae..6a62bb3aee 100644 --- a/Silicon/RISC-V/ProcessorPkg/Include/OpensbiTypes.h +++ b/Silicon/RISC-V/ProcessorPkg/Include/OpensbiTypes.h @@ -6,14 +6,15 @@ SPDX-License-Identifier: BSD-2-Clause-Patent=0D =0D **/=0D +=0D #ifndef EDK2_SBI_TYPES_H_=0D #define EDK2_SBI_TYPES_H_=0D =0D #include =0D =0D -typedef INT8 s8;=0D -typedef UINT8 u8;=0D -typedef UINT8 uint8_t;=0D +typedef INT8 s8;=0D +typedef UINT8 u8;=0D +typedef UINT8 uint8_t;=0D =0D typedef INT16 s16;=0D typedef UINT16 u16;=0D @@ -32,49 +33,49 @@ typedef UINT64 uint64_t; =0D // PRILX is not used in EDK2 but we need to define it here because when=0D // defining our own types, this constant is not defined but used by OpenSB= I.=0D -#define PRILX "016lx"=0D -=0D -typedef BOOLEAN bool;=0D -typedef unsigned long ulong;=0D -typedef UINT64 uintptr_t;=0D -typedef UINT64 size_t;=0D -typedef INT64 ssize_t;=0D -typedef UINT64 virtual_addr_t;=0D -typedef UINT64 virtual_size_t;=0D -typedef UINT64 physical_addr_t;=0D -typedef UINT64 physical_size_t;=0D -=0D -#define true TRUE=0D -#define false FALSE=0D -=0D -#define __packed __attribute__((packed))=0D -#define __noreturn __attribute__((noreturn))=0D -#define __aligned(x) __attribute__((aligned(x)))=0D -=0D -#if defined(__GNUC__) || defined(__clang__)=0D - #define likely(x) __builtin_expect((x), 1)=0D - #define unlikely(x) __builtin_expect((x), 0)=0D +#define PRILX "016lx"=0D +=0D +typedef BOOLEAN bool;=0D +typedef unsigned long ulong;=0D +typedef UINT64 uintptr_t;=0D +typedef UINT64 size_t;=0D +typedef INT64 ssize_t;=0D +typedef UINT64 virtual_addr_t;=0D +typedef UINT64 virtual_size_t;=0D +typedef UINT64 physical_addr_t;=0D +typedef UINT64 physical_size_t;=0D +=0D +#define true TRUE=0D +#define false FALSE=0D +=0D +#define __packed __attribute__((packed))=0D +#define __noreturn __attribute__((noreturn))=0D +#define __aligned(x) __attribute__((aligned(x)))=0D +=0D +#if defined (__GNUC__) || defined (__clang__)=0D +#define likely(x) __builtin_expect((x), 1)=0D +#define unlikely(x) __builtin_expect((x), 0)=0D #else=0D - #define likely(x) (x)=0D - #define unlikely(x) (x)=0D +#define likely(x) (x)=0D +#define unlikely(x) (x)=0D #endif=0D =0D #undef offsetof=0D #ifdef __compiler_offsetof=0D -#define offsetof(TYPE, MEMBER) __compiler_offsetof(TYPE,MEMBER)=0D +#define offsetof(TYPE, MEMBER) __compiler_offsetof(TYPE,MEMBER)=0D #else=0D -#define offsetof(TYPE, MEMBER) ((size_t) &((TYPE *)0)->MEMBER)=0D +#define offsetof(TYPE, MEMBER) ((size_t) &((TYPE *)0)->MEMBER)=0D #endif=0D =0D -#define container_of(ptr, type, member) ({ \=0D +#define container_of(ptr, type, member) ({ \=0D const typeof(((type *)0)->member) * __mptr =3D (ptr); \=0D (type *)((char *)__mptr - offsetof(type, member)); })=0D =0D -#define array_size(x) (sizeof(x) / sizeof((x)[0]))=0D +#define array_size(x) (sizeof(x) / sizeof((x)[0]))=0D =0D -#define CLAMP(a, lo, hi) MIN(MAX(a, lo), hi)=0D -#define ROUNDUP(a, b) ((((a)-1) / (b) + 1) * (b))=0D -#define ROUNDDOWN(a, b) ((a) / (b) * (b))=0D +#define CLAMP(a, lo, hi) MIN(MAX(a, lo), hi)=0D +#define ROUNDUP(a, b) ((((a)-1) / (b) + 1) * (b))=0D +#define ROUNDDOWN(a, b) ((a) / (b) * (b))=0D =0D /* clang-format on */=0D =0D diff --git a/Silicon/RISC-V/ProcessorPkg/Include/ProcessorSpecificHobData.h= b/Silicon/RISC-V/ProcessorPkg/Include/ProcessorSpecificHobData.h index 4b2a92e2f2..58dda7ff5b 100644 --- a/Silicon/RISC-V/ProcessorPkg/Include/ProcessorSpecificHobData.h +++ b/Silicon/RISC-V/ProcessorPkg/Include/ProcessorSpecificHobData.h @@ -6,6 +6,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent=0D =0D **/=0D +=0D #ifndef RISC_V_PROCESSOR_SPECIFIC_HOB_DATA_H_=0D #define RISC_V_PROCESSOR_SPECIFIC_HOB_DATA_H_=0D =0D @@ -13,10 +14,10 @@ #include =0D #include =0D =0D -#define TO_BE_FILLED 0=0D -#define TO_BE_FILLED_BY_VENDOR 0=0D -#define TO_BE_FILLED_BY_RISC_V_SMBIOS_DXE_DRIVER 0=0D -#define TO_BE_FILLED_BY_CODE 0=0D +#define TO_BE_FILLED 0=0D +#define TO_BE_FILLED_BY_VENDOR 0=0D +#define TO_BE_FILLED_BY_RISC_V_SMBIOS_DXE_DRIVER 0=0D +#define TO_BE_FILLED_BY_CODE 0=0D =0D #pragma pack(1)=0D =0D @@ -24,71 +25,71 @@ /// RISC-V processor specific data HOB=0D ///=0D typedef struct {=0D - EFI_GUID ParentProcessorGuid;=0D - UINTN ParentProcessorUid;=0D - EFI_GUID CoreGuid;=0D - VOID *Context; // The additional information of this core whi= ch=0D - // built in PEI phase and carried to DXE phase= .=0D - // The content is processor or platform specif= ic.=0D - SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA ProcessorSpecificData;=0D + EFI_GUID ParentProcessorGuid;=0D + UINTN ParentProcessorUid;=0D + EFI_GUID CoreGuid;=0D + VOID *Context; // The additional inf= ormation of this core which=0D + // built in PEI phase= and carried to DXE phase.=0D + // The content is pro= cessor or platform specific.=0D + SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA ProcessorSpecificData;=0D } RISC_V_PROCESSOR_SPECIFIC_HOB_DATA;=0D =0D ///=0D /// RISC-V SMBIOS type 4 (Processor) GUID data HOB=0D ///=0D typedef struct {=0D - EFI_GUID ProcessorGuid;=0D - UINTN ProcessorUid;=0D - SMBIOS_TABLE_TYPE4 SmbiosType4Processor;=0D - UINT16 EndingZero;=0D + EFI_GUID ProcessorGuid;=0D + UINTN ProcessorUid;=0D + SMBIOS_TABLE_TYPE4 SmbiosType4Processor;=0D + UINT16 EndingZero;=0D } RISC_V_PROCESSOR_TYPE4_HOB_DATA;=0D =0D -#define RISC_V_CACHE_INFO_NOT_PROVIDED 0xFFFF=0D -=0D -#define RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_MASK 0x7=0D - #define RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_1 0x01=0D - #define RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_2 0x02=0D - #define RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_3 0x03=0D -=0D -#define RISC_V_CACHE_CONFIGURATION_SOCKET_BIT_POSITION 3=0D -#define RISC_V_CACHE_CONFIGURATION_SOCKET_MASK (0x1 << RISC_V_CACHE_CONFIG= URATION_SOCKET_BIT_POSITION)=0D - #define RISC_V_CACHE_CONFIGURATION_SOCKET_SOCKETED (0x1 << RISC_V_CACHE_= CONFIGURATION_SOCKET_BIT_POSITION)=0D -=0D -#define RISC_V_CACHE_CONFIGURATION_LOCATION_BIT_POSITION 5=0D -#define RISC_V_CACHE_CONFIGURATION_LOCATION_MASK (0x3 << RISC_V_CACHE_CONF= IGURATION_LOCATION_BIT_POSITION)=0D - #define RISC_V_CACHE_CONFIGURATION_LOCATION_INTERNAL (0x0 << RISC_V_CACH= E_CONFIGURATION_LOCATION_BIT_POSITION)=0D - #define RISC_V_CACHE_CONFIGURATION_LOCATION_EXTERNAL (0x1 << RISC_V_CACH= E_CONFIGURATION_LOCATION_BIT_POSITION)=0D - #define RISC_V_CACHE_CONFIGURATION_LOCATION_RESERVED (0x2 << RISC_V_CACH= E_CONFIGURATION_LOCATION_BIT_POSITION)=0D - #define RISC_V_CACHE_CONFIGURATION_LOCATION_UNKNOWN (0x3 << RISC_V_CACH= E_CONFIGURATION_LOCATION_BIT_POSITION)=0D -=0D -#define RISC_V_CACHE_CONFIGURATION_ENABLE_BIT_POSITION 7=0D -#define RISC_V_CACHE_CONFIGURATION_ENABLE_MASK (0x1 << RISC_V_CACHE_= CONFIGURATION_ENABLE_BIT_POSITION)=0D - #define RISC_V_CACHE_CONFIGURATION_ENABLED (0x1 << RISC_V_CACH= E_CONFIGURATION_ENABLE_BIT_POSITION)=0D -=0D -#define RISC_V_CACHE_CONFIGURATION_MODE_BIT_POSITION 8=0D -#define RISC_V_CACHE_CONFIGURATION_MODE_MASK (0x3 << RISC_V_CACHE_CO= NFIGURATION_MODE_BIT_POSITION)=0D - #define RISC_V_CACHE_CONFIGURATION_MODE_WT (0x0 << RISC_V_CACHE_CO= NFIGURATION_MODE_BIT_POSITION)=0D - #define RISC_V_CACHE_CONFIGURATION_MODE_WB (0x1 << RISC_V_CACHE_CO= NFIGURATION_MODE_BIT_POSITION)=0D - #define RISC_V_CACHE_CONFIGURATION_MODE_VARIES (0x2 << RISC_V_CACHE_CO= NFIGURATION_MODE_BIT_POSITION)=0D - #define RISC_V_CACHE_CONFIGURATION_MODE_UNKNOWN (0x3 << RISC_V_CACHE_CO= NFIGURATION_MODE_BIT_POSITION)=0D +#define RISC_V_CACHE_INFO_NOT_PROVIDED 0xFFFF=0D +=0D +#define RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_MASK 0x7=0D +#define RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_1 0x01=0D +#define RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_2 0x02=0D +#define RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_3 0x03=0D +=0D +#define RISC_V_CACHE_CONFIGURATION_SOCKET_BIT_POSITION 3=0D +#define RISC_V_CACHE_CONFIGURATION_SOCKET_MASK (0x1 << RISC_V_CAC= HE_CONFIGURATION_SOCKET_BIT_POSITION)=0D +#define RISC_V_CACHE_CONFIGURATION_SOCKET_SOCKETED (0x1 << RISC_V_CAC= HE_CONFIGURATION_SOCKET_BIT_POSITION)=0D +=0D +#define RISC_V_CACHE_CONFIGURATION_LOCATION_BIT_POSITION 5=0D +#define RISC_V_CACHE_CONFIGURATION_LOCATION_MASK (0x3 << RISC_V_C= ACHE_CONFIGURATION_LOCATION_BIT_POSITION)=0D +#define RISC_V_CACHE_CONFIGURATION_LOCATION_INTERNAL (0x0 << RISC_V_C= ACHE_CONFIGURATION_LOCATION_BIT_POSITION)=0D +#define RISC_V_CACHE_CONFIGURATION_LOCATION_EXTERNAL (0x1 << RISC_V_C= ACHE_CONFIGURATION_LOCATION_BIT_POSITION)=0D +#define RISC_V_CACHE_CONFIGURATION_LOCATION_RESERVED (0x2 << RISC_V_C= ACHE_CONFIGURATION_LOCATION_BIT_POSITION)=0D +#define RISC_V_CACHE_CONFIGURATION_LOCATION_UNKNOWN (0x3 << RISC_V_C= ACHE_CONFIGURATION_LOCATION_BIT_POSITION)=0D +=0D +#define RISC_V_CACHE_CONFIGURATION_ENABLE_BIT_POSITION 7=0D +#define RISC_V_CACHE_CONFIGURATION_ENABLE_MASK (0x1 << RISC_V_CAC= HE_CONFIGURATION_ENABLE_BIT_POSITION)=0D +#define RISC_V_CACHE_CONFIGURATION_ENABLED (0x1 << RISC_V_CAC= HE_CONFIGURATION_ENABLE_BIT_POSITION)=0D +=0D +#define RISC_V_CACHE_CONFIGURATION_MODE_BIT_POSITION 8=0D +#define RISC_V_CACHE_CONFIGURATION_MODE_MASK (0x3 << RISC_V_CACHE= _CONFIGURATION_MODE_BIT_POSITION)=0D +#define RISC_V_CACHE_CONFIGURATION_MODE_WT (0x0 << RISC_V_CACHE= _CONFIGURATION_MODE_BIT_POSITION)=0D +#define RISC_V_CACHE_CONFIGURATION_MODE_WB (0x1 << RISC_V_CACHE= _CONFIGURATION_MODE_BIT_POSITION)=0D +#define RISC_V_CACHE_CONFIGURATION_MODE_VARIES (0x2 << RISC_V_CACHE= _CONFIGURATION_MODE_BIT_POSITION)=0D +#define RISC_V_CACHE_CONFIGURATION_MODE_UNKNOWN (0x3 << RISC_V_CACHE= _CONFIGURATION_MODE_BIT_POSITION)=0D ///=0D /// RISC-V SMBIOS type 7 (Cache) GUID data HOB=0D ///=0D typedef struct {=0D - EFI_GUID ProcessorGuid;=0D - UINTN ProcessorUid;=0D - SMBIOS_TABLE_TYPE7 SmbiosType7Cache;=0D - UINT16 EndingZero;=0D + EFI_GUID ProcessorGuid;=0D + UINTN ProcessorUid;=0D + SMBIOS_TABLE_TYPE7 SmbiosType7Cache;=0D + UINT16 EndingZero;=0D } RISC_V_PROCESSOR_TYPE7_HOB_DATA;=0D =0D ///=0D /// RISC-V SMBIOS type 7 (Cache) GUID data HOB=0D ///=0D typedef struct {=0D - RISC_V_PROCESSOR_TYPE4_HOB_DATA *Processor;=0D - RISC_V_PROCESSOR_TYPE7_HOB_DATA *L1Cache;=0D - RISC_V_PROCESSOR_TYPE7_HOB_DATA *L2Cache;=0D - RISC_V_PROCESSOR_TYPE7_HOB_DATA *L3Cache;=0D + RISC_V_PROCESSOR_TYPE4_HOB_DATA *Processor;=0D + RISC_V_PROCESSOR_TYPE7_HOB_DATA *L1Cache;=0D + RISC_V_PROCESSOR_TYPE7_HOB_DATA *L2Cache;=0D + RISC_V_PROCESSOR_TYPE7_HOB_DATA *L3Cache;=0D } RISC_V_PROCESSOR_SMBIOS_HOB_DATA;=0D =0D #pragma pack()=0D diff --git a/Silicon/RISC-V/ProcessorPkg/Include/RiscVImpl.h b/Silicon/RISC= -V/ProcessorPkg/Include/RiscVImpl.h index 14092df174..261de69869 100644 --- a/Silicon/RISC-V/ProcessorPkg/Include/RiscVImpl.h +++ b/Silicon/RISC-V/ProcessorPkg/Include/RiscVImpl.h @@ -1,7 +1,7 @@ /** @file=0D RISC-V package definitions.=0D =0D - Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. Al= l rights reserved.
=0D + Copyright (c) 2016 - 2022, Hewlett Packard Enterprise Development LP. Al= l rights reserved.
=0D =0D SPDX-License-Identifier: BSD-2-Clause-Patent=0D =0D @@ -20,7 +20,7 @@ .p2align 2 ; \=0D Name:=0D =0D -#define ASM_FUNC(Name) _ASM_FUNC(ASM_PFX(Name), .text. ## Name)=0D +#define ASM_FUNC(Name) _ASM_FUNC(ASM_PFX(Name), .text. ## Name)=0D =0D #if defined (MDE_CPU_RISCV64)=0D typedef UINT64 RISC_V_REGS_PROTOTYPE;=0D @@ -31,8 +31,8 @@ typedef UINT64 RISC_V_REGS_PROTOTYPE; // Structure for 128-bit value=0D //=0D typedef struct {=0D - UINT64 Value64_L;=0D - UINT64 Value64_H;=0D + UINT64 Value64_L;=0D + UINT64 Value64_H;=0D } RISCV_UINT128;=0D =0D #define RISCV_MACHINE_CONTEXT_SIZE 0x1000=0D @@ -42,46 +42,46 @@ typedef struct _RISCV_MACHINE_MODE_CONTEXT RISCV_MACHIN= E_MODE_CONTEXT; /// Exception handlers in context.=0D ///=0D typedef struct _EXCEPTION_HANDLER_CONTEXT {=0D - EFI_PHYSICAL_ADDRESS InstAddressMisalignedHander;=0D - EFI_PHYSICAL_ADDRESS InstAccessFaultHander;=0D - EFI_PHYSICAL_ADDRESS IllegalInstHander;=0D - EFI_PHYSICAL_ADDRESS BreakpointHander;=0D - EFI_PHYSICAL_ADDRESS LoadAddrMisalignedHander;=0D - EFI_PHYSICAL_ADDRESS LoadAccessFaultHander;=0D - EFI_PHYSICAL_ADDRESS StoreAmoAddrMisalignedHander;=0D - EFI_PHYSICAL_ADDRESS StoreAmoAccessFaultHander;=0D - EFI_PHYSICAL_ADDRESS EnvCallFromUModeHander;=0D - EFI_PHYSICAL_ADDRESS EnvCallFromSModeHander;=0D - EFI_PHYSICAL_ADDRESS EnvCallFromHModeHander;=0D - EFI_PHYSICAL_ADDRESS EnvCallFromMModeHander;=0D + EFI_PHYSICAL_ADDRESS InstAddressMisalignedHander;=0D + EFI_PHYSICAL_ADDRESS InstAccessFaultHander;=0D + EFI_PHYSICAL_ADDRESS IllegalInstHander;=0D + EFI_PHYSICAL_ADDRESS BreakpointHander;=0D + EFI_PHYSICAL_ADDRESS LoadAddrMisalignedHander;=0D + EFI_PHYSICAL_ADDRESS LoadAccessFaultHander;=0D + EFI_PHYSICAL_ADDRESS StoreAmoAddrMisalignedHander;=0D + EFI_PHYSICAL_ADDRESS StoreAmoAccessFaultHander;=0D + EFI_PHYSICAL_ADDRESS EnvCallFromUModeHander;=0D + EFI_PHYSICAL_ADDRESS EnvCallFromSModeHander;=0D + EFI_PHYSICAL_ADDRESS EnvCallFromHModeHander;=0D + EFI_PHYSICAL_ADDRESS EnvCallFromMModeHander;=0D } EXCEPTION_HANDLER_CONTEXT;=0D =0D ///=0D /// Exception handlers in context.=0D ///=0D typedef struct _INTERRUPT_HANDLER_CONTEXT {=0D - EFI_PHYSICAL_ADDRESS SoftwareIntHandler;=0D - EFI_PHYSICAL_ADDRESS TimerIntHandler;=0D + EFI_PHYSICAL_ADDRESS SoftwareIntHandler;=0D + EFI_PHYSICAL_ADDRESS TimerIntHandler;=0D } INTERRUPT_HANDLER_CONTEXT;=0D =0D ///=0D /// Interrupt handlers in context.=0D ///=0D typedef struct _TRAP_HANDLER_CONTEXT {=0D - EXCEPTION_HANDLER_CONTEXT ExceptionHandlerContext;=0D - INTERRUPT_HANDLER_CONTEXT IntHandlerContext;=0D + EXCEPTION_HANDLER_CONTEXT ExceptionHandlerContext;=0D + INTERRUPT_HANDLER_CONTEXT IntHandlerContext;=0D } TRAP_HANDLER_CONTEXT;=0D =0D ///=0D /// Machine mode context used for saveing hart-local context.=0D ///=0D typedef struct _RISCV_MACHINE_MODE_CONTEXT {=0D - EFI_PHYSICAL_ADDRESS PeiService; /// PEI service.=0D - EFI_PHYSICAL_ADDRESS MachineModeTrapHandler; /// Machine mode trap ha= ndler.=0D - EFI_PHYSICAL_ADDRESS HypervisorModeTrapHandler; /// Hypervisor mode trap= handler.=0D - EFI_PHYSICAL_ADDRESS SupervisorModeTrapHandler; /// Supervisor mode trap= handler.=0D - EFI_PHYSICAL_ADDRESS UserModeTrapHandler; /// USer mode trap handl= er.=0D - TRAP_HANDLER_CONTEXT MModeHandler; /// Handler for machine = mode.=0D + EFI_PHYSICAL_ADDRESS PeiService; /// PEI service.=0D + EFI_PHYSICAL_ADDRESS MachineModeTrapHandler; /// Machine mode trap= handler.=0D + EFI_PHYSICAL_ADDRESS HypervisorModeTrapHandler; /// Hypervisor mode t= rap handler.=0D + EFI_PHYSICAL_ADDRESS SupervisorModeTrapHandler; /// Supervisor mode t= rap handler.=0D + EFI_PHYSICAL_ADDRESS UserModeTrapHandler; /// USer mode trap ha= ndler.=0D + TRAP_HANDLER_CONTEXT MModeHandler; /// Handler for machi= ne mode.=0D } RISCV_MACHINE_MODE_CONTEXT;=0D =0D #endif=0D diff --git a/Silicon/RISC-V/ProcessorPkg/Include/SmbiosProcessorSpecificDat= a.h b/Silicon/RISC-V/ProcessorPkg/Include/SmbiosProcessorSpecificData.h index 85b8dcbe20..090c5320e0 100644 --- a/Silicon/RISC-V/ProcessorPkg/Include/SmbiosProcessorSpecificData.h +++ b/Silicon/RISC-V/ProcessorPkg/Include/SmbiosProcessorSpecificData.h @@ -8,6 +8,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent=0D =0D **/=0D +=0D #ifndef SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA_H_=0D #define SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA_H_=0D =0D @@ -16,42 +17,41 @@ =0D #pragma pack(1)=0D =0D -typedef enum{=0D +typedef enum {=0D RegisterUnsupported =3D 0x00,=0D RegisterLen32 =3D 0x01,=0D RegisterLen64 =3D 0x02,=0D RegisterLen128 =3D 0x03=0D } RISC_V_REGISTER_LENGTH;=0D =0D -#define SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA_REVISION 0x100=0D +#define SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA_REVISION 0x100=0D =0D -#define SMBIOS_RISC_V_PSD_MACHINE_MODE_SUPPORTED (0x01 << 0)=0D -#define SMBIOS_RISC_V_PSD_SUPERVISOR_MODE_SUPPORTED (0x01 << 2)=0D -#define SMBIOS_RISC_V_PSD_USER_MODE_SUPPORTED (0x01 << 3)=0D -#define SMBIOS_RISC_V_PSD_DEBUG_MODE_SUPPORTED (0x01 << 7)=0D +#define SMBIOS_RISC_V_PSD_MACHINE_MODE_SUPPORTED (0x01 << 0)=0D +#define SMBIOS_RISC_V_PSD_SUPERVISOR_MODE_SUPPORTED (0x01 << 2)=0D +#define SMBIOS_RISC_V_PSD_USER_MODE_SUPPORTED (0x01 << 3)=0D +#define SMBIOS_RISC_V_PSD_DEBUG_MODE_SUPPORTED (0x01 << 7)=0D =0D ///=0D /// RISC-V processor specific data for SMBIOS type 44=0D ///=0D typedef struct {=0D - UINT16 Revision;=0D - UINT8 Length;=0D - RISCV_UINT128 HartId;=0D - UINT8 BootHartId;=0D - RISCV_UINT128 MachineVendorId;=0D - RISCV_UINT128 MachineArchId;=0D - RISCV_UINT128 MachineImplId;=0D - UINT32 InstSetSupported;=0D - UINT8 PrivilegeModeSupported;=0D - RISCV_UINT128 MModeExcepDelegation;=0D - RISCV_UINT128 MModeInterruptDelegation;=0D - UINT8 HartXlen;=0D - UINT8 MachineModeXlen;=0D - UINT8 Reserved;=0D - UINT8 SupervisorModeXlen;=0D - UINT8 UserModeXlen;=0D + UINT16 Revision;=0D + UINT8 Length;=0D + RISCV_UINT128 HartId;=0D + UINT8 BootHartId;=0D + RISCV_UINT128 MachineVendorId;=0D + RISCV_UINT128 MachineArchId;=0D + RISCV_UINT128 MachineImplId;=0D + UINT32 InstSetSupported;=0D + UINT8 PrivilegeModeSupported;=0D + RISCV_UINT128 MModeExcepDelegation;=0D + RISCV_UINT128 MModeInterruptDelegation;=0D + UINT8 HartXlen;=0D + UINT8 MachineModeXlen;=0D + UINT8 Reserved;=0D + UINT8 SupervisorModeXlen;=0D + UINT8 UserModeXlen;=0D } SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA;=0D =0D #pragma pack()=0D #endif=0D -=0D diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVExceptionLib/CpuExcep= tionHandlerLib.h b/Silicon/RISC-V/ProcessorPkg/Library/RiscVExceptionLib/Cp= uExceptionHandlerLib.h index b316510020..350d20110a 100644 --- a/Silicon/RISC-V/ProcessorPkg/Library/RiscVExceptionLib/CpuExceptionHan= dlerLib.h +++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVExceptionLib/CpuExceptionHan= dlerLib.h @@ -2,7 +2,7 @@ =0D RISC-V Exception Handler library definition file.=0D =0D - Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All right= s reserved.
=0D + Copyright (c) 2019-2022, Hewlett Packard Enterprise Development LP. All = rights reserved.
=0D =0D SPDX-License-Identifier: BSD-2-Clause-Patent=0D =0D @@ -11,96 +11,99 @@ #ifndef RISCV_CPU_EXECPTION_HANDLER_LIB_H_=0D #define RISCV_CPU_EXECPTION_HANDLER_LIB_H_=0D =0D -extern void SupervisorModeTrap(void);=0D +extern void=0D +SupervisorModeTrap (=0D + void=0D + );=0D =0D //=0D // Index of SMode trap register=0D //=0D -#define SMODE_TRAP_REGS_zero 0=0D -#define SMODE_TRAP_REGS_ra 1=0D -#define SMODE_TRAP_REGS_sp 2=0D -#define SMODE_TRAP_REGS_gp 3=0D -#define SMODE_TRAP_REGS_tp 4=0D -#define SMODE_TRAP_REGS_t0 5=0D -#define SMODE_TRAP_REGS_t1 6=0D -#define SMODE_TRAP_REGS_t2 7=0D -#define SMODE_TRAP_REGS_s0 8=0D -#define SMODE_TRAP_REGS_s1 9=0D -#define SMODE_TRAP_REGS_a0 10=0D -#define SMODE_TRAP_REGS_a1 11=0D -#define SMODE_TRAP_REGS_a2 12=0D -#define SMODE_TRAP_REGS_a3 13=0D -#define SMODE_TRAP_REGS_a4 14=0D -#define SMODE_TRAP_REGS_a5 15=0D -#define SMODE_TRAP_REGS_a6 16=0D -#define SMODE_TRAP_REGS_a7 17=0D -#define SMODE_TRAP_REGS_s2 18=0D -#define SMODE_TRAP_REGS_s3 19=0D -#define SMODE_TRAP_REGS_s4 20=0D -#define SMODE_TRAP_REGS_s5 21=0D -#define SMODE_TRAP_REGS_s6 22=0D -#define SMODE_TRAP_REGS_s7 23=0D -#define SMODE_TRAP_REGS_s8 24=0D -#define SMODE_TRAP_REGS_s9 25=0D -#define SMODE_TRAP_REGS_s10 26=0D -#define SMODE_TRAP_REGS_s11 27=0D -#define SMODE_TRAP_REGS_t3 28=0D -#define SMODE_TRAP_REGS_t4 29=0D -#define SMODE_TRAP_REGS_t5 30=0D -#define SMODE_TRAP_REGS_t6 31=0D -#define SMODE_TRAP_REGS_sepc 32=0D -#define SMODE_TRAP_REGS_sstatus 33=0D -#define SMODE_TRAP_REGS_sie 34=0D -#define SMODE_TRAP_REGS_last 35=0D +#define SMODE_TRAP_REGS_zero 0=0D +#define SMODE_TRAP_REGS_ra 1=0D +#define SMODE_TRAP_REGS_sp 2=0D +#define SMODE_TRAP_REGS_gp 3=0D +#define SMODE_TRAP_REGS_tp 4=0D +#define SMODE_TRAP_REGS_t0 5=0D +#define SMODE_TRAP_REGS_t1 6=0D +#define SMODE_TRAP_REGS_t2 7=0D +#define SMODE_TRAP_REGS_s0 8=0D +#define SMODE_TRAP_REGS_s1 9=0D +#define SMODE_TRAP_REGS_a0 10=0D +#define SMODE_TRAP_REGS_a1 11=0D +#define SMODE_TRAP_REGS_a2 12=0D +#define SMODE_TRAP_REGS_a3 13=0D +#define SMODE_TRAP_REGS_a4 14=0D +#define SMODE_TRAP_REGS_a5 15=0D +#define SMODE_TRAP_REGS_a6 16=0D +#define SMODE_TRAP_REGS_a7 17=0D +#define SMODE_TRAP_REGS_s2 18=0D +#define SMODE_TRAP_REGS_s3 19=0D +#define SMODE_TRAP_REGS_s4 20=0D +#define SMODE_TRAP_REGS_s5 21=0D +#define SMODE_TRAP_REGS_s6 22=0D +#define SMODE_TRAP_REGS_s7 23=0D +#define SMODE_TRAP_REGS_s8 24=0D +#define SMODE_TRAP_REGS_s9 25=0D +#define SMODE_TRAP_REGS_s10 26=0D +#define SMODE_TRAP_REGS_s11 27=0D +#define SMODE_TRAP_REGS_t3 28=0D +#define SMODE_TRAP_REGS_t4 29=0D +#define SMODE_TRAP_REGS_t5 30=0D +#define SMODE_TRAP_REGS_t6 31=0D +#define SMODE_TRAP_REGS_sepc 32=0D +#define SMODE_TRAP_REGS_sstatus 33=0D +#define SMODE_TRAP_REGS_sie 34=0D +#define SMODE_TRAP_REGS_last 35=0D =0D -#define SMODE_TRAP_REGS_OFFSET(x) ((SMODE_TRAP_REGS_##x) * __SIZEOF_POINTE= R__)=0D -#define SMODE_TRAP_REGS_SIZE SMODE_TRAP_REGS_OFFSET(last)=0D +#define SMODE_TRAP_REGS_OFFSET(x) ((SMODE_TRAP_REGS_##x) * __SIZEOF_POINT= ER__)=0D +#define SMODE_TRAP_REGS_SIZE SMODE_TRAP_REGS_OFFSET(last)=0D =0D #pragma pack(1)=0D typedef struct {=0D -//=0D -// Below are follow the format of EFI_SYSTEM_CONTEXT=0D -//=0D - RISC_V_REGS_PROTOTYPE zero;=0D - RISC_V_REGS_PROTOTYPE ra;=0D - RISC_V_REGS_PROTOTYPE sp;=0D - RISC_V_REGS_PROTOTYPE gp;=0D - RISC_V_REGS_PROTOTYPE tp;=0D - RISC_V_REGS_PROTOTYPE t0;=0D - RISC_V_REGS_PROTOTYPE t1;=0D - RISC_V_REGS_PROTOTYPE t2;=0D - RISC_V_REGS_PROTOTYPE s0;=0D - RISC_V_REGS_PROTOTYPE s1;=0D - RISC_V_REGS_PROTOTYPE a0;=0D - RISC_V_REGS_PROTOTYPE a1;=0D - RISC_V_REGS_PROTOTYPE a2;=0D - RISC_V_REGS_PROTOTYPE a3;=0D - RISC_V_REGS_PROTOTYPE a4;=0D - RISC_V_REGS_PROTOTYPE a5;=0D - RISC_V_REGS_PROTOTYPE a6;=0D - RISC_V_REGS_PROTOTYPE a7;=0D - RISC_V_REGS_PROTOTYPE s2;=0D - RISC_V_REGS_PROTOTYPE s3;=0D - RISC_V_REGS_PROTOTYPE s4;=0D - RISC_V_REGS_PROTOTYPE s5;=0D - RISC_V_REGS_PROTOTYPE s6;=0D - RISC_V_REGS_PROTOTYPE s7;=0D - RISC_V_REGS_PROTOTYPE s8;=0D - RISC_V_REGS_PROTOTYPE s9;=0D - RISC_V_REGS_PROTOTYPE s10;=0D - RISC_V_REGS_PROTOTYPE s11;=0D - RISC_V_REGS_PROTOTYPE t3;=0D - RISC_V_REGS_PROTOTYPE t4;=0D - RISC_V_REGS_PROTOTYPE t5;=0D - RISC_V_REGS_PROTOTYPE t6;=0D -//=0D -// Below are the additional information to=0D -// EFI_SYSTEM_CONTEXT, private to supervisor mode trap=0D -// and not public to EFI environment.=0D -//=0D - RISC_V_REGS_PROTOTYPE sepc;=0D - RISC_V_REGS_PROTOTYPE sstatus;=0D - RISC_V_REGS_PROTOTYPE sie;=0D + //=0D + // Below are follow the format of EFI_SYSTEM_CONTEXT=0D + //=0D + RISC_V_REGS_PROTOTYPE zero;=0D + RISC_V_REGS_PROTOTYPE ra;=0D + RISC_V_REGS_PROTOTYPE sp;=0D + RISC_V_REGS_PROTOTYPE gp;=0D + RISC_V_REGS_PROTOTYPE tp;=0D + RISC_V_REGS_PROTOTYPE t0;=0D + RISC_V_REGS_PROTOTYPE t1;=0D + RISC_V_REGS_PROTOTYPE t2;=0D + RISC_V_REGS_PROTOTYPE s0;=0D + RISC_V_REGS_PROTOTYPE s1;=0D + RISC_V_REGS_PROTOTYPE a0;=0D + RISC_V_REGS_PROTOTYPE a1;=0D + RISC_V_REGS_PROTOTYPE a2;=0D + RISC_V_REGS_PROTOTYPE a3;=0D + RISC_V_REGS_PROTOTYPE a4;=0D + RISC_V_REGS_PROTOTYPE a5;=0D + RISC_V_REGS_PROTOTYPE a6;=0D + RISC_V_REGS_PROTOTYPE a7;=0D + RISC_V_REGS_PROTOTYPE s2;=0D + RISC_V_REGS_PROTOTYPE s3;=0D + RISC_V_REGS_PROTOTYPE s4;=0D + RISC_V_REGS_PROTOTYPE s5;=0D + RISC_V_REGS_PROTOTYPE s6;=0D + RISC_V_REGS_PROTOTYPE s7;=0D + RISC_V_REGS_PROTOTYPE s8;=0D + RISC_V_REGS_PROTOTYPE s9;=0D + RISC_V_REGS_PROTOTYPE s10;=0D + RISC_V_REGS_PROTOTYPE s11;=0D + RISC_V_REGS_PROTOTYPE t3;=0D + RISC_V_REGS_PROTOTYPE t4;=0D + RISC_V_REGS_PROTOTYPE t5;=0D + RISC_V_REGS_PROTOTYPE t6;=0D + //=0D + // Below are the additional information to=0D + // EFI_SYSTEM_CONTEXT, private to supervisor mode trap=0D + // and not public to EFI environment.=0D + //=0D + RISC_V_REGS_PROTOTYPE sepc;=0D + RISC_V_REGS_PROTOTYPE sstatus;=0D + RISC_V_REGS_PROTOTYPE sie;=0D } SMODE_TRAP_REGISTERS;=0D #pragma pack()=0D =0D diff --git a/Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxe.h b/Silico= n/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxe.h index c2c2739434..9d70d7b6e8 100644 --- a/Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxe.h +++ b/Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxe.h @@ -1,7 +1,7 @@ /** @file=0D RISC-V CPU DXE module header file.=0D =0D - Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. Al= l rights reserved.
=0D + Copyright (c) 2016 - 2022, Hewlett Packard Enterprise Development LP. Al= l rights reserved.
=0D =0D SPDX-License-Identifier: BSD-2-Clause-Patent=0D =0D @@ -38,10 +38,10 @@ EFI_STATUS=0D EFIAPI=0D CpuFlushCpuDataCache (=0D - IN EFI_CPU_ARCH_PROTOCOL *This,=0D - IN EFI_PHYSICAL_ADDRESS Start,=0D - IN UINT64 Length,=0D - IN EFI_CPU_FLUSH_TYPE FlushType=0D + IN EFI_CPU_ARCH_PROTOCOL *This,=0D + IN EFI_PHYSICAL_ADDRESS Start,=0D + IN UINT64 Length,=0D + IN EFI_CPU_FLUSH_TYPE FlushType=0D );=0D =0D /**=0D @@ -56,7 +56,7 @@ CpuFlushCpuDataCache ( EFI_STATUS=0D EFIAPI=0D CpuEnableInterrupt (=0D - IN EFI_CPU_ARCH_PROTOCOL *This=0D + IN EFI_CPU_ARCH_PROTOCOL *This=0D );=0D =0D /**=0D @@ -71,7 +71,7 @@ CpuEnableInterrupt ( EFI_STATUS=0D EFIAPI=0D CpuDisableInterrupt (=0D - IN EFI_CPU_ARCH_PROTOCOL *This=0D + IN EFI_CPU_ARCH_PROTOCOL *This=0D );=0D =0D /**=0D @@ -87,8 +87,8 @@ CpuDisableInterrupt ( EFI_STATUS=0D EFIAPI=0D CpuGetInterruptState (=0D - IN EFI_CPU_ARCH_PROTOCOL *This,=0D - OUT BOOLEAN *State=0D + IN EFI_CPU_ARCH_PROTOCOL *This,=0D + OUT BOOLEAN *State=0D );=0D =0D /**=0D @@ -106,8 +106,8 @@ CpuGetInterruptState ( EFI_STATUS=0D EFIAPI=0D CpuInit (=0D - IN EFI_CPU_ARCH_PROTOCOL *This,=0D - IN EFI_CPU_INIT_TYPE InitType=0D + IN EFI_CPU_ARCH_PROTOCOL *This,=0D + IN EFI_CPU_INIT_TYPE InitType=0D );=0D =0D /**=0D @@ -133,9 +133,9 @@ CpuInit ( EFI_STATUS=0D EFIAPI=0D CpuRegisterInterruptHandler (=0D - IN EFI_CPU_ARCH_PROTOCOL *This,=0D - IN EFI_EXCEPTION_TYPE InterruptType,=0D - IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler=0D + IN EFI_CPU_ARCH_PROTOCOL *This,=0D + IN EFI_EXCEPTION_TYPE InterruptType,=0D + IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler=0D );=0D =0D /**=0D @@ -164,10 +164,10 @@ CpuRegisterInterruptHandler ( EFI_STATUS=0D EFIAPI=0D CpuGetTimerValue (=0D - IN EFI_CPU_ARCH_PROTOCOL *This,=0D - IN UINT32 TimerIndex,=0D - OUT UINT64 *TimerValue,=0D - OUT UINT64 *TimerPeriod OPTIONAL=0D + IN EFI_CPU_ARCH_PROTOCOL *This,=0D + IN UINT32 TimerIndex,=0D + OUT UINT64 *TimerValue,=0D + OUT UINT64 *TimerPeriod OPTIONAL=0D );=0D =0D /**=0D @@ -189,11 +189,10 @@ CpuGetTimerValue ( EFI_STATUS=0D EFIAPI=0D CpuSetMemoryAttributes (=0D - IN EFI_CPU_ARCH_PROTOCOL *This,=0D - IN EFI_PHYSICAL_ADDRESS BaseAddress,=0D - IN UINT64 Length,=0D - IN UINT64 Attributes=0D + IN EFI_CPU_ARCH_PROTOCOL *This,=0D + IN EFI_PHYSICAL_ADDRESS BaseAddress,=0D + IN UINT64 Length,=0D + IN UINT64 Attributes=0D );=0D =0D #endif=0D -=0D diff --git a/Silicon/RISC-V/ProcessorPkg/Universal/SmbiosDxe/RiscVSmbiosDxe= .h b/Silicon/RISC-V/ProcessorPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.h index 1072877ad8..cbeb5ec37d 100644 --- a/Silicon/RISC-V/ProcessorPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.h +++ b/Silicon/RISC-V/ProcessorPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.h @@ -1,7 +1,7 @@ /** @file=0D RISC-V SMBIOS Builder DXE module header file.=0D =0D - Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All right= s reserved.
=0D + Copyright (c) 2019-2022, Hewlett Packard Enterprise Development LP. All = rights reserved.
=0D =0D SPDX-License-Identifier: BSD-2-Clause-Patent=0D =0D @@ -20,4 +20,3 @@ #include =0D #include =0D #endif=0D -=0D diff --git a/Silicon/RISC-V/ProcessorPkg/Library/PeiServicesTablePointerLib= OpenSbi/PeiServicesTablePointerOpenSbi.c b/Silicon/RISC-V/ProcessorPkg/Libr= ary/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerOpenSbi.c index 9aa74b4f9f..23607a4eba 100644 --- a/Silicon/RISC-V/ProcessorPkg/Library/PeiServicesTablePointerLibOpenSbi= /PeiServicesTablePointerOpenSbi.c +++ b/Silicon/RISC-V/ProcessorPkg/Library/PeiServicesTablePointerLibOpenSbi= /PeiServicesTablePointerOpenSbi.c @@ -1,7 +1,7 @@ /** @file=0D PEI Services Table Pointer Library.=0D =0D - Copyright (c) 2019 - 2021, Hewlett Packard Enterprise Development LP. Al= l rights reserved.
=0D + Copyright (c) 2019 - 2022, Hewlett Packard Enterprise Development LP. Al= l rights reserved.
=0D =0D SPDX-License-Identifier: BSD-2-Clause-Patent=0D **/=0D @@ -28,18 +28,20 @@ VOID=0D EFIAPI=0D SetPeiServicesTablePointer (=0D - IN CONST EFI_PEI_SERVICES ** PeiServicesTablePointer=0D + IN CONST EFI_PEI_SERVICES **PeiServicesTablePointer=0D )=0D {=0D - EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *FirmwareContext;=0D + EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *FirmwareContext;=0D =0D GetFirmwareContextPointer (&FirmwareContext);=0D FirmwareContext->PeiServiceTable =3D (VOID *)(UINTN)PeiServicesTablePoin= ter;=0D =0D - DEBUG ((DEBUG_INFO, "Set PEI Service 0x%x at OpenSBI Firmware Context at= 0x%x\n",=0D - PeiServicesTablePointer,=0D - FirmwareContext=0D - ));=0D + DEBUG ((=0D + DEBUG_INFO,=0D + "Set PEI Service 0x%x at OpenSBI Firmware Context at 0x%x\n",=0D + PeiServicesTablePointer,=0D + FirmwareContext=0D + ));=0D }=0D =0D /**=0D @@ -60,7 +62,7 @@ GetPeiServicesTablePointer ( VOID=0D )=0D {=0D - EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *FirmwareContext;=0D + EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *FirmwareContext;=0D =0D GetFirmwareContextPointer (&FirmwareContext);=0D return (CONST EFI_PEI_SERVICES **)FirmwareContext->PeiServiceTable;=0D @@ -81,8 +83,8 @@ GetPeiServicesTablePointer ( EFI_STATUS=0D EFIAPI=0D PeiServicesTablePointerLibOpenSbiConstructor (=0D - IN EFI_PEI_FILE_HANDLE FileHandle,=0D - IN CONST EFI_PEI_SERVICES **PeiServices=0D + IN EFI_PEI_FILE_HANDLE FileHandle,=0D + IN CONST EFI_PEI_SERVICES **PeiServices=0D )=0D {=0D SetPeiServicesTablePointer (PeiServices);=0D diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVEdk2SbiLib/RiscVEdk2S= biLib.c b/Silicon/RISC-V/ProcessorPkg/Library/RiscVEdk2SbiLib/RiscVEdk2SbiL= ib.c index a51139542d..a25e16ab34 100644 --- a/Silicon/RISC-V/ProcessorPkg/Library/RiscVEdk2SbiLib/RiscVEdk2SbiLib.c +++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVEdk2SbiLib/RiscVEdk2SbiLib.c @@ -31,14 +31,13 @@ #include =0D #include =0D =0D -=0D //=0D // Maximum arguments for SBI ecall=0D // It's possible to pass more but no SBI call uses more as of SBI 0.2.=0D // The additional arguments would have to be passed on the stack instead o= f as=0D // registers, like it's done now.=0D //=0D -#define SBI_CALL_MAX_ARGS 6=0D +#define SBI_CALL_MAX_ARGS 6=0D =0D /**=0D Call SBI call using ecall instruction.=0D @@ -50,53 +49,55 @@ @param[in] NumArgs Number of arguments to pass to the ecall.=0D @param[in] ... Argument list for the ecall.=0D =0D - @retval Returns SbiRet structure with value and error code.=0D + @retval Returns SBI_RET structure with value and error code.=0D =0D **/=0D STATIC=0D -SbiRet=0D +SBI_RET=0D EFIAPI=0D -SbiCall(=0D - IN UINTN ExtId,=0D - IN UINTN FuncId,=0D - IN UINTN NumArgs,=0D +SbiCall (=0D + IN UINTN ExtId,=0D + IN UINTN FuncId,=0D + IN UINTN NumArgs,=0D ...=0D )=0D {=0D - UINTN I;=0D - SbiRet Ret;=0D - UINTN Args[SBI_CALL_MAX_ARGS];=0D - VA_LIST ArgList;=0D - VA_START (ArgList, NumArgs);=0D -=0D - ASSERT (NumArgs <=3D SBI_CALL_MAX_ARGS);=0D -=0D - for (I =3D 0; I < SBI_CALL_MAX_ARGS; I++) {=0D - if (I < NumArgs) {=0D - Args[I] =3D VA_ARG (ArgList, UINTN);=0D - } else {=0D - // Default to 0 for all arguments that are not given=0D - Args[I] =3D 0;=0D - }=0D + UINTN I;=0D + SBI_RET Ret;=0D + UINTN Args[SBI_CALL_MAX_ARGS];=0D + VA_LIST ArgList;=0D +=0D + VA_START (ArgList, NumArgs);=0D +=0D + ASSERT (NumArgs <=3D SBI_CALL_MAX_ARGS);=0D +=0D + for (I =3D 0; I < SBI_CALL_MAX_ARGS; I++) {=0D + if (I < NumArgs) {=0D + Args[I] =3D VA_ARG (ArgList, UINTN);=0D + } else {=0D + // Default to 0 for all arguments that are not given=0D + Args[I] =3D 0;=0D }=0D + }=0D =0D - VA_END(ArgList);=0D -=0D - register UINTN a0 asm ("a0") =3D Args[0];=0D - register UINTN a1 asm ("a1") =3D Args[1];=0D - register UINTN a2 asm ("a2") =3D Args[2];=0D - register UINTN a3 asm ("a3") =3D Args[3];=0D - register UINTN a4 asm ("a4") =3D Args[4];=0D - register UINTN a5 asm ("a5") =3D Args[5];=0D - register UINTN a6 asm ("a6") =3D (UINTN)(FuncId);=0D - register UINTN a7 asm ("a7") =3D (UINTN)(ExtId);=0D - asm volatile ("ecall" \=0D - : "+r" (a0), "+r" (a1) \=0D - : "r" (a2), "r" (a3), "r" (a4), "r" (a5), "r" (a6), "r" (a7) \=0D - : "memory"); \=0D - Ret.Error =3D a0;=0D - Ret.Value =3D a1;=0D - return Ret;=0D + VA_END (ArgList);=0D +=0D + register UINTN a0 asm ("a0") =3D Args[0];=0D + register UINTN a1 asm ("a1") =3D Args[1];=0D + register UINTN a2 asm ("a2") =3D Args[2];=0D + register UINTN a3 asm ("a3") =3D Args[3];=0D + register UINTN a4 asm ("a4") =3D Args[4];=0D + register UINTN a5 asm ("a5") =3D Args[5];=0D + register UINTN a6 asm ("a6") =3D (UINTN)(FuncId);=0D + register UINTN a7 asm ("a7") =3D (UINTN)(ExtId);=0D +=0D + asm volatile ("ecall" \=0D + : "+r" (a0), "+r" (a1) \=0D + : "r" (a2), "r" (a3), "r" (a4), "r" (a5), "r" (a6), "r" (a7) \=0D + : "memory"); \=0D + Ret.Error =3D a0;=0D + Ret.Value =3D a1;=0D + return Ret;=0D }=0D =0D /**=0D @@ -105,12 +106,11 @@ SbiCall( @param[in] SbiError SBI error code=0D @retval EFI_STATUS=0D **/=0D -=0D STATIC=0D EFI_STATUS=0D EFIAPI=0D -TranslateError(=0D - IN UINTN SbiError=0D +TranslateError (=0D + IN UINTN SbiError=0D )=0D {=0D switch (SbiError) {=0D @@ -160,10 +160,12 @@ TranslateError( VOID=0D EFIAPI=0D SbiGetSpecVersion (=0D - OUT UINTN *SpecVersion=0D + OUT UINTN *SpecVersion=0D )=0D {=0D - SbiRet Ret =3D SbiCall (SBI_EXT_BASE, SBI_EXT_BASE_GET_SPEC_VERSION, 0);= =0D + SBI_RET Ret;=0D +=0D + Ret =3D SbiCall (SBI_EXT_BASE, SBI_EXT_BASE_GET_SPEC_VERSION, 0);=0D =0D if (!Ret.Error) {=0D *SpecVersion =3D (UINTN)Ret.Value;=0D @@ -181,10 +183,13 @@ SbiGetSpecVersion ( VOID=0D EFIAPI=0D SbiGetImplId (=0D - OUT UINTN *ImplId=0D + OUT UINTN *ImplId=0D )=0D {=0D - SbiRet Ret =3D SbiCall (SBI_EXT_BASE, SBI_EXT_BASE_GET_IMP_ID, 0);=0D + SBI_RET Ret;=0D +=0D + Ret =3D SbiCall (SBI_EXT_BASE, SBI_EXT_BASE_GET_IMP_ID, 0);=0D +=0D *ImplId =3D (UINTN)Ret.Value;=0D }=0D =0D @@ -199,10 +204,13 @@ SbiGetImplId ( VOID=0D EFIAPI=0D SbiGetImplVersion (=0D - OUT UINTN *ImplVersion=0D + OUT UINTN *ImplVersion=0D )=0D {=0D - SbiRet Ret =3D SbiCall (SBI_EXT_BASE, SBI_EXT_BASE_GET_IMP_VERSION, 0);= =0D + SBI_RET Ret;=0D +=0D + Ret =3D SbiCall (SBI_EXT_BASE, SBI_EXT_BASE_GET_IMP_VERSION, 0);=0D +=0D *ImplVersion =3D (UINTN)Ret.Value;=0D }=0D =0D @@ -218,11 +226,14 @@ SbiGetImplVersion ( VOID=0D EFIAPI=0D SbiProbeExtension (=0D - IN INTN ExtensionId,=0D - OUT INTN *ProbeResult=0D + IN INTN ExtensionId,=0D + OUT INTN *ProbeResult=0D )=0D {=0D - SbiRet Ret =3D SbiCall (SBI_EXT_BASE, SBI_EXT_BASE_PROBE_EXT, 0);=0D + SBI_RET Ret;=0D +=0D + Ret =3D SbiCall (SBI_EXT_BASE, SBI_EXT_BASE_PROBE_EXT, 0);=0D +=0D *ProbeResult =3D (UINTN)Ret.Value;=0D }=0D =0D @@ -236,10 +247,13 @@ SbiProbeExtension ( VOID=0D EFIAPI=0D SbiGetMachineVendorId (=0D - OUT UINTN *MachineVendorId=0D + OUT UINTN *MachineVendorId=0D )=0D {=0D - SbiRet Ret =3D SbiCall (SBI_EXT_BASE, SBI_EXT_BASE_GET_MVENDORID, 0);=0D + SBI_RET Ret;=0D +=0D + Ret =3D SbiCall (SBI_EXT_BASE, SBI_EXT_BASE_GET_MVENDORID, 0);=0D +=0D *MachineVendorId =3D (UINTN)Ret.Value;=0D }=0D =0D @@ -253,10 +267,13 @@ SbiGetMachineVendorId ( VOID=0D EFIAPI=0D SbiGetMachineArchId (=0D - OUT UINTN *MachineArchId=0D + OUT UINTN *MachineArchId=0D )=0D {=0D - SbiRet Ret =3D SbiCall (SBI_EXT_BASE, SBI_EXT_BASE_GET_MARCHID, 0);=0D + SBI_RET Ret;=0D +=0D + Ret =3D SbiCall (SBI_EXT_BASE, SBI_EXT_BASE_GET_MARCHID, 0);=0D +=0D *MachineArchId =3D (UINTN)Ret.Value;=0D }=0D =0D @@ -270,10 +287,13 @@ SbiGetMachineArchId ( VOID=0D EFIAPI=0D SbiGetMachineImplId (=0D - OUT UINTN *MachineImplId=0D + OUT UINTN *MachineImplId=0D )=0D {=0D - SbiRet Ret =3D SbiCall (SBI_EXT_BASE, SBI_EXT_BASE_GET_MIMPID, 0);=0D + SBI_RET Ret;=0D +=0D + Ret =3D SbiCall (SBI_EXT_BASE, SBI_EXT_BASE_GET_MIMPID, 0);=0D +=0D *MachineImplId =3D (UINTN)Ret.Value;=0D }=0D =0D @@ -307,19 +327,22 @@ SbiGetMachineImplId ( EFI_STATUS=0D EFIAPI=0D SbiHartStart (=0D - IN UINTN HartId,=0D - IN UINTN StartAddr,=0D - IN UINTN Priv=0D + IN UINTN HartId,=0D + IN UINTN StartAddr,=0D + IN UINTN Priv=0D )=0D {=0D - SbiRet Ret =3D SbiCall (=0D - SBI_EXT_HSM,=0D - SBI_EXT_HSM_HART_START,=0D - 3,=0D - HartId,=0D - StartAddr,=0D - Priv=0D - );=0D + SBI_RET Ret;=0D +=0D + Ret =3D SbiCall (=0D + SBI_EXT_HSM,=0D + SBI_EXT_HSM_HART_START,=0D + 3,=0D + HartId,=0D + StartAddr,=0D + Priv=0D + );=0D +=0D return TranslateError (Ret.Error);=0D }=0D =0D @@ -337,7 +360,10 @@ EFIAPI SbiHartStop (=0D )=0D {=0D - SbiRet Ret =3D SbiCall (SBI_EXT_HSM, SBI_EXT_HSM_HART_STOP, 0);=0D + SBI_RET Ret;=0D +=0D + Ret =3D SbiCall (SBI_EXT_HSM, SBI_EXT_HSM_HART_STOP, 0);=0D +=0D return TranslateError (Ret.Error);=0D }=0D =0D @@ -361,11 +387,13 @@ SbiHartStop ( EFI_STATUS=0D EFIAPI=0D SbiHartGetStatus (=0D - IN UINTN HartId,=0D - OUT UINTN *HartStatus=0D + IN UINTN HartId,=0D + OUT UINTN *HartStatus=0D )=0D {=0D - SbiRet Ret =3D SbiCall (SBI_EXT_HSM, SBI_EXT_HSM_HART_GET_STATUS, 1, Har= tId);=0D + SBI_RET Ret;=0D +=0D + Ret =3D SbiCall (SBI_EXT_HSM, SBI_EXT_HSM_HART_GET_STATUS, 1, HartId);=0D =0D if (!Ret.Error) {=0D *HartStatus =3D (UINTN)Ret.Value;=0D @@ -385,7 +413,7 @@ SbiHartGetStatus ( VOID=0D EFIAPI=0D SbiSetTimer (=0D - IN UINT64 Time=0D + IN UINT64 Time=0D )=0D {=0D SbiCall (SBI_EXT_TIME, SBI_EXT_TIME_SET_TIMER, 1, Time);=0D @@ -394,17 +422,20 @@ SbiSetTimer ( EFI_STATUS=0D EFIAPI=0D SbiSendIpi (=0D - IN UINTN *HartMask,=0D - IN UINTN HartMaskBase=0D + IN UINTN *HartMask,=0D + IN UINTN HartMaskBase=0D )=0D {=0D - SbiRet Ret =3D SbiCall (=0D - SBI_EXT_IPI,=0D - SBI_EXT_IPI_SEND_IPI,=0D - 2,=0D - (UINTN)HartMask,=0D - HartMaskBase=0D - );=0D + SBI_RET Ret;=0D +=0D + Ret =3D SbiCall (=0D + SBI_EXT_IPI,=0D + SBI_EXT_IPI_SEND_IPI,=0D + 2,=0D + (UINTN)HartMask,=0D + HartMaskBase=0D + );=0D +=0D return TranslateError (Ret.Error);=0D }=0D =0D @@ -424,17 +455,20 @@ SbiSendIpi ( EFI_STATUS=0D EFIAPI=0D SbiRemoteFenceI (=0D - IN UINTN *HartMask,=0D - IN UINTN HartMaskBase=0D + IN UINTN *HartMask,=0D + IN UINTN HartMaskBase=0D )=0D {=0D - SbiRet Ret =3D SbiCall (=0D - SBI_EXT_RFENCE,=0D - SBI_EXT_RFENCE_REMOTE_FENCE_I,=0D - 2,=0D - (UINTN)HartMask,=0D - HartMaskBase=0D - );=0D + SBI_RET Ret;=0D +=0D + Ret =3D SbiCall (=0D + SBI_EXT_RFENCE,=0D + SBI_EXT_RFENCE_REMOTE_FENCE_I,=0D + 2,=0D + (UINTN)HartMask,=0D + HartMaskBase=0D + );=0D +=0D return TranslateError (Ret.Error);=0D }=0D =0D @@ -462,21 +496,24 @@ SbiRemoteFenceI ( EFI_STATUS=0D EFIAPI=0D SbiRemoteSfenceVma (=0D - IN UINTN *HartMask,=0D - IN UINTN HartMaskBase,=0D - IN UINTN StartAddr,=0D - IN UINTN Size=0D + IN UINTN *HartMask,=0D + IN UINTN HartMaskBase,=0D + IN UINTN StartAddr,=0D + IN UINTN Size=0D )=0D {=0D - SbiRet Ret =3D SbiCall (=0D - SBI_EXT_RFENCE,=0D - SBI_EXT_RFENCE_REMOTE_SFENCE_VMA,=0D - 4,=0D - (UINTN)HartMask,=0D - HartMaskBase,=0D - StartAddr,=0D - Size=0D - );=0D + SBI_RET Ret;=0D +=0D + Ret =3D SbiCall (=0D + SBI_EXT_RFENCE,=0D + SBI_EXT_RFENCE_REMOTE_SFENCE_VMA,=0D + 4,=0D + (UINTN)HartMask,=0D + HartMaskBase,=0D + StartAddr,=0D + Size=0D + );=0D +=0D return TranslateError (Ret.Error);=0D }=0D =0D @@ -505,23 +542,26 @@ SbiRemoteSfenceVma ( EFI_STATUS=0D EFIAPI=0D SbiRemoteSfenceVmaAsid (=0D - IN UINTN *HartMask,=0D - IN UINTN HartMaskBase,=0D - IN UINTN StartAddr,=0D - IN UINTN Size,=0D - IN UINTN Asid=0D + IN UINTN *HartMask,=0D + IN UINTN HartMaskBase,=0D + IN UINTN StartAddr,=0D + IN UINTN Size,=0D + IN UINTN Asid=0D )=0D {=0D - SbiRet Ret =3D SbiCall (=0D - SBI_EXT_RFENCE,=0D - SBI_EXT_RFENCE_REMOTE_SFENCE_VMA_ASID,=0D - 5,=0D - (UINTN)HartMask,=0D - HartMaskBase,=0D - StartAddr,=0D - Size,=0D - Asid=0D - );=0D + SBI_RET Ret;=0D +=0D + Ret =3D SbiCall (=0D + SBI_EXT_RFENCE,=0D + SBI_EXT_RFENCE_REMOTE_SFENCE_VMA_ASID,=0D + 5,=0D + (UINTN)HartMask,=0D + HartMaskBase,=0D + StartAddr,=0D + Size,=0D + Asid=0D + );=0D +=0D return TranslateError (Ret.Error);=0D }=0D =0D @@ -554,23 +594,26 @@ SbiRemoteSfenceVmaAsid ( EFI_STATUS=0D EFIAPI=0D SbiRemoteHFenceGvmaVmid (=0D - IN UINTN *HartMask,=0D - IN UINTN HartMaskBase,=0D - IN UINTN StartAddr,=0D - IN UINTN Size,=0D - IN UINTN Vmid=0D + IN UINTN *HartMask,=0D + IN UINTN HartMaskBase,=0D + IN UINTN StartAddr,=0D + IN UINTN Size,=0D + IN UINTN Vmid=0D )=0D {=0D - SbiRet Ret =3D SbiCall (=0D - SBI_EXT_RFENCE,=0D - SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA,=0D - 5,=0D - (UINTN)HartMask,=0D - HartMaskBase,=0D - StartAddr,=0D - Size,=0D - Vmid=0D - );=0D + SBI_RET Ret;=0D +=0D + Ret =3D SbiCall (=0D + SBI_EXT_RFENCE,=0D + SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA,=0D + 5,=0D + (UINTN)HartMask,=0D + HartMaskBase,=0D + StartAddr,=0D + Size,=0D + Vmid=0D + );=0D +=0D return TranslateError (Ret.Error);=0D }=0D =0D @@ -602,21 +645,24 @@ SbiRemoteHFenceGvmaVmid ( EFI_STATUS=0D EFIAPI=0D SbiRemoteHFenceGvma (=0D - IN UINTN *HartMask,=0D - IN UINTN HartMaskBase,=0D - IN UINTN StartAddr,=0D - IN UINTN Size=0D + IN UINTN *HartMask,=0D + IN UINTN HartMaskBase,=0D + IN UINTN StartAddr,=0D + IN UINTN Size=0D )=0D {=0D - SbiRet Ret =3D SbiCall (=0D - SBI_EXT_RFENCE,=0D - SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA_VMID,=0D - 4,=0D - (UINTN)HartMask,=0D - HartMaskBase,=0D - StartAddr,=0D - Size=0D - );=0D + SBI_RET Ret;=0D +=0D + Ret =3D SbiCall (=0D + SBI_EXT_RFENCE,=0D + SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA_VMID,=0D + 4,=0D + (UINTN)HartMask,=0D + HartMaskBase,=0D + StartAddr,=0D + Size=0D + );=0D +=0D return TranslateError (Ret.Error);=0D }=0D =0D @@ -649,23 +695,26 @@ SbiRemoteHFenceGvma ( EFI_STATUS=0D EFIAPI=0D SbiRemoteHFenceVvmaAsid (=0D - IN UINTN *HartMask,=0D - IN UINTN HartMaskBase,=0D - IN UINTN StartAddr,=0D - IN UINTN Size,=0D - IN UINTN Asid=0D + IN UINTN *HartMask,=0D + IN UINTN HartMaskBase,=0D + IN UINTN StartAddr,=0D + IN UINTN Size,=0D + IN UINTN Asid=0D )=0D {=0D - SbiRet Ret =3D SbiCall (=0D - SBI_EXT_RFENCE,=0D - SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA,=0D - 5,=0D - (UINTN)HartMask,=0D - HartMaskBase,=0D - StartAddr,=0D - Size,=0D - Asid=0D - );=0D + SBI_RET Ret;=0D +=0D + Ret =3D SbiCall (=0D + SBI_EXT_RFENCE,=0D + SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA,=0D + 5,=0D + (UINTN)HartMask,=0D + HartMaskBase,=0D + StartAddr,=0D + Size,=0D + Asid=0D + );=0D +=0D return TranslateError (Ret.Error);=0D }=0D =0D @@ -697,21 +746,24 @@ SbiRemoteHFenceVvmaAsid ( EFI_STATUS=0D EFIAPI=0D SbiRemoteHFenceVvma (=0D - IN UINTN *HartMask,=0D - IN UINTN HartMaskBase,=0D - IN UINTN StartAddr,=0D - IN UINTN Size=0D + IN UINTN *HartMask,=0D + IN UINTN HartMaskBase,=0D + IN UINTN StartAddr,=0D + IN UINTN Size=0D )=0D {=0D - SbiRet Ret =3D SbiCall (=0D - SBI_EXT_RFENCE,=0D - SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA_ASID,=0D - 4,=0D - (UINTN)HartMask,=0D - HartMaskBase,=0D - StartAddr,=0D - Size=0D - );=0D + SBI_RET Ret;=0D +=0D + Ret =3D SbiCall (=0D + SBI_EXT_RFENCE,=0D + SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA_ASID,=0D + 4,=0D + (UINTN)HartMask,=0D + HartMaskBase,=0D + StartAddr,=0D + Size=0D + );=0D +=0D return TranslateError (Ret.Error);=0D }=0D =0D @@ -743,17 +795,20 @@ SbiRemoteHFenceVvma ( EFI_STATUS=0D EFIAPI=0D SbiSystemReset (=0D - IN UINTN ResetType,=0D - IN UINTN ResetReason=0D + IN UINTN ResetType,=0D + IN UINTN ResetReason=0D )=0D {=0D - SbiRet Ret =3D SbiCall (=0D - SBI_EXT_SRST,=0D - SBI_EXT_SRST_RESET,=0D - 2,=0D - ResetType,=0D - ResetReason=0D - );=0D + SBI_RET Ret;=0D +=0D + Ret =3D SbiCall (=0D + SBI_EXT_SRST,=0D + SBI_EXT_SRST_RESET,=0D + 2,=0D + ResetType,=0D + ResetReason=0D + );=0D +=0D return TranslateError (Ret.Error);=0D }=0D =0D @@ -777,59 +832,91 @@ SbiSystemReset ( EFI_STATUS=0D EFIAPI=0D SbiVendorCall (=0D - IN UINTN ExtensionId,=0D - IN UINTN FunctionId,=0D - IN UINTN NumArgs,=0D + IN UINTN ExtensionId,=0D + IN UINTN FunctionId,=0D + IN UINTN NumArgs,=0D ...=0D )=0D {=0D - SbiRet Ret;=0D - VA_LIST Args;=0D - VA_START (Args, NumArgs);=0D -=0D - ASSERT (ExtensionId >=3D SBI_EXT_VENDOR_START && ExtensionId <=3D SBI_= EXT_VENDOR_END);=0D - ASSERT (NumArgs <=3D SBI_CALL_MAX_ARGS);=0D -=0D - switch (NumArgs) {=0D - case 0:=0D - Ret =3D SbiCall (ExtensionId, FunctionId, NumArgs);=0D - break;=0D - case 1:=0D - Ret =3D SbiCall (ExtensionId, FunctionId, NumArgs, VA_ARG (Args, U= INTN));=0D - break;=0D - case 2:=0D - Ret =3D SbiCall (ExtensionId, FunctionId, NumArgs, VA_ARG (Args, U= INTN),=0D - VA_ARG (Args, UINTN));=0D - break;=0D - case 3:=0D - Ret =3D SbiCall (ExtensionId, FunctionId, NumArgs, VA_ARG (Args, U= INTN),=0D - VA_ARG (Args, UINTN), VA_ARG (Args, UINTN));=0D - break;=0D - case 4:=0D - Ret =3D SbiCall (ExtensionId, FunctionId, NumArgs, VA_ARG (Args, U= INTN),=0D - VA_ARG (Args, UINTN), VA_ARG (Args, UINTN),=0D - VA_ARG (Args, UINTN));=0D - break;=0D - case 5:=0D - Ret =3D SbiCall (ExtensionId, FunctionId, NumArgs, VA_ARG (Args, U= INTN),=0D - VA_ARG (Args, UINTN), VA_ARG (Args, UINTN),=0D - VA_ARG (Args, UINTN), VA_ARG (Args, UINTN));=0D - break;=0D - case 6:=0D - Ret =3D SbiCall (ExtensionId, FunctionId, NumArgs, VA_ARG (Args, U= INTN),=0D - VA_ARG (Args, UINTN), VA_ARG (Args, UINTN),=0D - VA_ARG (Args, UINTN), VA_ARG (Args, UINTN),=0D - VA_ARG (Args, UINTN));=0D - break;=0D - default:=0D - // Too many args. In theory SBI can handle more arguments when the= y are=0D - // passed on the stack but no SBI extension uses this, therefore i= t's=0D - // not yet implemented here.=0D - return EFI_INVALID_PARAMETER;=0D - }=0D -=0D - VA_END(Args);=0D - return TranslateError (Ret.Error);=0D + SBI_RET Ret;=0D + VA_LIST Args;=0D +=0D + VA_START (Args, NumArgs);=0D +=0D + ASSERT (ExtensionId >=3D SBI_EXT_VENDOR_START && ExtensionId <=3D SBI_EX= T_VENDOR_END);=0D + ASSERT (NumArgs <=3D SBI_CALL_MAX_ARGS);=0D +=0D + switch (NumArgs) {=0D + case 0:=0D + Ret =3D SbiCall (ExtensionId, FunctionId, NumArgs);=0D + break;=0D + case 1:=0D + Ret =3D SbiCall (ExtensionId, FunctionId, NumArgs, VA_ARG (Args, UIN= TN));=0D + break;=0D + case 2:=0D + Ret =3D SbiCall (=0D + ExtensionId,=0D + FunctionId,=0D + NumArgs,=0D + VA_ARG (Args, UINTN),=0D + VA_ARG (Args, UINTN)=0D + );=0D + break;=0D + case 3:=0D + Ret =3D SbiCall (=0D + ExtensionId,=0D + FunctionId,=0D + NumArgs,=0D + VA_ARG (Args, UINTN),=0D + VA_ARG (Args, UINTN),=0D + VA_ARG (Args, UINTN)=0D + );=0D + break;=0D + case 4:=0D + Ret =3D SbiCall (=0D + ExtensionId,=0D + FunctionId,=0D + NumArgs,=0D + VA_ARG (Args, UINTN),=0D + VA_ARG (Args, UINTN),=0D + VA_ARG (Args, UINTN),=0D + VA_ARG (Args, UINTN)=0D + );=0D + break;=0D + case 5:=0D + Ret =3D SbiCall (=0D + ExtensionId,=0D + FunctionId,=0D + NumArgs,=0D + VA_ARG (Args, UINTN),=0D + VA_ARG (Args, UINTN),=0D + VA_ARG (Args, UINTN),=0D + VA_ARG (Args, UINTN),=0D + VA_ARG (Args, UINTN)=0D + );=0D + break;=0D + case 6:=0D + Ret =3D SbiCall (=0D + ExtensionId,=0D + FunctionId,=0D + NumArgs,=0D + VA_ARG (Args, UINTN),=0D + VA_ARG (Args, UINTN),=0D + VA_ARG (Args, UINTN),=0D + VA_ARG (Args, UINTN),=0D + VA_ARG (Args, UINTN),=0D + VA_ARG (Args, UINTN)=0D + );=0D + break;=0D + default:=0D + // Too many args. In theory SBI can handle more arguments when they = are=0D + // passed on the stack but no SBI extension uses this, therefore it'= s=0D + // not yet implemented here.=0D + return EFI_INVALID_PARAMETER;=0D + }=0D +=0D + VA_END (Args);=0D + return TranslateError (Ret.Error);=0D }=0D =0D //=0D @@ -847,10 +934,12 @@ SbiVendorCall ( VOID=0D EFIAPI=0D SbiGetMscratch (=0D - OUT SBI_SCRATCH **ScratchSpace=0D + OUT SBI_SCRATCH **ScratchSpace=0D )=0D {=0D - SbiRet Ret =3D SbiCall (SBI_EDK2_FW_EXT, SBI_EXT_FW_MSCRATCH_FUNC, 0);=0D + SBI_RET Ret;=0D +=0D + Ret =3D SbiCall (SBI_EDK2_FW_EXT, SBI_EXT_FW_MSCRATCH_FUNC, 0);=0D =0D // Our ecall handler never returns an error, only when the func id is in= valid=0D ASSERT (Ret.Error =3D=3D SBI_OK);=0D @@ -867,16 +956,18 @@ SbiGetMscratch ( VOID=0D EFIAPI=0D SbiGetMscratchHartid (=0D - IN UINTN HartId,=0D - OUT SBI_SCRATCH **ScratchSpace=0D + IN UINTN HartId,=0D + OUT SBI_SCRATCH **ScratchSpace=0D )=0D {=0D - SbiRet Ret =3D SbiCall (=0D - SBI_EDK2_FW_EXT,=0D - SBI_EXT_FW_MSCRATCH_HARTID_FUNC,=0D - 1,=0D - HartId=0D - );=0D + SBI_RET Ret;=0D +=0D + Ret =3D SbiCall (=0D + SBI_EDK2_FW_EXT,=0D + SBI_EXT_FW_MSCRATCH_HARTID_FUNC,=0D + 1,=0D + HartId=0D + );=0D =0D // Our ecall handler never returns an error, only when the func id is in= valid=0D ASSERT (Ret.Error =3D=3D SBI_OK);=0D @@ -893,14 +984,14 @@ SbiGetMscratchHartid ( VOID=0D EFIAPI=0D SbiGetFirmwareContext (=0D - OUT EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT **FirmwareContext=0D + OUT EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT **FirmwareContext=0D )=0D {=0D - SBI_SCRATCH *ScratchSpace;=0D - SBI_PLATFORM *SbiPlatform;=0D + SBI_SCRATCH *ScratchSpace;=0D + SBI_PLATFORM *SbiPlatform;=0D =0D - SbiGetMscratch(&ScratchSpace);=0D - SbiPlatform =3D (SBI_PLATFORM *)sbi_platform_ptr(ScratchSpace);=0D + SbiGetMscratch (&ScratchSpace);=0D + SbiPlatform =3D (SBI_PLATFORM *)sbi_platform_ptr (ScratchSpace);=0D *FirmwareContext =3D (EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *)SbiPlatform->= firmware_context;=0D }=0D =0D @@ -912,14 +1003,14 @@ SbiGetFirmwareContext ( VOID=0D EFIAPI=0D SbiSetFirmwareContext (=0D - IN EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *FirmwareContext=0D + IN EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *FirmwareContext=0D )=0D {=0D - SBI_SCRATCH *ScratchSpace;=0D - SBI_PLATFORM *SbiPlatform;=0D + SBI_SCRATCH *ScratchSpace;=0D + SBI_PLATFORM *SbiPlatform;=0D =0D - SbiGetMscratch(&ScratchSpace);=0D + SbiGetMscratch (&ScratchSpace);=0D =0D - SbiPlatform =3D (SBI_PLATFORM *)sbi_platform_ptr (ScratchSpace);=0D + SbiPlatform =3D (SBI_PLATFORM *)sbi_platform_ptr (Scra= tchSpace);=0D SbiPlatform->firmware_context =3D (UINTN)FirmwareContext;=0D }=0D diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVExceptionLib/CpuExcep= tionHandlerLib.c b/Silicon/RISC-V/ProcessorPkg/Library/RiscVExceptionLib/Cp= uExceptionHandlerLib.c index a9316ae758..93fbde619f 100644 --- a/Silicon/RISC-V/ProcessorPkg/Library/RiscVExceptionLib/CpuExceptionHan= dlerLib.c +++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVExceptionLib/CpuExceptionHan= dlerLib.c @@ -1,7 +1,7 @@ /** @file=0D - RISC-V Exception Handler library implementition.=0D + RISC-V Exception Handler library implementation.=0D =0D - Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. Al= l rights reserved.
=0D + Copyright (c) 2016 - 2022, Hewlett Packard Enterprise Development LP. Al= l rights reserved.
=0D =0D SPDX-License-Identifier: BSD-2-Clause-Patent=0D =0D @@ -17,7 +17,7 @@ =0D #include "CpuExceptionHandlerLib.h"=0D =0D -STATIC EFI_CPU_INTERRUPT_HANDLER mInterruptHandlers[2];=0D +STATIC EFI_CPU_INTERRUPT_HANDLER mInterruptHandlers[2];=0D =0D /**=0D Initializes all CPU exceptions entries and provides the default exceptio= n handlers.=0D @@ -38,7 +38,7 @@ STATIC EFI_CPU_INTERRUPT_HANDLER mInterruptHandlers[2]; EFI_STATUS=0D EFIAPI=0D InitializeCpuExceptionHandlers (=0D - IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL=0D + IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL=0D )=0D {=0D return EFI_SUCCESS;=0D @@ -63,7 +63,7 @@ InitializeCpuExceptionHandlers ( EFI_STATUS=0D EFIAPI=0D InitializeCpuInterruptHandlers (=0D - IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL=0D + IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL=0D )=0D {=0D return EFI_SUCCESS;=0D @@ -95,15 +95,15 @@ InitializeCpuInterruptHandlers ( EFI_STATUS=0D EFIAPI=0D RegisterCpuInterruptHandler (=0D - IN EFI_EXCEPTION_TYPE InterruptType,=0D - IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler=0D + IN EFI_EXCEPTION_TYPE InterruptType,=0D + IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler=0D )=0D {=0D -=0D DEBUG ((DEBUG_INFO, "%a: Type:%x Handler: %x\n", __FUNCTION__, Interrupt= Type, InterruptHandler));=0D mInterruptHandlers[InterruptType] =3D InterruptHandler;=0D return EFI_SUCCESS;=0D }=0D +=0D /**=0D Machine mode trap handler.=0D =0D @@ -112,23 +112,23 @@ RegisterCpuInterruptHandler ( **/=0D VOID=0D RiscVSupervisorModeTrapHandler (=0D - SMODE_TRAP_REGISTERS *SmodeTrapReg=0D + SMODE_TRAP_REGISTERS *SmodeTrapReg=0D )=0D {=0D - UINTN SCause;=0D - EFI_SYSTEM_CONTEXT RiscVSystemContext;=0D + UINTN SCause;=0D + EFI_SYSTEM_CONTEXT RiscVSystemContext;=0D =0D RiscVSystemContext.SystemContextRiscV64 =3D (EFI_SYSTEM_CONTEXT_RISCV64 = *)SmodeTrapReg;=0D //=0D // Check scasue register.=0D //=0D - SCause =3D (UINTN)csr_read(RISCV_CSR_SUPERVISOR_SCAUSE);=0D + SCause =3D (UINTN)csr_read (RISCV_CSR_SUPERVISOR_SCAUSE);=0D if ((SCause & (1UL << (sizeof (UINTN) * 8- 1))) !=3D 0) {=0D //=0D // This is interrupt event.=0D //=0D SCause &=3D ~(1UL << (sizeof (UINTN) * 8- 1));=0D - if((SCause =3D=3D SCAUSE_SUPERVISOR_TIMER_INT) && (mInterruptHandlers[= EXCEPT_RISCV_TIMER_INT] !=3D NULL)) {=0D + if ((SCause =3D=3D SCAUSE_SUPERVISOR_TIMER_INT) && (mInterruptHandlers= [EXCEPT_RISCV_TIMER_INT] !=3D NULL)) {=0D mInterruptHandlers[EXCEPT_RISCV_TIMER_INT](EXCEPT_RISCV_TIMER_INT, R= iscVSystemContext);=0D }=0D }=0D @@ -160,8 +160,8 @@ RiscVSupervisorModeTrapHandler ( EFI_STATUS=0D EFIAPI=0D InitializeCpuExceptionHandlersEx (=0D - IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL,=0D - IN CPU_EXCEPTION_INIT_DATA *InitData OPTIONAL=0D + IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL,=0D + IN CPU_EXCEPTION_INIT_DATA *InitData OPTIONAL=0D )=0D {=0D return InitializeCpuExceptionHandlers (VectorInfo);=0D @@ -186,9 +186,9 @@ CpuExceptionHandlerLibConstructor ( )=0D {=0D //=0D - // Set Superviosr mode trap handler.=0D + // Set Supervisor mode trap handler.=0D //=0D - csr_write(CSR_STVEC, SupervisorModeTrap);=0D + csr_write (CSR_STVEC, SupervisorModeTrap);=0D =0D return EFI_SUCCESS;=0D }=0D diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSscrat= chLib/RiscVFirmwareContextSscratchLib.c b/Silicon/RISC-V/ProcessorPkg/Libra= ry/RiscVFirmwareContextSscratchLib/RiscVFirmwareContextSscratchLib.c index 2504e17132..1b1db65f60 100644 --- a/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSscratchLib/R= iscVFirmwareContextSscratchLib.c +++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSscratchLib/R= iscVFirmwareContextSscratchLib.c @@ -2,7 +2,7 @@ This instance uses Supervisor mode SCRATCH CSR to get/set the=0D pointer of firmware context.=0D =0D - Copyright (c) 2021 Hewlett Packard Enterprise Development LP. All rights= reserved.
=0D + Copyright (c) 2021-2022 Hewlett Packard Enterprise Development LP. All r= ights reserved.
=0D =0D SPDX-License-Identifier: BSD-2-Clause-Patent=0D **/=0D @@ -25,7 +25,7 @@ VOID=0D EFIAPI=0D GetFirmwareContextPointer (=0D - IN OUT EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT **FirmwareContextPtr=0D + IN OUT EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT **FirmwareContextPtr=0D )=0D {=0D *FirmwareContextPtr =3D (EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *)RiscVGetSu= pervisorScratch ();=0D @@ -41,7 +41,7 @@ GetFirmwareContextPointer ( VOID=0D EFIAPI=0D SetFirmwareContextPointer (=0D - IN EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *FirmwareContextPtr=0D + IN EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *FirmwareContextPtr=0D )=0D {=0D RiscVSetSupervisorScratch ((UINT64)FirmwareContextPtr);=0D diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextStvecL= ib/RiscVFirmwareContextStvecLib.c b/Silicon/RISC-V/ProcessorPkg/Library/Ris= cVFirmwareContextStvecLib/RiscVFirmwareContextStvecLib.c index cc5a7e2ccc..7198944af6 100644 --- a/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextStvecLib/Risc= VFirmwareContextStvecLib.c +++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextStvecLib/Risc= VFirmwareContextStvecLib.c @@ -25,7 +25,7 @@ VOID=0D EFIAPI=0D GetFirmwareContextPointer (=0D - IN OUT EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT **FirmwareContextPtr=0D + IN OUT EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT **FirmwareContextPtr=0D )=0D {=0D *FirmwareContextPtr =3D (EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *)RiscVGetSu= pervisorStvec ();=0D @@ -41,7 +41,7 @@ GetFirmwareContextPointer ( VOID=0D EFIAPI=0D SetFirmwareContextPointer (=0D - IN EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *FirmwareContextPtr=0D + IN EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *FirmwareContextPtr=0D )=0D {=0D RiscVSetSupervisorStvec ((UINT64)FirmwareContextPtr);=0D diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVTimerLib/RiscVTimerLi= b.c b/Silicon/RISC-V/ProcessorPkg/Library/RiscVTimerLib/RiscVTimerLib.c index 54ca99787e..85cd93c5e6 100644 --- a/Silicon/RISC-V/ProcessorPkg/Library/RiscVTimerLib/RiscVTimerLib.c +++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVTimerLib/RiscVTimerLib.c @@ -1,7 +1,7 @@ /** @file=0D RISC-V instance of Timer Library.=0D =0D - Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. Al= l rights reserved.
=0D + Copyright (c) 2016 - 2022, Hewlett Packard Enterprise Development LP. Al= l rights reserved.
=0D =0D SPDX-License-Identifier: BSD-2-Clause-Patent=0D =0D @@ -24,21 +24,21 @@ **/=0D VOID=0D InternalRiscVTimerDelay (=0D - IN UINT32 Delay=0D + IN UINT32 Delay=0D )=0D {=0D - UINT32 Ticks;=0D - UINT32 Times;=0D + UINT32 Ticks;=0D + UINT32 Times;=0D =0D - Times =3D Delay >> (RISCV_TIMER_COMPARE_BITS - 2);=0D - Delay &=3D (( 1 << (RISCV_TIMER_COMPARE_BITS - 2)) - 1);=0D + Times =3D Delay >> (RISCV_TIMER_COMPARE_BITS - 2);=0D + Delay &=3D ((1 << (RISCV_TIMER_COMPARE_BITS - 2)) - 1);=0D do {=0D //=0D // The target timer count is calculated here=0D //=0D Ticks =3D RiscVReadMachineTimerInterface () + Delay;=0D Delay =3D 1 << (RISCV_TIMER_COMPARE_BITS - 2);=0D - while (((Ticks - RiscVReadMachineTimerInterface ()) & ( 1 << (RISCV_TI= MER_COMPARE_BITS - 1))) =3D=3D 0) {=0D + while (((Ticks - RiscVReadMachineTimerInterface ()) & (1 << (RISCV_TIM= ER_COMPARE_BITS - 1))) =3D=3D 0) {=0D CpuPause ();=0D }=0D } while (Times-- > 0);=0D @@ -57,7 +57,7 @@ InternalRiscVTimerDelay ( UINTN=0D EFIAPI=0D MicroSecondDelay (=0D - IN UINTN MicroSeconds=0D + IN UINTN MicroSeconds=0D )=0D {=0D InternalRiscVTimerDelay (=0D @@ -85,7 +85,7 @@ MicroSecondDelay ( UINTN=0D EFIAPI=0D NanoSecondDelay (=0D - IN UINTN NanoSeconds=0D + IN UINTN NanoSeconds=0D )=0D {=0D InternalRiscVTimerDelay (=0D @@ -147,7 +147,7 @@ GetPerformanceCounter ( UINT64=0D EFIAPI=0D GetPerformanceCounterProperties (=0D - OUT UINT64 *StartValue, OPTIONAL=0D + OUT UINT64 *StartValue, OPTIONAL=0D OUT UINT64 *EndValue OPTIONAL=0D )=0D {=0D @@ -176,7 +176,7 @@ GetPerformanceCounterProperties ( UINT64=0D EFIAPI=0D GetTimeInNanoSecond (=0D - IN UINT64 Ticks=0D + IN UINT64 Ticks=0D )=0D {=0D UINT64 NanoSeconds;=0D @@ -193,7 +193,7 @@ GetTimeInNanoSecond ( // Frequency < 0x100000000, so Remainder < 0x100000000, then (Remainder = * 1,000,000,000)=0D // will not overflow 64-bit.=0D //=0D - NanoSeconds +=3D DivU64x32 (MultU64x32 ((UINT64) Remainder, 1000000000u)= , PcdGet64 (PcdRiscVMachineTimerFrequencyInHerz));=0D + NanoSeconds +=3D DivU64x32 (MultU64x32 ((UINT64)Remainder, 1000000000u),= PcdGet64 (PcdRiscVMachineTimerFrequencyInHerz));=0D =0D return NanoSeconds;=0D }=0D diff --git a/Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxe.c b/Silico= n/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxe.c index 3104c6d2de..8d4d406edf 100644 --- a/Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxe.c +++ b/Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxe.c @@ -1,7 +1,7 @@ /** @file=0D RISC-V CPU DXE driver.=0D =0D - Copyright (c) 2016 - 2021, Hewlett Packard Enterprise Development LP. Al= l rights reserved.
=0D + Copyright (c) 2016 - 2022, Hewlett Packard Enterprise Development LP. Al= l rights reserved.
=0D =0D SPDX-License-Identifier: BSD-2-Clause-Patent=0D =0D @@ -12,8 +12,8 @@ //=0D // Global Variables=0D //=0D -STATIC BOOLEAN mInterruptState =3D FALSE;=0D -STATIC EFI_HANDLE mCpuHandle =3D NULL;=0D +STATIC BOOLEAN mInterruptState =3D FALSE;=0D +STATIC EFI_HANDLE mCpuHandle =3D NULL;=0D =0D EFI_CPU_ARCH_PROTOCOL gCpu =3D {=0D CpuFlushCpuDataCache,=0D @@ -50,16 +50,15 @@ EFI_CPU_ARCH_PROTOCOL gCpu =3D { EFI_STATUS=0D EFIAPI=0D CpuFlushCpuDataCache (=0D - IN EFI_CPU_ARCH_PROTOCOL *This,=0D - IN EFI_PHYSICAL_ADDRESS Start,=0D - IN UINT64 Length,=0D - IN EFI_CPU_FLUSH_TYPE FlushType=0D + IN EFI_CPU_ARCH_PROTOCOL *This,=0D + IN EFI_PHYSICAL_ADDRESS Start,=0D + IN UINT64 Length,=0D + IN EFI_CPU_FLUSH_TYPE FlushType=0D )=0D {=0D return EFI_SUCCESS;=0D }=0D =0D -=0D /**=0D Enables CPU interrupts.=0D =0D @@ -72,7 +71,7 @@ CpuFlushCpuDataCache ( EFI_STATUS=0D EFIAPI=0D CpuEnableInterrupt (=0D - IN EFI_CPU_ARCH_PROTOCOL *This=0D + IN EFI_CPU_ARCH_PROTOCOL *This=0D )=0D {=0D EnableInterrupts ();=0D @@ -80,7 +79,6 @@ CpuEnableInterrupt ( return EFI_SUCCESS;=0D }=0D =0D -=0D /**=0D Disables CPU interrupts.=0D =0D @@ -93,7 +91,7 @@ CpuEnableInterrupt ( EFI_STATUS=0D EFIAPI=0D CpuDisableInterrupt (=0D - IN EFI_CPU_ARCH_PROTOCOL *This=0D + IN EFI_CPU_ARCH_PROTOCOL *This=0D )=0D {=0D DisableInterrupts ();=0D @@ -101,7 +99,6 @@ CpuDisableInterrupt ( return EFI_SUCCESS;=0D }=0D =0D -=0D /**=0D Return the state of interrupts.=0D =0D @@ -115,8 +112,8 @@ CpuDisableInterrupt ( EFI_STATUS=0D EFIAPI=0D CpuGetInterruptState (=0D - IN EFI_CPU_ARCH_PROTOCOL *This,=0D - OUT BOOLEAN *State=0D + IN EFI_CPU_ARCH_PROTOCOL *This,=0D + OUT BOOLEAN *State=0D )=0D {=0D if (State =3D=3D NULL) {=0D @@ -127,7 +124,6 @@ CpuGetInterruptState ( return EFI_SUCCESS;=0D }=0D =0D -=0D /**=0D Generates an INIT to the CPU.=0D =0D @@ -143,14 +139,13 @@ CpuGetInterruptState ( EFI_STATUS=0D EFIAPI=0D CpuInit (=0D - IN EFI_CPU_ARCH_PROTOCOL *This,=0D - IN EFI_CPU_INIT_TYPE InitType=0D + IN EFI_CPU_ARCH_PROTOCOL *This,=0D + IN EFI_CPU_INIT_TYPE InitType=0D )=0D {=0D return EFI_UNSUPPORTED;=0D }=0D =0D -=0D /**=0D Registers a function to be called from the CPU interrupt handler.=0D =0D @@ -174,15 +169,14 @@ CpuInit ( EFI_STATUS=0D EFIAPI=0D CpuRegisterInterruptHandler (=0D - IN EFI_CPU_ARCH_PROTOCOL *This,=0D - IN EFI_EXCEPTION_TYPE InterruptType,=0D - IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler=0D + IN EFI_CPU_ARCH_PROTOCOL *This,=0D + IN EFI_EXCEPTION_TYPE InterruptType,=0D + IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler=0D )=0D {=0D return RegisterCpuInterruptHandler (InterruptType, InterruptHandler);=0D }=0D =0D -=0D /**=0D Returns a timer value from one of the CPU's internal timers. There is no= =0D inherent time interval between ticks but is a function of the CPU freque= ncy.=0D @@ -209,10 +203,10 @@ CpuRegisterInterruptHandler ( EFI_STATUS=0D EFIAPI=0D CpuGetTimerValue (=0D - IN EFI_CPU_ARCH_PROTOCOL *This,=0D - IN UINT32 TimerIndex,=0D - OUT UINT64 *TimerValue,=0D - OUT UINT64 *TimerPeriod OPTIONAL=0D + IN EFI_CPU_ARCH_PROTOCOL *This,=0D + IN UINT32 TimerIndex,=0D + OUT UINT64 *TimerValue,=0D + OUT UINT64 *TimerPeriod OPTIONAL=0D )=0D {=0D if (TimerValue =3D=3D NULL) {=0D @@ -225,15 +219,15 @@ CpuGetTimerValue ( =0D *TimerValue =3D (UINT64)RiscVReadMachineTimerInterface ();=0D if (TimerPeriod !=3D NULL) {=0D - *TimerPeriod =3D DivU64x32 (=0D - 1000000000000000u,=0D - PcdGet64 (PcdRiscVMachineTimerFrequencyInHerz)=0D - );=0D + *TimerPeriod =3D DivU64x32 (=0D + 1000000000000000u,=0D + PcdGet64 (PcdRiscVMachineTimerFrequencyInHerz)=0D + );=0D }=0D +=0D return EFI_SUCCESS;=0D }=0D =0D -=0D /**=0D Implementation of SetMemoryAttributes() service of CPU Architecture Prot= ocol.=0D =0D @@ -262,10 +256,10 @@ CpuGetTimerValue ( EFI_STATUS=0D EFIAPI=0D CpuSetMemoryAttributes (=0D - IN EFI_CPU_ARCH_PROTOCOL *This,=0D - IN EFI_PHYSICAL_ADDRESS BaseAddress,=0D - IN UINT64 Length,=0D - IN UINT64 Attributes=0D + IN EFI_CPU_ARCH_PROTOCOL *This,=0D + IN EFI_PHYSICAL_ADDRESS BaseAddress,=0D + IN UINT64 Length,=0D + IN UINT64 Attributes=0D )=0D {=0D DEBUG ((DEBUG_INFO, "%a: Set memory attributes not supported yet\n", __F= UNCTION__));=0D @@ -286,8 +280,8 @@ CpuSetMemoryAttributes ( EFI_STATUS=0D EFIAPI=0D InitializeCpu (=0D - IN EFI_HANDLE ImageHandle,=0D - IN EFI_SYSTEM_TABLE *SystemTable=0D + IN EFI_HANDLE ImageHandle,=0D + IN EFI_SYSTEM_TABLE *SystemTable=0D )=0D {=0D EFI_STATUS Status;=0D @@ -307,10 +301,10 @@ InitializeCpu ( //=0D Status =3D gBS->InstallMultipleProtocolInterfaces (=0D &mCpuHandle,=0D - &gEfiCpuArchProtocolGuid, &gCpu,=0D + &gEfiCpuArchProtocolGuid,=0D + &gCpu,=0D NULL=0D );=0D ASSERT_EFI_ERROR (Status);=0D return Status;=0D }=0D -=0D diff --git a/Silicon/RISC-V/ProcessorPkg/Universal/FdtDxe/FdtDxe.c b/Silico= n/RISC-V/ProcessorPkg/Universal/FdtDxe/FdtDxe.c index 22b12027d3..1e76249237 100644 --- a/Silicon/RISC-V/ProcessorPkg/Universal/FdtDxe/FdtDxe.c +++ b/Silicon/RISC-V/ProcessorPkg/Universal/FdtDxe/FdtDxe.c @@ -6,7 +6,7 @@ it runs in S-Mode, it cannot get this information from mhartid. Instead = we=0D insert the id into the device tree, that the EFIFSTUB can read from the = config table.=0D =0D - Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All right= s reserved.
=0D + Copyright (c) 2021-2022, Hewlett Packard Enterprise Development LP. All = rights reserved.
=0D =0D SPDX-License-Identifier: BSD-2-Clause-Patent=0D **/=0D @@ -21,7 +21,8 @@ /**=0D Fix up the device tree with booting hartid for the kernel=0D =0D - @param DtbBlob The device tree. Is extended to fit the hart id.=0D + @param DtbBlob The device tree. Is extended to fit the hart id.=0D + @param BootingHartId The boot hart ID.=0D =0D @retval EFI_SUCCESS The device tree was success fixed up with = the hart id.=0D @retval EFI_OUT_OF_RESOURCES There is not enough memory available to co= mplete the operation.=0D @@ -29,25 +30,32 @@ EFI_STATUS=0D EFIAPI=0D FixDtb (=0D - IN OUT VOID *DtbBlob,=0D + IN OUT VOID *DtbBlob,=0D IN UINTN BootingHartId=0D )=0D {=0D - fdt32_t Size;=0D - UINT32 ChosenOffset, Err;=0D + fdt32_t Size;=0D + UINT32 ChosenOffset, Err;=0D =0D - DEBUG ((DEBUG_INFO, "Fixing up device tree with boot hart id: %d\n",=0D - BootingHartId));=0D + DEBUG ((=0D + DEBUG_INFO,=0D + "Fixing up device tree with boot hart id: %d\n",=0D + BootingHartId=0D + ));=0D =0D - Size =3D fdt_totalsize(DtbBlob);=0D - Err =3D fdt_open_into(DtbBlob, DtbBlob, Size + 32);=0D + Size =3D fdt_totalsize (DtbBlob);=0D + Err =3D fdt_open_into (DtbBlob, DtbBlob, Size + 32);=0D if (Err < 0) {=0D - DEBUG ((DEBUG_ERROR,=0D - "Device Tree can't be expanded to accommodate new node\n", __FUNCTIO= N__));=0D + DEBUG ((=0D + DEBUG_ERROR,=0D + "Device Tree can't be expanded to accommodate new node\n",=0D + __FUNCTION__=0D + ));=0D return EFI_OUT_OF_RESOURCES;=0D }=0D - ChosenOffset =3D fdt_path_offset(DtbBlob, "/chosen");=0D - fdt_setprop_u32(DtbBlob, ChosenOffset, "boot-hartid", BootingHartId);=0D +=0D + ChosenOffset =3D fdt_path_offset (DtbBlob, "/chosen");=0D + fdt_setprop_u32 (DtbBlob, ChosenOffset, "boot-hartid", BootingHartId);=0D =0D return EFI_SUCCESS;=0D }=0D @@ -61,32 +69,42 @@ FixDtb ( **/=0D EFI_STATUS=0D EFIAPI=0D -InstallFdtFromHob (VOID)=0D +InstallFdtFromHob (=0D + VOID=0D + )=0D {=0D EFI_STATUS Status;=0D - EFI_HOB_GUID_TYPE *GuidHob;=0D - VOID *DataInHob;=0D + EFI_HOB_GUID_TYPE *GuidHob;=0D + VOID *DataInHob;=0D UINTN DataSize;=0D =0D GuidHob =3D GetFirstGuidHob (&gFdtHobGuid);=0D if (GuidHob =3D=3D NULL) {=0D - DEBUG ((DEBUG_ERROR, "Failed to find RISC-V DTB Hob\n",=0D - __FUNCTION__));=0D + DEBUG ((=0D + DEBUG_ERROR,=0D + "Failed to find RISC-V DTB Hob\n",=0D + __FUNCTION__=0D + ));=0D return EFI_NOT_FOUND;=0D }=0D - DataInHob =3D (VOID *) *((UINTN *) GET_GUID_HOB_DATA (GuidHob));=0D +=0D + DataInHob =3D (VOID *)*((UINTN *)GET_GUID_HOB_DATA (GuidHob));=0D DataSize =3D GET_GUID_HOB_DATA_SIZE (GuidHob);=0D =0D - Status =3D FixDtb (DataInHob, PcdGet32(PcdBootHartId));=0D + Status =3D FixDtb (DataInHob, PcdGet32 (PcdBootHartId));=0D if (EFI_ERROR (Status)) {=0D return Status;=0D }=0D =0D Status =3D gBS->InstallConfigurationTable (&gFdtTableGuid, DataInHob);=0D if (EFI_ERROR (Status)) {=0D - DEBUG ((DEBUG_ERROR, "%a: failed to install FDT configuration table\n"= ,=0D - __FUNCTION__));=0D + DEBUG ((=0D + DEBUG_ERROR,=0D + "%a: failed to install FDT configuration table\n",=0D + __FUNCTION__=0D + ));=0D }=0D +=0D return Status;=0D }=0D =0D @@ -104,8 +122,8 @@ InstallFdtFromHob (VOID) EFI_STATUS=0D EFIAPI=0D InstallFdt (=0D - IN EFI_HANDLE ImageHandle,=0D - IN EFI_SYSTEM_TABLE *SystemTable=0D + IN EFI_HANDLE ImageHandle,=0D + IN EFI_SYSTEM_TABLE *SystemTable=0D )=0D {=0D EFI_STATUS Status;=0D diff --git a/Silicon/RISC-V/ProcessorPkg/Universal/PciCpuIo2Dxe/PciCpuIo2Dx= e.c b/Silicon/RISC-V/ProcessorPkg/Universal/PciCpuIo2Dxe/PciCpuIo2Dxe.c index 03e3070682..c0a79ef321 100644 --- a/Silicon/RISC-V/ProcessorPkg/Universal/PciCpuIo2Dxe/PciCpuIo2Dxe.c +++ b/Silicon/RISC-V/ProcessorPkg/Universal/PciCpuIo2Dxe/PciCpuIo2Dxe.c @@ -3,7 +3,7 @@ =0D Copyright (c) 2009 - 2012, Intel Corporation. All rights reserved.
=0D Copyright (c) 2016, Linaro Ltd. All rights reserved.
=0D -(C) Copyright 2021 Hewlett Packard Enterprise Development LP
=0D +(C) Copyright 2021-2022 Hewlett Packard Enterprise Development LP
=0D =0D SPDX-License-Identifier: BSD-2-Clause-Patent=0D =0D @@ -19,7 +19,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include =0D #include =0D =0D -#define MAX_IO_PORT_ADDRESS 0xFFFF=0D +#define MAX_IO_PORT_ADDRESS 0xFFFF=0D =0D //=0D // Handle for the CPU I/O 2 Protocol=0D @@ -29,7 +29,7 @@ STATIC EFI_HANDLE mHandle =3D NULL; //=0D // Lookup table for increment values based on transfer widths=0D //=0D -STATIC CONST UINT8 mInStride[] =3D {=0D +STATIC CONST UINT8 mInStride[] =3D {=0D 1, // EfiCpuIoWidthUint8=0D 2, // EfiCpuIoWidthUint16=0D 4, // EfiCpuIoWidthUint32=0D @@ -47,7 +47,7 @@ STATIC CONST UINT8 mInStride[] =3D { //=0D // Lookup table for increment values based on transfer widths=0D //=0D -STATIC CONST UINT8 mOutStride[] =3D {=0D +STATIC CONST UINT8 mOutStride[] =3D {=0D 1, // EfiCpuIoWidthUint8=0D 2, // EfiCpuIoWidthUint16=0D 4, // EfiCpuIoWidthUint32=0D @@ -118,14 +118,14 @@ CpuIoCheckParameter ( // For FIFO type, the target address won't increase during the access,=0D // so treat Count as 1=0D //=0D - if (Width >=3D EfiCpuIoWidthFifoUint8 && Width <=3D EfiCpuIoWidthFifoUin= t64) {=0D + if ((Width >=3D EfiCpuIoWidthFifoUint8) && (Width <=3D EfiCpuIoWidthFifo= Uint64)) {=0D Count =3D 1;=0D }=0D =0D //=0D // Check to see if Width is in the valid range for I/O Port operations=0D //=0D - Width =3D (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03);=0D + Width =3D (EFI_CPU_IO_PROTOCOL_WIDTH)(Width & 0x03);=0D if (!MmioOperation && (Width =3D=3D EfiCpuIoWidthUint64)) {=0D return EFI_INVALID_PARAMETER;=0D }=0D @@ -162,6 +162,7 @@ CpuIoCheckParameter ( if (MaxCount < (Count - 1)) {=0D return EFI_UNSUPPORTED;=0D }=0D +=0D if (Address > LShiftU64 (MaxCount - Count + 1, Width)) {=0D return EFI_UNSUPPORTED;=0D }=0D @@ -241,9 +242,9 @@ CpuMemoryServiceRead ( //=0D // Select loop based on the width of the transfer=0D //=0D - InStride =3D mInStride[Width];=0D - OutStride =3D mOutStride[Width];=0D - OperationWidth =3D (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03);=0D + InStride =3D mInStride[Width];=0D + OutStride =3D mOutStride[Width];=0D + OperationWidth =3D (EFI_CPU_IO_PROTOCOL_WIDTH)(Width & 0x03);=0D for (Uint8Buffer =3D Buffer; Count > 0; Address +=3D InStride, Uint8Buff= er +=3D OutStride, Count--) {=0D if (OperationWidth =3D=3D EfiCpuIoWidthUint8) {=0D *Uint8Buffer =3D MmioRead8 ((UINTN)Address);=0D @@ -255,6 +256,7 @@ CpuMemoryServiceRead ( *((UINT64 *)Uint8Buffer) =3D MmioRead64 ((UINTN)Address);=0D }=0D }=0D +=0D return EFI_SUCCESS;=0D }=0D =0D @@ -322,9 +324,9 @@ CpuMemoryServiceWrite ( //=0D // Select loop based on the width of the transfer=0D //=0D - InStride =3D mInStride[Width];=0D - OutStride =3D mOutStride[Width];=0D - OperationWidth =3D (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03);=0D + InStride =3D mInStride[Width];=0D + OutStride =3D mOutStride[Width];=0D + OperationWidth =3D (EFI_CPU_IO_PROTOCOL_WIDTH)(Width & 0x03);=0D for (Uint8Buffer =3D Buffer; Count > 0; Address +=3D InStride, Uint8Buff= er +=3D OutStride, Count--) {=0D if (OperationWidth =3D=3D EfiCpuIoWidthUint8) {=0D MmioWrite8 ((UINTN)Address, *Uint8Buffer);=0D @@ -336,6 +338,7 @@ CpuMemoryServiceWrite ( MmioWrite64 ((UINTN)Address, *((UINT64 *)Uint8Buffer));=0D }=0D }=0D +=0D return EFI_SUCCESS;=0D }=0D =0D @@ -405,9 +408,9 @@ CpuIoServiceRead ( //=0D // Select loop based on the width of the transfer=0D //=0D - InStride =3D mInStride[Width];=0D - OutStride =3D mOutStride[Width];=0D - OperationWidth =3D (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03);=0D + InStride =3D mInStride[Width];=0D + OutStride =3D mOutStride[Width];=0D + OperationWidth =3D (EFI_CPU_IO_PROTOCOL_WIDTH)(Width & 0x03);=0D =0D for (Uint8Buffer =3D Buffer; Count > 0; Address +=3D InStride, Uint8Buff= er +=3D OutStride, Count--) {=0D if (OperationWidth =3D=3D EfiCpuIoWidthUint8) {=0D @@ -491,9 +494,9 @@ CpuIoServiceWrite ( //=0D // Select loop based on the width of the transfer=0D //=0D - InStride =3D mInStride[Width];=0D - OutStride =3D mOutStride[Width];=0D - OperationWidth =3D (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03);=0D + InStride =3D mInStride[Width];=0D + OutStride =3D mOutStride[Width];=0D + OperationWidth =3D (EFI_CPU_IO_PROTOCOL_WIDTH)(Width & 0x03);=0D =0D for (Uint8Buffer =3D (UINT8 *)Buffer; Count > 0; Address +=3D InStride, = Uint8Buffer +=3D OutStride, Count--) {=0D if (OperationWidth =3D=3D EfiCpuIoWidthUint8) {=0D @@ -511,7 +514,7 @@ CpuIoServiceWrite ( //=0D // CPU I/O 2 Protocol instance=0D //=0D -STATIC EFI_CPU_IO2_PROTOCOL mCpuIo2 =3D {=0D +STATIC EFI_CPU_IO2_PROTOCOL mCpuIo2 =3D {=0D {=0D CpuMemoryServiceRead,=0D CpuMemoryServiceWrite=0D @@ -522,7 +525,6 @@ STATIC EFI_CPU_IO2_PROTOCOL mCpuIo2 =3D { }=0D };=0D =0D -=0D /**=0D The user Entry Point for module CpuIo2Dxe. The user code starts with thi= s function.=0D =0D @@ -540,12 +542,13 @@ PciCpuIo2Initialize ( IN EFI_SYSTEM_TABLE *SystemTable=0D )=0D {=0D - EFI_STATUS Status;=0D + EFI_STATUS Status;=0D =0D ASSERT_PROTOCOL_ALREADY_INSTALLED (NULL, &gEfiCpuIo2ProtocolGuid);=0D Status =3D gBS->InstallMultipleProtocolInterfaces (=0D &mHandle,=0D - &gEfiCpuIo2ProtocolGuid, &mCpuIo2,=0D + &gEfiCpuIo2ProtocolGuid,=0D + &mCpuIo2,=0D NULL=0D );=0D ASSERT_EFI_ERROR (Status);=0D diff --git a/Silicon/RISC-V/ProcessorPkg/Universal/SmbiosDxe/RiscVSmbiosDxe= .c b/Silicon/RISC-V/ProcessorPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.c index 14f62c4036..1375bb0afc 100644 --- a/Silicon/RISC-V/ProcessorPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.c +++ b/Silicon/RISC-V/ProcessorPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.c @@ -9,7 +9,7 @@ =0D #include "RiscVSmbiosDxe.h"=0D =0D -STATIC EFI_SMBIOS_PROTOCOL *mSmbios;=0D +STATIC EFI_SMBIOS_PROTOCOL *mSmbios;=0D =0D /**=0D This function builds SMBIOS type 7 record according to=0D @@ -25,28 +25,31 @@ STATIC EFI_SMBIOS_PROTOCOL *mSmbios; STATIC=0D EFI_STATUS=0D BuildSmbiosType7 (=0D - IN RISC_V_PROCESSOR_TYPE4_HOB_DATA *Type4HobData,=0D - IN RISC_V_PROCESSOR_TYPE7_HOB_DATA *Type7DataHob,=0D - OUT SMBIOS_HANDLE *SmbiosHandle=0D -)=0D + IN RISC_V_PROCESSOR_TYPE4_HOB_DATA *Type4HobData,=0D + IN RISC_V_PROCESSOR_TYPE7_HOB_DATA *Type7DataHob,=0D + OUT SMBIOS_HANDLE *SmbiosHandle=0D + )=0D {=0D - EFI_STATUS Status;=0D - SMBIOS_HANDLE Handle;=0D + EFI_STATUS Status;=0D + SMBIOS_HANDLE Handle;=0D =0D if (!CompareGuid (&Type4HobData->ProcessorGuid, &Type7DataHob->Processor= Guid) ||=0D - Type4HobData->ProcessorUid !=3D Type7DataHob->ProcessorUid) {=0D + (Type4HobData->ProcessorUid !=3D Type7DataHob->ProcessorUid))=0D + {=0D return EFI_INVALID_PARAMETER;=0D }=0D - Handle =3D SMBIOS_HANDLE_PI_RESERVED;=0D - Type7DataHob->SmbiosType7Cache.Hdr.Type =3D SMBIOS_TYPE_CACHE_INFORMATIO= N;=0D - Type7DataHob->SmbiosType7Cache.Hdr.Length =3D sizeof(SMBIOS_TABLE_TYPE7)= ;=0D +=0D + Handle =3D SMBIOS_HANDLE_PI_RESERVED;= =0D + Type7DataHob->SmbiosType7Cache.Hdr.Type =3D SMBIOS_TYPE_CACHE_INFORMAT= ION;=0D + Type7DataHob->SmbiosType7Cache.Hdr.Length =3D sizeof (SMBIOS_TABLE_TYPE7= );=0D Type7DataHob->SmbiosType7Cache.Hdr.Handle =3D 0;=0D - Type7DataHob->EndingZero =3D 0;=0D - Status =3D mSmbios->Add (mSmbios, NULL, &Handle, &Type7DataHob->SmbiosTy= pe7Cache.Hdr);=0D - if (EFI_ERROR(Status)) {=0D + Type7DataHob->EndingZero =3D 0;=0D + Status =3D mSmbios->Add (mSmbios, NUL= L, &Handle, &Type7DataHob->SmbiosType7Cache.Hdr);=0D + if (EFI_ERROR (Status)) {=0D DEBUG ((DEBUG_ERROR, "%a: Fail to add SMBIOS Type 7\n", __FUNCTION__))= ;=0D return Status;=0D }=0D +=0D DEBUG ((DEBUG_INFO, "SMBIOS Type 7 was added. SMBIOS Handle: 0x%x\n", Ha= ndle));=0D DEBUG ((DEBUG_VERBOSE, " Cache belone to processor GUID: %g\n", &Typ= e7DataHob->ProcessorGuid));=0D DEBUG ((DEBUG_VERBOSE, " Cache belone processor UID: %d\n", Type7Da= taHob->ProcessorUid));=0D @@ -79,15 +82,15 @@ BuildSmbiosType7 ( STATIC=0D EFI_STATUS=0D BuildSmbiosType4 (=0D - IN RISC_V_PROCESSOR_TYPE4_HOB_DATA *Type4HobData,=0D - OUT SMBIOS_HANDLE *SmbiosHandle=0D + IN RISC_V_PROCESSOR_TYPE4_HOB_DATA *Type4HobData,=0D + OUT SMBIOS_HANDLE *SmbiosHandle=0D )=0D {=0D - EFI_HOB_GUID_TYPE *GuidHob;=0D - RISC_V_PROCESSOR_TYPE7_HOB_DATA *Type7HobData;=0D - SMBIOS_HANDLE Cache;=0D - SMBIOS_HANDLE Processor;=0D - EFI_STATUS Status;=0D + EFI_HOB_GUID_TYPE *GuidHob;=0D + RISC_V_PROCESSOR_TYPE7_HOB_DATA *Type7HobData;=0D + SMBIOS_HANDLE Cache;=0D + SMBIOS_HANDLE Processor;=0D + EFI_STATUS Status;=0D =0D DEBUG ((DEBUG_INFO, "Building Type 4.\n"));=0D DEBUG ((DEBUG_INFO, " Processor GUID: %g\n", &Type4HobData->Processor= Guid));=0D @@ -96,55 +99,66 @@ BuildSmbiosType4 ( Type4HobData->SmbiosType4Processor.L1CacheHandle =3D RISC_V_CACHE_INFO_N= OT_PROVIDED;=0D Type4HobData->SmbiosType4Processor.L2CacheHandle =3D RISC_V_CACHE_INFO_N= OT_PROVIDED;=0D Type4HobData->SmbiosType4Processor.L3CacheHandle =3D RISC_V_CACHE_INFO_N= OT_PROVIDED;=0D - GuidHob =3D (EFI_HOB_GUID_TYPE *)GetFirstGuidHob ((EFI_GUID *)PcdGetPtr(= PcdProcessorSmbiosType7GuidHobGuid));=0D + GuidHob =3D (EFI_HOB_GUID_TYPE = *)GetFirstGuidHob ((EFI_GUID *)PcdGetPtr (PcdProcessorSmbiosType7GuidHobGui= d));=0D if (GuidHob =3D=3D NULL) {=0D DEBUG ((DEBUG_ERROR, "No RISC-V SMBIOS Type7 data HOB found.\n"));=0D return EFI_NOT_FOUND;=0D }=0D +=0D //=0D // Go through each RISC_V_PROCESSOR_TYPE4_HOB_DATA for multiple processo= rs.=0D //=0D do {=0D Type7HobData =3D (RISC_V_PROCESSOR_TYPE7_HOB_DATA *)GET_GUID_HOB_DATA = (GuidHob);=0D - Status =3D BuildSmbiosType7 (Type4HobData, Type7HobData, &Cache);=0D + Status =3D BuildSmbiosType7 (Type4HobData, Type7HobData, &Cache)= ;=0D if (EFI_ERROR (Status)) {=0D return Status;=0D }=0D +=0D if ((Type7HobData->SmbiosType7Cache.SystemCacheType & RISC_V_CACHE_CON= FIGURATION_CACHE_LEVEL_MASK) =3D=3D=0D - RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_1) {=0D + RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_1)=0D + {=0D Type4HobData->SmbiosType4Processor.L1CacheHandle =3D Cache;=0D } else if ((Type7HobData->SmbiosType7Cache.SystemCacheType & RISC_V_CA= CHE_CONFIGURATION_CACHE_LEVEL_MASK) =3D=3D=0D - RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_2) {=0D + RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_2)=0D + {=0D Type4HobData->SmbiosType4Processor.L2CacheHandle =3D Cache;=0D } else if ((Type7HobData->SmbiosType7Cache.SystemCacheType & RISC_V_CA= CHE_CONFIGURATION_CACHE_LEVEL_MASK) =3D=3D=0D - RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_3) {=0D + RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_3)=0D + {=0D Type4HobData->SmbiosType4Processor.L3CacheHandle =3D Cache;=0D } else {=0D DEBUG ((DEBUG_ERROR, "Improper cache level of SMBIOS handle %d\n", C= ache));=0D }=0D - GuidHob =3D GetNextGuidHob((EFI_GUID *)PcdGetPtr(PcdProcessorSmbiosTyp= e7GuidHobGuid), GET_NEXT_HOB(GuidHob));=0D +=0D + GuidHob =3D GetNextGuidHob ((EFI_GUID *)PcdGetPtr (PcdProcessorSmbiosT= ype7GuidHobGuid), GET_NEXT_HOB (GuidHob));=0D } while (GuidHob !=3D NULL);=0D =0D //=0D // Build SMBIOS Type 4 record=0D //=0D - Processor =3D SMBIOS_HANDLE_PI_RESERVED;=0D - Type4HobData->SmbiosType4Processor.Hdr.Type =3D SMBIOS_TYPE_PROCESSOR_IN= FORMATION;=0D - Type4HobData->SmbiosType4Processor.Hdr.Length =3D sizeof(SMBIOS_TABLE_TY= PE4);=0D + Processor =3D SMBIOS_HANDLE_PI_RESER= VED;=0D + Type4HobData->SmbiosType4Processor.Hdr.Type =3D SMBIOS_TYPE_PROCESSOR_= INFORMATION;=0D + Type4HobData->SmbiosType4Processor.Hdr.Length =3D sizeof (SMBIOS_TABLE_T= YPE4);=0D Type4HobData->SmbiosType4Processor.Hdr.Handle =3D 0;=0D - Type4HobData->EndingZero =3D 0;=0D - Status =3D mSmbios->Add (mSmbios, NULL, &Processor, &Type4HobData->Smbio= sType4Processor.Hdr);=0D - if (EFI_ERROR(Status)) {=0D + Type4HobData->EndingZero =3D 0;=0D + Status =3D mSmbios->Add (mSmbios,= NULL, &Processor, &Type4HobData->SmbiosType4Processor.Hdr);=0D + if (EFI_ERROR (Status)) {=0D DEBUG ((DEBUG_ERROR, "Fail to add SMBIOS Type 4\n"));=0D return Status;=0D }=0D +=0D DEBUG ((DEBUG_INFO, "SMBIOS Type 4 was added. SMBIOS Handle: 0x%x\n", Pr= ocessor));=0D DEBUG ((DEBUG_VERBOSE, " Socket StringID: %d\n", Type4HobData->Smbio= sType4Processor.Socket));=0D DEBUG ((DEBUG_VERBOSE, " Processor Type: 0x%x\n", Type4HobData->Smbi= osType4Processor.ProcessorType));=0D DEBUG ((DEBUG_VERBOSE, " Processor Family: 0x%x\n", Type4HobData->Sm= biosType4Processor.ProcessorFamily));=0D DEBUG ((DEBUG_VERBOSE, " Processor Manufacture StringID: %d\n", Type= 4HobData->SmbiosType4Processor.ProcessorManufacturer));=0D - DEBUG ((DEBUG_VERBOSE, " Processor Id: 0x%x:0x%x\n", \=0D - Type4HobData->SmbiosType4Processor.ProcessorId.Signature, Type4H= obData->SmbiosType4Processor.ProcessorId.FeatureFlags));=0D + DEBUG ((=0D + DEBUG_VERBOSE,=0D + " Processor Id: 0x%x:0x%x\n", \=0D + Type4HobData->SmbiosType4Processor.ProcessorId.Signature,=0D + Type4HobData->SmbiosType4Processor.ProcessorId.FeatureFlags=0D + ));=0D DEBUG ((DEBUG_VERBOSE, " Processor Version StringID: %d\n", Type4Hob= Data->SmbiosType4Processor.ProcessorVersion));=0D DEBUG ((DEBUG_VERBOSE, " Voltage: 0x%x\n", Type4HobData->SmbiosType4= Processor.Voltage));=0D DEBUG ((DEBUG_VERBOSE, " External Clock: 0x%x\n", Type4HobData->Smbi= osType4Processor.ExternalClock));=0D @@ -153,7 +167,7 @@ BuildSmbiosType4 ( DEBUG ((DEBUG_VERBOSE, " Status: 0x%x\n", Type4HobData->SmbiosType4P= rocessor.Status));=0D DEBUG ((DEBUG_VERBOSE, " ProcessorUpgrade: 0x%x\n", Type4HobData->Sm= biosType4Processor.ProcessorUpgrade));=0D DEBUG ((DEBUG_VERBOSE, " L1 Cache Handle: 0x%x\n", Type4HobData->Smb= iosType4Processor.L1CacheHandle));=0D - DEBUG ((DEBUG_VERBOSE, " L2 Cache Handle: 0x%x\n",Type4HobData->Smbi= osType4Processor.L2CacheHandle));=0D + DEBUG ((DEBUG_VERBOSE, " L2 Cache Handle: 0x%x\n", Type4HobData->Smb= iosType4Processor.L2CacheHandle));=0D DEBUG ((DEBUG_VERBOSE, " L3 Cache Handle: 0x%x\n", Type4HobData->Smb= iosType4Processor.L3CacheHandle));=0D DEBUG ((DEBUG_VERBOSE, " Serial Number StringID: %d\n", Type4HobData= ->SmbiosType4Processor.SerialNumber));=0D DEBUG ((DEBUG_VERBOSE, " Asset Tag StringID: %d\n", Type4HobData->Sm= biosType4Processor.AssetTag));=0D @@ -182,51 +196,55 @@ BuildSmbiosType4 ( **/=0D EFI_STATUS=0D BuildSmbiosType44 (=0D - IN RISC_V_PROCESSOR_TYPE4_HOB_DATA *Type4HobData,=0D - IN SMBIOS_HANDLE Type4Handle=0D + IN RISC_V_PROCESSOR_TYPE4_HOB_DATA *Type4HobData,=0D + IN SMBIOS_HANDLE Type4Handle=0D )=0D {=0D - EFI_HOB_GUID_TYPE *GuidHob;=0D - RISC_V_PROCESSOR_SPECIFIC_HOB_DATA *ProcessorSpecificData;=0D - SMBIOS_HANDLE RiscVType44;=0D - SMBIOS_TABLE_TYPE44 *Type44Ptr;=0D - EFI_STATUS Status;=0D + EFI_HOB_GUID_TYPE *GuidHob;=0D + RISC_V_PROCESSOR_SPECIFIC_HOB_DATA *ProcessorSpecificData;=0D + SMBIOS_HANDLE RiscVType44;=0D + SMBIOS_TABLE_TYPE44 *Type44Ptr;=0D + EFI_STATUS Status;=0D =0D DEBUG ((DEBUG_INFO, "Building Type 44 for...\n"));=0D DEBUG ((DEBUG_VERBOSE, " Processor GUID: %g\n", &Type4HobData->Proce= ssorGuid));=0D DEBUG ((DEBUG_VERBOSE, " Processor UUID: %d\n", Type4HobData->Proces= sorUid));=0D =0D - GuidHob =3D (EFI_HOB_GUID_TYPE *)GetFirstGuidHob ((EFI_GUID *)PcdGetPtr(= PcdProcessorSpecificDataGuidHobGuid));=0D + GuidHob =3D (EFI_HOB_GUID_TYPE *)GetFirstGuidHob ((EFI_GUID *)PcdGetPtr = (PcdProcessorSpecificDataGuidHobGuid));=0D if (GuidHob =3D=3D NULL) {=0D DEBUG ((DEBUG_ERROR, "No RISC_V_PROCESSOR_SPECIFIC_HOB_DATA found.\n")= );=0D return EFI_NOT_FOUND;=0D }=0D +=0D //=0D // Go through each RISC_V_PROCESSOR_SPECIFIC_HOB_DATA for multiple cores= .=0D //=0D do {=0D ProcessorSpecificData =3D (RISC_V_PROCESSOR_SPECIFIC_HOB_DATA *)GET_GU= ID_HOB_DATA (GuidHob);=0D if (!CompareGuid (&ProcessorSpecificData->ParentProcessorGuid, &Type4H= obData->ProcessorGuid) ||=0D - ProcessorSpecificData->ParentProcessorUid !=3D Type4HobData->Process= orUid) {=0D - GuidHob =3D GetNextGuidHob((EFI_GUID *)PcdGetPtr(PcdProcessorSpecifi= cDataGuidHobGuid), GET_NEXT_HOB(GuidHob));=0D + (ProcessorSpecificData->ParentProcessorUid !=3D Type4HobData->Proc= essorUid))=0D + {=0D + GuidHob =3D GetNextGuidHob ((EFI_GUID *)PcdGetPtr (PcdProcessorSpeci= ficDataGuidHobGuid), GET_NEXT_HOB (GuidHob));=0D if (GuidHob =3D=3D NULL) {=0D break;=0D }=0D +=0D continue;=0D }=0D =0D DEBUG ((DEBUG_VERBOSE, "=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D\n"));=0D DEBUG ((DEBUG_VERBOSE, "Core GUID: %g\n", &ProcessorSpecificData->Core= Guid));=0D =0D - Type44Ptr =3D AllocateZeroPool(sizeof(SMBIOS_TABLE_TYPE44) + sizeof(SM= BIOS_RISC_V_PROCESSOR_SPECIFIC_DATA) + 2); // Two ending zero.=0D + Type44Ptr =3D AllocateZeroPool (sizeof (SMBIOS_TABLE_TYPE44) + sizeof = (SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA) + 2); // Two ending zero.=0D if (Type44Ptr =3D=3D NULL) {=0D return EFI_NOT_FOUND;=0D }=0D - Type44Ptr->Hdr.Type =3D SMBIOS_TYPE_PROCESSOR_ADDITIONAL_INFORMATION;= =0D - Type44Ptr->Hdr.Handle =3D 0;=0D - Type44Ptr->Hdr.Length =3D sizeof(SMBIOS_TABLE_TYPE44) + sizeof(SMBIOS_= RISC_V_PROCESSOR_SPECIFIC_DATA);=0D - Type44Ptr->RefHandle =3D Type4Handle;=0D - Type44Ptr->ProcessorSpecificBlock.Length =3D sizeof(SMBIOS_RISC_V_PROC= ESSOR_SPECIFIC_DATA);=0D +=0D + Type44Ptr->Hdr.Type =3D SMBIOS_TYPE_PR= OCESSOR_ADDITIONAL_INFORMATION;=0D + Type44Ptr->Hdr.Handle =3D 0;=0D + Type44Ptr->Hdr.Length =3D sizeof (SMBIOS= _TABLE_TYPE44) + sizeof (SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA);=0D + Type44Ptr->RefHandle =3D Type4Handle;=0D + Type44Ptr->ProcessorSpecificBlock.Length =3D sizeof (SMBIOS= _RISC_V_PROCESSOR_SPECIFIC_DATA);=0D Type44Ptr->ProcessorSpecificBlock.ProcessorArchType =3D Type4HobData->= SmbiosType4Processor.ProcessorFamily2 -=0D ProcessorFamilyR= iscvRV32 + \=0D ProcessorSpecifi= cBlockArchTypeRiscVRV32;=0D @@ -251,15 +269,17 @@ BuildSmbiosType44 ( // Add to SMBIOS table.=0D //=0D RiscVType44 =3D SMBIOS_HANDLE_PI_RESERVED;=0D - Status =3D mSmbios->Add (mSmbios, NULL, &RiscVType44, &Type44Ptr->Hdr)= ;=0D - if (EFI_ERROR(Status)) {=0D + Status =3D mSmbios->Add (mSmbios, NULL, &RiscVType44, &Type44Ptr-= >Hdr);=0D + if (EFI_ERROR (Status)) {=0D DEBUG ((DEBUG_ERROR, "Fail to add SMBIOS Type 44\n"));=0D return Status;=0D }=0D +=0D DEBUG ((DEBUG_INFO, "SMBIOS Type 44 was added. SMBIOS Handle: 0x%x\n",= RiscVType44));=0D =0D - GuidHob =3D GetNextGuidHob((EFI_GUID *)PcdGetPtr(PcdProcessorSpecificD= ataGuidHobGuid), GET_NEXT_HOB(GuidHob));=0D + GuidHob =3D GetNextGuidHob ((EFI_GUID *)PcdGetPtr (PcdProcessorSpecifi= cDataGuidHobGuid), GET_NEXT_HOB (GuidHob));=0D } while (GuidHob !=3D NULL);=0D +=0D return EFI_SUCCESS;=0D }=0D =0D @@ -277,14 +297,14 @@ BuildSmbiosType44 ( EFI_STATUS=0D EFIAPI=0D RiscVSmbiosBuilderEntry (=0D - IN EFI_HANDLE ImageHandle,=0D - IN EFI_SYSTEM_TABLE *SystemTable=0D + IN EFI_HANDLE ImageHandle,=0D + IN EFI_SYSTEM_TABLE *SystemTable=0D )=0D {=0D - EFI_STATUS Status;=0D - EFI_HOB_GUID_TYPE *GuidHob;=0D - RISC_V_PROCESSOR_TYPE4_HOB_DATA *Type4HobData;=0D - SMBIOS_HANDLE Processor;=0D + EFI_STATUS Status;=0D + EFI_HOB_GUID_TYPE *GuidHob;=0D + RISC_V_PROCESSOR_TYPE4_HOB_DATA *Type4HobData;=0D + SMBIOS_HANDLE Processor;=0D =0D DEBUG ((DEBUG_INFO, "%a: entry\n", __FUNCTION__));=0D =0D @@ -297,13 +317,15 @@ RiscVSmbiosBuilderEntry ( DEBUG ((DEBUG_ERROR, "Locate SMBIOS Protocol fail\n"));=0D return Status;=0D }=0D - GuidHob =3D (EFI_HOB_GUID_TYPE *)GetFirstGuidHob ((EFI_GUID *)PcdGetPtr(= PcdProcessorSmbiosType4GuidHobGuid));=0D +=0D + GuidHob =3D (EFI_HOB_GUID_TYPE *)GetFirstGuidHob ((EFI_GUID *)PcdGetPtr = (PcdProcessorSmbiosType4GuidHobGuid));=0D if (GuidHob =3D=3D NULL) {=0D DEBUG ((DEBUG_ERROR, "No RISC-V SMBIOS information found.\n"));=0D return EFI_NOT_FOUND;=0D }=0D +=0D Type4HobData =3D (RISC_V_PROCESSOR_TYPE4_HOB_DATA *)GET_GUID_HOB_DATA (G= uidHob);=0D - Status =3D EFI_NOT_FOUND;=0D + Status =3D EFI_NOT_FOUND;=0D //=0D // Go through each RISC_V_PROCESSOR_TYPE4_HOB_DATA for multiple processo= rs.=0D //=0D @@ -313,15 +335,16 @@ RiscVSmbiosBuilderEntry ( DEBUG ((DEBUG_ERROR, "No RISC-V SMBIOS type 4 created.\n"));=0D ASSERT (FALSE);=0D }=0D +=0D Status =3D BuildSmbiosType44 (Type4HobData, Processor);=0D if (EFI_ERROR (Status)) {=0D DEBUG ((DEBUG_ERROR, "No RISC-V SMBIOS type 44 found.\n"));=0D ASSERT (FALSE);=0D }=0D =0D - GuidHob =3D GetNextGuidHob((EFI_GUID *)PcdGetPtr(PcdProcessorSmbiosTyp= e4GuidHobGuid), GET_NEXT_HOB(GuidHob));=0D + GuidHob =3D GetNextGuidHob ((EFI_GUID *)PcdGetPtr (PcdProcessorSmbiosT= ype4GuidHobGuid), GET_NEXT_HOB (GuidHob));=0D } while (GuidHob !=3D NULL);=0D +=0D DEBUG ((DEBUG_INFO, "%a: exit\n", __FUNCTION__));=0D return Status;=0D }=0D -=0D diff --git a/Silicon/RISC-V/ProcessorPkg/Library/PeiServicesTablePointerLib= OpenSbi/PeiServicesTablePointerLibOpenSbi.uni b/Silicon/RISC-V/ProcessorPkg= /Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerLibOpenSb= i.uni index f6fad8bcb5..9472496fb2 100644 --- a/Silicon/RISC-V/ProcessorPkg/Library/PeiServicesTablePointerLibOpenSbi= /PeiServicesTablePointerLibOpenSbi.uni +++ b/Silicon/RISC-V/ProcessorPkg/Library/PeiServicesTablePointerLibOpenSbi= /PeiServicesTablePointerLibOpenSbi.uni @@ -1,23 +1,16 @@ // /** @file=0D //=0D // Instance of PEI Services Table Pointer Library using RISC-V OpenSBI Fir= mwareContext.=0D -//=0D // PEI Services Table Pointer Library implementation that retrieves a poin= ter to the=0D // PEI Services Table from a RISC-V OpenSBI sbi_platform firmware context = structure.=0D //=0D -// Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
=0D +// Copyright (c) 2029-2022, Hewlett Packard Enterprise Development LP. All= rights reserved.
=0D //=0D -// This program and the accompanying materials=0D -// are licensed and made available under the terms and conditions of the B= SD License=0D -// which accompanies this distribution. The full text of the license may b= e found at=0D -// http://opensource.org/licenses/bsd-license.php.=0D -// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,=0D -// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED.=0D +// SPDX-License-Identifier: BSD-2-Clause-Patent=0D //=0D // **/=0D =0D -=0D #string STR_MODULE_ABSTRACT #language en-US "Instance of PEI S= ervices Table Pointer Library using global variable for the table pointer"= =0D -=0D -#string STR_MODULE_DESCRIPTION #language en-US "The PEI Services = Table Pointer Library implementation that retrieves a pointer to the PEI Se= rvices Table from a global variable. Not available to modules that execute = from read-only memory."=0D +#string STR_MODULE_DESCRIPTION #language en-US "The PEI Services = Table Pointer Library implementation that retrieves a pointer to the PEI Se= rvices Table from a global variable."=0D + "Not available to = modules that execute from read-only memory."=0D =0D --=20 2.31.1