From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mx0a-002e3701.pphosted.com (mx0a-002e3701.pphosted.com [148.163.147.86]) by mx.groups.io with SMTP id smtpd.web08.5990.1642838098147755601 for ; Fri, 21 Jan 2022 23:54:58 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@hpe.com header.s=pps0720 header.b=X0qq07qG; spf=permerror, err=parse error for token &{10 18 %{ir}.%{v}.%{d}.spf.has.pphosted.com}: invalid domain name (domain: hpe.com, ip: 148.163.147.86, mailfrom: prvs=00215b754f=abner.chang@hpe.com) Received: from pps.filterd (m0134421.ppops.net [127.0.0.1]) by mx0b-002e3701.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 20M6WAYa012805; Sat, 22 Jan 2022 07:54:57 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=hpe.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : content-transfer-encoding : mime-version; s=pps0720; bh=eqQLb49cJAtJq+e+lzLJcL6apIV06QIpvxbZJsxxNuA=; b=X0qq07qG0vpEgsJOZ3OOtjFVYlaF7gBUWXkxJuxDtxS2g7dyTOKSIhPJ3L/Je5hTEvse PEaFai7BqV4mjLJMmLzBAO4IvaxJNpMOL7ERGlq4tqYt28nM/mB2aBECkiYun7DuNgQV HaRNwBgAxANnN1ytS5m53bBOXVSFSopRC1jABOx0CDtP00TL19IFamzGpKTHfH892cMz ucEGMsE7AkEXx1uBPKKDBjHb3uxqzx96MT89XXR78d13Y0WzB6PeCO4gSz3BGdpFjv6Y bQa0wTHSBnB1HmU+wybBi0ZQJKW6uX5eUNj5xbuLCYKXrG43kcyPLt4zT002P+R3+OG3 Gg== Received: from g9t5009.houston.hpe.com (g9t5009.houston.hpe.com [15.241.48.73]) by mx0b-002e3701.pphosted.com (PPS) with ESMTPS id 3drb350r2p-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Sat, 22 Jan 2022 07:54:57 +0000 Received: from g4t3433.houston.hpecorp.net (g4t3433.houston.hpecorp.net [16.208.49.245]) by g9t5009.houston.hpe.com (Postfix) with ESMTP id 8B6B05C; Sat, 22 Jan 2022 07:54:56 +0000 (UTC) Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.229]) by g4t3433.houston.hpecorp.net (Postfix) with ESMTP id 7563845; Sat, 22 Jan 2022 07:54:55 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com, Daniel Schaefer , Sunil V L Subject: [edk2-platforms][PATCH V2 04/14] RISC-V/PlatformPkg: Address Spelling check errors. Date: Sat, 22 Jan 2022 14:53:08 +0800 Message-Id: <20220122065318.21808-5-abner.chang@hpe.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20220122065318.21808-1-abner.chang@hpe.com> References: <20220122065318.21808-1-abner.chang@hpe.com> X-Proofpoint-GUID: tdK8VC68cSEdaJkUCXcKxStRNLAj19bX X-Proofpoint-ORIG-GUID: tdK8VC68cSEdaJkUCXcKxStRNLAj19bX X-Proofpoint-UnRewURL: 0 URL was un-rewritten MIME-Version: 1.0 X-HPE-SCL: -1 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.816,Hydra:6.0.425,FMLib:17.11.62.513 definitions=2022-01-22_03,2022-01-21_01,2021-12-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 spamscore=0 lowpriorityscore=0 suspectscore=0 mlxlogscore=999 bulkscore=0 clxscore=1015 adultscore=0 mlxscore=0 impostorscore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2201110000 definitions=main-2201220050 Content-Transfer-Encoding: quoted-printable Signed-off-by: Abner Chang Cc: Daniel Schaefer Cc: Sunil V L --- Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec | 4 ++-- .../FirmwareContextProcessorSpecificLib.inf | 2 +- .../PlatformPkg/Universal/FdtPeim/FdtPeim.inf | 2 +- .../Library/FirmwareContextProcessorSpecificLib.h | 4 ++-- .../RISC-V/PlatformPkg/Universal/Sec/SecMain.h | 4 ++-- .../Edk2OpensbiPlatformWrapperLib.c | 10 +++++----- .../FirmwareContextProcessorSpecificLib.c | 8 ++++---- .../PlatformBootManagerLib/PlatformBootManager.c | 4 ++-- .../Universal/Pei/PlatformPei/Platform.c | 4 ++-- .../RISC-V/PlatformPkg/Universal/Sec/SecMain.c | 10 +++++----- Platform/RISC-V/PlatformPkg/Readme.md | 14 +++++++------- .../PlatformPkg/Universal/Sec/Riscv64/SecEntry.S | 8 ++++---- 12 files changed, 37 insertions(+), 37 deletions(-) diff --git a/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec b/Platform/RI= SC-V/PlatformPkg/RiscVPlatformPkg.dec index 53d424c901..f3217e4a05 100644 --- a/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec +++ b/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec @@ -1,7 +1,7 @@ ## @file RiscVPlatformPkg.dec=0D # This Package provides UEFI RISC-V platform modules and libraries.=0D #=0D -# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All right= s reserved.
=0D +# Copyright (c) 2021-2022, Hewlett Packard Enterprise Development LP. All = rights reserved.
=0D #=0D # SPDX-License-Identifier: BSD-2-Clause-Patent=0D #=0D @@ -20,7 +20,7 @@ [LibraryClasses]=0D FirmwareContextProcessorSpecificLib|Include/Library/FirmwareContextProce= ssorSpecificLib.h=0D RiscVPlatformTempMemoryInitLib|Include/Library/RiscVPlatformTempMemoryIn= itLib.h=0D - Edk2OpensbiPlatformiLib|Include/Library/Edk2OpensbiPlatformiWrapperLib.h= =0D + Edk2OpensbiPlatformWrapperLib|Include/Library/Edk2OpensbiPlatformWrapper= Lib.h=0D =0D [Guids]=0D gUefiRiscVPlatformPkgTokenSpaceGuid =3D {0x6A67AF99, 0x4592, 0x40F8, { = 0xB6, 0xBE, 0x62, 0xBC, 0xA1, 0x0D, 0xA1, 0xEC}}=0D diff --git a/Platform/RISC-V/PlatformPkg/Library/FirmwareContextProcessorSp= ecificLib/FirmwareContextProcessorSpecificLib.inf b/Platform/RISC-V/Platfor= mPkg/Library/FirmwareContextProcessorSpecificLib/FirmwareContextProcessorSp= ecificLib.inf index ea2550ce2c..8b645e2c5c 100644 --- a/Platform/RISC-V/PlatformPkg/Library/FirmwareContextProcessorSpecificL= ib/FirmwareContextProcessorSpecificLib.inf +++ b/Platform/RISC-V/PlatformPkg/Library/FirmwareContextProcessorSpecificL= ib/FirmwareContextProcessorSpecificLib.inf @@ -1,6 +1,6 @@ ## @file=0D # This is the library module of RISC-V EDK2 OpenSBI Firmware Context=0D -# Processor Specific hwardware information.=0D +# Processor Specific hardware information.=0D #=0D # Copyright (c) 2019-2022, Hewlett Packard Enterprise Development LP. All= rights reserved.
=0D #=0D diff --git a/Platform/RISC-V/PlatformPkg/Universal/FdtPeim/FdtPeim.inf b/Pl= atform/RISC-V/PlatformPkg/Universal/FdtPeim/FdtPeim.inf index dc3a685d58..2579dafe86 100644 --- a/Platform/RISC-V/PlatformPkg/Universal/FdtPeim/FdtPeim.inf +++ b/Platform/RISC-V/PlatformPkg/Universal/FdtPeim/FdtPeim.inf @@ -1,7 +1,7 @@ ## @file=0D # The FDT Peim driver is used to pass the device tree to DXE phase.=0D #=0D -# Copyright (c) 2021, Hewlett Packard Enterprise Developmente LP. All righ= ts reserved.
=0D +# Copyright (c) 2021-2022, Hewlett Packard Enterprise Development LP. All = rights reserved.
=0D #=0D # SPDX-License-Identifier: BSD-2-Clause-Patent=0D #=0D diff --git a/Platform/RISC-V/PlatformPkg/Include/Library/FirmwareContextPro= cessorSpecificLib.h b/Platform/RISC-V/PlatformPkg/Include/Library/FirmwareC= ontextProcessorSpecificLib.h index 3920c61155..0eec62033b 100644 --- a/Platform/RISC-V/PlatformPkg/Include/Library/FirmwareContextProcessorS= pecificLib.h +++ b/Platform/RISC-V/PlatformPkg/Include/Library/FirmwareContextProcessorS= pecificLib.h @@ -1,7 +1,7 @@ /** @file=0D Firmware Context Processor-specific common library=0D =0D - Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All right= s reserved.
=0D + Copyright (c) 2019-2022, Hewlett Packard Enterprise Development LP. All = rights reserved.
=0D =0D SPDX-License-Identifier: BSD-2-Clause-Patent=0D =0D @@ -18,7 +18,7 @@ =0D @param FirmwareContextHartSpecific Pointer to EFI_RISCV_FIRMWARE_CONTE= XT_HART_SPECIFIC=0D @param ParentProcessorGuid Pointer to GUID of Processor which = contains this core=0D - @param ParentProcessorUid Unique ID of pysical processor whic= h owns this core.=0D + @param ParentProcessorUid Unique ID of physical processor whi= ch owns this core.=0D @param CoreGuid Pointer to GUID of core=0D @param HartId Hart ID of this core.=0D @param IsBootHart This is boot hart or not=0D diff --git a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.h b/Platform= /RISC-V/PlatformPkg/Universal/Sec/SecMain.h index 63a610fbd0..4098bd7d92 100644 --- a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.h +++ b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.h @@ -1,7 +1,7 @@ /** @file=0D RISC-V SEC phase module definitions..=0D =0D - Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All right= s reserved.
=0D + Copyright (c) 2019-2022, Hewlett Packard Enterprise Development LP. All = rights reserved.
=0D =0D SPDX-License-Identifier: BSD-2-Clause-Patent=0D =0D @@ -35,7 +35,7 @@ =0D **/=0D INT32=0D -SecPostOpenSbiPlatformEarlylInit(=0D +SecPostOpenSbiPlatformEarlyInit(=0D IN BOOLEAN ColdBoot=0D );=0D =0D diff --git a/Platform/RISC-V/PlatformPkg/Library/Edk2OpensbiPlatformWrapper= Lib/Edk2OpensbiPlatformWrapperLib.c b/Platform/RISC-V/PlatformPkg/Library/E= dk2OpensbiPlatformWrapperLib/Edk2OpensbiPlatformWrapperLib.c index 2137c6c619..0bd1b44241 100644 --- a/Platform/RISC-V/PlatformPkg/Library/Edk2OpensbiPlatformWrapperLib/Edk= 2OpensbiPlatformWrapperLib.c +++ b/Platform/RISC-V/PlatformPkg/Library/Edk2OpensbiPlatformWrapperLib/Edk= 2OpensbiPlatformWrapperLib.c @@ -1,7 +1,7 @@ /** @file=0D EDK2 OpenSBI generic platform wrapper library=0D =0D - Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All right= s reserved.
=0D + Copyright (c) 2019-2022, Hewlett Packard Enterprise Development LP. All = rights reserved.
=0D =0D SPDX-License-Identifier: BSD-2-Clause-Patent=0D =0D @@ -43,7 +43,7 @@ SecSetEdk2FwMemoryRegions ( fw_memregs.flags =3D SBI_DOMAIN_MEMREGION_EXECUTABLE | SBI_DOMAIN_MEMREG= ION_READABLE;=0D Ret =3D sbi_domain_root_add_memregion ((CONST struct sbi_domain_memregio= n *)&fw_memregs);=0D if (Ret !=3D 0) {=0D - DEBUG ((DEBUG_ERROR, "%a: Add firmware regiosn of FW Domain fail\n", _= _FUNCTION__));=0D + DEBUG ((DEBUG_ERROR, "%a: Add firmware regions of FW Domain fail\n", _= _FUNCTION__));=0D }=0D =0D //=0D @@ -54,7 +54,7 @@ SecSetEdk2FwMemoryRegions ( fw_memregs.flags =3D SBI_DOMAIN_MEMREGION_READABLE | SBI_DOMAIN_MEMREGIO= N_WRITEABLE;=0D Ret =3D sbi_domain_root_add_memregion ((CONST struct sbi_domain_memregio= n *)&fw_memregs);=0D if (Ret !=3D 0) {=0D - DEBUG ((DEBUG_ERROR, "%a: Add firmware regiosn of variable FW Domain f= ail\n", __FUNCTION__));=0D + DEBUG ((DEBUG_ERROR, "%a: Add firmware regions of variable FW Domain f= ail\n", __FUNCTION__));=0D }=0D return Ret;=0D }=0D @@ -66,7 +66,7 @@ SecSetEdk2FwMemoryRegions ( =0D **/=0D INT32=0D -SecPostOpenSbiPlatformEarlylInit(=0D +SecPostOpenSbiPlatformEarlyInit(=0D IN BOOLEAN ColdBoot=0D )=0D {=0D @@ -190,7 +190,7 @@ Edk2OpensbiPlatformEarlyInit ( }=0D }=0D if (ColdBoot) {=0D - return SecPostOpenSbiPlatformEarlylInit(ColdBoot);=0D + return SecPostOpenSbiPlatformEarlyInit(ColdBoot);=0D }=0D return 0;=0D }=0D diff --git a/Platform/RISC-V/PlatformPkg/Library/FirmwareContextProcessorSp= ecificLib/FirmwareContextProcessorSpecificLib.c b/Platform/RISC-V/PlatformP= kg/Library/FirmwareContextProcessorSpecificLib/FirmwareContextProcessorSpec= ificLib.c index 143c18d62c..c94f7881c2 100644 --- a/Platform/RISC-V/PlatformPkg/Library/FirmwareContextProcessorSpecificL= ib/FirmwareContextProcessorSpecificLib.c +++ b/Platform/RISC-V/PlatformPkg/Library/FirmwareContextProcessorSpecificL= ib/FirmwareContextProcessorSpecificLib.c @@ -1,7 +1,7 @@ /** @file=0D - Common library to build upfirmware context processor-specific informatio= n=0D + Common library to build up firmware context processor-specific informati= on=0D =0D - Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All right= s reserved.
=0D + Copyright (c) 2019-2022, Hewlett Packard Enterprise Development LP. All = rights reserved.
=0D =0D SPDX-License-Identifier: BSD-2-Clause-Patent=0D =0D @@ -28,7 +28,7 @@ =0D @param FirmwareContextHartSpecific Pointer to EFI_RISCV_FIRMWARE_CONTE= XT_HART_SPECIFIC=0D @param ParentProcessorGuid Pointer to GUID of Processor which = contains this core=0D - @param ParentProcessorUid Unique ID of pysical processor whic= h owns this core.=0D + @param ParentProcessorUid Unique ID of physical processor whi= ch owns this core.=0D @param CoreGuid Pointer to GUID of core=0D @param HartId Hart ID of this core.=0D @param IsBootHart This is boot hart or not=0D @@ -52,7 +52,7 @@ CommonFirmwareContextHartSpecificInfo ( //=0D // Build up RISC_V_PROCESSOR_SPECIFIC_DATA_HOB.=0D //=0D - CopyGuid (&ProcessorSpecificDataHob->ParentPrcessorGuid, ParentProcessor= Guid);=0D + CopyGuid (&ProcessorSpecificDataHob->ParentProcessorGuid, ParentProcesso= rGuid);=0D ProcessorSpecificDataHob->ParentProcessorUid =3D ParentProcessorUid;=0D CopyGuid (&ProcessorSpecificDataHob->CoreGuid, CoreGuid);=0D ProcessorSpecificDataHob->Context =3D NULL;=0D diff --git a/Platform/RISC-V/PlatformPkg/Library/PlatformBootManagerLib/Pla= tformBootManager.c b/Platform/RISC-V/PlatformPkg/Library/PlatformBootManage= rLib/PlatformBootManager.c index deaad7d5a1..9ad4ef17db 100644 --- a/Platform/RISC-V/PlatformPkg/Library/PlatformBootManagerLib/PlatformBo= otManager.c +++ b/Platform/RISC-V/PlatformPkg/Library/PlatformBootManagerLib/PlatformBo= otManager.c @@ -1,7 +1,7 @@ /** @file=0D This file include all platform actions=0D =0D -Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights = reserved.
=0D +Copyright (c) 2021-2022, Hewlett Packard Enterprise Development LP. All ri= ghts reserved.
=0D Copyright (c) 2015, Intel Corporation. All rights reserved.
=0D =0D SPDX-License-Identifier: BSD-2-Clause-Patent=0D @@ -215,7 +215,7 @@ PlatformBootManagerBeforeConsole ( Signal console ready platform customized event;=0D Run diagnostics like memory testing;=0D Connect certain devices;=0D - Dispatch aditional option roms.=0D + Dispatch additional option roms.=0D **/=0D VOID=0D EFIAPI=0D diff --git a/Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei/Platform= .c b/Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei/Platform.c index 972a429fb9..c28b2ed373 100644 --- a/Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei/Platform.c +++ b/Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei/Platform.c @@ -296,7 +296,7 @@ BootModeInitialization ( {=0D EFI_STATUS Status;=0D =0D - if (CheckResumeFromS3 ()) {=0D + if (CheckResumeFromS3) {=0D DEBUG ((DEBUG_INFO, "This is wake from S3\n"));=0D } else {=0D DEBUG ((DEBUG_INFO, "This is normal boot\n"));=0D @@ -357,7 +357,7 @@ InitializePlatform ( MiscInitialization ();=0D Status =3D BuildCoreInformationHob ();=0D if (EFI_ERROR (Status)) {=0D - DEBUG ((DEBUG_ERROR, "Fail to build processor informstion HOB.\n"));=0D + DEBUG ((DEBUG_ERROR, "Fail to build processor information HOB.\n"));=0D ASSERT(FALSE);=0D }=0D return EFI_SUCCESS;=0D diff --git a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c b/Platform= /RISC-V/PlatformPkg/Universal/Sec/SecMain.c index 1fafed2799..7a79eeec2d 100644 --- a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c +++ b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c @@ -291,7 +291,7 @@ FindPeiCoreImageBase ( /**=0D Find and return Pei Core entry point.=0D =0D - It also find SEC and PEI Core file debug inforamtion. It will report the= m if=0D + It also find SEC and PEI Core file debug information. It will report the= m if=0D remote debug is enabled.=0D =0D @param[in] BootFirmwareVolumePtr The firmware volume pointer to searc= h=0D @@ -516,7 +516,7 @@ LaunchPeiCore ( @param[in] FuncArg1 Arg1 to pass to next phase entry point addres= s.=0D @param[in] NextAddr Entry point of next phase.=0D @param[in] NextMode Privilege mode of next phase.=0D - @param[in] NextVirt Next phase is in virtualiztion.=0D + @param[in] NextVirt Next phase is in virtualization.=0D =0D **/=0D VOID=0D @@ -600,7 +600,7 @@ Edk2PlatformHartIndex2Id ( }=0D =0D /**=0D - This function initilizes hart specific information and SBI.=0D + This function initializes hart specific information and SBI.=0D For the boot hart, it boots system through PEI core and initial SBI in t= he DXE IPL.=0D For others, it goes to initial SBI and halt.=0D =0D @@ -658,9 +658,9 @@ SecCoreStartUpWithStack( HartFirmwareContext->HartSwitchMode =3D RiscVOpenSbiHartSwitchMode;=0D =0D //=0D - // Hook platorm_ops with EDK2 one. Thus we can have interface=0D + // Hook platform_ops with EDK2 one. Thus we can have interface=0D // call out to OEM EDK2 platform code in M-mode before switching=0D - // to S-mode in opensbo init.=0D + // to S-mode in opensbi init.=0D //=0D ThisSbiPlatform =3D (struct sbi_platform *)sbi_platform_ptr(Scratch);=0D ThisSbiPlatform->platform_ops_addr =3D (unsigned long)&Edk2OpensbiPlatfo= rmOps;=0D diff --git a/Platform/RISC-V/PlatformPkg/Readme.md b/Platform/RISC-V/Platfo= rmPkg/Readme.md index 66fba15544..5a344a864a 100644 --- a/Platform/RISC-V/PlatformPkg/Readme.md +++ b/Platform/RISC-V/PlatformPkg/Readme.md @@ -26,16 +26,16 @@ differently from the default settings according to the = OEM platform design. to align with OpenSBI project. As mentioned earlier, ***RiscVOpensbiLib***= provides the RISC-V SBI=0D implementation and initialize the OpenSBI boot flow. SEC module is also li= nked with below libraries,=0D - edk2 [OpenSbiPlatformLib](#OpenSbiPlatformLib-library) library that prov= ides the generic RISC-V platform initialization code.=0D -- edk2 [RiscVSpecifialPlatformLib](#RiscVSpecifialPlatformLib-library) lib= rary which is provided by the RISC-V=0D +- edk2 [RiscVSpecialPlatformLib](#RiscVSpecialPlatformLib-library) library= which is provided by the RISC-V=0D platform vendor for the platform-specific initialization. The underlying i= mplementation of above two edk2 libraries=0D are from OpenSBI project. edk2 libraries are introduced as the wrapper lib= raries that separates and organizes OpenSBI core and platform code based on= edk2 framework and the the build mechanism for edk2 RISC-V platforms. ***R= iscVOpensbiLib*** library is located under [RISC-V ProcessorPkg](https://gi= thub.com/tianocore/edk2-platforms/tree/master/Silicon/RISC-V/ProcessorPkg) = while the platform code (e.g. OpenSbiPlatformLib) is located under [RISC-V = PlatformPkg](https://github.com/tianocore/edk2-platforms/tree/master/Platfo= rm/RISC-V/PlatformPkg).=0D -- edk2 [RiscVSpecifialPlatformLib](#riscvspecifialplatformlib) library is = provided by the platform vendor and located under edk2 RISC-V platform-spec= ific folder.=0D +- edk2 [RiscVSpecialPlatformLib](#riscvspecialplatformlib) library is prov= ided by the platform vendor and located under edk2 RISC-V platform-specific= folder.=0D =0D ##### OpenSbiPlatformLib Library=0D [Indicated as #2 in the figure](#risc-v-edk2-port-design-diagrams)=0D > ***OpenSbiPlatformLib*** provides the generic RISC-V platform initializa= tion code. Platform vendor can just utilize this library if they don't have= additional requirements on the platform initialization.=0D =0D -##### RiscVSpecifialPlatformLib Library=0D +##### RiscVSpecialPlatformLib Library=0D [Indicated as #3 in the figure](#risc-v-edk2-port-design-diagrams)=0D > The major use case of this library is to facilitate the interfaces for p= latform vendors to provide the special=0D platform initialization based on the generic platform initialization libra= ry.=0D @@ -57,7 +57,7 @@ privilege according to the PCD. =0D #### PEI Phase=0D SEC module hands off the boot process to PEI core in the privilege configu= red by ***PcdPeiCorePrivilegeMode*** PCD *(TODO, currently the privilege is= forced to S-mode)*. PEI and later phases are allowed to executed in M-mode= =0D -if the platform doesn't require Hypervisor-extended Supervisor mode (HS-mo= de) for the virtualization. RISC-V edk2 port provides its own instance ***P= eiCoreEntryPoint*** library [(indicated as #7 in the figure)](#risc-v-edk2-= port-design-diagrams) and linked with [PlatformSecPpiLib](#platformsecppili= b-library) in order to support the S-mode PEI phase. PEI core requires [Ris= cVFirmwareContextLib](#riscVfirmwarecontextlib-library) library to retrieve= the information of RISC-V HARTs and platform (e.g. FDT) configurations tha= t built up in SEC phase. ***PeiServicePointer*** is also maintained in the = ***RISC-V OpenSBI FirmwareContext*** structure and the pointer is retrieved= by [PeiServiceTablePointerOpensbi](#peiservicetablepointeropensbi-library)= library.=0D +if the platform doesn't require Hypervisor-extended Supervisor mode (HS-mo= de) for the virtualization. RISC-V edk2 port provides its own instance ***P= eiCoreEntryPoint*** library [(indicated as #7 in the figure)](#risc-v-edk2-= port-design-diagrams) and linked with [PlatformSecPpiLib](#platformsecppili= b-library) in order to support the S-mode PEI phase. PEI core requires [Ris= cVFirmwareContextLib](#riscvfirmwarecontextlib-library) library to retrieve= the information of RISC-V HARTs and platform (e.g. FDT) configurations tha= t built up in SEC phase. ***PeiServicePointer*** is also maintained in the = ***RISC-V OpenSBI FirmwareContext*** structure and the pointer is retrieved= by [PeiServiceTablePointerOpensbi](#peiservicetablepointeropensbi-library)= library.=0D =0D ##### PlatformSecPpiLib Library=0D [Indicated as #8 in the figure](#risc-v-edk2-port-design-diagrams)=0D @@ -178,7 +178,7 @@ The PCD settings regard to EFI Variable |PcdVariableFdSize| The EFI variable firmware device size|=0D |PcdVariableFdBlockSize| The block size of EFI variable firmware device|=0D |PcdPlatformFlashNvStorageVariableBase| EFI variable base address within f= irmware device|=0D -|PcdPlatformFlashNvStorageFtwWorkingBase| The base address of EFI variable= fault tolerance worksapce (FTW) within firmware device|=0D +|PcdPlatformFlashNvStorageFtwWorkingBase| The base address of EFI variable= fault tolerance workspace (FTW) within firmware device|=0D |PcdPlatformFlashNvStorageFtwSpareBase| The base address of EFI variable s= pare FTW within firmware device|=0D =0D ### RISC-V Physical Memory Protection (PMP) Region Settings=0D @@ -190,7 +190,7 @@ Below PCDs could be set in platform FDF file. |PcdRootFirmwareDomainSize| The size of root firmware domain|-|-|=0D |PcdFirmwareDomainBaseAddress| The starting address of firmware domain tha= t can be accessed and executed in S-mode|Full access|Readable and Executabl= e|=0D |PcdFirmwareDomainSize| The size of firmware domain|-|-|=0D -|PcdVariableFirmwareRegionBaseAddress| The starting address of EFI variabl= e region that can be accessed in S-mode|Full access|Readale and Writable|=0D +|PcdVariableFirmwareRegionBaseAddress| The starting address of EFI variabl= e region that can be accessed in S-mode|Full access|Readable and Writable|= =0D |PcdVariableFirmwareRegionSize| The size of EFI variable firmware region|-= |-|=0D =0D ### RISC-V Processor HART Settings=0D @@ -198,7 +198,7 @@ Below PCDs could be set in platform FDF file. | **PCD name** |**Usage**|=0D |--------------|---------|=0D |PcdHartCount| Number of RISC-V HARTs, the value is processor-implementati= on specific|=0D -|PcdBootHartId| The ID of RISC-V HART to execute main fimrware code and bo= ot system to OS|=0D +|PcdBootHartId| The ID of RISC-V HART to execute main firmware code and bo= ot system to OS|=0D |PcdBootableHartNumber|The bootable HART number, which is incorporate with= RISC-V OpenSBI platform hart_index2id value|=0D |PcdBootableHartIndexToId| if PcdBootableHartNumber =3D=3D 0, hart_index2i= d is built from Device Tree, otherwise this is an array of HART index to HA= RT ID|=0D =0D diff --git a/Platform/RISC-V/PlatformPkg/Universal/Sec/Riscv64/SecEntry.S b= /Platform/RISC-V/PlatformPkg/Universal/Sec/Riscv64/SecEntry.S index 0fc7817665..a96dd9474b 100644 --- a/Platform/RISC-V/PlatformPkg/Universal/Sec/Riscv64/SecEntry.S +++ b/Platform/RISC-V/PlatformPkg/Universal/Sec/Riscv64/SecEntry.S @@ -67,7 +67,7 @@ skip_fw_init: * DTB for this processor. We allocate the=0D * scratch buffer according to this number.=0D */=0D - la a4, _pysical_hart_count=0D + la a4, _physical_hart_count=0D sd s7, (a4)=0D =0D li s8, FixedPcdGet32 (PcdOpenSbiStackSize)=0D @@ -227,7 +227,7 @@ _start_warm: csrr a0, CSR_MHARTID=0D j _uninitialized_hart_wait=0D 4:=0D - la a5, _pysical_hart_count=0D + la a5, _physical_hart_count=0D ld s7, (a5)=0D /* Find the scratch space for this hart=0D *=0D @@ -294,7 +294,7 @@ _start_warm: .section .data, "aw"=0D _boot_hart_done:=0D RISCV_PTR 0=0D -_pysical_hart_count:=0D +_physical_hart_count:=0D RISCV_PTR 0=0D =0D .align 3=0D @@ -323,7 +323,7 @@ _hartid_to_scratch: lw s0, SBI_PLATFORM_HART_STACK_SIZE_OFFSET(s2)=0D #endif=0D =0D - la s1, _pysical_hart_count /* total HART count */=0D + la s1, _physical_hart_count /* total HART count */=0D ld s2, (s1)=0D mul s2, s2, s0=0D li s1, FixedPcdGet32 (PcdScratchRamBase)=0D --=20 2.31.1