From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mx0a-002e3701.pphosted.com (mx0a-002e3701.pphosted.com [148.163.147.86]) by mx.groups.io with SMTP id smtpd.web11.4517.1643036037542219462 for ; Mon, 24 Jan 2022 06:53:57 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@hpe.com header.s=pps0720 header.b=BWmNtGLH; spf=permerror, err=parse error for token &{10 18 %{ir}.%{v}.%{d}.spf.has.pphosted.com}: invalid domain name (domain: hpe.com, ip: 148.163.147.86, mailfrom: prvs=00231bd929=abner.chang@hpe.com) Received: from pps.filterd (m0134420.ppops.net [127.0.0.1]) by mx0b-002e3701.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 20ODISA7023608; Mon, 24 Jan 2022 14:53:54 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=hpe.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding; s=pps0720; bh=3QQ0U+Ibd7OipsSW345Hz+UCYVQwDdF91m4s6Dr1D5c=; b=BWmNtGLH/ByTk+Ea6ecpjlYHuHpqqFj9Cs6p0mo4tAAR7aP+Rk3xKfen1I2cmF63OzYn quQ5J3YN2PUWkMvsY500LGZYxE+rQ08pOk9wAMUgQ7d3e9lge82y1ZABM2uFsKi8rFow FVSSMNdW71sOTo0eaMESlJkQp8zMAUTnySK9PZy2H6DnG/yHOuR6rgDOHmyzFL5RA/Jd sC6Tqk/uISSL6f4An0pCIzv7IlidVbq44NGKduxyjGw+nqpw9Jxe+HHMpRy5NPIWLwRX mxwskipkCeTn7m2qC6/v43SyHkoS9Spoha8sgfwU5lLuoMFDCoSgxSa2rLi/yoCthsTU /A== Received: from g2t2352.austin.hpe.com (g2t2352.austin.hpe.com [15.233.44.25]) by mx0b-002e3701.pphosted.com (PPS) with ESMTPS id 3dspjfkywg-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 24 Jan 2022 14:53:54 +0000 Received: from g2t2360.austin.hpecorp.net (g2t2360.austin.hpecorp.net [16.196.225.135]) by g2t2352.austin.hpe.com (Postfix) with ESMTP id 3EBEEB0; Mon, 24 Jan 2022 14:53:53 +0000 (UTC) Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.229]) by g2t2360.austin.hpecorp.net (Postfix) with ESMTP id 4E43540; Mon, 24 Jan 2022 14:53:51 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com, Daniel Schaefer , Sunil V L , Ard Biesheuvel , Leif Lindholm , Sami Mujawar , Gerd Hoffmann Subject: [PATCH 2/2] ArmVirtPkg/BaseCachingPciExpressLib: Remove BaseCachingPciExpressLib Date: Mon, 24 Jan 2022 21:52:09 +0800 Message-Id: <20220124135209.8371-3-abner.chang@hpe.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20220124135209.8371-1-abner.chang@hpe.com> References: <20220124135209.8371-1-abner.chang@hpe.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: YPNNl-RqVWXADjuWoFKSwvf7cNjBMthQ X-Proofpoint-GUID: YPNNl-RqVWXADjuWoFKSwvf7cNjBMthQ X-HPE-SCL: -1 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.816,Hydra:6.0.425,FMLib:17.11.62.513 definitions=2022-01-24_08,2022-01-24_02,2021-12-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 suspectscore=0 phishscore=0 clxscore=1015 mlxlogscore=999 bulkscore=0 spamscore=0 impostorscore=0 mlxscore=0 lowpriorityscore=0 adultscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2201110000 definitions=main-2201240099 Content-Transfer-Encoding: quoted-printable Remove BaseCachingPciExpressLib library from ArmVirtPkg and use the one und= er OvmfPkg instead. BaseCachingPciExpressLib is cloned to under OvmfPkg, with this change the R= ISC-V Virt platform can leverage the same library. Signed-off-by: Abner Chang Cc: Daniel Schaefer Cc: Sunil V L Cc: Ard Biesheuvel Cc: Leif Lindholm Cc: Sami Mujawar Cc: Gerd Hoffmann --- ArmVirtPkg/ArmVirt.dsc.inc | 2 +- ArmVirtPkg/ArmVirtKvmTool.dsc | 6 +- .../BaseCachingPciExpressLib.inf | 43 - .../BaseCachingPciExpressLib/PciExpressLib.c | 1420 ----------------- 4 files changed, 4 insertions(+), 1467 deletions(-) delete mode 100644 ArmVirtPkg/Library/BaseCachingPciExpressLib/BaseCaching= PciExpressLib.inf delete mode 100644 ArmVirtPkg/Library/BaseCachingPciExpressLib/PciExpressL= ib.c diff --git a/ArmVirtPkg/ArmVirt.dsc.inc b/ArmVirtPkg/ArmVirt.dsc.inc index 5a1598d90c..4db8ad5a79 100644 --- a/ArmVirtPkg/ArmVirt.dsc.inc +++ b/ArmVirtPkg/ArmVirt.dsc.inc @@ -141,7 +141,7 @@ =0D # PCI Libraries=0D PciLib|MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf=0D - PciExpressLib|ArmVirtPkg/Library/BaseCachingPciExpressLib/BaseCachingPci= ExpressLib.inf=0D + PciExpressLib|OvmfPkg/Library/BaseCachingPciExpressLib/BaseCachingPciExp= ressLib.inf=0D PciCapLib|OvmfPkg/Library/BasePciCapLib/BasePciCapLib.inf=0D PciCapPciSegmentLib|OvmfPkg/Library/BasePciCapPciSegmentLib/BasePciCapPc= iSegmentLib.inf=0D PciCapPciIoLib|OvmfPkg/Library/UefiPciCapPciIoLib/UefiPciCapPciIoLib.inf= =0D diff --git a/ArmVirtPkg/ArmVirtKvmTool.dsc b/ArmVirtPkg/ArmVirtKvmTool.dsc index 9d23072d8f..4a54d13735 100644 --- a/ArmVirtPkg/ArmVirtKvmTool.dsc +++ b/ArmVirtPkg/ArmVirtKvmTool.dsc @@ -339,17 +339,17 @@ ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf {=0D =0D NULL|OvmfPkg/Fdt/FdtPciPcdProducerLib/FdtPciPcdProducerLib.inf=0D - NULL|ArmVirtPkg/Library/BaseCachingPciExpressLib/BaseCachingPciExpre= ssLib.inf=0D + NULL|OvmfPkg/Library/BaseCachingPciExpressLib/BaseCachingPciExpressL= ib.inf=0D }=0D MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf {=0D =0D NULL|OvmfPkg/Fdt/FdtPciPcdProducerLib/FdtPciPcdProducerLib.inf=0D - NULL|ArmVirtPkg/Library/BaseCachingPciExpressLib/BaseCachingPciExpre= ssLib.inf=0D + NULL|OvmfPkg/Library/BaseCachingPciExpressLib/BaseCachingPciExpressL= ib.inf=0D }=0D MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf {=0D =0D NULL|OvmfPkg/Fdt/FdtPciPcdProducerLib/FdtPciPcdProducerLib.inf=0D - NULL|ArmVirtPkg/Library/BaseCachingPciExpressLib/BaseCachingPciExpre= ssLib.inf=0D + NULL|OvmfPkg/Library/BaseCachingPciExpressLib/BaseCachingPciExpressL= ib.inf=0D }=0D OvmfPkg/VirtioPciDeviceDxe/VirtioPciDeviceDxe.inf=0D OvmfPkg/Virtio10Dxe/Virtio10.inf=0D diff --git a/ArmVirtPkg/Library/BaseCachingPciExpressLib/BaseCachingPciExpr= essLib.inf b/ArmVirtPkg/Library/BaseCachingPciExpressLib/BaseCachingPciExpr= essLib.inf deleted file mode 100644 index 33568f568f..0000000000 --- a/ArmVirtPkg/Library/BaseCachingPciExpressLib/BaseCachingPciExpressLib.= inf +++ /dev/null @@ -1,43 +0,0 @@ -## @file=0D -# Instance of PCI Express Library using the 256 MB PCI Express MMIO windo= w.=0D -#=0D -# PCI Express Library that uses the 256 MB PCI Express MMIO window to per= form=0D -# PCI Configuration cycles. Layers on top of an I/O Library instance.=0D -#=0D -# Copyright (c) 2007 - 2014, Intel Corporation. All rights reserved.
= =0D -#=0D -# SPDX-License-Identifier: BSD-2-Clause-Patent=0D -#=0D -#=0D -##=0D -=0D -[Defines]=0D - INF_VERSION =3D 0x00010005=0D - BASE_NAME =3D BaseCachingPciExpressLib=0D - FILE_GUID =3D 3f3ffd80-04dc-4a2b-9d25-ecca55c2e520= =0D - MODULE_TYPE =3D BASE=0D - VERSION_STRING =3D 1.0=0D - LIBRARY_CLASS =3D PciExpressLib|DXE_DRIVER UEFI_DRIVER = UEFI_APPLICATION=0D - CONSTRUCTOR =3D PciExpressLibInitialize=0D -=0D -#=0D -# VALID_ARCHITECTURES =3D ARM AARCH64=0D -#=0D -=0D -[Sources]=0D - PciExpressLib.c=0D -=0D -[Packages]=0D - ArmVirtPkg/ArmVirtPkg.dec=0D - MdePkg/MdePkg.dec=0D -=0D -[LibraryClasses]=0D - BaseLib=0D - PcdLib=0D - DebugLib=0D - IoLib=0D - PciPcdProducerLib=0D -=0D -[Pcd]=0D - gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## CONSUMES=0D -=0D diff --git a/ArmVirtPkg/Library/BaseCachingPciExpressLib/PciExpressLib.c b/= ArmVirtPkg/Library/BaseCachingPciExpressLib/PciExpressLib.c deleted file mode 100644 index 2474128697..0000000000 --- a/ArmVirtPkg/Library/BaseCachingPciExpressLib/PciExpressLib.c +++ /dev/null @@ -1,1420 +0,0 @@ -/** @file=0D - Functions in this library instance make use of MMIO functions in IoLib t= o=0D - access memory mapped PCI configuration space.=0D -=0D - All assertions for I/O operations are handled in MMIO functions in the I= oLib=0D - Library.=0D -=0D - Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.
=0D - SPDX-License-Identifier: BSD-2-Clause-Patent=0D -=0D -**/=0D -=0D -#include =0D -=0D -#include =0D -#include =0D -#include =0D -#include =0D -#include =0D -=0D -/**=0D - Assert the validity of a PCI address. A valid PCI address should contain= 1's=0D - only in the low 28 bits.=0D -=0D - @param A The address to validate.=0D -=0D -**/=0D -#define ASSERT_INVALID_PCI_ADDRESS(A) \=0D - ASSERT (((A) & ~0xfffffff) =3D=3D 0)=0D -=0D -/**=0D - Registers a PCI device so PCI configuration registers may be accessed af= ter=0D - SetVirtualAddressMap().=0D -=0D - Registers the PCI device specified by Address so all the PCI configurati= on=0D - registers associated with that PCI device may be accessed after SetVirtu= alAddressMap()=0D - is called.=0D -=0D - If Address > 0x0FFFFFFF, then ASSERT().=0D -=0D - @param Address The address that encodes the PCI Bus, Device, Function a= nd=0D - Register.=0D -=0D - @retval RETURN_SUCCESS The PCI device was registered for runti= me access.=0D - @retval RETURN_UNSUPPORTED An attempt was made to call this functi= on=0D - after ExitBootServices().=0D - @retval RETURN_UNSUPPORTED The resources required to access the PC= I device=0D - at runtime could not be mapped.=0D - @retval RETURN_OUT_OF_RESOURCES There are not enough resources availabl= e to=0D - complete the registration.=0D -=0D -**/=0D -RETURN_STATUS=0D -EFIAPI=0D -PciExpressRegisterForRuntimeAccess (=0D - IN UINTN Address=0D - )=0D -{=0D - ASSERT_INVALID_PCI_ADDRESS (Address);=0D - return RETURN_UNSUPPORTED;=0D -}=0D -=0D -STATIC UINT64 mPciExpressBaseAddress;=0D -=0D -RETURN_STATUS=0D -EFIAPI=0D -PciExpressLibInitialize (=0D - VOID=0D - )=0D -{=0D - mPciExpressBaseAddress =3D PcdGet64 (PcdPciExpressBaseAddress);=0D - return RETURN_SUCCESS;=0D -}=0D -=0D -/**=0D - Gets the base address of PCI Express.=0D -=0D - @return The base address of PCI Express.=0D -=0D -**/=0D -VOID *=0D -GetPciExpressBaseAddress (=0D - VOID=0D - )=0D -{=0D - return (VOID *)(UINTN)mPciExpressBaseAddress;=0D -}=0D -=0D -/**=0D - Reads an 8-bit PCI configuration register.=0D -=0D - Reads and returns the 8-bit PCI configuration register specified by Addr= ess.=0D - This function must guarantee that all PCI read and write operations are= =0D - serialized.=0D -=0D - If Address > 0x0FFFFFFF, then ASSERT().=0D -=0D - @param Address The address that encodes the PCI Bus, Device, Function a= nd=0D - Register.=0D -=0D - @return The read value from the PCI configuration register.=0D -=0D -**/=0D -UINT8=0D -EFIAPI=0D -PciExpressRead8 (=0D - IN UINTN Address=0D - )=0D -{=0D - ASSERT_INVALID_PCI_ADDRESS (Address);=0D - return MmioRead8 ((UINTN)GetPciExpressBaseAddress () + Address);=0D -}=0D -=0D -/**=0D - Writes an 8-bit PCI configuration register.=0D -=0D - Writes the 8-bit PCI configuration register specified by Address with th= e=0D - value specified by Value. Value is returned. This function must guarante= e=0D - that all PCI read and write operations are serialized.=0D -=0D - If Address > 0x0FFFFFFF, then ASSERT().=0D -=0D - @param Address The address that encodes the PCI Bus, Device, Function a= nd=0D - Register.=0D - @param Value The value to write.=0D -=0D - @return The value written to the PCI configuration register.=0D -=0D -**/=0D -UINT8=0D -EFIAPI=0D -PciExpressWrite8 (=0D - IN UINTN Address,=0D - IN UINT8 Value=0D - )=0D -{=0D - ASSERT_INVALID_PCI_ADDRESS (Address);=0D - return MmioWrite8 ((UINTN)GetPciExpressBaseAddress () + Address, Value);= =0D -}=0D -=0D -/**=0D - Performs a bitwise OR of an 8-bit PCI configuration register with=0D - an 8-bit value.=0D -=0D - Reads the 8-bit PCI configuration register specified by Address, perform= s a=0D - bitwise OR between the read result and the value specified by=0D - OrData, and writes the result to the 8-bit PCI configuration register=0D - specified by Address. The value written to the PCI configuration registe= r is=0D - returned. This function must guarantee that all PCI read and write opera= tions=0D - are serialized.=0D -=0D - If Address > 0x0FFFFFFF, then ASSERT().=0D -=0D - @param Address The address that encodes the PCI Bus, Device, Function a= nd=0D - Register.=0D - @param OrData The value to OR with the PCI configuration register.=0D -=0D - @return The value written back to the PCI configuration register.=0D -=0D -**/=0D -UINT8=0D -EFIAPI=0D -PciExpressOr8 (=0D - IN UINTN Address,=0D - IN UINT8 OrData=0D - )=0D -{=0D - ASSERT_INVALID_PCI_ADDRESS (Address);=0D - return MmioOr8 ((UINTN)GetPciExpressBaseAddress () + Address, OrData);=0D -}=0D -=0D -/**=0D - Performs a bitwise AND of an 8-bit PCI configuration register with an 8-= bit=0D - value.=0D -=0D - Reads the 8-bit PCI configuration register specified by Address, perform= s a=0D - bitwise AND between the read result and the value specified by AndData, = and=0D - writes the result to the 8-bit PCI configuration register specified by=0D - Address. The value written to the PCI configuration register is returned= .=0D - This function must guarantee that all PCI read and write operations are= =0D - serialized.=0D -=0D - If Address > 0x0FFFFFFF, then ASSERT().=0D -=0D - @param Address The address that encodes the PCI Bus, Device, Function a= nd=0D - Register.=0D - @param AndData The value to AND with the PCI configuration register.=0D -=0D - @return The value written back to the PCI configuration register.=0D -=0D -**/=0D -UINT8=0D -EFIAPI=0D -PciExpressAnd8 (=0D - IN UINTN Address,=0D - IN UINT8 AndData=0D - )=0D -{=0D - ASSERT_INVALID_PCI_ADDRESS (Address);=0D - return MmioAnd8 ((UINTN)GetPciExpressBaseAddress () + Address, AndData);= =0D -}=0D -=0D -/**=0D - Performs a bitwise AND of an 8-bit PCI configuration register with an 8-= bit=0D - value, followed a bitwise OR with another 8-bit value.=0D -=0D - Reads the 8-bit PCI configuration register specified by Address, perform= s a=0D - bitwise AND between the read result and the value specified by AndData,= =0D - performs a bitwise OR between the result of the AND operation and=0D - the value specified by OrData, and writes the result to the 8-bit PCI=0D - configuration register specified by Address. The value written to the PC= I=0D - configuration register is returned. This function must guarantee that al= l PCI=0D - read and write operations are serialized.=0D -=0D - If Address > 0x0FFFFFFF, then ASSERT().=0D -=0D - @param Address The address that encodes the PCI Bus, Device, Function a= nd=0D - Register.=0D - @param AndData The value to AND with the PCI configuration register.=0D - @param OrData The value to OR with the result of the AND operation.=0D -=0D - @return The value written back to the PCI configuration register.=0D -=0D -**/=0D -UINT8=0D -EFIAPI=0D -PciExpressAndThenOr8 (=0D - IN UINTN Address,=0D - IN UINT8 AndData,=0D - IN UINT8 OrData=0D - )=0D -{=0D - ASSERT_INVALID_PCI_ADDRESS (Address);=0D - return MmioAndThenOr8 (=0D - (UINTN)GetPciExpressBaseAddress () + Address,=0D - AndData,=0D - OrData=0D - );=0D -}=0D -=0D -/**=0D - Reads a bit field of a PCI configuration register.=0D -=0D - Reads the bit field in an 8-bit PCI configuration register. The bit fiel= d is=0D - specified by the StartBit and the EndBit. The value of the bit field is= =0D - returned.=0D -=0D - If Address > 0x0FFFFFFF, then ASSERT().=0D - If StartBit is greater than 7, then ASSERT().=0D - If EndBit is greater than 7, then ASSERT().=0D - If EndBit is less than StartBit, then ASSERT().=0D -=0D - @param Address The PCI configuration register to read.=0D - @param StartBit The ordinal of the least significant bit in the bit fi= eld.=0D - Range 0..7.=0D - @param EndBit The ordinal of the most significant bit in the bit fie= ld.=0D - Range 0..7.=0D -=0D - @return The value of the bit field read from the PCI configuration regis= ter.=0D -=0D -**/=0D -UINT8=0D -EFIAPI=0D -PciExpressBitFieldRead8 (=0D - IN UINTN Address,=0D - IN UINTN StartBit,=0D - IN UINTN EndBit=0D - )=0D -{=0D - ASSERT_INVALID_PCI_ADDRESS (Address);=0D - return MmioBitFieldRead8 (=0D - (UINTN)GetPciExpressBaseAddress () + Address,=0D - StartBit,=0D - EndBit=0D - );=0D -}=0D -=0D -/**=0D - Writes a bit field to a PCI configuration register.=0D -=0D - Writes Value to the bit field of the PCI configuration register. The bit= =0D - field is specified by the StartBit and the EndBit. All other bits in the= =0D - destination PCI configuration register are preserved. The new value of t= he=0D - 8-bit register is returned.=0D -=0D - If Address > 0x0FFFFFFF, then ASSERT().=0D - If StartBit is greater than 7, then ASSERT().=0D - If EndBit is greater than 7, then ASSERT().=0D - If EndBit is less than StartBit, then ASSERT().=0D - If Value is larger than the bitmask value range specified by StartBit an= d EndBit, then ASSERT().=0D -=0D - @param Address The PCI configuration register to write.=0D - @param StartBit The ordinal of the least significant bit in the bit fi= eld.=0D - Range 0..7.=0D - @param EndBit The ordinal of the most significant bit in the bit fie= ld.=0D - Range 0..7.=0D - @param Value The new value of the bit field.=0D -=0D - @return The value written back to the PCI configuration register.=0D -=0D -**/=0D -UINT8=0D -EFIAPI=0D -PciExpressBitFieldWrite8 (=0D - IN UINTN Address,=0D - IN UINTN StartBit,=0D - IN UINTN EndBit,=0D - IN UINT8 Value=0D - )=0D -{=0D - ASSERT_INVALID_PCI_ADDRESS (Address);=0D - return MmioBitFieldWrite8 (=0D - (UINTN)GetPciExpressBaseAddress () + Address,=0D - StartBit,=0D - EndBit,=0D - Value=0D - );=0D -}=0D -=0D -/**=0D - Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, = and=0D - writes the result back to the bit field in the 8-bit port.=0D -=0D - Reads the 8-bit PCI configuration register specified by Address, perform= s a=0D - bitwise OR between the read result and the value specified by=0D - OrData, and writes the result to the 8-bit PCI configuration register=0D - specified by Address. The value written to the PCI configuration registe= r is=0D - returned. This function must guarantee that all PCI read and write opera= tions=0D - are serialized. Extra left bits in OrData are stripped.=0D -=0D - If Address > 0x0FFFFFFF, then ASSERT().=0D - If StartBit is greater than 7, then ASSERT().=0D - If EndBit is greater than 7, then ASSERT().=0D - If EndBit is less than StartBit, then ASSERT().=0D - If OrData is larger than the bitmask value range specified by StartBit a= nd EndBit, then ASSERT().=0D -=0D - @param Address The PCI configuration register to write.=0D - @param StartBit The ordinal of the least significant bit in the bit fi= eld.=0D - Range 0..7.=0D - @param EndBit The ordinal of the most significant bit in the bit fie= ld.=0D - Range 0..7.=0D - @param OrData The value to OR with the PCI configuration register.=0D -=0D - @return The value written back to the PCI configuration register.=0D -=0D -**/=0D -UINT8=0D -EFIAPI=0D -PciExpressBitFieldOr8 (=0D - IN UINTN Address,=0D - IN UINTN StartBit,=0D - IN UINTN EndBit,=0D - IN UINT8 OrData=0D - )=0D -{=0D - ASSERT_INVALID_PCI_ADDRESS (Address);=0D - return MmioBitFieldOr8 (=0D - (UINTN)GetPciExpressBaseAddress () + Address,=0D - StartBit,=0D - EndBit,=0D - OrData=0D - );=0D -}=0D -=0D -/**=0D - Reads a bit field in an 8-bit PCI configuration register, performs a bit= wise=0D - AND, and writes the result back to the bit field in the 8-bit register.= =0D -=0D - Reads the 8-bit PCI configuration register specified by Address, perform= s a=0D - bitwise AND between the read result and the value specified by AndData, = and=0D - writes the result to the 8-bit PCI configuration register specified by=0D - Address. The value written to the PCI configuration register is returned= .=0D - This function must guarantee that all PCI read and write operations are= =0D - serialized. Extra left bits in AndData are stripped.=0D -=0D - If Address > 0x0FFFFFFF, then ASSERT().=0D - If StartBit is greater than 7, then ASSERT().=0D - If EndBit is greater than 7, then ASSERT().=0D - If EndBit is less than StartBit, then ASSERT().=0D - If AndData is larger than the bitmask value range specified by StartBit = and EndBit, then ASSERT().=0D -=0D - @param Address The PCI configuration register to write.=0D - @param StartBit The ordinal of the least significant bit in the bit fi= eld.=0D - Range 0..7.=0D - @param EndBit The ordinal of the most significant bit in the bit fie= ld.=0D - Range 0..7.=0D - @param AndData The value to AND with the PCI configuration register.= =0D -=0D - @return The value written back to the PCI configuration register.=0D -=0D -**/=0D -UINT8=0D -EFIAPI=0D -PciExpressBitFieldAnd8 (=0D - IN UINTN Address,=0D - IN UINTN StartBit,=0D - IN UINTN EndBit,=0D - IN UINT8 AndData=0D - )=0D -{=0D - ASSERT_INVALID_PCI_ADDRESS (Address);=0D - return MmioBitFieldAnd8 (=0D - (UINTN)GetPciExpressBaseAddress () + Address,=0D - StartBit,=0D - EndBit,=0D - AndData=0D - );=0D -}=0D -=0D -/**=0D - Reads a bit field in an 8-bit port, performs a bitwise AND followed by a= =0D - bitwise OR, and writes the result back to the bit field in the=0D - 8-bit port.=0D -=0D - Reads the 8-bit PCI configuration register specified by Address, perform= s a=0D - bitwise AND followed by a bitwise OR between the read result and=0D - the value specified by AndData, and writes the result to the 8-bit PCI=0D - configuration register specified by Address. The value written to the PC= I=0D - configuration register is returned. This function must guarantee that al= l PCI=0D - read and write operations are serialized. Extra left bits in both AndDat= a and=0D - OrData are stripped.=0D -=0D - If Address > 0x0FFFFFFF, then ASSERT().=0D - If StartBit is greater than 7, then ASSERT().=0D - If EndBit is greater than 7, then ASSERT().=0D - If EndBit is less than StartBit, then ASSERT().=0D - If AndData is larger than the bitmask value range specified by StartBit = and EndBit, then ASSERT().=0D - If OrData is larger than the bitmask value range specified by StartBit a= nd EndBit, then ASSERT().=0D -=0D - @param Address The PCI configuration register to write.=0D - @param StartBit The ordinal of the least significant bit in the bit fi= eld.=0D - Range 0..7.=0D - @param EndBit The ordinal of the most significant bit in the bit fie= ld.=0D - Range 0..7.=0D - @param AndData The value to AND with the PCI configuration register.= =0D - @param OrData The value to OR with the result of the AND operation.= =0D -=0D - @return The value written back to the PCI configuration register.=0D -=0D -**/=0D -UINT8=0D -EFIAPI=0D -PciExpressBitFieldAndThenOr8 (=0D - IN UINTN Address,=0D - IN UINTN StartBit,=0D - IN UINTN EndBit,=0D - IN UINT8 AndData,=0D - IN UINT8 OrData=0D - )=0D -{=0D - ASSERT_INVALID_PCI_ADDRESS (Address);=0D - return MmioBitFieldAndThenOr8 (=0D - (UINTN)GetPciExpressBaseAddress () + Address,=0D - StartBit,=0D - EndBit,=0D - AndData,=0D - OrData=0D - );=0D -}=0D -=0D -/**=0D - Reads a 16-bit PCI configuration register.=0D -=0D - Reads and returns the 16-bit PCI configuration register specified by Add= ress.=0D - This function must guarantee that all PCI read and write operations are= =0D - serialized.=0D -=0D - If Address > 0x0FFFFFFF, then ASSERT().=0D - If Address is not aligned on a 16-bit boundary, then ASSERT().=0D -=0D - @param Address The address that encodes the PCI Bus, Device, Function a= nd=0D - Register.=0D -=0D - @return The read value from the PCI configuration register.=0D -=0D -**/=0D -UINT16=0D -EFIAPI=0D -PciExpressRead16 (=0D - IN UINTN Address=0D - )=0D -{=0D - ASSERT_INVALID_PCI_ADDRESS (Address);=0D - return MmioRead16 ((UINTN)GetPciExpressBaseAddress () + Address);=0D -}=0D -=0D -/**=0D - Writes a 16-bit PCI configuration register.=0D -=0D - Writes the 16-bit PCI configuration register specified by Address with t= he=0D - value specified by Value. Value is returned. This function must guarante= e=0D - that all PCI read and write operations are serialized.=0D -=0D - If Address > 0x0FFFFFFF, then ASSERT().=0D - If Address is not aligned on a 16-bit boundary, then ASSERT().=0D -=0D - @param Address The address that encodes the PCI Bus, Device, Function a= nd=0D - Register.=0D - @param Value The value to write.=0D -=0D - @return The value written to the PCI configuration register.=0D -=0D -**/=0D -UINT16=0D -EFIAPI=0D -PciExpressWrite16 (=0D - IN UINTN Address,=0D - IN UINT16 Value=0D - )=0D -{=0D - ASSERT_INVALID_PCI_ADDRESS (Address);=0D - return MmioWrite16 ((UINTN)GetPciExpressBaseAddress () + Address, Value)= ;=0D -}=0D -=0D -/**=0D - Performs a bitwise OR of a 16-bit PCI configuration register with=0D - a 16-bit value.=0D -=0D - Reads the 16-bit PCI configuration register specified by Address, perfor= ms a=0D - bitwise OR between the read result and the value specified by=0D - OrData, and writes the result to the 16-bit PCI configuration register=0D - specified by Address. The value written to the PCI configuration registe= r is=0D - returned. This function must guarantee that all PCI read and write opera= tions=0D - are serialized.=0D -=0D - If Address > 0x0FFFFFFF, then ASSERT().=0D - If Address is not aligned on a 16-bit boundary, then ASSERT().=0D -=0D - @param Address The address that encodes the PCI Bus, Device, Function a= nd=0D - Register.=0D - @param OrData The value to OR with the PCI configuration register.=0D -=0D - @return The value written back to the PCI configuration register.=0D -=0D -**/=0D -UINT16=0D -EFIAPI=0D -PciExpressOr16 (=0D - IN UINTN Address,=0D - IN UINT16 OrData=0D - )=0D -{=0D - ASSERT_INVALID_PCI_ADDRESS (Address);=0D - return MmioOr16 ((UINTN)GetPciExpressBaseAddress () + Address, OrData);= =0D -}=0D -=0D -/**=0D - Performs a bitwise AND of a 16-bit PCI configuration register with a 16-= bit=0D - value.=0D -=0D - Reads the 16-bit PCI configuration register specified by Address, perfor= ms a=0D - bitwise AND between the read result and the value specified by AndData, = and=0D - writes the result to the 16-bit PCI configuration register specified by= =0D - Address. The value written to the PCI configuration register is returned= .=0D - This function must guarantee that all PCI read and write operations are= =0D - serialized.=0D -=0D - If Address > 0x0FFFFFFF, then ASSERT().=0D - If Address is not aligned on a 16-bit boundary, then ASSERT().=0D -=0D - @param Address The address that encodes the PCI Bus, Device, Function a= nd=0D - Register.=0D - @param AndData The value to AND with the PCI configuration register.=0D -=0D - @return The value written back to the PCI configuration register.=0D -=0D -**/=0D -UINT16=0D -EFIAPI=0D -PciExpressAnd16 (=0D - IN UINTN Address,=0D - IN UINT16 AndData=0D - )=0D -{=0D - ASSERT_INVALID_PCI_ADDRESS (Address);=0D - return MmioAnd16 ((UINTN)GetPciExpressBaseAddress () + Address, AndData)= ;=0D -}=0D -=0D -/**=0D - Performs a bitwise AND of a 16-bit PCI configuration register with a 16-= bit=0D - value, followed a bitwise OR with another 16-bit value.=0D -=0D - Reads the 16-bit PCI configuration register specified by Address, perfor= ms a=0D - bitwise AND between the read result and the value specified by AndData,= =0D - performs a bitwise OR between the result of the AND operation and=0D - the value specified by OrData, and writes the result to the 16-bit PCI=0D - configuration register specified by Address. The value written to the PC= I=0D - configuration register is returned. This function must guarantee that al= l PCI=0D - read and write operations are serialized.=0D -=0D - If Address > 0x0FFFFFFF, then ASSERT().=0D - If Address is not aligned on a 16-bit boundary, then ASSERT().=0D -=0D - @param Address The address that encodes the PCI Bus, Device, Function a= nd=0D - Register.=0D - @param AndData The value to AND with the PCI configuration register.=0D - @param OrData The value to OR with the result of the AND operation.=0D -=0D - @return The value written back to the PCI configuration register.=0D -=0D -**/=0D -UINT16=0D -EFIAPI=0D -PciExpressAndThenOr16 (=0D - IN UINTN Address,=0D - IN UINT16 AndData,=0D - IN UINT16 OrData=0D - )=0D -{=0D - ASSERT_INVALID_PCI_ADDRESS (Address);=0D - return MmioAndThenOr16 (=0D - (UINTN)GetPciExpressBaseAddress () + Address,=0D - AndData,=0D - OrData=0D - );=0D -}=0D -=0D -/**=0D - Reads a bit field of a PCI configuration register.=0D -=0D - Reads the bit field in a 16-bit PCI configuration register. The bit fiel= d is=0D - specified by the StartBit and the EndBit. The value of the bit field is= =0D - returned.=0D -=0D - If Address > 0x0FFFFFFF, then ASSERT().=0D - If Address is not aligned on a 16-bit boundary, then ASSERT().=0D - If StartBit is greater than 15, then ASSERT().=0D - If EndBit is greater than 15, then ASSERT().=0D - If EndBit is less than StartBit, then ASSERT().=0D -=0D - @param Address The PCI configuration register to read.=0D - @param StartBit The ordinal of the least significant bit in the bit fi= eld.=0D - Range 0..15.=0D - @param EndBit The ordinal of the most significant bit in the bit fie= ld.=0D - Range 0..15.=0D -=0D - @return The value of the bit field read from the PCI configuration regis= ter.=0D -=0D -**/=0D -UINT16=0D -EFIAPI=0D -PciExpressBitFieldRead16 (=0D - IN UINTN Address,=0D - IN UINTN StartBit,=0D - IN UINTN EndBit=0D - )=0D -{=0D - ASSERT_INVALID_PCI_ADDRESS (Address);=0D - return MmioBitFieldRead16 (=0D - (UINTN)GetPciExpressBaseAddress () + Address,=0D - StartBit,=0D - EndBit=0D - );=0D -}=0D -=0D -/**=0D - Writes a bit field to a PCI configuration register.=0D -=0D - Writes Value to the bit field of the PCI configuration register. The bit= =0D - field is specified by the StartBit and the EndBit. All other bits in the= =0D - destination PCI configuration register are preserved. The new value of t= he=0D - 16-bit register is returned.=0D -=0D - If Address > 0x0FFFFFFF, then ASSERT().=0D - If Address is not aligned on a 16-bit boundary, then ASSERT().=0D - If StartBit is greater than 15, then ASSERT().=0D - If EndBit is greater than 15, then ASSERT().=0D - If EndBit is less than StartBit, then ASSERT().=0D - If Value is larger than the bitmask value range specified by StartBit an= d EndBit, then ASSERT().=0D -=0D - @param Address The PCI configuration register to write.=0D - @param StartBit The ordinal of the least significant bit in the bit fi= eld.=0D - Range 0..15.=0D - @param EndBit The ordinal of the most significant bit in the bit fie= ld.=0D - Range 0..15.=0D - @param Value The new value of the bit field.=0D -=0D - @return The value written back to the PCI configuration register.=0D -=0D -**/=0D -UINT16=0D -EFIAPI=0D -PciExpressBitFieldWrite16 (=0D - IN UINTN Address,=0D - IN UINTN StartBit,=0D - IN UINTN EndBit,=0D - IN UINT16 Value=0D - )=0D -{=0D - ASSERT_INVALID_PCI_ADDRESS (Address);=0D - return MmioBitFieldWrite16 (=0D - (UINTN)GetPciExpressBaseAddress () + Address,=0D - StartBit,=0D - EndBit,=0D - Value=0D - );=0D -}=0D -=0D -/**=0D - Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, = and=0D - writes the result back to the bit field in the 16-bit port.=0D -=0D - Reads the 16-bit PCI configuration register specified by Address, perfor= ms a=0D - bitwise OR between the read result and the value specified by=0D - OrData, and writes the result to the 16-bit PCI configuration register=0D - specified by Address. The value written to the PCI configuration registe= r is=0D - returned. This function must guarantee that all PCI read and write opera= tions=0D - are serialized. Extra left bits in OrData are stripped.=0D -=0D - If Address > 0x0FFFFFFF, then ASSERT().=0D - If Address is not aligned on a 16-bit boundary, then ASSERT().=0D - If StartBit is greater than 15, then ASSERT().=0D - If EndBit is greater than 15, then ASSERT().=0D - If EndBit is less than StartBit, then ASSERT().=0D - If OrData is larger than the bitmask value range specified by StartBit a= nd EndBit, then ASSERT().=0D -=0D - @param Address The PCI configuration register to write.=0D - @param StartBit The ordinal of the least significant bit in the bit fi= eld.=0D - Range 0..15.=0D - @param EndBit The ordinal of the most significant bit in the bit fie= ld.=0D - Range 0..15.=0D - @param OrData The value to OR with the PCI configuration register.=0D -=0D - @return The value written back to the PCI configuration register.=0D -=0D -**/=0D -UINT16=0D -EFIAPI=0D -PciExpressBitFieldOr16 (=0D - IN UINTN Address,=0D - IN UINTN StartBit,=0D - IN UINTN EndBit,=0D - IN UINT16 OrData=0D - )=0D -{=0D - ASSERT_INVALID_PCI_ADDRESS (Address);=0D - return MmioBitFieldOr16 (=0D - (UINTN)GetPciExpressBaseAddress () + Address,=0D - StartBit,=0D - EndBit,=0D - OrData=0D - );=0D -}=0D -=0D -/**=0D - Reads a bit field in a 16-bit PCI configuration register, performs a bit= wise=0D - AND, and writes the result back to the bit field in the 16-bit register.= =0D -=0D - Reads the 16-bit PCI configuration register specified by Address, perfor= ms a=0D - bitwise AND between the read result and the value specified by AndData, = and=0D - writes the result to the 16-bit PCI configuration register specified by= =0D - Address. The value written to the PCI configuration register is returned= .=0D - This function must guarantee that all PCI read and write operations are= =0D - serialized. Extra left bits in AndData are stripped.=0D -=0D - If Address > 0x0FFFFFFF, then ASSERT().=0D - If Address is not aligned on a 16-bit boundary, then ASSERT().=0D - If StartBit is greater than 15, then ASSERT().=0D - If EndBit is greater than 15, then ASSERT().=0D - If EndBit is less than StartBit, then ASSERT().=0D - If AndData is larger than the bitmask value range specified by StartBit = and EndBit, then ASSERT().=0D -=0D - @param Address The PCI configuration register to write.=0D - @param StartBit The ordinal of the least significant bit in the bit fi= eld.=0D - Range 0..15.=0D - @param EndBit The ordinal of the most significant bit in the bit fie= ld.=0D - Range 0..15.=0D - @param AndData The value to AND with the PCI configuration register.= =0D -=0D - @return The value written back to the PCI configuration register.=0D -=0D -**/=0D -UINT16=0D -EFIAPI=0D -PciExpressBitFieldAnd16 (=0D - IN UINTN Address,=0D - IN UINTN StartBit,=0D - IN UINTN EndBit,=0D - IN UINT16 AndData=0D - )=0D -{=0D - ASSERT_INVALID_PCI_ADDRESS (Address);=0D - return MmioBitFieldAnd16 (=0D - (UINTN)GetPciExpressBaseAddress () + Address,=0D - StartBit,=0D - EndBit,=0D - AndData=0D - );=0D -}=0D -=0D -/**=0D - Reads a bit field in a 16-bit port, performs a bitwise AND followed by a= =0D - bitwise OR, and writes the result back to the bit field in the=0D - 16-bit port.=0D -=0D - Reads the 16-bit PCI configuration register specified by Address, perfor= ms a=0D - bitwise AND followed by a bitwise OR between the read result and=0D - the value specified by AndData, and writes the result to the 16-bit PCI= =0D - configuration register specified by Address. The value written to the PC= I=0D - configuration register is returned. This function must guarantee that al= l PCI=0D - read and write operations are serialized. Extra left bits in both AndDat= a and=0D - OrData are stripped.=0D -=0D - If Address > 0x0FFFFFFF, then ASSERT().=0D - If Address is not aligned on a 16-bit boundary, then ASSERT().=0D - If StartBit is greater than 15, then ASSERT().=0D - If EndBit is greater than 15, then ASSERT().=0D - If EndBit is less than StartBit, then ASSERT().=0D - If AndData is larger than the bitmask value range specified by StartBit = and EndBit, then ASSERT().=0D - If OrData is larger than the bitmask value range specified by StartBit a= nd EndBit, then ASSERT().=0D -=0D - @param Address The PCI configuration register to write.=0D - @param StartBit The ordinal of the least significant bit in the bit fi= eld.=0D - Range 0..15.=0D - @param EndBit The ordinal of the most significant bit in the bit fie= ld.=0D - Range 0..15.=0D - @param AndData The value to AND with the PCI configuration register.= =0D - @param OrData The value to OR with the result of the AND operation.= =0D -=0D - @return The value written back to the PCI configuration register.=0D -=0D -**/=0D -UINT16=0D -EFIAPI=0D -PciExpressBitFieldAndThenOr16 (=0D - IN UINTN Address,=0D - IN UINTN StartBit,=0D - IN UINTN EndBit,=0D - IN UINT16 AndData,=0D - IN UINT16 OrData=0D - )=0D -{=0D - ASSERT_INVALID_PCI_ADDRESS (Address);=0D - return MmioBitFieldAndThenOr16 (=0D - (UINTN)GetPciExpressBaseAddress () + Address,=0D - StartBit,=0D - EndBit,=0D - AndData,=0D - OrData=0D - );=0D -}=0D -=0D -/**=0D - Reads a 32-bit PCI configuration register.=0D -=0D - Reads and returns the 32-bit PCI configuration register specified by Add= ress.=0D - This function must guarantee that all PCI read and write operations are= =0D - serialized.=0D -=0D - If Address > 0x0FFFFFFF, then ASSERT().=0D - If Address is not aligned on a 32-bit boundary, then ASSERT().=0D -=0D - @param Address The address that encodes the PCI Bus, Device, Function a= nd=0D - Register.=0D -=0D - @return The read value from the PCI configuration register.=0D -=0D -**/=0D -UINT32=0D -EFIAPI=0D -PciExpressRead32 (=0D - IN UINTN Address=0D - )=0D -{=0D - ASSERT_INVALID_PCI_ADDRESS (Address);=0D - return MmioRead32 ((UINTN)GetPciExpressBaseAddress () + Address);=0D -}=0D -=0D -/**=0D - Writes a 32-bit PCI configuration register.=0D -=0D - Writes the 32-bit PCI configuration register specified by Address with t= he=0D - value specified by Value. Value is returned. This function must guarante= e=0D - that all PCI read and write operations are serialized.=0D -=0D - If Address > 0x0FFFFFFF, then ASSERT().=0D - If Address is not aligned on a 32-bit boundary, then ASSERT().=0D -=0D - @param Address The address that encodes the PCI Bus, Device, Function a= nd=0D - Register.=0D - @param Value The value to write.=0D -=0D - @return The value written to the PCI configuration register.=0D -=0D -**/=0D -UINT32=0D -EFIAPI=0D -PciExpressWrite32 (=0D - IN UINTN Address,=0D - IN UINT32 Value=0D - )=0D -{=0D - ASSERT_INVALID_PCI_ADDRESS (Address);=0D - return MmioWrite32 ((UINTN)GetPciExpressBaseAddress () + Address, Value)= ;=0D -}=0D -=0D -/**=0D - Performs a bitwise OR of a 32-bit PCI configuration register with=0D - a 32-bit value.=0D -=0D - Reads the 32-bit PCI configuration register specified by Address, perfor= ms a=0D - bitwise OR between the read result and the value specified by=0D - OrData, and writes the result to the 32-bit PCI configuration register=0D - specified by Address. The value written to the PCI configuration registe= r is=0D - returned. This function must guarantee that all PCI read and write opera= tions=0D - are serialized.=0D -=0D - If Address > 0x0FFFFFFF, then ASSERT().=0D - If Address is not aligned on a 32-bit boundary, then ASSERT().=0D -=0D - @param Address The address that encodes the PCI Bus, Device, Function a= nd=0D - Register.=0D - @param OrData The value to OR with the PCI configuration register.=0D -=0D - @return The value written back to the PCI configuration register.=0D -=0D -**/=0D -UINT32=0D -EFIAPI=0D -PciExpressOr32 (=0D - IN UINTN Address,=0D - IN UINT32 OrData=0D - )=0D -{=0D - ASSERT_INVALID_PCI_ADDRESS (Address);=0D - return MmioOr32 ((UINTN)GetPciExpressBaseAddress () + Address, OrData);= =0D -}=0D -=0D -/**=0D - Performs a bitwise AND of a 32-bit PCI configuration register with a 32-= bit=0D - value.=0D -=0D - Reads the 32-bit PCI configuration register specified by Address, perfor= ms a=0D - bitwise AND between the read result and the value specified by AndData, = and=0D - writes the result to the 32-bit PCI configuration register specified by= =0D - Address. The value written to the PCI configuration register is returned= .=0D - This function must guarantee that all PCI read and write operations are= =0D - serialized.=0D -=0D - If Address > 0x0FFFFFFF, then ASSERT().=0D - If Address is not aligned on a 32-bit boundary, then ASSERT().=0D -=0D - @param Address The address that encodes the PCI Bus, Device, Function a= nd=0D - Register.=0D - @param AndData The value to AND with the PCI configuration register.=0D -=0D - @return The value written back to the PCI configuration register.=0D -=0D -**/=0D -UINT32=0D -EFIAPI=0D -PciExpressAnd32 (=0D - IN UINTN Address,=0D - IN UINT32 AndData=0D - )=0D -{=0D - ASSERT_INVALID_PCI_ADDRESS (Address);=0D - return MmioAnd32 ((UINTN)GetPciExpressBaseAddress () + Address, AndData)= ;=0D -}=0D -=0D -/**=0D - Performs a bitwise AND of a 32-bit PCI configuration register with a 32-= bit=0D - value, followed a bitwise OR with another 32-bit value.=0D -=0D - Reads the 32-bit PCI configuration register specified by Address, perfor= ms a=0D - bitwise AND between the read result and the value specified by AndData,= =0D - performs a bitwise OR between the result of the AND operation and=0D - the value specified by OrData, and writes the result to the 32-bit PCI=0D - configuration register specified by Address. The value written to the PC= I=0D - configuration register is returned. This function must guarantee that al= l PCI=0D - read and write operations are serialized.=0D -=0D - If Address > 0x0FFFFFFF, then ASSERT().=0D - If Address is not aligned on a 32-bit boundary, then ASSERT().=0D -=0D - @param Address The address that encodes the PCI Bus, Device, Function a= nd=0D - Register.=0D - @param AndData The value to AND with the PCI configuration register.=0D - @param OrData The value to OR with the result of the AND operation.=0D -=0D - @return The value written back to the PCI configuration register.=0D -=0D -**/=0D -UINT32=0D -EFIAPI=0D -PciExpressAndThenOr32 (=0D - IN UINTN Address,=0D - IN UINT32 AndData,=0D - IN UINT32 OrData=0D - )=0D -{=0D - ASSERT_INVALID_PCI_ADDRESS (Address);=0D - return MmioAndThenOr32 (=0D - (UINTN)GetPciExpressBaseAddress () + Address,=0D - AndData,=0D - OrData=0D - );=0D -}=0D -=0D -/**=0D - Reads a bit field of a PCI configuration register.=0D -=0D - Reads the bit field in a 32-bit PCI configuration register. The bit fiel= d is=0D - specified by the StartBit and the EndBit. The value of the bit field is= =0D - returned.=0D -=0D - If Address > 0x0FFFFFFF, then ASSERT().=0D - If Address is not aligned on a 32-bit boundary, then ASSERT().=0D - If StartBit is greater than 31, then ASSERT().=0D - If EndBit is greater than 31, then ASSERT().=0D - If EndBit is less than StartBit, then ASSERT().=0D -=0D - @param Address The PCI configuration register to read.=0D - @param StartBit The ordinal of the least significant bit in the bit fi= eld.=0D - Range 0..31.=0D - @param EndBit The ordinal of the most significant bit in the bit fie= ld.=0D - Range 0..31.=0D -=0D - @return The value of the bit field read from the PCI configuration regis= ter.=0D -=0D -**/=0D -UINT32=0D -EFIAPI=0D -PciExpressBitFieldRead32 (=0D - IN UINTN Address,=0D - IN UINTN StartBit,=0D - IN UINTN EndBit=0D - )=0D -{=0D - ASSERT_INVALID_PCI_ADDRESS (Address);=0D - return MmioBitFieldRead32 (=0D - (UINTN)GetPciExpressBaseAddress () + Address,=0D - StartBit,=0D - EndBit=0D - );=0D -}=0D -=0D -/**=0D - Writes a bit field to a PCI configuration register.=0D -=0D - Writes Value to the bit field of the PCI configuration register. The bit= =0D - field is specified by the StartBit and the EndBit. All other bits in the= =0D - destination PCI configuration register are preserved. The new value of t= he=0D - 32-bit register is returned.=0D -=0D - If Address > 0x0FFFFFFF, then ASSERT().=0D - If Address is not aligned on a 32-bit boundary, then ASSERT().=0D - If StartBit is greater than 31, then ASSERT().=0D - If EndBit is greater than 31, then ASSERT().=0D - If EndBit is less than StartBit, then ASSERT().=0D - If Value is larger than the bitmask value range specified by StartBit an= d EndBit, then ASSERT().=0D -=0D - @param Address The PCI configuration register to write.=0D - @param StartBit The ordinal of the least significant bit in the bit fi= eld.=0D - Range 0..31.=0D - @param EndBit The ordinal of the most significant bit in the bit fie= ld.=0D - Range 0..31.=0D - @param Value The new value of the bit field.=0D -=0D - @return The value written back to the PCI configuration register.=0D -=0D -**/=0D -UINT32=0D -EFIAPI=0D -PciExpressBitFieldWrite32 (=0D - IN UINTN Address,=0D - IN UINTN StartBit,=0D - IN UINTN EndBit,=0D - IN UINT32 Value=0D - )=0D -{=0D - ASSERT_INVALID_PCI_ADDRESS (Address);=0D - return MmioBitFieldWrite32 (=0D - (UINTN)GetPciExpressBaseAddress () + Address,=0D - StartBit,=0D - EndBit,=0D - Value=0D - );=0D -}=0D -=0D -/**=0D - Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, = and=0D - writes the result back to the bit field in the 32-bit port.=0D -=0D - Reads the 32-bit PCI configuration register specified by Address, perfor= ms a=0D - bitwise OR between the read result and the value specified by=0D - OrData, and writes the result to the 32-bit PCI configuration register=0D - specified by Address. The value written to the PCI configuration registe= r is=0D - returned. This function must guarantee that all PCI read and write opera= tions=0D - are serialized. Extra left bits in OrData are stripped.=0D -=0D - If Address > 0x0FFFFFFF, then ASSERT().=0D - If Address is not aligned on a 32-bit boundary, then ASSERT().=0D - If StartBit is greater than 31, then ASSERT().=0D - If EndBit is greater than 31, then ASSERT().=0D - If EndBit is less than StartBit, then ASSERT().=0D - If OrData is larger than the bitmask value range specified by StartBit a= nd EndBit, then ASSERT().=0D -=0D - @param Address The PCI configuration register to write.=0D - @param StartBit The ordinal of the least significant bit in the bit fi= eld.=0D - Range 0..31.=0D - @param EndBit The ordinal of the most significant bit in the bit fie= ld.=0D - Range 0..31.=0D - @param OrData The value to OR with the PCI configuration register.=0D -=0D - @return The value written back to the PCI configuration register.=0D -=0D -**/=0D -UINT32=0D -EFIAPI=0D -PciExpressBitFieldOr32 (=0D - IN UINTN Address,=0D - IN UINTN StartBit,=0D - IN UINTN EndBit,=0D - IN UINT32 OrData=0D - )=0D -{=0D - ASSERT_INVALID_PCI_ADDRESS (Address);=0D - return MmioBitFieldOr32 (=0D - (UINTN)GetPciExpressBaseAddress () + Address,=0D - StartBit,=0D - EndBit,=0D - OrData=0D - );=0D -}=0D -=0D -/**=0D - Reads a bit field in a 32-bit PCI configuration register, performs a bit= wise=0D - AND, and writes the result back to the bit field in the 32-bit register.= =0D -=0D - Reads the 32-bit PCI configuration register specified by Address, perfor= ms a=0D - bitwise AND between the read result and the value specified by AndData, = and=0D - writes the result to the 32-bit PCI configuration register specified by= =0D - Address. The value written to the PCI configuration register is returned= .=0D - This function must guarantee that all PCI read and write operations are= =0D - serialized. Extra left bits in AndData are stripped.=0D -=0D - If Address > 0x0FFFFFFF, then ASSERT().=0D - If Address is not aligned on a 32-bit boundary, then ASSERT().=0D - If StartBit is greater than 31, then ASSERT().=0D - If EndBit is greater than 31, then ASSERT().=0D - If EndBit is less than StartBit, then ASSERT().=0D - If AndData is larger than the bitmask value range specified by StartBit = and EndBit, then ASSERT().=0D -=0D - @param Address The PCI configuration register to write.=0D - @param StartBit The ordinal of the least significant bit in the bit fi= eld.=0D - Range 0..31.=0D - @param EndBit The ordinal of the most significant bit in the bit fie= ld.=0D - Range 0..31.=0D - @param AndData The value to AND with the PCI configuration register.= =0D -=0D - @return The value written back to the PCI configuration register.=0D -=0D -**/=0D -UINT32=0D -EFIAPI=0D -PciExpressBitFieldAnd32 (=0D - IN UINTN Address,=0D - IN UINTN StartBit,=0D - IN UINTN EndBit,=0D - IN UINT32 AndData=0D - )=0D -{=0D - ASSERT_INVALID_PCI_ADDRESS (Address);=0D - return MmioBitFieldAnd32 (=0D - (UINTN)GetPciExpressBaseAddress () + Address,=0D - StartBit,=0D - EndBit,=0D - AndData=0D - );=0D -}=0D -=0D -/**=0D - Reads a bit field in a 32-bit port, performs a bitwise AND followed by a= =0D - bitwise OR, and writes the result back to the bit field in the=0D - 32-bit port.=0D -=0D - Reads the 32-bit PCI configuration register specified by Address, perfor= ms a=0D - bitwise AND followed by a bitwise OR between the read result and=0D - the value specified by AndData, and writes the result to the 32-bit PCI= =0D - configuration register specified by Address. The value written to the PC= I=0D - configuration register is returned. This function must guarantee that al= l PCI=0D - read and write operations are serialized. Extra left bits in both AndDat= a and=0D - OrData are stripped.=0D -=0D - If Address > 0x0FFFFFFF, then ASSERT().=0D - If Address is not aligned on a 32-bit boundary, then ASSERT().=0D - If StartBit is greater than 31, then ASSERT().=0D - If EndBit is greater than 31, then ASSERT().=0D - If EndBit is less than StartBit, then ASSERT().=0D - If AndData is larger than the bitmask value range specified by StartBit = and EndBit, then ASSERT().=0D - If OrData is larger than the bitmask value range specified by StartBit a= nd EndBit, then ASSERT().=0D -=0D - @param Address The PCI configuration register to write.=0D - @param StartBit The ordinal of the least significant bit in the bit fi= eld.=0D - Range 0..31.=0D - @param EndBit The ordinal of the most significant bit in the bit fie= ld.=0D - Range 0..31.=0D - @param AndData The value to AND with the PCI configuration register.= =0D - @param OrData The value to OR with the result of the AND operation.= =0D -=0D - @return The value written back to the PCI configuration register.=0D -=0D -**/=0D -UINT32=0D -EFIAPI=0D -PciExpressBitFieldAndThenOr32 (=0D - IN UINTN Address,=0D - IN UINTN StartBit,=0D - IN UINTN EndBit,=0D - IN UINT32 AndData,=0D - IN UINT32 OrData=0D - )=0D -{=0D - ASSERT_INVALID_PCI_ADDRESS (Address);=0D - return MmioBitFieldAndThenOr32 (=0D - (UINTN)GetPciExpressBaseAddress () + Address,=0D - StartBit,=0D - EndBit,=0D - AndData,=0D - OrData=0D - );=0D -}=0D -=0D -/**=0D - Reads a range of PCI configuration registers into a caller supplied buff= er.=0D -=0D - Reads the range of PCI configuration registers specified by StartAddress= and=0D - Size into the buffer specified by Buffer. This function only allows the = PCI=0D - configuration registers from a single PCI function to be read. Size is=0D - returned. When possible 32-bit PCI configuration read cycles are used to= read=0D - from StartAddress to StartAddress + Size. Due to alignment restrictions,= 8-bit=0D - and 16-bit PCI configuration read cycles may be used at the beginning an= d the=0D - end of the range.=0D -=0D - If StartAddress > 0x0FFFFFFF, then ASSERT().=0D - If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().=0D - If Size > 0 and Buffer is NULL, then ASSERT().=0D -=0D - @param StartAddress The starting address that encodes the PCI Bus, Dev= ice,=0D - Function and Register.=0D - @param Size The size in bytes of the transfer.=0D - @param Buffer The pointer to a buffer receiving the data read.=0D -=0D - @return Size read data from StartAddress.=0D -=0D -**/=0D -UINTN=0D -EFIAPI=0D -PciExpressReadBuffer (=0D - IN UINTN StartAddress,=0D - IN UINTN Size,=0D - OUT VOID *Buffer=0D - )=0D -{=0D - UINTN ReturnValue;=0D -=0D - ASSERT_INVALID_PCI_ADDRESS (StartAddress);=0D - ASSERT (((StartAddress & 0xFFF) + Size) <=3D 0x1000);=0D -=0D - if (Size =3D=3D 0) {=0D - return Size;=0D - }=0D -=0D - ASSERT (Buffer !=3D NULL);=0D -=0D - //=0D - // Save Size for return=0D - //=0D - ReturnValue =3D Size;=0D -=0D - if ((StartAddress & 1) !=3D 0) {=0D - //=0D - // Read a byte if StartAddress is byte aligned=0D - //=0D - *(volatile UINT8 *)Buffer =3D PciExpressRead8 (StartAddress);=0D - StartAddress +=3D sizeof (UINT8);=0D - Size -=3D sizeof (UINT8);=0D - Buffer =3D (UINT8 *)Buffer + 1;=0D - }=0D -=0D - if ((Size >=3D sizeof (UINT16)) && ((StartAddress & 2) !=3D 0)) {=0D - //=0D - // Read a word if StartAddress is word aligned=0D - //=0D - WriteUnaligned16 ((UINT16 *)Buffer, (UINT16)PciExpressRead16 (StartAdd= ress));=0D -=0D - StartAddress +=3D sizeof (UINT16);=0D - Size -=3D sizeof (UINT16);=0D - Buffer =3D (UINT16 *)Buffer + 1;=0D - }=0D -=0D - while (Size >=3D sizeof (UINT32)) {=0D - //=0D - // Read as many double words as possible=0D - //=0D - WriteUnaligned32 ((UINT32 *)Buffer, (UINT32)PciExpressRead32 (StartAdd= ress));=0D -=0D - StartAddress +=3D sizeof (UINT32);=0D - Size -=3D sizeof (UINT32);=0D - Buffer =3D (UINT32 *)Buffer + 1;=0D - }=0D -=0D - if (Size >=3D sizeof (UINT16)) {=0D - //=0D - // Read the last remaining word if exist=0D - //=0D - WriteUnaligned16 ((UINT16 *)Buffer, (UINT16)PciExpressRead16 (StartAdd= ress));=0D - StartAddress +=3D sizeof (UINT16);=0D - Size -=3D sizeof (UINT16);=0D - Buffer =3D (UINT16 *)Buffer + 1;=0D - }=0D -=0D - if (Size >=3D sizeof (UINT8)) {=0D - //=0D - // Read the last remaining byte if exist=0D - //=0D - *(volatile UINT8 *)Buffer =3D PciExpressRead8 (StartAddress);=0D - }=0D -=0D - return ReturnValue;=0D -}=0D -=0D -/**=0D - Copies the data in a caller supplied buffer to a specified range of PCI= =0D - configuration space.=0D -=0D - Writes the range of PCI configuration registers specified by StartAddres= s and=0D - Size from the buffer specified by Buffer. This function only allows the = PCI=0D - configuration registers from a single PCI function to be written. Size i= s=0D - returned. When possible 32-bit PCI configuration write cycles are used t= o=0D - write from StartAddress to StartAddress + Size. Due to alignment restric= tions,=0D - 8-bit and 16-bit PCI configuration write cycles may be used at the begin= ning=0D - and the end of the range.=0D -=0D - If StartAddress > 0x0FFFFFFF, then ASSERT().=0D - If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().=0D - If Size > 0 and Buffer is NULL, then ASSERT().=0D -=0D - @param StartAddress The starting address that encodes the PCI Bus, Dev= ice,=0D - Function and Register.=0D - @param Size The size in bytes of the transfer.=0D - @param Buffer The pointer to a buffer containing the data to wri= te.=0D -=0D - @return Size written to StartAddress.=0D -=0D -**/=0D -UINTN=0D -EFIAPI=0D -PciExpressWriteBuffer (=0D - IN UINTN StartAddress,=0D - IN UINTN Size,=0D - IN VOID *Buffer=0D - )=0D -{=0D - UINTN ReturnValue;=0D -=0D - ASSERT_INVALID_PCI_ADDRESS (StartAddress);=0D - ASSERT (((StartAddress & 0xFFF) + Size) <=3D 0x1000);=0D -=0D - if (Size =3D=3D 0) {=0D - return 0;=0D - }=0D -=0D - ASSERT (Buffer !=3D NULL);=0D -=0D - //=0D - // Save Size for return=0D - //=0D - ReturnValue =3D Size;=0D -=0D - if ((StartAddress & 1) !=3D 0) {=0D - //=0D - // Write a byte if StartAddress is byte aligned=0D - //=0D - PciExpressWrite8 (StartAddress, *(UINT8 *)Buffer);=0D - StartAddress +=3D sizeof (UINT8);=0D - Size -=3D sizeof (UINT8);=0D - Buffer =3D (UINT8 *)Buffer + 1;=0D - }=0D -=0D - if ((Size >=3D sizeof (UINT16)) && ((StartAddress & 2) !=3D 0)) {=0D - //=0D - // Write a word if StartAddress is word aligned=0D - //=0D - PciExpressWrite16 (StartAddress, ReadUnaligned16 ((UINT16 *)Buffer));= =0D - StartAddress +=3D sizeof (UINT16);=0D - Size -=3D sizeof (UINT16);=0D - Buffer =3D (UINT16 *)Buffer + 1;=0D - }=0D -=0D - while (Size >=3D sizeof (UINT32)) {=0D - //=0D - // Write as many double words as possible=0D - //=0D - PciExpressWrite32 (StartAddress, ReadUnaligned32 ((UINT32 *)Buffer));= =0D - StartAddress +=3D sizeof (UINT32);=0D - Size -=3D sizeof (UINT32);=0D - Buffer =3D (UINT32 *)Buffer + 1;=0D - }=0D -=0D - if (Size >=3D sizeof (UINT16)) {=0D - //=0D - // Write the last remaining word if exist=0D - //=0D - PciExpressWrite16 (StartAddress, ReadUnaligned16 ((UINT16 *)Buffer));= =0D - StartAddress +=3D sizeof (UINT16);=0D - Size -=3D sizeof (UINT16);=0D - Buffer =3D (UINT16 *)Buffer + 1;=0D - }=0D -=0D - if (Size >=3D sizeof (UINT8)) {=0D - //=0D - // Write the last remaining byte if exist=0D - //=0D - PciExpressWrite8 (StartAddress, *(UINT8 *)Buffer);=0D - }=0D -=0D - return ReturnValue;=0D -}=0D --=20 2.31.1