From: "Khasim Mohammed" <khasim.mohammed@arm.com>
To: devel@edk2.groups.io
Cc: nd@arm.com, sami.mujawar@arm.com, pierre.gondois@arm.com,
Khasim Syed Mohammed <khasim.mohammed@arm.com>
Subject: [PATCH v7 0/6] Enable CCIX port as PCIe root host on N1SDP
Date: Mon, 24 Jan 2022 21:25:30 +0530 [thread overview]
Message-ID: <20220124155536.14078-1-khasim.mohammed@arm.com> (raw)
The patch series removes PciExpressLib and enables CCIX port
as PCIe root on N1SDP.
V7:
- Spit the patches to separate Platform and Silicon specific files
V6:
- Sort PCDs in alphabetical order
- Replace ASSERT calls with a if condition to capture the failure
V5:
- Split the CCIX patch, separate PCD updates and CCIX root port enablement.
- Use GET_SEG_ macro for segment detection and update logic accordingly.
V4:
- Remove PciExpressLib and use PciSegmentLib instead. More detailed explanation
is included in the patch.
V3:
- The conditional logic in GetPciExpressAddress is made simple.
- Removed few more PCD entries that were unused.
- Removed hardcoded entries.
V2:
- Removed few PCDs entries that were not used.
- Migrated to latest version edk2-platform and validated the patches.
V1:
- The PciExpressLib is updated to validate the PCIe addresses
and introducing corresponding PCD entries.
- A custom PCI Segment library is adapted from SynQuacerPciSegmentLib
and ported for N1Sdp.
- The root complex node info in PciHostBridge library is updated to
include the CCIX port information.
The changes can be seen at:
https://github.com/khasim/edk2-platforms-n1sdp/tree/n1sdp-ccix-root
Khasim Syed Mohammed (6):
Silicon/ARM/NeoverseN1Soc: Port PCI Segment Library
Silicon/ARM/NeoverseN1Soc: Update PCDs to support multiple PCI root
ports
Platform/ARM/N1Sdp: Update PCDs to support multiple PCI root ports
Silicon/ARM/NeoverseN1Soc: Add CCIX root complex support
Silicon/ARM/NeoverseN1Soc: Remove PciExpressLib use PciSegmentLib
instead
Platform/ARM/N1Sdp: Remove PciExpressLib use PciSegmentLib instead
.../AslTables/SsdtPci.asl | 8 +-
.../AslTables/SsdtRemotePci.asl | 4 +-
.../ConfigurationManager.c | 24 +-
.../ConfigurationManagerDxe.inf | 18 +-
Platform/ARM/N1Sdp/N1SdpPlatform.dec | 8 -
Platform/ARM/N1Sdp/N1SdpPlatform.dsc | 5 +-
.../PciExpressLib.c | 1589 ----------------
.../PciExpressLib.inf | 56 -
.../PciHostBridgeLib/PciHostBridgeLib.c | 71 +-
.../PciHostBridgeLib/PciHostBridgeLib.inf | 11 +-
.../Library/PciSegmentLib/PciSegmentLib.c | 1622 +++++++++++++++++
.../Library/PciSegmentLib/PciSegmentLib.inf | 38 +
.../Library/PlatformLib/PlatformLib.inf | 1 +
.../Library/PlatformLib/PlatformLibMem.c | 4 +-
Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec | 64 +-
15 files changed, 1808 insertions(+), 1715 deletions(-)
delete mode 100644 Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciExpressLib/PciExpressLib.c
delete mode 100644 Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciExpressLib/PciExpressLib.inf
create mode 100644 Silicon/ARM/NeoverseN1Soc/Library/PciSegmentLib/PciSegmentLib.c
create mode 100644 Silicon/ARM/NeoverseN1Soc/Library/PciSegmentLib/PciSegmentLib.inf
--
2.17.1
next reply other threads:[~2022-01-24 15:56 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-01-24 15:55 Khasim Mohammed [this message]
2022-01-24 15:55 ` [PATCH v7 1/6] Silicon/ARM/NeoverseN1Soc: Port PCI Segment Library Khasim Mohammed
2022-01-24 15:55 ` [PATCH v7 2/6] Silicon/ARM/NeoverseN1Soc: Update PCDs to support multiple PCI root ports Khasim Mohammed
2022-01-24 15:55 ` [PATCH v7 3/6] Platform/ARM/N1Sdp: " Khasim Mohammed
2022-01-24 15:55 ` [PATCH v7 4/6] Silicon/ARM/NeoverseN1Soc: Add CCIX root complex support Khasim Mohammed
2022-01-24 15:55 ` [PATCH v7 5/6] Silicon/ARM/NeoverseN1Soc: Remove PciExpressLib use PciSegmentLib instead Khasim Mohammed
2022-01-24 15:55 ` [PATCH v7 6/6] Platform/ARM/N1Sdp: " Khasim Mohammed
2022-01-24 18:14 ` [PATCH v7 0/6] Enable CCIX port as PCIe root host on N1SDP Sami Mujawar
[not found] ` <16CD478DB32B2FBE.3350@groups.io>
2022-01-24 18:19 ` [edk2-devel] " Sami Mujawar
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-list from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20220124155536.14078-1-khasim.mohammed@arm.com \
--to=devel@edk2.groups.io \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox