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X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Jan 2022 15:57:09.8956 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b208dc62-9f81-482f-f9c1-08d9df522ded X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[63.35.35.123];Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: VE1EUR03FT058.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PA4PR08MB6191 Content-Type: text/plain PCD entries are updated to add support for multiple PCI root ports. Signed-off-by: Khasim Syed Mohammed --- .../AslTables/SsdtPci.asl | 8 +++---- .../AslTables/SsdtRemotePci.asl | 4 ++-- .../ConfigurationManager.c | 24 +++++++++---------- .../ConfigurationManagerDxe.inf | 18 ++++++++++---- Platform/ARM/N1Sdp/N1SdpPlatform.dec | 8 ------- Platform/ARM/N1Sdp/N1SdpPlatform.dsc | 1 - 6 files changed, 31 insertions(+), 32 deletions(-) diff --git a/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/AslTables/SsdtPci.asl b/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/AslTables/SsdtPci.asl index cdbd42c154..9922673d0d 100644 --- a/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/AslTables/SsdtPci.asl +++ b/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/AslTables/SsdtPci.asl @@ -80,8 +80,8 @@ DefinitionBlock("SsdtPci.aml", "SSDT", 1, "ARMLTD", "N1Sdp", Device(PCI0) { Name (_HID, EISAID("PNP0A08")) // PCI Express Root Bridge Name (_CID, EISAID("PNP0A03")) // Compatible PCI Root Bridge - Name (_SEG, Zero) // PCI Segment Group number - Name (_BBN, Zero) // PCI Base Bus Number + Name (_SEG, FixedPcdGet32 (PcdPcieSegmentNumber)) // Segment Number + Name (_BBN, FixedPcdGet32 (PcdPcieBusBaseNumber)) // Bus Base Number Name (_CCA, 1) // Cache Coherency Attribute // Root Complex 0 @@ -166,8 +166,8 @@ DefinitionBlock("SsdtPci.aml", "SSDT", 1, "ARMLTD", "N1Sdp", Device(PCI1) { Name (_HID, EISAID("PNP0A08")) // PCI Express Root Bridge Name (_CID, EISAID("PNP0A03")) // Compatible PCI Root Bridge - Name (_SEG, 1) // PCI Segment Group number - Name (_BBN, Zero) // PCI Base Bus Number + Name (_SEG, FixedPcdGet32 (PcdCcixSegmentNumber)) // Segment Number + Name (_BBN, FixedPcdGet32 (PcdCcixBusBaseNumber)) // Bus Base Number Name (_CCA, 1) // Cache Coherency Attribute // Root Complex 1 diff --git a/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/AslTables/SsdtRemotePci.asl b/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/AslTables/SsdtRemotePci.asl index b6bec7c106..4c6e0c762f 100644 --- a/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/AslTables/SsdtRemotePci.asl +++ b/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/AslTables/SsdtRemotePci.asl @@ -76,8 +76,8 @@ DefinitionBlock("SsdtRemotePci.aml", "SSDT", 1, "ARMLTD", "N1Sdp", Device(PCI2) { Name (_HID, EISAID("PNP0A08")) // PCI Express Root Bridge Name (_CID, EISAID("PNP0A03")) // Compatible PCI Root Bridge - Name (_SEG, 2) // PCI Segment Group number - Name (_BBN, Zero) // PCI Base Bus Number + Name (_SEG, FixedPcdGet32 (PcdRemotePcieSegmentNumber)) // Segment Number + Name (_BBN, FixedPcdGet32 (PcdRemotePcieBusBaseNumber)) // BusBase Number Name (_CCA, 1) // Cache Coherency Attribute // Remote Root Complex 0 diff --git a/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c b/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c index 9c91372c11..f50623ae3f 100644 --- a/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c +++ b/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c @@ -1047,24 +1047,24 @@ EDKII_PLATFORM_REPOSITORY_INFO N1sdpRepositoryInfo = { { // PCIe ECAM { - 0x70000000, // Base Address - 0x0, // Segment Group Number - 0x0, // Start Bus Number - 17 // End Bus Number + FixedPcdGet64 (PcdPcieExpressBaseAddress), // Base Address + FixedPcdGet32 (PcdPcieSegmentNumber), // Segment Group Number + FixedPcdGet32 (PcdPcieBusMin), // Start Bus Number + FixedPcdGet32 (PcdPcieBusMax) // End Bus Number }, // CCIX ECAM { - 0x68000000, // Base Address - 0x1, // Segment Group Number - 0x0, // Start Bus Number - 17 // End Bus Number + FixedPcdGet32 (PcdCcixExpressBaseAddress), // Base Address + FixedPcdGet32 (PcdCcixSegmentNumber), // Segment Group Number + FixedPcdGet32 (PcdCcixBusMin), // Start Bus Number + FixedPcdGet32 (PcdCcixBusMax) // End Bus Number }, //Remote Chip PCIe ECAM { - 0x40070000000, // Base Address - 0x2, // Segment Group Number - 0x0, // Start Bus Number - 17 // End Bus Number + FixedPcdGet64 (PcdRemotePcieBaseAddress), // Base Address + FixedPcdGet32 (PcdRemotePcieSegmentNumber), // Segment Group Number + FixedPcdGet32 (PcdRemotePcieBusMin), // Start Bus Number + FixedPcdGet32 (PcdRemotePcieBusMax) // End Bus Number } }, diff --git a/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerDxe.inf b/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerDxe.inf index 027a4202ff..4f8e7f1302 100644 --- a/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerDxe.inf +++ b/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerDxe.inf @@ -76,8 +76,6 @@ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate - gArmN1SdpTokenSpaceGuid.PcdPcieExpressBaseAddress - gArmNeoverseN1SocTokenSpaceGuid.PcdExtMemorySpace gArmNeoverseN1SocTokenSpaceGuid.PcdDramBlock2Base @@ -88,9 +86,11 @@ gArmTokenSpaceGuid.PcdSystemMemorySize #PCIe + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusBaseNumber gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusCount gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusMax gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusMin + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieExpressBaseAddress gArmNeoverseN1SocTokenSpaceGuid.PcdPcieIoBase gArmNeoverseN1SocTokenSpaceGuid.PcdPcieIoMaxBase gArmNeoverseN1SocTokenSpaceGuid.PcdPcieIoSize @@ -105,8 +105,10 @@ gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio64Translation gArmNeoverseN1SocTokenSpaceGuid.PcdPcieRootPortConfigBaseAddress gArmNeoverseN1SocTokenSpaceGuid.PcdPcieRootPortConfigBaseSize + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieSegmentNumber # CCIX + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixBusBaseNumber gArmNeoverseN1SocTokenSpaceGuid.PcdCcixBusCount gArmNeoverseN1SocTokenSpaceGuid.PcdCcixBusMax gArmNeoverseN1SocTokenSpaceGuid.PcdCcixBusMin @@ -125,6 +127,7 @@ gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio64Translation gArmNeoverseN1SocTokenSpaceGuid.PcdCcixRootPortConfigBaseAddress gArmNeoverseN1SocTokenSpaceGuid.PcdCcixRootPortConfigBaseSize + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixSegmentNumber # Coresight gArmN1SdpTokenSpaceGuid.PcdCsComponentSize @@ -158,9 +161,14 @@ gArmN1SdpTokenSpaceGuid.PcdCsTpiuMaxBase # Remote PCIe - gArmN1SdpTokenSpaceGuid.PcdRemotePcieIoTranslation - gArmN1SdpTokenSpaceGuid.PcdRemotePcieMmio32Translation - gArmN1SdpTokenSpaceGuid.PcdRemotePcieMmio64Translation + gArmNeoverseN1SocTokenSpaceGuid.PcdRemotePcieBaseAddress + gArmNeoverseN1SocTokenSpaceGuid.PcdRemotePcieBusBaseNumber + gArmNeoverseN1SocTokenSpaceGuid.PcdRemotePcieBusMax + gArmNeoverseN1SocTokenSpaceGuid.PcdRemotePcieBusMin + gArmNeoverseN1SocTokenSpaceGuid.PcdRemotePcieIoTranslation + gArmNeoverseN1SocTokenSpaceGuid.PcdRemotePcieMmio32Translation + gArmNeoverseN1SocTokenSpaceGuid.PcdRemotePcieMmio64Translation + gArmNeoverseN1SocTokenSpaceGuid.PcdRemotePcieSegmentNumber [Depex] TRUE diff --git a/Platform/ARM/N1Sdp/N1SdpPlatform.dec b/Platform/ARM/N1Sdp/N1SdpPlatform.dec index 2ab6c20dcc..16937197b8 100644 --- a/Platform/ARM/N1Sdp/N1SdpPlatform.dec +++ b/Platform/ARM/N1Sdp/N1SdpPlatform.dec @@ -34,9 +34,6 @@ gArmN1SdpTokenSpaceGuid.PcdRamDiskBase|0x88000000|UINT32|0x00000001 gArmN1SdpTokenSpaceGuid.PcdRamDiskSize|0x18000000|UINT32|0x00000002 - # PCIe - gArmN1SdpTokenSpaceGuid.PcdPcieExpressBaseAddress|0x70000000|UINT32|0x00000007 - # External memory gArmNeoverseN1SocTokenSpaceGuid.PcdExtMemorySpace|0|UINT64|0x00000029 @@ -92,8 +89,3 @@ # unmapped reserved region results in a DECERR response. # gArmN1SdpTokenSpaceGuid.PcdCsComponentSize|0x1000|UINT32|0x00000049 - - # Remote Chip PCIe - gArmN1SdpTokenSpaceGuid.PcdRemotePcieIoTranslation|0x40075200000|UINT64|0x0000004A - gArmN1SdpTokenSpaceGuid.PcdRemotePcieMmio32Translation|0x40000000000|UINT64|0x0000004B - gArmN1SdpTokenSpaceGuid.PcdRemotePcieMmio64Translation|0x40000000000|UINT64|0x0000004C diff --git a/Platform/ARM/N1Sdp/N1SdpPlatform.dsc b/Platform/ARM/N1Sdp/N1SdpPlatform.dsc index 7488bdc036..cb2049966c 100644 --- a/Platform/ARM/N1Sdp/N1SdpPlatform.dsc +++ b/Platform/ARM/N1Sdp/N1SdpPlatform.dsc @@ -127,7 +127,6 @@ gArmTokenSpaceGuid.PcdGicRedistributorsBase|0x300C0000 # PCIe - gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x70000000 gEmbeddedTokenSpaceGuid.PcdPrePiCpuIoSize|24 gEfiMdeModulePkgTokenSpaceGuid.PcdSrIovSupport|FALSE -- 2.17.1