From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by mx.groups.io with SMTP id smtpd.web09.3918.1643092552922625005 for ; Mon, 24 Jan 2022 22:35:53 -0800 Authentication-Results: mx.groups.io; dkim=fail reason="unable to parse pub key" header.i=@intel.com header.s=intel header.b=gBDsiDIR; spf=pass (domain: intel.com, ip: 192.55.52.151, mailfrom: min.m.xu@intel.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1643092552; x=1674628552; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=gYxMZTVcDNVOh91I2LFndnb2+xNp6pSizN5KRcftwVo=; b=gBDsiDIRbr5nVvHIu8Ao5s9jRMegAwfcXMLaLQJt2Dy5QivWiL1p4OAF /p11k+0lYnxWskwARhAOHR2JSp8uMcLu74fqU040nWhbbskrBhfihdgOG 6TrkCxGaL3mqH3DxO8Ok73HSw4s1DTlcy14K40tc/IaMGo43T5hPKFNpS Cu+1dbJKD+WX0txBnol6SZs/ppoaULYQVPHeRnY03xOCwNKVjjouGfC40 9gRw1+HhCeH/BwI2xL5B5R4PdaDj6hTpf5Yee1kk5TlVTVAXvUFGQXicr R3vinjx9M1nVsmSPehcOtuaRotQWlBpo0zhRScfnHIU5FojF2Y/GUGcgA A==; X-IronPort-AV: E=McAfee;i="6200,9189,10237"; a="226904861" X-IronPort-AV: E=Sophos;i="5.88,314,1635231600"; d="scan'208";a="226904861" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Jan 2022 22:35:44 -0800 X-IronPort-AV: E=Sophos;i="5.88,314,1635231600"; d="scan'208";a="534592677" Received: from mxu9-mobl1.ccr.corp.intel.com ([10.238.0.72]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Jan 2022 22:35:42 -0800 From: "Min Xu" To: devel@edk2.groups.io Cc: Min Xu , Michael D Kinney , Brijesh Singh , Erdem Aktas , James Bottomley , Jiewen Yao , Tom Lendacky , Gerd Hoffmann Subject: [PATCH V2 05/10] OvmfPkg: Update EFI_HOB_PLATFORM_INFO with more platform settings Date: Tue, 25 Jan 2022 14:33:13 +0800 Message-Id: <20220125063318.862-6-min.m.xu@intel.com> X-Mailer: git-send-email 2.29.2.windows.2 In-Reply-To: <20220125063318.862-1-min.m.xu@intel.com> References: <20220125063318.862-1-min.m.xu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3429 This patch-sets is to bring up Legacy guest and Tdx guest without PEI phase. So platform initialization has to be done in SEC phase. It is similar with the work of OvmfPkg/PlatformPei. In OvmfPkg/PlatformPei some PCDs are set during platform initialization, such as PcdPciMmio64Base. But in PEI-less boot, PCDs cannot be set. So these values are saved in EFI_HOB_PLATFORM_INFO. Then in the early stage of DXE phase this hob will be parsed and PCDs are set accordingly. Cc: Michael D Kinney Cc: Brijesh Singh Cc: Erdem Aktas Cc: James Bottomley Cc: Jiewen Yao Cc: Tom Lendacky Cc: Gerd Hoffmann Signed-off-by: Min Xu --- OvmfPkg/Include/IndustryStandard/IntelTdx.h | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/OvmfPkg/Include/IndustryStandard/IntelTdx.h b/OvmfPkg/Include/IndustryStandard/IntelTdx.h index 44155adefd58..a37ad28f7bf4 100644 --- a/OvmfPkg/Include/IndustryStandard/IntelTdx.h +++ b/OvmfPkg/Include/IndustryStandard/IntelTdx.h @@ -65,6 +65,23 @@ typedef struct { typedef struct { EFI_HOB_GUID_TYPE GuidHeader; UINT16 HostBridgePciDevId; + BOOLEAN PcdSetNxForStack; + UINT8 SystemStates[6]; + + UINT64 PcdConfidentialComputingGuestAttr; + BOOLEAN PcdIa32EferChangeAllowed; + UINT64 PcdTdxSharedBitMask; + + UINT64 PcdPciMmio64Base; + UINT64 PcdPciMmio64Size; + UINT32 PcdPciMmio32Base; + UINT32 PcdPciMmio32Size; + UINT64 PcdPciIoBase; + UINT64 PcdPciIoSize; + + UINT64 PcdEmuVariableNvStoreReserved; + UINT32 PcdCpuBootLogicalProcessorNumber; + UINT32 PcdCpuMaxLogicalProcessorNumber; } EFI_HOB_PLATFORM_INFO; #pragma pack() -- 2.29.2.windows.2