[PATCH v3 3/8] DynamicTablesPkg: AcpiSsdtPcieLibArm: Fix _PRT description

["PierreGondois" <pierre.gondois@arm.com>]

From: Pierre Gondois <Pierre.Gondois@arm.com>

In ACPI 6.4, s6.2.13, _PRT objects describing PCI legacy interrupts
can be defined following 2 models.
In the first model, a _SRS object must be described to modify the PCI
interrupt. The _CRS and _PRS object allows to describe the PCI
interrupt (level/edge triggered, active high/low).
In the second model, the PCI interrupt cannot be described with a
similar granularity. PCI interrupts are by default level triggered,
active low.

GicV2 SPI interrupts are level or edge triggered, active high. To
correctly describe PCI interrupts, the first model is used, even though
Arm Base Boot Requirements v1.0 requires to use the second mode.

Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com>
---

Notes:
    v3:
     - New patch. [Pierre]

 .../AcpiSsdtPcieLibArm/SsdtPcieGenerator.c    | 47 +++++++++++++++++--
 1 file changed, 44 insertions(+), 3 deletions(-)

diff --git a/DynamicTablesPkg/Library/Acpi/Arm/AcpiSsdtPcieLibArm/SsdtPcieGenerator.c b/DynamicTablesPkg/Library/Acpi/Arm/AcpiSsdtPcieLibArm/SsdtPcieGenerator.c
index 3e22587d4a25..6823a98795c8 100644
--- a/DynamicTablesPkg/Library/Acpi/Arm/AcpiSsdtPcieLibArm/SsdtPcieGenerator.c
+++ b/DynamicTablesPkg/Library/Acpi/Arm/AcpiSsdtPcieLibArm/SsdtPcieGenerator.c
@@ -1,7 +1,7 @@
 /** @file
   SSDT Pcie Table Generator.
 
-  Copyright (c) 2021, Arm Limited. All rights reserved.<BR>
+  Copyright (c) 2021 - 2022, Arm Limited. All rights reserved.<BR>
 
   SPDX-License-Identifier: BSD-2-Clause-Patent
 
@@ -295,6 +295,10 @@ GeneratePciDeviceInfo (
     Method (_CRS, 0) {
       Return CRS0
       })
+    Method (_PRS, 0) {
+      Return CRS0
+      })
+    Method (_SRS, 1) { }
     Method (_DIS) { }
   }
 
@@ -302,9 +306,12 @@ GeneratePciDeviceInfo (
   PCI Firmware Specification - Revision 3.3,
   s3.5. "Device State at Firmware/Operating System Handoff"
 
-  The _PRS and _SRS are not supported, cf Arm Base Boot Requirements v1.0:
+  Warning: The Arm Base Boot Requirements v1.0 states the following:
   "The _PRS (Possible Resource Settings) and _SRS (Set Resource Settings)
   are not supported."
+  However, the first model to describe PCI legacy interrupts is used (cf. ACPI
+  6.4 s6.2.13) as PCI defaults (Level Triggered, Active Low) are not compatible
+  with GICv2 (must be Active High).
 
   @param [in]       Irq         Interrupt controller interrupt.
   @param [in]       IrqFlags    Interrupt flags.
@@ -416,7 +423,41 @@ GenerateLinkDevice (
     return Status;
   }
 
-  // ASL:Method (_DIS, 1) {}
+  // ASL:
+  // Method (_PRS, 0) {
+  //   Return (CRS0)
+  // }
+  Status = AmlCodeGenMethodRetNameString (
+             "_PRS",
+             "CRS0",
+             0,
+             FALSE,
+             0,
+             LinkNode,
+             NULL
+             );
+  if (EFI_ERROR (Status)) {
+    ASSERT (0);
+    return Status;
+  }
+
+  // ASL:Method (_SRS, 1) {}
+  // Not possible to disable interrupts.
+  Status = AmlCodeGenMethodRetNameString (
+             "_SRS",
+             NULL,
+             1,
+             FALSE,
+             0,
+             LinkNode,
+             NULL
+             );
+  if (EFI_ERROR (Status)) {
+    ASSERT (0);
+    return Status;
+  }
+
+  // ASL:Method (_DIS, 0) {}
   // Not possible to disable interrupts.
   Status = AmlCodeGenMethodRetNameString (
              "_DIS",
-- 
2.25.1