From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.web11.51793.1643736167698807450 for ; Tue, 01 Feb 2022 09:22:47 -0800 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: arm.com, ip: 217.140.110.172, mailfrom: pierre.gondois@arm.com) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 4F2DD11B3; Tue, 1 Feb 2022 09:22:47 -0800 (PST) Received: from e126645.home (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id B3C2C3F40C; Tue, 1 Feb 2022 09:22:45 -0800 (PST) From: "PierreGondois" To: devel@edk2.groups.io Cc: Ard Biesheuvel , Sami Mujawar , Rebecca Cran , Pierre Gondois Subject: [PATCH v5 2/9] DynamicTablesPkg: FdtHwInfoParserLib: Parse Pmu info Date: Tue, 1 Feb 2022 18:22:45 +0100 Message-Id: <20220201172252.799725-3-Pierre.Gondois@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220201172252.799725-1-Pierre.Gondois@arm.com> References: <20220201172252.799725-1-Pierre.Gondois@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable From: Pierre Gondois Parse the Pmu interrupts if a pmu compatible node is present, and populate the MADT GicC structure accordingly. Signed-off-by: Pierre Gondois --- Notes: v3: - New patch. [Pierre] v4: - Add more information in ASSERT () checks. [Ard] .../FdtHwInfoParserLib/Gic/ArmGicCParser.c | 132 +++++++++++++++++- .../FdtHwInfoParserLib/Gic/ArmGicCParser.h | 8 +- 2 files changed, 136 insertions(+), 4 deletions(-) diff --git a/DynamicTablesPkg/Library/FdtHwInfoParserLib/Gic/ArmGicCParse= r.c b/DynamicTablesPkg/Library/FdtHwInfoParserLib/Gic/ArmGicCParser.c index b4e6729a4ab2..fb01aa0d19e2 100644 --- a/DynamicTablesPkg/Library/FdtHwInfoParserLib/Gic/ArmGicCParser.c +++ b/DynamicTablesPkg/Library/FdtHwInfoParserLib/Gic/ArmGicCParser.c @@ -1,13 +1,14 @@ /** @file Arm Gic cpu parser. =20 - Copyright (c) 2021, ARM Limited. All rights reserved.
+ Copyright (c) 2021 - 2022, Arm Limited. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent =20 @par Reference(s): - linux/Documentation/devicetree/bindings/arm/cpus.yaml - linux/Documentation/devicetree/bindings/interrupt-controller/arm,gic= .yaml - linux/Documentation/devicetree/bindings/interrupt-controller/arm,gic= -v3.yaml + - linux/Documentation/devicetree/bindings/arm/pmu.yaml **/ =20 #include "FdtHwInfoParser.h" @@ -34,6 +35,21 @@ STATIC CONST COMPATIBILITY_INFO CpuCompatibleInfo =3D= { CpuCompatibleStr }; =20 +/** Pmu compatible strings. + + Any other "compatible" value is not supported by this module. +*/ +STATIC CONST COMPATIBILITY_STR PmuCompatibleStr[] =3D { + { "arm,armv8-pmuv3" } +}; + +/** COMPATIBILITY_INFO structure for the PmuCompatibleStr. +*/ +CONST COMPATIBILITY_INFO PmuCompatibleInfo =3D { + ARRAY_SIZE (PmuCompatibleStr), + PmuCompatibleStr +}; + /** Parse a "cpu" node. =20 @param [in] Fdt Pointer to a Flattened Device Tree (Fdt)= . @@ -639,6 +655,111 @@ GicCv3IntcNodeParser ( return EFI_SUCCESS; } =20 +/** Parse a Pmu compatible node, extracting Pmu information. + + This function modifies a CM_OBJ_DESCRIPTOR object. + The following CM_ARM_GICC_INFO fields are patched: + - PerformanceInterruptGsiv; + + @param [in] Fdt Pointer to a Flattened Device Tree = (Fdt). + @param [in] GicIntcNode Offset of a Gic compatible + interrupt-controller node. + @param [in, out] GicCCmObjDesc The CM_ARM_GICC_INFO to patch. + + @retval EFI_SUCCESS The function completed successfully. + @retval EFI_ABORTED An error occurred. + @retval EFI_INVALID_PARAMETER Invalid parameter. +**/ +STATIC +EFI_STATUS +EFIAPI +GicCPmuNodeParser ( + IN CONST VOID *Fdt, + IN INT32 GicIntcNode, + IN OUT CM_OBJ_DESCRIPTOR *GicCCmObjDesc + ) +{ + EFI_STATUS Status; + INT32 IntCells; + INT32 PmuNode; + UINT32 PmuNodeCount; + UINT32 PmuIrq; + UINT32 Index; + CM_ARM_GICC_INFO *GicCInfo; + CONST UINT8 *Data; + INT32 DataSize; + + if (GicCCmObjDesc =3D=3D NULL) { + ASSERT (GicCCmObjDesc !=3D NULL); + return EFI_INVALID_PARAMETER; + } + + GicCInfo =3D (CM_ARM_GICC_INFO *)GicCCmObjDesc->Data; + PmuNode =3D 0; + + // Count the number of pmu nodes. + Status =3D FdtCountCompatNodeInBranch ( + Fdt, + 0, + &PmuCompatibleInfo, + &PmuNodeCount + ); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return Status; + } + + if (PmuNodeCount =3D=3D 0) { + return EFI_NOT_FOUND; + } + + Status =3D FdtGetNextCompatNodeInBranch ( + Fdt, + 0, + &PmuCompatibleInfo, + &PmuNode + ); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + if (Status =3D=3D EFI_NOT_FOUND) { + // Should have found the node. + Status =3D EFI_ABORTED; + } + } + + // Get the number of cells used to encode an interrupt. + Status =3D FdtGetInterruptCellsInfo (Fdt, GicIntcNode, &IntCells); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return Status; + } + + Data =3D fdt_getprop (Fdt, PmuNode, "interrupts", &DataSize); + if ((Data =3D=3D NULL) || (DataSize !=3D (IntCells * sizeof (UINT32)))= ) { + // If error or not 1 interrupt. + ASSERT (Data !=3D NULL); + ASSERT (DataSize =3D=3D (IntCells * sizeof (UINT32))); + return EFI_ABORTED; + } + + PmuIrq =3D FdtGetInterruptId ((CONST UINT32 *)Data); + + // Only supports PPI 23 for now. + // According to BSA 1.0 s3.6 PPI assignments, PMU IRQ ID is 23. A non = BSA + // compliant system may assign a different IRQ for the PMU, however th= is + // is not implemented for now. + if (PmuIrq !=3D BSA_PMU_IRQ) { + ASSERT (PmuIrq =3D=3D BSA_PMU_IRQ); + return EFI_ABORTED; + } + + for (Index =3D 0; Index < GicCCmObjDesc->Count; Index++) { + GicCInfo[Index].PerformanceInterruptGsiv =3D PmuIrq; + } + + return EFI_SUCCESS; +} + /** CM_ARM_GICC_INFO parser function. =20 This parser expects FdtBranch to be the "\cpus" node node. @@ -649,7 +770,7 @@ GicCv3IntcNodeParser ( UINT32 AcpiProcessorUid; // {Populated} UINT32 Flags; // {Populated} UINT32 ParkingProtocolVersion; // {default =3D 0} - UINT32 PerformanceInterruptGsiv; // {default =3D 0} + UINT32 PerformanceInterruptGsiv; // {Populated} UINT64 ParkedAddress; // {default =3D 0} UINT64 PhysicalBaseAddress; // {Populated} UINT64 GICV; // {Populated} @@ -764,6 +885,13 @@ ArmGicCInfoParser ( goto exit_handler; } =20 + // Parse the Pmu Interrupt. + Status =3D GicCPmuNodeParser (Fdt, IntcNode, NewCmObjDesc); + if (EFI_ERROR (Status) && (Status !=3D EFI_NOT_FOUND)) { + ASSERT_EFI_ERROR (Status); + goto exit_handler; + } + // Add all the CmObjs to the Configuration Manager. Status =3D AddMultipleCmObj (FdtParserHandle, NewCmObjDesc, 0, NULL); if (EFI_ERROR (Status)) { diff --git a/DynamicTablesPkg/Library/FdtHwInfoParserLib/Gic/ArmGicCParse= r.h b/DynamicTablesPkg/Library/FdtHwInfoParserLib/Gic/ArmGicCParser.h index 2a0f966bf0c2..fd980484a28d 100644 --- a/DynamicTablesPkg/Library/FdtHwInfoParserLib/Gic/ArmGicCParser.h +++ b/DynamicTablesPkg/Library/FdtHwInfoParserLib/Gic/ArmGicCParser.h @@ -1,7 +1,7 @@ /** @file Arm Gic cpu parser. =20 - Copyright (c) 2021, ARM Limited. All rights reserved.
+ Copyright (c) 2021 - 2022, Arm Limited. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent =20 @par Reference(s): @@ -12,6 +12,10 @@ #ifndef ARM_GICC_PARSER_H_ #define ARM_GICC_PARSER_H_ =20 +/* According to BSA 1.0 s3.6 PPI assignments, PMU IRQ ID is 23. +*/ +#define BSA_PMU_IRQ 23 + /** CM_ARM_GICC_INFO parser function. =20 This parser expects FdtBranch to be the "\cpus" node node. @@ -22,7 +26,7 @@ UINT32 AcpiProcessorUid; // {Populated} UINT32 Flags; // {Populated} UINT32 ParkingProtocolVersion; // {default =3D 0} - UINT32 PerformanceInterruptGsiv; // {default =3D 0} + UINT32 PerformanceInterruptGsiv; // {Populated} UINT64 ParkedAddress; // {default =3D 0} UINT64 PhysicalBaseAddress; // {Populated} UINT64 GICV; // {Populated} --=20 2.25.1