From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from loongson.cn (loongson.cn [114.242.206.163]) by mx.groups.io with SMTP id smtpd.web12.23553.1644389744847698208 for ; Tue, 08 Feb 2022 22:55:45 -0800 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: loongson.cn, ip: 114.242.206.163, mailfrom: lichao@loongson.cn) Received: from code-server.gen (unknown [10.2.9.245]) by mail.loongson.cn (Coremail) with SMTP id AQAAf9Ax2uBuZQNizIsIAA--.25492S2; Wed, 09 Feb 2022 14:55:42 +0800 (CST) From: "Chao Li" To: devel@edk2.groups.io Cc: Michael D Kinney , Liming Gao , Zhiguang Liu , Baoqi Zhang Subject: [staging/LoongArch RESEND PATCH v1 21/33] MdePkg/BaseLib: BaseLib for LOONGARCH64 architecture. Date: Wed, 9 Feb 2022 14:55:42 +0800 Message-Id: <20220209065542.2986555-1-lichao@loongson.cn> X-Mailer: git-send-email 2.27.0 MIME-Version: 1.0 X-CM-TRANSID: AQAAf9Ax2uBuZQNizIsIAA--.25492S2 X-Coremail-Antispam: 1UD129KBjvAXoWfXw17JF47Ww4kGrW3Aw1DKFg_yoW8ur4xAo WUZr4xCw4jyr18Ar1kArnrXw12qrs3Wr45Jr40gF18GF4rtF1jkrWDA34UGw15WFZ8KrWD G348XayxGFZxtr18n29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7v73VFW2AGmfu7bjvjm3 AaLaJ3UjIYCTnIWjp_UUUYa7k0a2IF6w4kM7kC6x804xWl14x267AKxVWUJVW8JwAFc2x0 x2IEx4CE42xK8VAvwI8IcIk0rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2ocxC64kIII0Yj4 1l84x0c7CEw4AK67xGY2AK021l84ACjcxK6xIIjxv20xvE14v26F1j6w1UM28EF7xvwVC0 I7IYx2IY6xkF7I0E14v26r4UJVWxJr1l84ACjcxK6I8E87Iv67AKxVWxJr0_GcWl84ACjc xK6I8E87Iv6xkF7I0E14v26rxl6s0DM2AIxVAIcxkEcVAq07x20xvEncxIr21l5I8CrVAC Y4xI64kE6c02F40Ex7xfMcIj6xIIjxv20xvE14v26r1q6rW5McIj6xkF7I0En7xvr7AKxV WUJVW8JwAv7VC2z280aVAFwI0_Gr0_Cr1lOx8S6xCaFVCjc4AY6r1j6r4UM4x0Y48IcxkI 7VAKI48JMxkIecxEwVCm-wCF04k20xvY0x0EwIxGrwCFx2IqxVCFs4IE7xkEbVWUJVW8Jw C20s026c02F40E14v26r1j6r18MI8I3I0E7480Y4vE14v26r106r1rMI8E67AF67kF1VAF wI0_JF0_Jw1lIxkGc2Ij64vIr41lIxAIcVC0I7IYx2IY67AKxVW5JVW7JwCI42IY6xIIjx v20xvEc7CjxVAFwI0_Cr0_Gr1UMIIF0xvE42xK8VAvwI8IcIk0rVWUCVW8JwCI42IY6I8E 87Iv67AKxVW8JVWxJwCI42IY6I8E87Iv6xkF7I0E14v26r4UJVWxJrUvcSsGvfC2KfnxnU UI43ZEXa7IU5RBT5UUUUU== X-CM-SenderInfo: xolfxt3r6o00pqjv00gofq/1tbiAQAMCF3QvO0LrgALs3 Content-Transfer-Encoding: quoted-printable Add LoongArch LOONGARCH64 BaseLib functions. Cc: Michael D Kinney Cc: Liming Gao Cc: Zhiguang Liu Signed-off-by: Chao Li Co-authored-by: Baoqi Zhang --- MdePkg/Include/Library/BaseLib.h | 24 ++ MdePkg/Library/BaseLib/BaseLib.inf | 13 + .../BaseLib/LoongArch64/CpuBreakpoint.S | 24 ++ MdePkg/Library/BaseLib/LoongArch64/CpuPause.S | 31 +++ .../BaseLib/LoongArch64/DisableInterrupts.S | 21 ++ .../BaseLib/LoongArch64/EnableInterrupts.S | 21 ++ .../BaseLib/LoongArch64/GetInterruptState.S | 35 +++ .../BaseLib/LoongArch64/InternalSwitchStack.c | 58 +++++ .../Library/BaseLib/LoongArch64/MemoryFence.S | 19 ++ .../BaseLib/LoongArch64/SetJumpLongJump.S | 49 ++++ .../Library/BaseLib/LoongArch64/SwitchStack.S | 39 +++ .../Library/BaseLib/LoongArch64/Unaligned.c | 244 ++++++++++++++++++ 12 files changed, 578 insertions(+) create mode 100644 MdePkg/Library/BaseLib/LoongArch64/CpuBreakpoint.S create mode 100644 MdePkg/Library/BaseLib/LoongArch64/CpuPause.S create mode 100644 MdePkg/Library/BaseLib/LoongArch64/DisableInterrupts.S create mode 100644 MdePkg/Library/BaseLib/LoongArch64/EnableInterrupts.S create mode 100644 MdePkg/Library/BaseLib/LoongArch64/GetInterruptState.S create mode 100644 MdePkg/Library/BaseLib/LoongArch64/InternalSwitchStack.c create mode 100644 MdePkg/Library/BaseLib/LoongArch64/MemoryFence.S create mode 100644 MdePkg/Library/BaseLib/LoongArch64/SetJumpLongJump.S create mode 100644 MdePkg/Library/BaseLib/LoongArch64/SwitchStack.S create mode 100644 MdePkg/Library/BaseLib/LoongArch64/Unaligned.c diff --git a/MdePkg/Include/Library/BaseLib.h b/MdePkg/Include/Library/Base= Lib.h index 6aa0d97218..3c27e2ea93 100644 --- a/MdePkg/Include/Library/BaseLib.h +++ b/MdePkg/Include/Library/BaseLib.h @@ -6,6 +6,7 @@ Copyright (c) 2006 - 2021, Intel Corporation. All rights re= served.
Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
=0D Copyright (c) Microsoft Corporation.
=0D Portions Copyright (c) 2020, Hewlett Packard Enterprise Development LP. Al= l rights reserved.
=0D +Portions Copyright (c) 2022, Loongson Technology Corporation Limited. All = rights reserved.
=0D =0D SPDX-License-Identifier: BSD-2-Clause-Patent=0D =0D @@ -152,6 +153,29 @@ typedef struct { =0D #endif // defined (MDE_CPU_RISCV64)=0D =0D +#if defined (MDE_CPU_LOONGARCH64)=0D +///=0D +/// The LoongArch architecture context buffer used by SetJump() and LongJu= mp()=0D +///=0D +typedef struct {=0D + UINT64 S0;=0D + UINT64 S1;=0D + UINT64 S2;=0D + UINT64 S3;=0D + UINT64 S4;=0D + UINT64 S5;=0D + UINT64 S6;=0D + UINT64 S7;=0D + UINT64 S8;=0D + UINT64 SP;=0D + UINT64 FP;=0D + UINT64 RA;=0D +} BASE_LIBRARY_JUMP_BUFFER;=0D +=0D +#define BASE_LIBRARY_JUMP_BUFFER_ALIGNMENT 8=0D +=0D +#endif // defined (MDE_CPU_LOONGARCH64)=0D +=0D //=0D // String Services=0D //=0D diff --git a/MdePkg/Library/BaseLib/BaseLib.inf b/MdePkg/Library/BaseLib/Ba= seLib.inf index cebda3b210..4c9b6b50dd 100644 --- a/MdePkg/Library/BaseLib/BaseLib.inf +++ b/MdePkg/Library/BaseLib/BaseLib.inf @@ -409,6 +409,19 @@ RiscV64/RiscVInterrupt.S | GCC=0D RiscV64/FlushCache.S | GCC=0D =0D +[Sources.LOONGARCH64]=0D + Math64.c=0D + LoongArch64/Unaligned.c=0D + LoongArch64/InternalSwitchStack.c=0D + LoongArch64/GetInterruptState.S | GCC=0D + LoongArch64/EnableInterrupts.S | GCC=0D + LoongArch64/DisableInterrupts.S | GCC=0D + LoongArch64/MemoryFence.S | GCC=0D + LoongArch64/CpuBreakpoint.S | GCC=0D + LoongArch64/CpuPause.S | GCC=0D + LoongArch64/SetJumpLongJump.S | GCC=0D + LoongArch64/SwitchStack.S | GCC=0D +=0D [Packages]=0D MdePkg/MdePkg.dec=0D =0D diff --git a/MdePkg/Library/BaseLib/LoongArch64/CpuBreakpoint.S b/MdePkg/Li= brary/BaseLib/LoongArch64/CpuBreakpoint.S new file mode 100644 index 0000000000..4e022e9bb5 --- /dev/null +++ b/MdePkg/Library/BaseLib/LoongArch64/CpuBreakpoint.S @@ -0,0 +1,24 @@ +#-------------------------------------------------------------------------= -----=0D +#=0D +# CpuBreakpoint for LoongArch=0D +#=0D +# Copyright (c) 2022, Loongson Technology Corporation Limited. All rights = reserved.
=0D +#=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +#-------------------------------------------------------------------------= -----=0D +=0D +ASM_GLOBAL ASM_PFX(CpuBreakpoint)=0D +=0D +#/**=0D +# Generates a breakpoint on the CPU.=0D +#=0D +# Generates a breakpoint on the CPU. The breakpoint must be implemented s= uch=0D +# that code can resume normal execution after the breakpoint.=0D +#=0D +#**/=0D +=0D +ASM_PFX(CpuBreakpoint):=0D + break 3=0D + jirl $zero, $ra, 0=0D + .end=0D diff --git a/MdePkg/Library/BaseLib/LoongArch64/CpuPause.S b/MdePkg/Library= /BaseLib/LoongArch64/CpuPause.S new file mode 100644 index 0000000000..b98dd48f4d --- /dev/null +++ b/MdePkg/Library/BaseLib/LoongArch64/CpuPause.S @@ -0,0 +1,31 @@ +#-------------------------------------------------------------------------= -----=0D +#=0D +# CpuPause for LoongArch=0D +#=0D +# Copyright (c) 2022, Loongson Technology Corporation Limited. All rights = reserved.
=0D +#=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +#-------------------------------------------------------------------------= -----=0D +=0D +ASM_GLOBAL ASM_PFX(CpuPause)=0D +=0D +#/**=0D +# Requests CPU to pause for a short period of time.=0D +#=0D +# Requests CPU to pause for a short period of time. Typically used in MP= =0D +# systems to prevent memory starvation while waiting for a spin lock.=0D +#=0D +#**/=0D +=0D +ASM_PFX(CpuPause):=0D + andi $zero, $zero, 0x0 //nop=0D + andi $zero, $zero, 0x0 //nop=0D + andi $zero, $zero, 0x0 //nop=0D + andi $zero, $zero, 0x0 //nop=0D + andi $zero, $zero, 0x0 //nop=0D + andi $zero, $zero, 0x0 //nop=0D + andi $zero, $zero, 0x0 //nop=0D + andi $zero, $zero, 0x0 //nop=0D + jirl $zero, $ra, 0=0D + .end=0D diff --git a/MdePkg/Library/BaseLib/LoongArch64/DisableInterrupts.S b/MdePk= g/Library/BaseLib/LoongArch64/DisableInterrupts.S new file mode 100644 index 0000000000..0f228339af --- /dev/null +++ b/MdePkg/Library/BaseLib/LoongArch64/DisableInterrupts.S @@ -0,0 +1,21 @@ +#-------------------------------------------------------------------------= -----=0D +#=0D +# LoongArch interrupt disable=0D +#=0D +# Copyright (c) 2022, Loongson Technology Corporation Limited. All rights = reserved.
=0D +#=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +#-------------------------------------------------------------------------= -----=0D +=0D +ASM_GLOBAL ASM_PFX(DisableInterrupts)=0D +=0D +#/**=0D +# Disables CPU interrupts.=0D +#**/=0D +=0D +ASM_PFX(DisableInterrupts):=0D + li.w $t0, 0x4=0D + csrxchg $zero, $t0, 0x0=0D + jirl $zero, $ra, 0=0D + .end=0D diff --git a/MdePkg/Library/BaseLib/LoongArch64/EnableInterrupts.S b/MdePkg= /Library/BaseLib/LoongArch64/EnableInterrupts.S new file mode 100644 index 0000000000..3c34fb2cdd --- /dev/null +++ b/MdePkg/Library/BaseLib/LoongArch64/EnableInterrupts.S @@ -0,0 +1,21 @@ +#-------------------------------------------------------------------------= -----=0D +#=0D +# LoongArch interrupt enable=0D +#=0D +# Copyright (c) 2022, Loongson Technology Corporation Limited. All rights = reserved.
=0D +#=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +#-------------------------------------------------------------------------= -----=0D +=0D +ASM_GLOBAL ASM_PFX(EnableInterrupts)=0D +=0D +#/**=0D +# Enables CPU interrupts.=0D +#**/=0D +=0D +ASM_PFX(EnableInterrupts):=0D + li.w $t0, 0x4=0D + csrxchg $t0, $t0, 0x0=0D + jirl $zero, $ra, 0=0D + .end=0D diff --git a/MdePkg/Library/BaseLib/LoongArch64/GetInterruptState.S b/MdePk= g/Library/BaseLib/LoongArch64/GetInterruptState.S new file mode 100644 index 0000000000..bfd1f2d5f7 --- /dev/null +++ b/MdePkg/Library/BaseLib/LoongArch64/GetInterruptState.S @@ -0,0 +1,35 @@ +#-------------------------------------------------------------------------= -----=0D +#=0D +# Get LoongArch interrupt status=0D +#=0D +# Copyright (c) 2022, Loongson Technology Corporation Limited. All rights = reserved.
=0D +#=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +#-------------------------------------------------------------------------= -----=0D +=0D +ASM_GLOBAL ASM_PFX(GetInterruptState)=0D +=0D +#/**=0D +# Retrieves the current CPU interrupt state.=0D +#=0D +# Returns TRUE means interrupts are currently enabled. Otherwise,=0D +# returns FALSE.=0D +#=0D +# @retval TRUE CPU interrupts are enabled.=0D +# @retval FALSE CPU interrupts are disabled.=0D +#=0D +#**/=0D +=0D +ASM_PFX(GetInterruptState):=0D + li.w $t1, 0x4=0D + csrrd $t0, 0x0=0D + and $t0, $t0, $t1=0D + beqz $t0, 1f=0D + li.w $a0, 0x1=0D + b 2f=0D +1:=0D + li.w $a0, 0x0=0D +2:=0D + jirl $zero, $ra, 0=0D + .end=0D diff --git a/MdePkg/Library/BaseLib/LoongArch64/InternalSwitchStack.c b/Mde= Pkg/Library/BaseLib/LoongArch64/InternalSwitchStack.c new file mode 100644 index 0000000000..1f1e43106f --- /dev/null +++ b/MdePkg/Library/BaseLib/LoongArch64/InternalSwitchStack.c @@ -0,0 +1,58 @@ +/** @file=0D + SwitchStack() function for LoongArch.=0D +=0D + Copyright (c) 2022, Loongson Technology Corporation Limited. All rights = reserved.
=0D +=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +=0D +#include "BaseLibInternals.h"=0D +=0D +UINTN=0D +EFIAPI=0D +InternalSwitchStackAsm (=0D + IN BASE_LIBRARY_JUMP_BUFFER *JumpBuffer=0D + );=0D +=0D +/**=0D + Transfers control to a function starting with a new stack.=0D +=0D + Transfers control to the function specified by EntryPoint using the=0D + new stack specified by NewStack and passing in the parameters specified= =0D + by Context1 and Context2. Context1 and Context2 are optional and may=0D + be NULL. The function EntryPoint must never return.=0D +=0D + If EntryPoint is NULL, then ASSERT().=0D + If NewStack is NULL, then ASSERT().=0D +=0D + @param EntryPoint A pointer to function to call with the new stack.=0D + @param Context1 A pointer to the context to pass into the EntryPoint= =0D + function.=0D + @param Context2 A pointer to the context to pass into the EntryPoint= =0D + function.=0D + @param NewStack A pointer to the new stack to use for the EntryPoint= =0D + function.=0D + @param Marker VA_LIST marker for the variable argument list.=0D +=0D +**/=0D +VOID=0D +EFIAPI=0D +InternalSwitchStack (=0D + IN SWITCH_STACK_ENTRY_POINT EntryPoint,=0D + IN VOID *Context1, OPTIONAL=0D + IN VOID *Context2, OPTIONAL=0D + IN VOID *NewStack,=0D + IN VA_LIST Marker=0D + )=0D +=0D +{=0D + BASE_LIBRARY_JUMP_BUFFER JumpBuffer;=0D +=0D + JumpBuffer.RA =3D (UINTN)EntryPoint;=0D + JumpBuffer.SP =3D (UINTN)NewStack - sizeof (VOID*);=0D + JumpBuffer.SP -=3D sizeof (Context1) + sizeof (Context2);=0D + ((VOID **)(UINTN)JumpBuffer.SP)[0] =3D Context1;=0D + ((VOID **)(UINTN)JumpBuffer.SP)[1] =3D Context2;=0D +=0D + InternalSwitchStackAsm(&JumpBuffer);=0D +}=0D diff --git a/MdePkg/Library/BaseLib/LoongArch64/MemoryFence.S b/MdePkg/Libr= ary/BaseLib/LoongArch64/MemoryFence.S new file mode 100644 index 0000000000..0d8dc10914 --- /dev/null +++ b/MdePkg/Library/BaseLib/LoongArch64/MemoryFence.S @@ -0,0 +1,19 @@ +#-------------------------------------------------------------------------= -----=0D +#=0D +# MemoryFence() for LoongArch64=0D +#=0D +# Copyright (c) 2022, Loongson Technology Corporation Limited. All rights = reserved.
=0D +#=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +#-------------------------------------------------------------------------= -----=0D +=0D +ASM_GLOBAL ASM_PFX(MemoryFence)=0D +=0D +#=0D +# Memory fence for LoongArch64=0D +#=0D +ASM_PFX(MemoryFence):=0D + dbar 0=0D + jirl $zero, $ra, 0=0D + .end=0D diff --git a/MdePkg/Library/BaseLib/LoongArch64/SetJumpLongJump.S b/MdePkg/= Library/BaseLib/LoongArch64/SetJumpLongJump.S new file mode 100644 index 0000000000..35267c925f --- /dev/null +++ b/MdePkg/Library/BaseLib/LoongArch64/SetJumpLongJump.S @@ -0,0 +1,49 @@ +#-------------------------------------------------------------------------= -----=0D +#=0D +# Set/Long jump for LoongArch=0D +#=0D +# Copyright (c) 2022, Loongson Technology Corporation Limited. All rights = reserved.
=0D +#=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +#-------------------------------------------------------------------------= -----=0D +=0D +#define STORE st.d /* 64 bit mode regsave instruction */=0D +#define LOAD ld.d /* 64 bit mode regload instruction */=0D +#define RSIZE 8 /* 64 bit mode register size */=0D +=0D +ASM_GLOBAL ASM_PFX(SetJump)=0D +ASM_GLOBAL ASM_PFX(InternalLongJump)=0D +=0D +ASM_PFX(SetJump):=0D + STORE $s0, $a0, RSIZE * 0=0D + STORE $s1, $a0, RSIZE * 1=0D + STORE $s2, $a0, RSIZE * 2=0D + STORE $s3, $a0, RSIZE * 3=0D + STORE $s4, $a0, RSIZE * 4=0D + STORE $s5, $a0, RSIZE * 5=0D + STORE $s6, $a0, RSIZE * 6=0D + STORE $s7, $a0, RSIZE * 7=0D + STORE $s8, $a0, RSIZE * 8=0D + STORE $sp, $a0, RSIZE * 9=0D + STORE $fp, $a0, RSIZE * 10=0D + STORE $ra, $a0, RSIZE * 11=0D + li.w $a0, 0 # Setjmp return=0D + jirl $zero, $ra, 0=0D +=0D +ASM_PFX(InternalLongJump):=0D + LOAD $ra, $a0, RSIZE * 11=0D + LOAD $s0, $a0, RSIZE * 0=0D + LOAD $s1, $a0, RSIZE * 1=0D + LOAD $s2, $a0, RSIZE * 2=0D + LOAD $s3, $a0, RSIZE * 3=0D + LOAD $s4, $a0, RSIZE * 4=0D + LOAD $s5, $a0, RSIZE * 5=0D + LOAD $s6, $a0, RSIZE * 6=0D + LOAD $s7, $a0, RSIZE * 7=0D + LOAD $s8, $a0, RSIZE * 8=0D + LOAD $sp, $a0, RSIZE * 9=0D + LOAD $fp, $a0, RSIZE * 10=0D + move $a0, $a1=0D + jirl $zero, $ra, 0=0D + .end=0D diff --git a/MdePkg/Library/BaseLib/LoongArch64/SwitchStack.S b/MdePkg/Libr= ary/BaseLib/LoongArch64/SwitchStack.S new file mode 100644 index 0000000000..4facc76082 --- /dev/null +++ b/MdePkg/Library/BaseLib/LoongArch64/SwitchStack.S @@ -0,0 +1,39 @@ +#-------------------------------------------------------------------------= -----=0D +#=0D +# InternalSwitchStackAsm for LoongArch=0D +#=0D +# Copyright (c) 2022, Loongson Technology Corporation Limited. All rights = reserved.
=0D +#=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +#-------------------------------------------------------------------------= -----=0D +=0D +#define STORE st.d /* 64 bit mode regsave instruction */=0D +#define LOAD ld.d /* 64 bit mode regload instruction */=0D +#define RSIZE 8 /* 64 bit mode register size */=0D +=0D +ASM_GLOBAL ASM_PFX(InternalSwitchStackAsm)=0D +=0D +/**=0D + This allows the caller to switch the stack and goes to the new entry poi= nt=0D +=0D + @param JumpBuffer A pointer to CPU context buffer.=0D +**/=0D +=0D +ASM_PFX(InternalSwitchStackAsm):=0D + LOAD $ra, $a0, RSIZE * 11=0D + LOAD $s0, $a0, RSIZE * 0=0D + LOAD $s1, $a0, RSIZE * 1=0D + LOAD $s2, $a0, RSIZE * 2=0D + LOAD $s3, $a0, RSIZE * 3=0D + LOAD $s4, $a0, RSIZE * 4=0D + LOAD $s5, $a0, RSIZE * 5=0D + LOAD $s6, $a0, RSIZE * 6=0D + LOAD $s7, $a0, RSIZE * 7=0D + LOAD $s8, $a0, RSIZE * 8=0D + LOAD $sp, $a0, RSIZE * 9=0D + LOAD $fp, $a0, RSIZE * 10=0D + LOAD $a0, $sp, 0=0D + LOAD $a1, $sp, 8=0D + jirl $zero, $ra, 0=0D + .end=0D diff --git a/MdePkg/Library/BaseLib/LoongArch64/Unaligned.c b/MdePkg/Librar= y/BaseLib/LoongArch64/Unaligned.c new file mode 100644 index 0000000000..33fa3d2eed --- /dev/null +++ b/MdePkg/Library/BaseLib/LoongArch64/Unaligned.c @@ -0,0 +1,244 @@ +/** @file=0D + Unaligned access functions of BaseLib for LoongArch.=0D +=0D + Copyright (c) 2022, Loongson Technology Corporation Limited. All rights = reserved.
=0D +=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +=0D +#include "BaseLibInternals.h"=0D +=0D +/**=0D + Reads a 16-bit value from memory that may be unaligned.=0D +=0D + This function returns the 16-bit value pointed to by Buffer. The functio= n=0D + guarantees that the read operation does not produce an alignment fault.= =0D +=0D + If the Buffer is NULL, then ASSERT().=0D +=0D + @param Buffer The pointer to a 16-bit value that may be unaligned.=0D +=0D + @return The 16-bit value read from Buffer.=0D +=0D +**/=0D +UINT16=0D +EFIAPI=0D +ReadUnaligned16 (=0D + IN CONST UINT16 *Buffer=0D + )=0D +{=0D + volatile UINT8 LowerByte;=0D + volatile UINT8 HigherByte;=0D +=0D + ASSERT (Buffer !=3D NULL);=0D +=0D + LowerByte =3D ((UINT8*)Buffer)[0];=0D + HigherByte =3D ((UINT8*)Buffer)[1];=0D +=0D + return (UINT16)(LowerByte | (HigherByte << 8));=0D +}=0D +=0D +/**=0D + Writes a 16-bit value to memory that may be unaligned.=0D +=0D + This function writes the 16-bit value specified by Value to Buffer. Valu= e is=0D + returned. The function guarantees that the write operation does not prod= uce=0D + an alignment fault.=0D +=0D + If the Buffer is NULL, then ASSERT().=0D +=0D + @param Buffer The pointer to a 16-bit value that may be unaligned.=0D + @param Value 16-bit value to write to Buffer.=0D +=0D + @return The 16-bit value to write to Buffer.=0D +=0D +**/=0D +UINT16=0D +EFIAPI=0D +WriteUnaligned16 (=0D + OUT UINT16 *Buffer,=0D + IN UINT16 Value=0D + )=0D +{=0D + ASSERT (Buffer !=3D NULL);=0D +=0D + ((volatile UINT8*)Buffer)[0] =3D (UINT8)Value;=0D + ((volatile UINT8*)Buffer)[1] =3D (UINT8)(Value >> 8);=0D +=0D + return Value;=0D +}=0D +=0D +/**=0D + Reads a 24-bit value from memory that may be unaligned.=0D +=0D + This function returns the 24-bit value pointed to by Buffer. The functio= n=0D + guarantees that the read operation does not produce an alignment fault.= =0D +=0D + If the Buffer is NULL, then ASSERT().=0D +=0D + @param Buffer The pointer to a 24-bit value that may be unaligned.=0D +=0D + @return The 24-bit value read from Buffer.=0D +=0D +**/=0D +UINT32=0D +EFIAPI=0D +ReadUnaligned24 (=0D + IN CONST UINT32 *Buffer=0D + )=0D +{=0D + ASSERT (Buffer !=3D NULL);=0D +=0D + return (UINT32)(=0D + ReadUnaligned16 ((UINT16*)Buffer) |=0D + (((UINT8*)Buffer)[2] << 16)=0D + );=0D +}=0D +=0D +/**=0D + Writes a 24-bit value to memory that may be unaligned.=0D +=0D + This function writes the 24-bit value specified by Value to Buffer. Valu= e is=0D + returned. The function guarantees that the write operation does not prod= uce=0D + an alignment fault.=0D +=0D + If the Buffer is NULL, then ASSERT().=0D +=0D + @param Buffer The pointer to a 24-bit value that may be unaligned.=0D + @param Value 24-bit value to write to Buffer.=0D +=0D + @return The 24-bit value to write to Buffer.=0D +=0D +**/=0D +UINT32=0D +EFIAPI=0D +WriteUnaligned24 (=0D + OUT UINT32 *Buffer,=0D + IN UINT32 Value=0D + )=0D +{=0D + ASSERT (Buffer !=3D NULL);=0D +=0D + WriteUnaligned16 ((UINT16*)Buffer, (UINT16)Value);=0D + *(UINT8*)((UINT16*)Buffer + 1) =3D (UINT8)(Value >> 16);=0D + return Value;=0D +}=0D +=0D +/**=0D + Reads a 32-bit value from memory that may be unaligned.=0D +=0D + This function returns the 32-bit value pointed to by Buffer. The functio= n=0D + guarantees that the read operation does not produce an alignment fault.= =0D +=0D + If the Buffer is NULL, then ASSERT().=0D +=0D + @param Buffer The pointer to a 32-bit value that may be unaligned.=0D +=0D + @return The 32-bit value read from Buffer.=0D +=0D +**/=0D +UINT32=0D +EFIAPI=0D +ReadUnaligned32 (=0D + IN CONST UINT32 *Buffer=0D + )=0D +{=0D + UINT16 LowerBytes;=0D + UINT16 HigherBytes;=0D +=0D + ASSERT (Buffer !=3D NULL);=0D +=0D + LowerBytes =3D ReadUnaligned16 ((UINT16*) Buffer);=0D + HigherBytes =3D ReadUnaligned16 ((UINT16*) Buffer + 1);=0D +=0D + return (UINT32) (LowerBytes | (HigherBytes << 16));=0D +}=0D +=0D +/**=0D + Writes a 32-bit value to memory that may be unaligned.=0D +=0D + This function writes the 32-bit value specified by Value to Buffer. Valu= e is=0D + returned. The function guarantees that the write operation does not prod= uce=0D + an alignment fault.=0D +=0D + If the Buffer is NULL, then ASSERT().=0D +=0D + @param Buffer The pointer to a 32-bit value that may be unaligned.=0D + @param Value 32-bit value to write to Buffer.=0D +=0D + @return The 32-bit value to write to Buffer.=0D +=0D +**/=0D +UINT32=0D +EFIAPI=0D +WriteUnaligned32 (=0D + OUT UINT32 *Buffer,=0D + IN UINT32 Value=0D + )=0D +{=0D + ASSERT (Buffer !=3D NULL);=0D +=0D + WriteUnaligned16 ((UINT16*)Buffer, (UINT16)Value);=0D + WriteUnaligned16 ((UINT16*)Buffer + 1, (UINT16)(Value >> 16));=0D + return Value;=0D +}=0D +=0D +/**=0D + Reads a 64-bit value from memory that may be unaligned.=0D +=0D + This function returns the 64-bit value pointed to by Buffer. The functio= n=0D + guarantees that the read operation does not produce an alignment fault.= =0D +=0D + If the Buffer is NULL, then ASSERT().=0D +=0D + @param Buffer The pointer to a 64-bit value that may be unaligned.=0D +=0D + @return The 64-bit value read from Buffer.=0D +=0D +**/=0D +UINT64=0D +EFIAPI=0D +ReadUnaligned64 (=0D + IN CONST UINT64 *Buffer=0D + )=0D +{=0D + UINT32 LowerBytes;=0D + UINT32 HigherBytes;=0D +=0D + ASSERT (Buffer !=3D NULL);=0D +=0D + LowerBytes =3D ReadUnaligned32 ((UINT32*) Buffer);=0D + HigherBytes =3D ReadUnaligned32 ((UINT32*) Buffer + 1);=0D +=0D + return (UINT64) (LowerBytes | LShiftU64 (HigherBytes, 32));=0D +}=0D +=0D +/**=0D + Writes a 64-bit value to memory that may be unaligned.=0D +=0D + This function writes the 64-bit value specified by Value to Buffer. Valu= e is=0D + returned. The function guarantees that the write operation does not prod= uce=0D + an alignment fault.=0D +=0D + If the Buffer is NULL, then ASSERT().=0D +=0D + @param Buffer The pointer to a 64-bit value that may be unaligned.=0D + @param Value 64-bit value to write to Buffer.=0D +=0D + @return The 64-bit value to write to Buffer.=0D +=0D +**/=0D +UINT64=0D +EFIAPI=0D +WriteUnaligned64 (=0D + OUT UINT64 *Buffer,=0D + IN UINT64 Value=0D + )=0D +{=0D + ASSERT (Buffer !=3D NULL);=0D +=0D + WriteUnaligned32 ((UINT32*)Buffer, (UINT32)Value);=0D + WriteUnaligned32 ((UINT32*)Buffer + 1, (UINT32)RShiftU64 (Value, 32));=0D + return Value;=0D +}=0D --=20 2.27.0