* [edk2-platforms][PATCH V1 0/6] Add non-discoverable IO block for Rd-N2
@ 2022-02-14 12:13 Vivek Kumar Gautam
2022-02-14 12:13 ` [edk2-platforms][PATCH V1 1/6] Platform/Sgi: add PCDs for SMMUv3 base address and interrupts Vivek Kumar Gautam
` (5 more replies)
0 siblings, 6 replies; 10+ messages in thread
From: Vivek Kumar Gautam @ 2022-02-14 12:13 UTC (permalink / raw)
To: devel; +Cc: Sami Mujawar, Ard Biesheuvel, Leif Lindholm, Vivek Gautam
Arm reference design platforms such as RD-N2 and RD-N2-Cfg1 have multiple
I/O virtualization blocks that allow connecting PCIe root bus or non-PCIe
(non-discoverable) devices to the system. Each of the I/O virtualization
blocks consists of an Arm SMMUv3 compliant MMU-700 controller to handle
address translations and a GIC-700 Interrupt Translation Service (ITS)
to support message signaled interrupts (MSIs).
Platforms can connect various devices to these I/O virtualization blocks
through x4/x8/x16 ports exposed by the system. For example, there are two
PL011 UART controllers and two PL330 DMA controllers connected to the
non-PCIe IO virtualization block on RD-N2 and RD-N2-Cfg1 platforms.
This patch series adds ACPI table support - SSDT and IORT, for Rd-N2 and
Rd-N2-Cfg1 platforms to describe the devices connected devices to the I/O
virtualization block. The patches also add suppot for platform DXE driver
to initialize the UART controllers connected on Rd-N2 and Rd-N2-Cfg1
platforms.
More details on how to obtain the platform software stack and how to test
non-discoverable I/O virtualization blocks can be found on gitlab:
https://gitlab.arm.com/arm-reference-solutions/arm-reference-solutions-docs/-/blob/master/docs/infra/common/iovirt_nonpcie.rst
Link to github branch with the patches in this series -
https://github.com/vivgau01/edk2-platforms/tree/topics/non-PCI-IO-virt-blk
Shriram K (1):
Platform/Sgi: Initialize additional uart controllers
Vivek Gautam (5):
Platform/Sgi: add PCDs for SMMUv3 base address and interrupts
Platform/Sgi: add ssdt table for non-discoverable IO virtualization
block
Platform/Sgi: add helper macros for ITS, SMMUv3 and DMA IORT nodes
Platform/Sgi: add IORT table for I/O virtualization block on
RD-N2-Cfg1
Platform/Sgi: add IORT table for I/O virtualization block on RD-N2
Platform/ARM/SgiPkg/SgiPlatform.dec | 56 ++++-
Platform/ARM/SgiPkg/SgiMemoryMap.dsc.inc | 6 +-
Platform/ARM/SgiPkg/SgiMemoryMap2.dsc.inc | 49 ++++-
Platform/ARM/SgiPkg/RdN2/RdN2.dsc | 4 +
Platform/ARM/SgiPkg/RdN2Cfg1/RdN2Cfg1.dsc | 6 +-
.../SgiPkg/AcpiTables/RdE1EdgeAcpiTables.inf | 8 +-
.../SgiPkg/AcpiTables/RdN1EdgeAcpiTables.inf | 8 +-
.../AcpiTables/RdN1EdgeX2AcpiTables.inf | 8 +-
.../ARM/SgiPkg/AcpiTables/RdN2AcpiTables.inf | 58 ++++-
.../SgiPkg/AcpiTables/RdN2Cfg1AcpiTables.inf | 57 ++++-
.../ARM/SgiPkg/AcpiTables/RdV1AcpiTables.inf | 8 +-
.../SgiPkg/AcpiTables/RdV1McAcpiTables.inf | 8 +-
.../SgiPkg/AcpiTables/Sgi575AcpiTables.inf | 8 +-
.../Drivers/PlatformDxe/PlatformDxe.inf | 7 +-
.../Library/PlatformLib/PlatformLib.inf | 8 +-
Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h | 197 ++++++++++++++++-
.../SgiPkg/Drivers/PlatformDxe/PlatformDxe.c | 73 ++++++-
.../Library/PlatformLib/PlatformLibMem.c | 19 +-
Platform/ARM/SgiPkg/AcpiTables/Iort.aslc | 14 +-
.../AcpiTables/RdN2/IortNonPciIoVirtBlk.aslc | 58 +++++
.../RdN2Cfg1/IortNonPciIoVirtBlk.aslc | 58 +++++
.../SgiPkg/AcpiTables/SsdtNonPciIoVirtBlk.asl | 203 ++++++++++++++++++
22 files changed, 890 insertions(+), 31 deletions(-)
create mode 100644 Platform/ARM/SgiPkg/AcpiTables/RdN2/IortNonPciIoVirtBlk.aslc
create mode 100644 Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/IortNonPciIoVirtBlk.aslc
create mode 100644 Platform/ARM/SgiPkg/AcpiTables/SsdtNonPciIoVirtBlk.asl
--
2.17.1
^ permalink raw reply [flat|nested] 10+ messages in thread
* [edk2-platforms][PATCH V1 1/6] Platform/Sgi: add PCDs for SMMUv3 base address and interrupts
2022-02-14 12:13 [edk2-platforms][PATCH V1 0/6] Add non-discoverable IO block for Rd-N2 Vivek Kumar Gautam
@ 2022-02-14 12:13 ` Vivek Kumar Gautam
2022-02-14 12:13 ` [edk2-platforms][PATCH V1 2/6] Platform/Sgi: add ssdt table for non-discoverable IO virtualization block Vivek Kumar Gautam
` (4 subsequent siblings)
5 siblings, 0 replies; 10+ messages in thread
From: Vivek Kumar Gautam @ 2022-02-14 12:13 UTC (permalink / raw)
To: devel; +Cc: Sami Mujawar, Ard Biesheuvel, Leif Lindholm, Vivek Gautam
The SMMUv3 node in IORT table requires interrupt vector information
of 4 programmable interrupts - Event, PRI, Global error, and Sync.
In addition to these interrupt vectors, DeviceID information is
required to support MSI interrupts using GIC ITS block. Add the
PCD entries for SMMUv3 base address, the interrupt vectors, and
the MSI DeviceID, and update SMMUv3 node to use these PCDs rather
than using hardcoded values.
Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
Signed-off-by: Vivek Gautam <vivek.gautam@arm.com>
---
Platform/ARM/SgiPkg/SgiPlatform.dec | 7 ++++++-
Platform/ARM/SgiPkg/SgiMemoryMap.dsc.inc | 6 +++++-
Platform/ARM/SgiPkg/SgiMemoryMap2.dsc.inc | 3 ++-
Platform/ARM/SgiPkg/AcpiTables/RdE1EdgeAcpiTables.inf | 8 +++++++-
Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeAcpiTables.inf | 8 +++++++-
Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2AcpiTables.inf | 8 +++++++-
Platform/ARM/SgiPkg/AcpiTables/RdV1AcpiTables.inf | 8 +++++++-
Platform/ARM/SgiPkg/AcpiTables/RdV1McAcpiTables.inf | 8 +++++++-
Platform/ARM/SgiPkg/AcpiTables/Sgi575AcpiTables.inf | 8 +++++++-
Platform/ARM/SgiPkg/AcpiTables/Iort.aslc | 14 +++++++-------
10 files changed, 62 insertions(+), 16 deletions(-)
diff --git a/Platform/ARM/SgiPkg/SgiPlatform.dec b/Platform/ARM/SgiPkg/SgiPlatform.dec
index 8cd818a9bf64..05079743c452 100644
--- a/Platform/ARM/SgiPkg/SgiPlatform.dec
+++ b/Platform/ARM/SgiPkg/SgiPlatform.dec
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2018-2020, ARM Limited. All rights reserved.
+# Copyright (c) 2018-2022, ARM Limited. All rights reserved.
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -75,6 +75,11 @@
# SMMU
gArmSgiTokenSpaceGuid.PcdSmmuBase|0|UINT32|0x0000001D
gArmSgiTokenSpaceGuid.PcdSmmuSize|0|UINT32|0x0000001E
+ gArmSgiTokenSpaceGuid.PcdSmmuEventGsiv|0|UINT32|0x00000027
+ gArmSgiTokenSpaceGuid.PcdSmmuGErrorGsiv|0|UINT32|0x00000028
+ gArmSgiTokenSpaceGuid.PcdSmmuPriGsiv|0|UINT32|0x00000029
+ gArmSgiTokenSpaceGuid.PcdSmmuSyncGsiv|0|UINT32|0x0000002A
+ gArmSgiTokenSpaceGuid.PcdSmmuDevIDBase|0|UINT32|0x0000002B
# GPIO Controller
gArmSgiTokenSpaceGuid.PcdGpioController0BaseAddress|0|UINT32|0x0000001F
diff --git a/Platform/ARM/SgiPkg/SgiMemoryMap.dsc.inc b/Platform/ARM/SgiPkg/SgiMemoryMap.dsc.inc
index 76707be73d7b..6430af346404 100644
--- a/Platform/ARM/SgiPkg/SgiMemoryMap.dsc.inc
+++ b/Platform/ARM/SgiPkg/SgiMemoryMap.dsc.inc
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2020, ARM Limited. All rights reserved.
+# Copyright (c) 2020-2022, ARM Limited. All rights reserved.
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -59,6 +59,10 @@
# SMMU
gArmSgiTokenSpaceGuid.PcdSmmuBase|0x4F000000
gArmSgiTokenSpaceGuid.PcdSmmuSize|0x01000000
+ gArmSgiTokenSpaceGuid.PcdSmmuEventGsiv|260
+ gArmSgiTokenSpaceGuid.PcdSmmuGErrorGsiv|262
+ gArmSgiTokenSpaceGuid.PcdSmmuSyncGsiv|261
+ gArmSgiTokenSpaceGuid.PcdSmmuDevIDBase|0x10000
# GPIO Controller
gArmSgiTokenSpaceGuid.PcdGpioController0BaseAddress|0x1C1D0000
diff --git a/Platform/ARM/SgiPkg/SgiMemoryMap2.dsc.inc b/Platform/ARM/SgiPkg/SgiMemoryMap2.dsc.inc
index 2d612f9b9674..94be353ca3ab 100644
--- a/Platform/ARM/SgiPkg/SgiMemoryMap2.dsc.inc
+++ b/Platform/ARM/SgiPkg/SgiMemoryMap2.dsc.inc
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2020, ARM Limited. All rights reserved.
+# Copyright (c) 2020-2022, ARM Limited. All rights reserved.
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -59,6 +59,7 @@
# SMMU
gArmSgiTokenSpaceGuid.PcdSmmuBase|0x40000000
gArmSgiTokenSpaceGuid.PcdSmmuSize|0x10000000
+ gArmSgiTokenSpaceGuid.PcdSmmuDevIDBase|0x80000
# GPIO controller
gArmSgiTokenSpaceGuid.PcdGpioController0BaseAddress|0x0C1D0000
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdE1EdgeAcpiTables.inf b/Platform/ARM/SgiPkg/AcpiTables/RdE1EdgeAcpiTables.inf
index 8c34c2fa73e4..0418b9ab2631 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdE1EdgeAcpiTables.inf
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdE1EdgeAcpiTables.inf
@@ -1,7 +1,7 @@
## @file
# ACPI table data and ASL sources required to boot the platform.
#
-# Copyright (c) 2018-2021, ARM Ltd. All rights reserved.
+# Copyright (c) 2018-2022, ARM Ltd. All rights reserved.
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -57,6 +57,12 @@
gArmSgiTokenSpaceGuid.PcdGpioController0Interrupt
gArmSgiTokenSpaceGuid.PcdGtFrame0Gsiv
gArmSgiTokenSpaceGuid.PcdGtFrame1Gsiv
+ gArmSgiTokenSpaceGuid.PcdSmmuBase
+ gArmSgiTokenSpaceGuid.PcdSmmuEventGsiv
+ gArmSgiTokenSpaceGuid.PcdSmmuGErrorGsiv
+ gArmSgiTokenSpaceGuid.PcdSmmuPriGsiv
+ gArmSgiTokenSpaceGuid.PcdSmmuSyncGsiv
+ gArmSgiTokenSpaceGuid.PcdSmmuDevIDBase
gArmSgiTokenSpaceGuid.PcdSp804DualTimerBaseAddress
gArmSgiTokenSpaceGuid.PcdSp804DualTimerSize
gArmSgiTokenSpaceGuid.PcdSp804DualTimerInterrupt
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeAcpiTables.inf b/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeAcpiTables.inf
index ce89aa93ea7b..600feb2453b7 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeAcpiTables.inf
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeAcpiTables.inf
@@ -1,7 +1,7 @@
## @file
# ACPI table data and ASL sources required to boot the platform.
#
-# Copyright (c) 2018-2021, ARM Ltd. All rights reserved.
+# Copyright (c) 2018-2022, ARM Ltd. All rights reserved.
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -58,6 +58,12 @@
gArmSgiTokenSpaceGuid.PcdGtFrame0Gsiv
gArmSgiTokenSpaceGuid.PcdGtFrame1Gsiv
gArmSgiTokenSpaceGuid.PcdOscLpiEnable
+ gArmSgiTokenSpaceGuid.PcdSmmuBase
+ gArmSgiTokenSpaceGuid.PcdSmmuEventGsiv
+ gArmSgiTokenSpaceGuid.PcdSmmuGErrorGsiv
+ gArmSgiTokenSpaceGuid.PcdSmmuPriGsiv
+ gArmSgiTokenSpaceGuid.PcdSmmuSyncGsiv
+ gArmSgiTokenSpaceGuid.PcdSmmuDevIDBase
gArmSgiTokenSpaceGuid.PcdSp804DualTimerBaseAddress
gArmSgiTokenSpaceGuid.PcdSp804DualTimerSize
gArmSgiTokenSpaceGuid.PcdSp804DualTimerInterrupt
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2AcpiTables.inf b/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2AcpiTables.inf
index 1999bc1553e9..c11f5e35c536 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2AcpiTables.inf
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2AcpiTables.inf
@@ -1,7 +1,7 @@
## @file
# ACPI table data and ASL sources required to boot the platform.
#
-# Copyright (c) 2020-2021, ARM Ltd. All rights reserved.
+# Copyright (c) 2020-2022, ARM Ltd. All rights reserved.
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -67,6 +67,12 @@
gArmSgiTokenSpaceGuid.PcdGtFrame0Gsiv
gArmSgiTokenSpaceGuid.PcdGtFrame1Gsiv
gArmSgiTokenSpaceGuid.PcdOscLpiEnable
+ gArmSgiTokenSpaceGuid.PcdSmmuBase
+ gArmSgiTokenSpaceGuid.PcdSmmuEventGsiv
+ gArmSgiTokenSpaceGuid.PcdSmmuGErrorGsiv
+ gArmSgiTokenSpaceGuid.PcdSmmuPriGsiv
+ gArmSgiTokenSpaceGuid.PcdSmmuSyncGsiv
+ gArmSgiTokenSpaceGuid.PcdSmmuDevIDBase
gArmSgiTokenSpaceGuid.PcdSp804DualTimerBaseAddress
gArmSgiTokenSpaceGuid.PcdSp804DualTimerSize
gArmSgiTokenSpaceGuid.PcdSp804DualTimerInterrupt
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdV1AcpiTables.inf b/Platform/ARM/SgiPkg/AcpiTables/RdV1AcpiTables.inf
index 97a87462932b..6afab12bef28 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdV1AcpiTables.inf
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdV1AcpiTables.inf
@@ -1,7 +1,7 @@
## @file
# ACPI table data and ASL sources required to boot the platform.
#
-# Copyright (c) 2020-2021, Arm Ltd. All rights reserved.
+# Copyright (c) 2020-2022, Arm Ltd. All rights reserved.
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -59,6 +59,12 @@
gArmSgiTokenSpaceGuid.PcdGtFrame1Gsiv
gArmSgiTokenSpaceGuid.PcdOscLpiEnable
gArmSgiTokenSpaceGuid.PcdOscCppcEnable
+ gArmSgiTokenSpaceGuid.PcdSmmuBase
+ gArmSgiTokenSpaceGuid.PcdSmmuEventGsiv
+ gArmSgiTokenSpaceGuid.PcdSmmuGErrorGsiv
+ gArmSgiTokenSpaceGuid.PcdSmmuPriGsiv
+ gArmSgiTokenSpaceGuid.PcdSmmuSyncGsiv
+ gArmSgiTokenSpaceGuid.PcdSmmuDevIDBase
gArmSgiTokenSpaceGuid.PcdSp804DualTimerBaseAddress
gArmSgiTokenSpaceGuid.PcdSp804DualTimerSize
gArmSgiTokenSpaceGuid.PcdSp804DualTimerInterrupt
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdV1McAcpiTables.inf b/Platform/ARM/SgiPkg/AcpiTables/RdV1McAcpiTables.inf
index deaca3719ae4..d34ce2b77344 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdV1McAcpiTables.inf
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdV1McAcpiTables.inf
@@ -1,7 +1,7 @@
## @file
# ACPI table data and ASL sources required to boot the platform.
#
-# Copyright (c) 2020-2021, Arm Ltd. All rights reserved.
+# Copyright (c) 2020-2022, Arm Ltd. All rights reserved.
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -68,6 +68,12 @@
gArmSgiTokenSpaceGuid.PcdGtFrame1Gsiv
gArmSgiTokenSpaceGuid.PcdOscLpiEnable
gArmSgiTokenSpaceGuid.PcdOscCppcEnable
+ gArmSgiTokenSpaceGuid.PcdSmmuBase
+ gArmSgiTokenSpaceGuid.PcdSmmuEventGsiv
+ gArmSgiTokenSpaceGuid.PcdSmmuGErrorGsiv
+ gArmSgiTokenSpaceGuid.PcdSmmuPriGsiv
+ gArmSgiTokenSpaceGuid.PcdSmmuSyncGsiv
+ gArmSgiTokenSpaceGuid.PcdSmmuDevIDBase
gArmSgiTokenSpaceGuid.PcdSp804DualTimerBaseAddress
gArmSgiTokenSpaceGuid.PcdSp804DualTimerSize
gArmSgiTokenSpaceGuid.PcdSp804DualTimerInterrupt
diff --git a/Platform/ARM/SgiPkg/AcpiTables/Sgi575AcpiTables.inf b/Platform/ARM/SgiPkg/AcpiTables/Sgi575AcpiTables.inf
index a1bd71fde761..04d0a61d1794 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/Sgi575AcpiTables.inf
+++ b/Platform/ARM/SgiPkg/AcpiTables/Sgi575AcpiTables.inf
@@ -1,7 +1,7 @@
## @file
# ACPI table data and ASL sources required to boot the platform.
#
-# Copyright (c) 2018 - 2021, ARM Ltd. All rights reserved.
+# Copyright (c) 2018 - 2022, ARM Ltd. All rights reserved.
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -58,6 +58,12 @@
gArmSgiTokenSpaceGuid.PcdGtFrame0Gsiv
gArmSgiTokenSpaceGuid.PcdGtFrame1Gsiv
gArmSgiTokenSpaceGuid.PcdOscLpiEnable
+ gArmSgiTokenSpaceGuid.PcdSmmuBase
+ gArmSgiTokenSpaceGuid.PcdSmmuEventGsiv
+ gArmSgiTokenSpaceGuid.PcdSmmuGErrorGsiv
+ gArmSgiTokenSpaceGuid.PcdSmmuPriGsiv
+ gArmSgiTokenSpaceGuid.PcdSmmuSyncGsiv
+ gArmSgiTokenSpaceGuid.PcdSmmuDevIDBase
gArmSgiTokenSpaceGuid.PcdSp804DualTimerBaseAddress
gArmSgiTokenSpaceGuid.PcdSp804DualTimerSize
gArmSgiTokenSpaceGuid.PcdSp804DualTimerInterrupt
diff --git a/Platform/ARM/SgiPkg/AcpiTables/Iort.aslc b/Platform/ARM/SgiPkg/AcpiTables/Iort.aslc
index fcc28a71c82e..462798664160 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/Iort.aslc
+++ b/Platform/ARM/SgiPkg/AcpiTables/Iort.aslc
@@ -1,7 +1,7 @@
/** @file
* I/O Remapping Table (Iort)
*
-* Copyright (c) 2018, ARM Ltd. All rights reserved.
+* Copyright (c) 2018-2022, ARM Ltd. All rights reserved.
*
* SPDX-License-Identifier: BSD-2-Clause-Patent
*
@@ -86,15 +86,15 @@ ARM_EFI_ACPI_6_0_IO_REMAPPING_TABLE Iort =
2, // NumIdMapping
OFFSET_OF (ARM_EFI_ACPI_6_0_IO_REMAPPING_SMMU3_NODE, SmmuIdMap), // IdReference
},
- 0x4F000000, // Base address
+ FixedPcdGet32 (PcdSmmuBase), // Base address
EFI_ACPI_IORT_SMMUv3_FLAG_COHAC_OVERRIDE, // Flags
0, // Reserved
0, // VATOS address
EFI_ACPI_IORT_SMMUv3_MODEL_GENERIC, // SMMUv3 Model
- 260, // Event
- 0, // Pri
- 262, // Gerror
- 261, // Sync
+ FixedPcdGet32 (PcdSmmuEventGsiv), // Event
+ FixedPcdGet32 (PcdSmmuPriGsiv), // Pri
+ FixedPcdGet32 (PcdSmmuGErrorGsiv), // Gerror
+ FixedPcdGet32 (PcdSmmuSyncGsiv), // Sync
0, // Proximity domain
1, // DevIDMappingIndex
},
@@ -110,7 +110,7 @@ ARM_EFI_ACPI_6_0_IO_REMAPPING_TABLE Iort =
{
0x0, // InputBase
0x1, // NumIds
- 0x10000, // OutputBase
+ FixedPcdGet32 (PcdSmmuDevIDBase), // OutputBase
OFFSET_OF (ARM_EFI_ACPI_6_0_IO_REMAPPING_TABLE, ItsNode), // OutputReference
EFI_ACPI_IORT_ID_MAPPING_FLAGS_SINGLE, // Flags
},
--
2.17.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [edk2-platforms][PATCH V1 2/6] Platform/Sgi: add ssdt table for non-discoverable IO virtualization block
2022-02-14 12:13 [edk2-platforms][PATCH V1 0/6] Add non-discoverable IO block for Rd-N2 Vivek Kumar Gautam
2022-02-14 12:13 ` [edk2-platforms][PATCH V1 1/6] Platform/Sgi: add PCDs for SMMUv3 base address and interrupts Vivek Kumar Gautam
@ 2022-02-14 12:13 ` Vivek Kumar Gautam
2022-12-07 13:34 ` [edk2-devel] " PierreGondois
2022-02-14 12:13 ` [edk2-platforms][PATCH V1 3/6] Platform/Sgi: Initialize additional uart controllers Vivek Kumar Gautam
` (3 subsequent siblings)
5 siblings, 1 reply; 10+ messages in thread
From: Vivek Kumar Gautam @ 2022-02-14 12:13 UTC (permalink / raw)
To: devel; +Cc: Sami Mujawar, Ard Biesheuvel, Leif Lindholm, Vivek Gautam
Arm reference design platforms such as RD-N2 and RD-N2-Cfg1 have multiple
IO virtualization blocks that allow connecting PCIe root bus or non-PCIe
devices to the system. For platforms that connect non-discoverable (non-
PCI) devices to IO virtualization block, add a SSDT table to describe
such devices and use PCDs for the memory region and interrupts of these
devices in the table entry.
There are two PL011 UART controllers and two PL330 DMA controllers
connected to the non-PCIe IO virtualization block on RD-N2 and
RD-N2-Cfg1 platforms. List them in the SSDT ACPI table.
While we are adding SSDT table entries for RD-N2 and RD-N2-Cfg1
remove the source file entries for incorrect SSDT and MCFG tables
for RD-N2 and RD-N2-Cfg1 platforms.
Signed-off-by: Vivek Gautam <vivek.gautam@arm.com>
---
Platform/ARM/SgiPkg/SgiPlatform.dec | 42 ++++
Platform/ARM/SgiPkg/SgiMemoryMap2.dsc.inc | 40 ++++
Platform/ARM/SgiPkg/AcpiTables/RdN2AcpiTables.inf | 45 ++++-
Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1AcpiTables.inf | 45 ++++-
Platform/ARM/SgiPkg/AcpiTables/SsdtNonPciIoVirtBlk.asl | 203 ++++++++++++++++++++
5 files changed, 369 insertions(+), 6 deletions(-)
diff --git a/Platform/ARM/SgiPkg/SgiPlatform.dec b/Platform/ARM/SgiPkg/SgiPlatform.dec
index 05079743c452..6b3e28c3a08e 100644
--- a/Platform/ARM/SgiPkg/SgiPlatform.dec
+++ b/Platform/ARM/SgiPkg/SgiPlatform.dec
@@ -95,5 +95,47 @@
gArmSgiTokenSpaceGuid.PcdOscLpiEnable|0|UINT32|0x00000025
gArmSgiTokenSpaceGuid.PcdOscCppcEnable|0|UINT32|0x00000026
+ # IO virtualization block PL011 UARTs
+ gArmSgiTokenSpaceGuid.PcdIoVirtBlkUart0Base|0|UINT64|0x0000002C
+ gArmSgiTokenSpaceGuid.PcdIoVirtBlkUart0End|0|UINT64|0x0000002D
+ gArmSgiTokenSpaceGuid.PcdIoVirtBlkUart0Size|0|UINT64|0x0000002E
+ gArmSgiTokenSpaceGuid.PcdIoVirtBlkUart0Interrupt|0|UINT32|0x0000002F
+
+ gArmSgiTokenSpaceGuid.PcdIoVirtBlkUart1Base|0|UINT64|0x00000030
+ gArmSgiTokenSpaceGuid.PcdIoVirtBlkUart1End|0|UINT64|0x00000031
+ gArmSgiTokenSpaceGuid.PcdIoVirtBlkUart1Size|0|UINT64|0x00000032
+ gArmSgiTokenSpaceGuid.PcdIoVirtBlkUart1Interrupt|0|UINT32|0x00000033
+
+ # IO virtualization block PL330 DMA controllers
+ gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma0Base|0|UINT64|0x00000034
+ gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma0End|0|UINT64|0x00000035
+ gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma0Size|0|UINT32|0x00000036
+ gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma0NumCh|0|UINT32|0x00000037
+ gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma0Ch0Gsiv|0|UINT32|0x00000038
+ gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma0Ch1Gsiv|0|UINT32|0x00000039
+ gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma0Ch2Gsiv|0|UINT32|0x0000003A
+ gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma0Ch3Gsiv|0|UINT32|0x0000003B
+ gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma0Ch4Gsiv|0|UINT32|0x0000003C
+ gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma0Ch5Gsiv|0|UINT32|0x0000003D
+ gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma0Ch6Gsiv|0|UINT32|0x0000003E
+ gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma0Ch7Gsiv|0|UINT32|0x0000003F
+ gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma0AbortGsiv|0|UINT32|0x00000040
+ gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma0StreamIDBase|0|UINT32|0x00000041
+
+ gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma1Base|0|UINT64|0x00000042
+ gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma1End|0|UINT64|0x00000043
+ gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma1Size|0|UINT32|0x00000044
+ gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma1NumCh|0|UINT32|0x00000045
+ gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma1Ch0Gsiv|0|UINT32|0x00000046
+ gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma1Ch1Gsiv|0|UINT32|0x00000047
+ gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma1Ch2Gsiv|0|UINT32|0x00000048
+ gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma1Ch3Gsiv|0|UINT32|0x00000049
+ gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma1Ch4Gsiv|0|UINT32|0x0000004A
+ gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma1Ch5Gsiv|0|UINT32|0x0000004B
+ gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma1Ch6Gsiv|0|UINT32|0x0000004C
+ gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma1Ch7Gsiv|0|UINT32|0x0000004D
+ gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma1AbortGsiv|0|UINT32|0x0000004E
+ gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma1StreamIDBase|0|UINT32|0x0000004F
+
[Ppis]
gNtFwConfigDtInfoPpiGuid = { 0x6f606eb3, 0x9123, 0x4e15, { 0xa8, 0x9b, 0x0f, 0xac, 0x66, 0xef, 0xd0, 0x17 } }
diff --git a/Platform/ARM/SgiPkg/SgiMemoryMap2.dsc.inc b/Platform/ARM/SgiPkg/SgiMemoryMap2.dsc.inc
index 94be353ca3ab..472795193b9e 100644
--- a/Platform/ARM/SgiPkg/SgiMemoryMap2.dsc.inc
+++ b/Platform/ARM/SgiPkg/SgiMemoryMap2.dsc.inc
@@ -65,3 +65,43 @@
gArmSgiTokenSpaceGuid.PcdGpioController0BaseAddress|0x0C1D0000
gArmSgiTokenSpaceGuid.PcdGpioController0Size|0x00010000
gArmSgiTokenSpaceGuid.PcdGpioController0Interrupt|392
+
+ # IO virtualization block PL011 UARTs
+ gArmSgiTokenSpaceGuid.PcdIoVirtBlkUart0Base|0xC00000000000
+ gArmSgiTokenSpaceGuid.PcdIoVirtBlkUart0End|0xC0000000FFFF
+ gArmSgiTokenSpaceGuid.PcdIoVirtBlkUart0Size|0x10000
+ gArmSgiTokenSpaceGuid.PcdIoVirtBlkUart0Interrupt|492
+
+ gArmSgiTokenSpaceGuid.PcdIoVirtBlkUart1Base|0xC00020000000
+ gArmSgiTokenSpaceGuid.PcdIoVirtBlkUart1End|0xC0002000FFFF
+ gArmSgiTokenSpaceGuid.PcdIoVirtBlkUart1Size|0x10000
+ gArmSgiTokenSpaceGuid.PcdIoVirtBlkUart1Interrupt|502
+
+ # IO virtualization block PL330 DMA controllers
+ gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma0Base|0xC00010000000
+ gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma0End|0xC0001000FFFF
+ gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma0Size|0x10000
+ gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma0NumCh|8
+ gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma0Ch0Gsiv|493
+ gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma0Ch1Gsiv|494
+ gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma0Ch2Gsiv|495
+ gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma0Ch3Gsiv|496
+ gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma0Ch4Gsiv|497
+ gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma0Ch5Gsiv|498
+ gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma0Ch6Gsiv|499
+ gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma0Ch7Gsiv|500
+ gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma0AbortGsiv|501
+
+ gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma1Base|0xC00030000000
+ gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma1End|0xC0003000FFFF
+ gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma1Size|0x10000
+ gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma1NumCh|8
+ gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma1Ch0Gsiv|503
+ gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma1Ch1Gsiv|504
+ gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma1Ch2Gsiv|505
+ gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma1Ch3Gsiv|506
+ gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma1Ch4Gsiv|507
+ gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma1Ch5Gsiv|508
+ gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma1Ch6Gsiv|509
+ gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma1Ch7Gsiv|510
+ gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma1AbortGsiv|511
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN2AcpiTables.inf b/Platform/ARM/SgiPkg/AcpiTables/RdN2AcpiTables.inf
index 25be2e276e85..fe50a7b6e44a 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdN2AcpiTables.inf
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN2AcpiTables.inf
@@ -1,7 +1,7 @@
## @file
# ACPI table data and ASL sources required to boot the platform.
#
-# Copyright (c) 2020-2021, Arm Ltd. All rights reserved.
+# Copyright (c) 2020-2022, Arm Ltd. All rights reserved.
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -19,14 +19,13 @@
Fadt.aslc
Gtdt.aslc
Iort.aslc
- Mcfg.aslc
RdN2/Dsdt.asl
RdN2/Madt.aslc
RdN2/Pptt.aslc
Spcr.aslc
- Ssdt.asl
SsdtRos.asl
SsdtEvents.asl
+ SsdtNonPciIoVirtBlk.asl
[Packages]
ArmPkg/ArmPkg.dec
@@ -71,4 +70,44 @@
gArmSgiTokenSpaceGuid.PcdWdogWS0Gsiv
gArmSgiTokenSpaceGuid.PcdWdogWS1Gsiv
+ gArmSgiTokenSpaceGuid.PcdIoVirtBlkUart0Base
+ gArmSgiTokenSpaceGuid.PcdIoVirtBlkUart0End
+ gArmSgiTokenSpaceGuid.PcdIoVirtBlkUart0Size
+ gArmSgiTokenSpaceGuid.PcdIoVirtBlkUart0Interrupt
+
+ gArmSgiTokenSpaceGuid.PcdIoVirtBlkUart1Base
+ gArmSgiTokenSpaceGuid.PcdIoVirtBlkUart1End
+ gArmSgiTokenSpaceGuid.PcdIoVirtBlkUart1Size
+ gArmSgiTokenSpaceGuid.PcdIoVirtBlkUart1Interrupt
+
+ gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma0Base
+ gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma0End
+ gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma0Size
+ gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma0NumCh
+ gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma0Ch0Gsiv
+ gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma0Ch1Gsiv
+ gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma0Ch2Gsiv
+ gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma0Ch3Gsiv
+ gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma0Ch4Gsiv
+ gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma0Ch5Gsiv
+ gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma0Ch6Gsiv
+ gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma0Ch7Gsiv
+ gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma0AbortGsiv
+ gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma0StreamIDBase
+
+ gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma1Base
+ gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma1End
+ gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma1Size
+ gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma1NumCh
+ gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma1Ch0Gsiv
+ gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma1Ch1Gsiv
+ gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma1Ch2Gsiv
+ gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma1Ch3Gsiv
+ gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma1Ch4Gsiv
+ gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma1Ch5Gsiv
+ gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma1Ch6Gsiv
+ gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma1Ch7Gsiv
+ gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma1AbortGsiv
+ gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma1StreamIDBase
+
gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1AcpiTables.inf b/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1AcpiTables.inf
index 4b36c3e5ceb2..b5612e817d01 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1AcpiTables.inf
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1AcpiTables.inf
@@ -1,7 +1,7 @@
## @file
# ACPI table data and ASL sources required to boot the platform.
#
-# Copyright (c) 2021, Arm Ltd. All rights reserved.
+# Copyright (c) 2021-2022, Arm Ltd. All rights reserved.
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -19,14 +19,13 @@
Fadt.aslc
Gtdt.aslc
Iort.aslc
- Mcfg.aslc
RdN2Cfg1/Dsdt.asl
RdN2Cfg1/Madt.aslc
RdN2Cfg1/Pptt.aslc
Spcr.aslc
- Ssdt.asl
SsdtRos.asl
SsdtEvents.asl
+ SsdtNonPciIoVirtBlk.asl
[Packages]
ArmPkg/ArmPkg.dec
@@ -72,4 +71,44 @@
gArmSgiTokenSpaceGuid.PcdWdogWS0Gsiv
gArmSgiTokenSpaceGuid.PcdWdogWS1Gsiv
+ gArmSgiTokenSpaceGuid.PcdIoVirtBlkUart0Base
+ gArmSgiTokenSpaceGuid.PcdIoVirtBlkUart0End
+ gArmSgiTokenSpaceGuid.PcdIoVirtBlkUart0Size
+ gArmSgiTokenSpaceGuid.PcdIoVirtBlkUart0Interrupt
+
+ gArmSgiTokenSpaceGuid.PcdIoVirtBlkUart1Base
+ gArmSgiTokenSpaceGuid.PcdIoVirtBlkUart1End
+ gArmSgiTokenSpaceGuid.PcdIoVirtBlkUart1Size
+ gArmSgiTokenSpaceGuid.PcdIoVirtBlkUart1Interrupt
+
+ gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma0Base
+ gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma0End
+ gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma0Size
+ gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma0NumCh
+ gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma0Ch0Gsiv
+ gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma0Ch1Gsiv
+ gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma0Ch2Gsiv
+ gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma0Ch3Gsiv
+ gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma0Ch4Gsiv
+ gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma0Ch5Gsiv
+ gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma0Ch6Gsiv
+ gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma0Ch7Gsiv
+ gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma0AbortGsiv
+ gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma0StreamIDBase
+
+ gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma1Base
+ gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma1End
+ gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma1Size
+ gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma1NumCh
+ gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma1Ch0Gsiv
+ gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma1Ch1Gsiv
+ gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma1Ch2Gsiv
+ gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma1Ch3Gsiv
+ gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma1Ch4Gsiv
+ gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma1Ch5Gsiv
+ gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma1Ch6Gsiv
+ gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma1Ch7Gsiv
+ gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma1AbortGsiv
+ gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma1StreamIDBase
+
gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
diff --git a/Platform/ARM/SgiPkg/AcpiTables/SsdtNonPciIoVirtBlk.asl b/Platform/ARM/SgiPkg/AcpiTables/SsdtNonPciIoVirtBlk.asl
new file mode 100644
index 000000000000..a035186b88db
--- /dev/null
+++ b/Platform/ARM/SgiPkg/AcpiTables/SsdtNonPciIoVirtBlk.asl
@@ -0,0 +1,203 @@
+/** @file
+ Secondary System Description Table (SSDT) for Non-PCIe IO
+ Virtualization Block.
+
+ The IO virtualization block present on reference design platforms
+ such as RD-N2 and RD-N2-Cfg1 allows connecting PCIe and non-PCIe
+ devices. The non-discoverable (non-PCIe) devices that are connected
+ to the IO virtualization block include two PL011 UART and two PL330
+ DMA controllers.
+
+ Copyright (c) 2022, Arm Ltd. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Specification Reference:
+ - ACPI 6.4, Chapter 5, Section 5.2.11.2, Secondary System Description Table
+**/
+
+#include "SgiPlatform.h"
+#include "SgiAcpiHeader.h"
+
+DefinitionBlock ("SsdtIoVirtBlk.aml", "SSDT", 2, "ARMLTD", "ARMSGI",
+ EFI_ACPI_ARM_OEM_REVISION) {
+ Scope (_SB) {
+
+ // IO Virtualization Block - PL011 UART0
+ Device (COM4) {
+ Name (_HID, "ARMH0011")
+ Name (_UID, 4)
+ Name (_STA, 0xF)
+
+ Name (_CRS, ResourceTemplate () {
+ QWordMemory (
+ ResourceProducer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0,
+ FixedPcdGet64 (PcdIoVirtBlkUart0Base),
+ FixedPcdGet64 (PcdIoVirtBlkUart0End),
+ 0x0,
+ FixedPcdGet32 (PcdIoVirtBlkUart0Size),
+ ,
+ ,
+ ,
+ AddressRangeMemory,
+ TypeStatic
+ )
+
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) {
+ FixedPcdGet32 (PcdIoVirtBlkUart0Interrupt)
+ }
+ })
+ }
+
+ // IO Virtualization Block - PL011 UART1
+ Device (COM5) {
+ Name (_HID, "ARMH0011")
+ Name (_UID, 5)
+ Name (_STA, 0xF)
+
+ Name (_CRS, ResourceTemplate () {
+ QWordMemory (
+ ResourceProducer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0,
+ FixedPcdGet64 (PcdIoVirtBlkUart1Base),
+ FixedPcdGet64 (PcdIoVirtBlkUart1End),
+ 0x0,
+ FixedPcdGet32 (PcdIoVirtBlkUart1Size),
+ ,
+ ,
+ ,
+ AddressRangeMemory,
+ TypeStatic
+ )
+
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) {
+ FixedPcdGet32 (PcdIoVirtBlkUart1Interrupt)
+ }
+ })
+ }
+
+ // IO Virtualization Block - PL330 DMA0
+ Device (\_SB.DMA0) {
+ Name (_HID, "ARMH0330")
+ Name (_UID, 0)
+ Name (_CCA, 1)
+ Name (_STA, 0xF)
+
+ Name (_CRS, ResourceTemplate () {
+ QWordMemory (
+ ResourceProducer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0,
+ FixedPcdGet64 (PcdIoVirtBlkDma0Base),
+ FixedPcdGet64 (PcdIoVirtBlkDma0End),
+ 0x0,
+ FixedPcdGet32 (PcdIoVirtBlkDma0Size),
+ ,
+ ,
+ ,
+ AddressRangeMemory,
+ TypeStatic
+ )
+
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) {
+ FixedPcdGet32 (PcdIoVirtBlkDma0Ch0Gsiv)
+ }
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) {
+ FixedPcdGet32 (PcdIoVirtBlkDma0Ch1Gsiv)
+ }
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) {
+ FixedPcdGet32 (PcdIoVirtBlkDma0Ch2Gsiv)
+ }
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) {
+ FixedPcdGet32 (PcdIoVirtBlkDma0Ch3Gsiv)
+ }
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) {
+ FixedPcdGet32 (PcdIoVirtBlkDma0Ch4Gsiv)
+ }
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) {
+ FixedPcdGet32 (PcdIoVirtBlkDma0Ch5Gsiv)
+ }
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) {
+ FixedPcdGet32 (PcdIoVirtBlkDma0Ch6Gsiv)
+ }
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) {
+ FixedPcdGet32 (PcdIoVirtBlkDma0Ch7Gsiv)
+ }
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) {
+ FixedPcdGet32 (PcdIoVirtBlkDma0AbortGsiv)
+ }
+ })
+ }
+
+ // IO Virtualization Block - PL330 DMA1
+ Device (\_SB.DMA1) {
+ Name (_HID, "ARMH0330")
+ Name (_UID, 1)
+ Name (_CCA, 1)
+ Name (_STA, 0xF)
+
+ Name (_CRS, ResourceTemplate () {
+ QWordMemory (
+ ResourceProducer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0,
+ FixedPcdGet64 (PcdIoVirtBlkDma1Base),
+ FixedPcdGet64 (PcdIoVirtBlkDma1End),
+ 0x0,
+ FixedPcdGet32 (PcdIoVirtBlkDma1Size),
+ ,
+ ,
+ ,
+ AddressRangeMemory,
+ TypeStatic
+ )
+
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) {
+ FixedPcdGet32 (PcdIoVirtBlkDma1Ch0Gsiv)
+ }
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) {
+ FixedPcdGet32 (PcdIoVirtBlkDma1Ch1Gsiv)
+ }
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) {
+ FixedPcdGet32 (PcdIoVirtBlkDma1Ch2Gsiv)
+ }
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) {
+ FixedPcdGet32 (PcdIoVirtBlkDma1Ch3Gsiv)
+ }
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) {
+ FixedPcdGet32 (PcdIoVirtBlkDma1Ch4Gsiv)
+ }
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) {
+ FixedPcdGet32 (PcdIoVirtBlkDma1Ch5Gsiv)
+ }
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) {
+ FixedPcdGet32 (PcdIoVirtBlkDma1Ch6Gsiv)
+ }
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) {
+ FixedPcdGet32 (PcdIoVirtBlkDma1Ch7Gsiv)
+ }
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) {
+ FixedPcdGet32 (PcdIoVirtBlkDma1AbortGsiv)
+ }
+ })
+ }
+ } // Scope(_SB)
+}
--
2.17.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [edk2-platforms][PATCH V1 3/6] Platform/Sgi: Initialize additional uart controllers
2022-02-14 12:13 [edk2-platforms][PATCH V1 0/6] Add non-discoverable IO block for Rd-N2 Vivek Kumar Gautam
2022-02-14 12:13 ` [edk2-platforms][PATCH V1 1/6] Platform/Sgi: add PCDs for SMMUv3 base address and interrupts Vivek Kumar Gautam
2022-02-14 12:13 ` [edk2-platforms][PATCH V1 2/6] Platform/Sgi: add ssdt table for non-discoverable IO virtualization block Vivek Kumar Gautam
@ 2022-02-14 12:13 ` Vivek Kumar Gautam
2022-12-07 13:34 ` [edk2-devel] " PierreGondois
2022-02-14 12:13 ` [edk2-platforms][PATCH V1 4/6] Platform/Sgi: add helper macros for ITS, SMMUv3 and DMA IORT nodes Vivek Kumar Gautam
` (2 subsequent siblings)
5 siblings, 1 reply; 10+ messages in thread
From: Vivek Kumar Gautam @ 2022-02-14 12:13 UTC (permalink / raw)
To: devel; +Cc: Sami Mujawar, Ard Biesheuvel, Leif Lindholm, Vivek Gautam
From: Shriram K <shriram.k@arm.com>
The IO virtualization block on reference design platforms allow
connecting non-discoverable devices such as PL011 UART. On platforms
that support this, initialize the UART controller connected to the
IO virtualization block.
Signed-off-by: Shriram K <shriram.k@arm.com>
Signed-off-by: Vivek Gautam <vivek.gautam@arm.com>
---
Platform/ARM/SgiPkg/SgiPlatform.dec | 1 +
Platform/ARM/SgiPkg/RdN2/RdN2.dsc | 4 ++
Platform/ARM/SgiPkg/RdN2Cfg1/RdN2Cfg1.dsc | 6 +-
Platform/ARM/SgiPkg/Drivers/PlatformDxe/PlatformDxe.inf | 7 +-
Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.inf | 8 ++-
Platform/ARM/SgiPkg/Drivers/PlatformDxe/PlatformDxe.c | 73 +++++++++++++++++++-
Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLibMem.c | 19 ++++-
7 files changed, 112 insertions(+), 6 deletions(-)
diff --git a/Platform/ARM/SgiPkg/SgiPlatform.dec b/Platform/ARM/SgiPkg/SgiPlatform.dec
index 6b3e28c3a08e..fa057f6344ee 100644
--- a/Platform/ARM/SgiPkg/SgiPlatform.dec
+++ b/Platform/ARM/SgiPkg/SgiPlatform.dec
@@ -31,6 +31,7 @@
[PcdsFeatureFlag.common]
gArmSgiTokenSpaceGuid.PcdVirtioBlkSupported|FALSE|BOOLEAN|0x00000001
gArmSgiTokenSpaceGuid.PcdVirtioNetSupported|FALSE|BOOLEAN|0x00000010
+ gArmSgiTokenSpaceGuid.PcdIoVirtBlkNonDiscoverable|FALSE|BOOLEAN|0x00000050
[PcdsFixedAtBuild]
gArmSgiTokenSpaceGuid.PcdDramBlock2Base|0|UINT64|0x00000002
diff --git a/Platform/ARM/SgiPkg/RdN2/RdN2.dsc b/Platform/ARM/SgiPkg/RdN2/RdN2.dsc
index 49a317a930e0..b4f557805dcf 100644
--- a/Platform/ARM/SgiPkg/RdN2/RdN2.dsc
+++ b/Platform/ARM/SgiPkg/RdN2/RdN2.dsc
@@ -45,6 +45,10 @@
gArmPlatformTokenSpaceGuid.PcdCoreCount|1
gArmPlatformTokenSpaceGuid.PcdClusterCount|16
+[PcdsFeatureFlag.common]
+ # IO virtualization block non-discoverable peripherals
+ gArmSgiTokenSpaceGuid.PcdIoVirtBlkNonDiscoverable|TRUE
+
################################################################################
#
# Components Section - list of all EDK II Modules needed by this Platform
diff --git a/Platform/ARM/SgiPkg/RdN2Cfg1/RdN2Cfg1.dsc b/Platform/ARM/SgiPkg/RdN2Cfg1/RdN2Cfg1.dsc
index c26f652cb9e9..4ebb4af3a57d 100644
--- a/Platform/ARM/SgiPkg/RdN2Cfg1/RdN2Cfg1.dsc
+++ b/Platform/ARM/SgiPkg/RdN2Cfg1/RdN2Cfg1.dsc
@@ -1,7 +1,7 @@
## @file
# Platform Description file for RD-N2-Cfg1 platform.
#
-# Copyright (c) 2017 - 2020, Arm Limited. All rights reserved.<BR>
+# Copyright (c) 2017 - 2022, Arm Limited. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
##
@@ -47,6 +47,10 @@
gArmPlatformTokenSpaceGuid.PcdCoreCount|1
gArmPlatformTokenSpaceGuid.PcdClusterCount|8
+[PcdsFeatureFlag.common]
+ # IO virtualization block non-discoverable peripherals
+ gArmSgiTokenSpaceGuid.PcdIoVirtBlkNonDiscoverable|TRUE
+
################################################################################
#
# Components Section - list of all EDK II Modules needed by this Platform
diff --git a/Platform/ARM/SgiPkg/Drivers/PlatformDxe/PlatformDxe.inf b/Platform/ARM/SgiPkg/Drivers/PlatformDxe/PlatformDxe.inf
index 9d89314a594e..0b07f01f0a99 100644
--- a/Platform/ARM/SgiPkg/Drivers/PlatformDxe/PlatformDxe.inf
+++ b/Platform/ARM/SgiPkg/Drivers/PlatformDxe/PlatformDxe.inf
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2018, ARM Limited. All rights reserved.
+# Copyright (c) 2018-2022, ARM Limited. All rights reserved.
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -17,6 +17,7 @@
VirtioDevices.c
[Packages]
+ ArmPlatformPkg/ArmPlatformPkg.dec
EmbeddedPkg/EmbeddedPkg.dec
MdePkg/MdePkg.dec
OvmfPkg/OvmfPkg.dec
@@ -35,12 +36,16 @@
[FeaturePcd]
gArmSgiTokenSpaceGuid.PcdVirtioBlkSupported
gArmSgiTokenSpaceGuid.PcdVirtioNetSupported
+ gArmSgiTokenSpaceGuid.PcdIoVirtBlkNonDiscoverable
[FixedPcd]
gArmSgiTokenSpaceGuid.PcdVirtioBlkBaseAddress
gArmSgiTokenSpaceGuid.PcdVirtioBlkSize
gArmSgiTokenSpaceGuid.PcdVirtioNetBaseAddress
gArmSgiTokenSpaceGuid.PcdVirtioNetSize
+ gArmPlatformTokenSpaceGuid.PcdSerialDbgUartClkInHz
+ gArmSgiTokenSpaceGuid.PcdIoVirtBlkUart0Base
+ gArmSgiTokenSpaceGuid.PcdIoVirtBlkUart1Base
[Depex]
TRUE
diff --git a/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.inf b/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.inf
index 22e247ea4fae..6c81543a800d 100644
--- a/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.inf
+++ b/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.inf
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2018-2020, ARM Limited. All rights reserved.
+# Copyright (c) 2018-2022, ARM Limited. All rights reserved.
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -83,6 +83,12 @@
gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64
gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase
+ gArmSgiTokenSpaceGuid.PcdIoVirtBlkUart0Base
+ gArmSgiTokenSpaceGuid.PcdIoVirtBlkUart1Base
+
+[FeaturePcd]
+ gArmSgiTokenSpaceGuid.PcdIoVirtBlkNonDiscoverable
+
[Guids]
gArmSgiPlatformIdDescriptorGuid
gEfiHobListGuid ## CONSUMES ## SystemTable
diff --git a/Platform/ARM/SgiPkg/Drivers/PlatformDxe/PlatformDxe.c b/Platform/ARM/SgiPkg/Drivers/PlatformDxe/PlatformDxe.c
index 2f72e7152ff3..48ef7cd2a59a 100644
--- a/Platform/ARM/SgiPkg/Drivers/PlatformDxe/PlatformDxe.c
+++ b/Platform/ARM/SgiPkg/Drivers/PlatformDxe/PlatformDxe.c
@@ -1,6 +1,6 @@
/** @file
*
-* Copyright (c) 2018, ARM Limited. All rights reserved.
+* Copyright (c) 2018-2022, ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-2-Clause-Patent
*
@@ -9,6 +9,8 @@
#include <Library/AcpiLib.h>
#include <Library/DebugLib.h>
#include <Library/HobLib.h>
+#include <Library/PL011UartLib.h>
+
#include <SgiPlatform.h>
VOID
@@ -16,6 +18,74 @@ InitVirtioDevices (
VOID
);
+/**
+ Initialize UART controllers connected to IO Virtualization block.
+
+ Use PL011UartLib Library to initialize UART controllers connected
+ to x4_0 and x8 port of the IO Virtualization block on infrastructure
+ reference design (RD) platforms.
+
+ @retval None
+**/
+STATIC
+VOID
+InitIoVirtBlkUartControllers (VOID)
+{
+ EFI_STATUS Status;
+ EFI_PARITY_TYPE Parity;
+ EFI_STOP_BITS_TYPE StopBits;
+ UINT64 BaudRate;
+ UINT32 ReceiveFifoDepth;
+ UINT8 DataBits;
+
+ if (!FeaturePcdGet (PcdIoVirtBlkNonDiscoverable))
+ return;
+
+ ReceiveFifoDepth = 0;
+ Parity = 1;
+ DataBits = 8;
+ StopBits = 1;
+ BaudRate = 115200;
+
+ // Use PL011Uart Library to initialize the x4: PL011_UART0
+ Status = PL011UartInitializePort (
+ (UINTN)FixedPcdGet64 (PcdIoVirtBlkUart0Base),
+ FixedPcdGet32 (PcdSerialDbgUartClkInHz),
+ &BaudRate,
+ &ReceiveFifoDepth,
+ &Parity,
+ &DataBits,
+ &StopBits
+ );
+
+ if (EFI_ERROR (Status)) {
+ DEBUG ((
+ DEBUG_ERROR,
+ "Failed to init PL011_UART0 on IO Virt Block port x4_0, status: %r\n",
+ Status
+ ));
+ }
+
+ // Use PL011Uart Library to initialize the x8: PL011_UART1
+ Status = PL011UartInitializePort (
+ (UINTN)FixedPcdGet64 (PcdIoVirtBlkUart1Base),
+ FixedPcdGet32 (PcdSerialDbgUartClkInHz),
+ &BaudRate,
+ &ReceiveFifoDepth,
+ &Parity,
+ &DataBits,
+ &StopBits
+ );
+
+ if (EFI_ERROR (Status)) {
+ DEBUG ((
+ DEBUG_ERROR,
+ "Failed to init PL011_UART1 on IO Virt Block port x8, status: %r\n",
+ Status
+ ));
+ }
+}
+
EFI_STATUS
EFIAPI
ArmSgiPkgEntryPoint (
@@ -32,6 +102,7 @@ ArmSgiPkgEntryPoint (
}
InitVirtioDevices ();
+ InitIoVirtBlkUartControllers ();
return Status;
}
diff --git a/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLibMem.c b/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLibMem.c
index 8139b75d8ee4..26fd873fa647 100644
--- a/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLibMem.c
+++ b/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLibMem.c
@@ -1,6 +1,6 @@
/** @file
*
-* Copyright (c) 2018-2020, ARM Limited. All rights reserved.
+* Copyright (c) 2018-2022, ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-2-Clause-Patent
*
@@ -17,7 +17,8 @@
// Total number of descriptors, including the final "end-of-table" descriptor.
#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS \
- (14 + (FixedPcdGet32 (PcdChipCount) * 2))
+ (14 + (FixedPcdGet32 (PcdChipCount) * 2)) + \
+ (FeaturePcdGet (PcdIoVirtBlkNonDiscoverable) * 2)
/**
Returns the Virtual Memory Map of the platform.
@@ -171,6 +172,20 @@ ArmPlatformGetVirtualMemoryMap (
VirtualMemoryTable[Index].Length = SIZE_64KB;
VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+#if (FeaturePcdGet (PcdIoVirtBlkNonDiscoverable) == true)
+ // IO Virt Block x4_0: UART0
+ VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdIoVirtBlkUart0Base);
+ VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdIoVirtBlkUart0Base);;
+ VirtualMemoryTable[Index].Length = SIZE_64KB;
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+ // IO Virt Block x8: UART1
+ VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdIoVirtBlkUart1Base);
+ VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdIoVirtBlkUart1Base);
+ VirtualMemoryTable[Index].Length = SIZE_64KB;
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+#endif
+
// DDR - (2GB - 16MB)
VirtualMemoryTable[++Index].PhysicalBase = PcdGet64 (PcdSystemMemoryBase);
VirtualMemoryTable[Index].VirtualBase = PcdGet64 (PcdSystemMemoryBase);
--
2.17.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [edk2-platforms][PATCH V1 4/6] Platform/Sgi: add helper macros for ITS, SMMUv3 and DMA IORT nodes
2022-02-14 12:13 [edk2-platforms][PATCH V1 0/6] Add non-discoverable IO block for Rd-N2 Vivek Kumar Gautam
` (2 preceding siblings ...)
2022-02-14 12:13 ` [edk2-platforms][PATCH V1 3/6] Platform/Sgi: Initialize additional uart controllers Vivek Kumar Gautam
@ 2022-02-14 12:13 ` Vivek Kumar Gautam
2022-02-14 12:13 ` [edk2-platforms][PATCH V1 5/6] Platform/Sgi: add IORT table for IO virtualization block on RD-N2-Cfg1 Vivek Kumar Gautam
2022-02-14 12:13 ` [edk2-platforms][PATCH V1 6/6] Platform/Sgi: add IORT table for IO virtualization block on RD-N2 Vivek Kumar Gautam
5 siblings, 0 replies; 10+ messages in thread
From: Vivek Kumar Gautam @ 2022-02-14 12:13 UTC (permalink / raw)
To: devel; +Cc: Sami Mujawar, Ard Biesheuvel, Leif Lindholm, Vivek Gautam
Add preprocessor macros for ITS, SMMUv3 and DMA named component nodes
of IORT table that can be used to describe the IO topology connected
to the IO Virtualization block. An IO virtualization block could be
used to connect PCIe root bus or non-PCIe devices.
For a non-PCIe IO-Virtualization block, there are DMA masters
connected to SMMUv3 in the following manner -
0x0 ------------- 0x30000 ------------
| DMA device |---------->| SMMU |
| (ID) | | (StreamID) |
0x9 ------------- 0x30009 ------------
The DMA master consists of 8 data channels and 1 instruction channel.
The IDs emitted by DMA go to the SMMUv3 as StreamID and the SMMUv3
programs the corresponding translation contexts.
The PCIe root bus or non-PCIe devices are connected to one of the
x16/x8/x4_1/x4_0 ports of IO virtualization block. Each of these
ports have a base DeviceID that is added to the RequesterID or
StreamID of the devices connected to ports to create the IDs sent
to the SMMUv3 and ITS.
Stream ID coming at SMMUv3 is calculated as below:
Stream ID = DMA Channel Index + Base PCI port index, e.g.
For example, for channel 1 of DMA0 device (connected to x16 port
whose baseID is 0x30000, the streamID that SMMUv3 sees is:
(1 + 0x30000) = 0x30001.
Signed-off-by: Vivek Gautam <vivek.gautam@arm.com>
---
Platform/ARM/SgiPkg/SgiPlatform.dec | 6 +
Platform/ARM/SgiPkg/SgiMemoryMap2.dsc.inc | 6 +
| 197 +++++++++++++++++++-
3 files changed, 208 insertions(+), 1 deletion(-)
diff --git a/Platform/ARM/SgiPkg/SgiPlatform.dec b/Platform/ARM/SgiPkg/SgiPlatform.dec
index fa057f6344ee..c4559ab4f8cc 100644
--- a/Platform/ARM/SgiPkg/SgiPlatform.dec
+++ b/Platform/ARM/SgiPkg/SgiPlatform.dec
@@ -138,5 +138,11 @@
gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma1AbortGsiv|0|UINT32|0x0000004E
gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma1StreamIDBase|0|UINT32|0x0000004F
+ # Base Device IDs for ports on I/O virtualization block
+ gArmSgiTokenSpaceGuid.PcdPciex16DevIDBase|0|UINT64|0x00000051
+ gArmSgiTokenSpaceGuid.PcdPciex8DevIDBase|0|UINT64|0x00000052
+ gArmSgiTokenSpaceGuid.PcdPciex41DevIDBase|0|UINT64|0x00000053
+ gArmSgiTokenSpaceGuid.PcdPciex40DevIDBase|0|UINT64|0x00000054
+
[Ppis]
gNtFwConfigDtInfoPpiGuid = { 0x6f606eb3, 0x9123, 0x4e15, { 0xa8, 0x9b, 0x0f, 0xac, 0x66, 0xef, 0xd0, 0x17 } }
diff --git a/Platform/ARM/SgiPkg/SgiMemoryMap2.dsc.inc b/Platform/ARM/SgiPkg/SgiMemoryMap2.dsc.inc
index 472795193b9e..0fb934b3e51f 100644
--- a/Platform/ARM/SgiPkg/SgiMemoryMap2.dsc.inc
+++ b/Platform/ARM/SgiPkg/SgiMemoryMap2.dsc.inc
@@ -105,3 +105,9 @@
gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma1Ch6Gsiv|509
gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma1Ch7Gsiv|510
gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma1AbortGsiv|511
+
+ # Base device IDs for x16/x8/x4_1/x4_0 ports
+ gArmSgiTokenSpaceGuid.PcdPciex16DevIDBase|0x30000
+ gArmSgiTokenSpaceGuid.PcdPciex8DevIDBase|0x20000
+ gArmSgiTokenSpaceGuid.PcdPciex41DevIDBase|0x10000
+ gArmSgiTokenSpaceGuid.PcdPciex40DevIDBase|0x00000
--git a/Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h b/Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h
index d75d54055436..4aba1e702d8f 100644
--- a/Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h
+++ b/Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h
@@ -1,6 +1,6 @@
/** @file
*
-* Copyright (c) 2018-2021, ARM Limited. All rights reserved.
+* Copyright (c) 2018-2022, ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-2-Clause-Patent
*
@@ -10,6 +10,7 @@
#define __SGI_ACPI_HEADER__
#include <IndustryStandard/Acpi.h>
+#include <IndustryStandard/IoRemappingTable.h>
//
// ACPI table information used to initialize tables.
@@ -508,4 +509,198 @@ typedef struct {
1 /* Processors */ \
}
+#pragma pack(1)
+typedef struct
+{
+ EFI_ACPI_6_0_IO_REMAPPING_ITS_NODE ItsNode;
+ UINT32 ItsIdentifiers;
+} ARM_EFI_ACPI_6_0_IO_REMAPPING_ITS_NODE;
+
+typedef struct
+{
+ EFI_ACPI_6_0_IO_REMAPPING_SMMU3_NODE SmmuNode;
+ EFI_ACPI_6_0_IO_REMAPPING_ID_TABLE SmmuIdMap[3];
+} ARM_EFI_ACPI_6_0_IO_REMAPPING_SMMU3_NODE;
+
+typedef struct
+{
+ EFI_ACPI_6_0_IO_REMAPPING_NAMED_COMP_NODE DmaNode;
+ CONST CHAR8 Name[16];
+ EFI_ACPI_6_0_IO_REMAPPING_ID_TABLE DmaIdMap[9];
+} ARM_EFI_ACPI_6_0_IO_REMAPPING_DMA_NC_NODE;
+#pragma pack ()
+
+/** Helper macro for ITS group node initialization for Arm Iort table.
+ See Table 12 of Arm IORT specification, version E.b.
+
+ @param [in] IoVirtBlkIdx Index of IO virtualization block in which
+ the ITS block is present.
+**/
+#define EFI_ACPI_ITS_INIT(IoVirtBlkIdx) \
+ /* ARM_EFI_ACPI_6_0_IO_REMAPPING_ITS_NODE */ \
+ { \
+ /* EFI_ACPI_6_0_IO_REMAPPING_ITS_NODE */ \
+ { \
+ /* EFI_ACPI_6_0_IO_REMAPPING_NODE */ \
+ { \
+ EFI_ACPI_IORT_TYPE_ITS_GROUP, /* Type */ \
+ sizeof (ARM_EFI_ACPI_6_0_IO_REMAPPING_ITS_NODE), /* Length */ \
+ 1, /* Revision */ \
+ 0, /* Identifier */ \
+ 0, /* NumIdMappings */ \
+ 0, /* IdReference */ \
+ }, \
+ 1, /* ITS count */ \
+ }, \
+ IoVirtBlkIdx, /* GIC ITS Identifiers */ \
+ }
+
+/** Helper macro for ID mapping table initialization of SMMUv3 IORT node.
+ See Table 4 of Arm IORT specification, version E.b.
+
+ @param [in] BaseStreamId Starting ID in the range of StreamIDs allowed
+ by SMMUv3. Since SMMUv3 doesn't offset input
+ IDs, so InputBase and OutputBase are identical.
+
+ @param [in] NumIds Number of StreamIDs in the StreamID range.
+**/
+#define EFI_ACPI_SMMUv3_ID_TABLE_INIT(BaseStreamId, NumIds) \
+ { \
+ BaseStreamId, /* InputBase */ \
+ NumIds, /* NumIds */ \
+ BaseStreamId, /* OutputBase */ \
+ OFFSET_OF (ARM_EFI_ACPI_6_0_IO_REMAPPING_TABLE, \
+ ItsNode), /* OutputReference */ \
+ 0, /* Flags */ \
+ }
+
+// StreamID base for PL330 DMA0 controller
+#define DMA0_STREAM_ID_BASE \
+ FixedPcdGet32 (PcdPciex41DevIDBase) + \
+ FixedPcdGet32 (PcdIoVirtBlkDma0StreamIDBase)
+
+// StreamID base for PL330 DMA1 controller
+#define DMA1_STREAM_ID_BASE \
+ FixedPcdGet32 (PcdPciex16DevIDBase) + \
+ FixedPcdGet32 (PcdIoVirtBlkDma1StreamIDBase)
+
+/** Helper macro for SMMUv3 node initialization for Arm Iort table.
+ See Table 9 of Arm IORT specification, version E.b.
+
+ @param [in] IoVirtBlkIdx Index of IO virtualization block in which
+ the SMMUv3 block is present.
+**/
+#define EFI_ACPI_SMMUv3_INIT(IoVirtBlkIdx) \
+ /* ARM_EFI_ACPI_6_0_IO_REMAPPING_SMMU3_NODE */ \
+ { \
+ /* EFI_ACPI_6_0_IO_REMAPPING_SMMU3_NODE */ \
+ { \
+ /* EFI_ACPI_6_0_IO_REMAPPING_NODE */ \
+ { \
+ EFI_ACPI_IORT_TYPE_SMMUv3, /* Type */ \
+ sizeof (ARM_EFI_ACPI_6_0_IO_REMAPPING_SMMU3_NODE), /* Length */ \
+ 4, /* Revision */ \
+ 0, /* Identifier */ \
+ 3, /* NumIdMapping */ \
+ OFFSET_OF (ARM_EFI_ACPI_6_0_IO_REMAPPING_SMMU3_NODE, \
+ SmmuIdMap), /* IdReference */ \
+ }, \
+ (FixedPcdGet32 (PcdSmmuBase) + (0x2000000 * IoVirtBlkIdx)), \
+ /* Base address */ \
+ EFI_ACPI_IORT_SMMUv3_FLAG_COHAC_OVERRIDE, /* Flags */ \
+ 0, /* Reserved */ \
+ 0x0, /* VATOS address */ \
+ EFI_ACPI_IORT_SMMUv3_MODEL_GENERIC, /* SMMUv3 Model */ \
+ FixedPcdGet32 (PcdSmmuEventGsiv), /* Event */ \
+ FixedPcdGet32 (PcdSmmuPriGsiv), /* Pri */ \
+ FixedPcdGet32 (PcdSmmuGErrorGsiv), /* Gerror */ \
+ FixedPcdGet32 (PcdSmmuSyncGsiv), /* Sync */ \
+ 0, /* Proximity domain */ \
+ 2, /* DevIDMappingIndex */ \
+ }, \
+ /* EFI_ACPI_6_0_IO_REMAPPING_ID_TABLE */ \
+ { \
+ EFI_ACPI_SMMUv3_ID_TABLE_INIT(DMA0_STREAM_ID_BASE, \
+ (FixedPcdGet32 (PcdIoVirtBlkDma0NumCh) + 1)), \
+ EFI_ACPI_SMMUv3_ID_TABLE_INIT(DMA1_STREAM_ID_BASE, \
+ (FixedPcdGet32 (PcdIoVirtBlkDma1NumCh) + 1)), \
+ { \
+ 0x0, /* InputBase */ \
+ 1, /* NumIds */ \
+ FixedPcdGet32 (PcdSmmuDevIDBase), /* OutputBase */ \
+ OFFSET_OF (ARM_EFI_ACPI_6_0_IO_REMAPPING_TABLE, \
+ ItsNode), /* OutputReference */ \
+ EFI_ACPI_IORT_ID_MAPPING_FLAGS_SINGLE, /* Flags */ \
+ }, \
+ }, \
+ }
+
+/** Helper macro for ID mapping table initialization of DMA Named Component
+ IORT node.
+ See Table 4 of Arm IORT specification, version E.b.
+ Output StreamID for a channel can be calculated as -
+ ((IDBase for x16/x8/x4_1/x4_0) + BaseSID of DMA controller) + Channel Idx).
+
+ @param [in] DmaIdx Index of DMA pl330 controller connected to
+ a non-PCIe IO virtualization block.
+ @param [in] ChStreamIdx Channel index within one DMA controller -
+ 0 to 8.
+**/
+#define EFI_ACPI_DMA_NC_ID_TABLE_INIT(DmaIdx, ChStreamIdx) \
+ { \
+ ChStreamIdx, /* InputBase */ \
+ 1, /* NumIds */ \
+ DMA ##DmaIdx ## _STREAM_ID_BASE + ChStreamIdx, /* OutputBase */ \
+ OFFSET_OF (ARM_EFI_ACPI_6_0_IO_REMAPPING_TABLE, \
+ SmmuNode), /* OutputReference */ \
+ EFI_ACPI_IORT_ID_MAPPING_FLAGS_SINGLE, /* Flags */ \
+ }
+
+/** Helper macro for DMA Named Component node initialization for Arm Iort
+ table.
+ See Table 13 of Arm IORT specification, version E.b.
+
+ @param [in] DmaIdx Index of DMA pl330 controller connected to
+ a non-PCIe IO virtualization block.
+
+ @param [in] RefName Device object name in the ACPI namespace.
+**/
+#define EFI_ACPI_DMA_NC_INIT(DmaIdx, RefName) \
+ /* ARM_EFI_ACPI_6_0_IO_REMAPPING_DMA_NC_NODE */ \
+ { \
+ /* EFI_ACPI_6_0_IO_REMAPPING_NAMED_COMP_NODE */ \
+ { \
+ { \
+ EFI_ACPI_IORT_TYPE_NAMED_COMP, /* Type */ \
+ sizeof (ARM_EFI_ACPI_6_0_IO_REMAPPING_DMA_NC_NODE), /* Length */ \
+ 4, /* Revision */ \
+ 0, /* Identifier */ \
+ 9, /* NumIdMappings */ \
+ OFFSET_OF (ARM_EFI_ACPI_6_0_IO_REMAPPING_DMA_NC_NODE, \
+ DmaIdMap) /* IdReference */ \
+ }, \
+ 0x0, /* Flags */ \
+ 0x1, /* CacheCoherent */ \
+ 0x0, /* AllocationHints */ \
+ 0x0, /* Reserved */ \
+ 0x0, /* MemoryAccessFlags */ \
+ 0x30, /* AddressSizeLimit */ \
+ }, \
+ { \
+ RefName, \
+ }, \
+ /* ID mapping table */ \
+ { \
+ EFI_ACPI_DMA_NC_ID_TABLE_INIT(DmaIdx, 0), /* Data Channel - 0 */ \
+ EFI_ACPI_DMA_NC_ID_TABLE_INIT(DmaIdx, 1), /* Data Channel - 1 */ \
+ EFI_ACPI_DMA_NC_ID_TABLE_INIT(DmaIdx, 2), /* Data Channel - 2 */ \
+ EFI_ACPI_DMA_NC_ID_TABLE_INIT(DmaIdx, 3), /* Data Channel - 3 */ \
+ EFI_ACPI_DMA_NC_ID_TABLE_INIT(DmaIdx, 4), /* Data Channel - 4 */ \
+ EFI_ACPI_DMA_NC_ID_TABLE_INIT(DmaIdx, 5), /* Data Channel - 5 */ \
+ EFI_ACPI_DMA_NC_ID_TABLE_INIT(DmaIdx, 6), /* Data Channel - 6 */ \
+ EFI_ACPI_DMA_NC_ID_TABLE_INIT(DmaIdx, 7), /* Data Channel - 7 */ \
+ EFI_ACPI_DMA_NC_ID_TABLE_INIT(DmaIdx, 8), /* Instruction channel */ \
+ }, \
+ }
+
#endif /* __SGI_ACPI_HEADER__ */
--
2.17.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [edk2-platforms][PATCH V1 5/6] Platform/Sgi: add IORT table for IO virtualization block on RD-N2-Cfg1
2022-02-14 12:13 [edk2-platforms][PATCH V1 0/6] Add non-discoverable IO block for Rd-N2 Vivek Kumar Gautam
` (3 preceding siblings ...)
2022-02-14 12:13 ` [edk2-platforms][PATCH V1 4/6] Platform/Sgi: add helper macros for ITS, SMMUv3 and DMA IORT nodes Vivek Kumar Gautam
@ 2022-02-14 12:13 ` Vivek Kumar Gautam
2022-02-14 12:13 ` [edk2-platforms][PATCH V1 6/6] Platform/Sgi: add IORT table for IO virtualization block on RD-N2 Vivek Kumar Gautam
5 siblings, 0 replies; 10+ messages in thread
From: Vivek Kumar Gautam @ 2022-02-14 12:13 UTC (permalink / raw)
To: devel; +Cc: Sami Mujawar, Ard Biesheuvel, Leif Lindholm, Vivek Gautam
Arm reference design RD-N2-Cfg1 platform has multiple I/O virtualization
blocks that allow connecting PCIe root bus or non-PCIe devices to the
system. Each of the I/O virtualization blocks (IoVirtBlk) consists of
an Arm SMMUv3 compliant MMU-700 controller to handle address translation
and a GIC-700 Interrupt Translation Service (ITS) to support message
signaled interrupts (MSIs).
Add an IORT table for non-discoverable (non-PCIe) devices connected
to one of the I/O virtualization blocks - IoVirtBlk #1 on RD-N2-Cfg1.
In addition to SMMUv3 and ITS nodes, two Named Compoenent nodes are
also added for PL330 DMA controllers connected to IoVirtBlk #1.
While we are adding the IORT table entries for RD-N2-Cfg1 platform
remove the source file entries for incorrect IORT table.
Signed-off-by: Vivek Gautam <vivek.gautam@arm.com>
---
Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1AcpiTables.inf | 12 +++-
Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/IortNonPciIoVirtBlk.aslc | 58 ++++++++++++++++++++
2 files changed, 69 insertions(+), 1 deletion(-)
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1AcpiTables.inf b/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1AcpiTables.inf
index b5612e817d01..f522919d8099 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1AcpiTables.inf
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1AcpiTables.inf
@@ -18,8 +18,8 @@
Dbg2.aslc
Fadt.aslc
Gtdt.aslc
- Iort.aslc
RdN2Cfg1/Dsdt.asl
+ RdN2Cfg1/IortNonPciIoVirtBlk.aslc
RdN2Cfg1/Madt.aslc
RdN2Cfg1/Pptt.aslc
Spcr.aslc
@@ -59,6 +59,11 @@
gArmSgiTokenSpaceGuid.PcdOscLpiEnable
gArmSgiTokenSpaceGuid.PcdOscCppcEnable
gArmSgiTokenSpaceGuid.PcdSmmuBase
+ gArmSgiTokenSpaceGuid.PcdSmmuEventGsiv
+ gArmSgiTokenSpaceGuid.PcdSmmuGErrorGsiv
+ gArmSgiTokenSpaceGuid.PcdSmmuPriGsiv
+ gArmSgiTokenSpaceGuid.PcdSmmuSyncGsiv
+ gArmSgiTokenSpaceGuid.PcdSmmuDevIDBase
gArmSgiTokenSpaceGuid.PcdSp804DualTimerBaseAddress
gArmSgiTokenSpaceGuid.PcdSp804DualTimerSize
gArmSgiTokenSpaceGuid.PcdSp804DualTimerInterrupt
@@ -71,6 +76,11 @@
gArmSgiTokenSpaceGuid.PcdWdogWS0Gsiv
gArmSgiTokenSpaceGuid.PcdWdogWS1Gsiv
+ gArmSgiTokenSpaceGuid.PcdPciex16DevIDBase
+ gArmSgiTokenSpaceGuid.PcdPciex8DevIDBase
+ gArmSgiTokenSpaceGuid.PcdPciex41DevIDBase
+ gArmSgiTokenSpaceGuid.PcdPciex40DevIDBase
+
gArmSgiTokenSpaceGuid.PcdIoVirtBlkUart0Base
gArmSgiTokenSpaceGuid.PcdIoVirtBlkUart0End
gArmSgiTokenSpaceGuid.PcdIoVirtBlkUart0Size
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/IortNonPciIoVirtBlk.aslc b/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/IortNonPciIoVirtBlk.aslc
new file mode 100644
index 000000000000..15ba2861ecde
--- /dev/null
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/IortNonPciIoVirtBlk.aslc
@@ -0,0 +1,58 @@
+/** @file
+ I/O Remapping Table (IORT) for RD-N2-Cfg1 platform.
+
+ This file presents the I/O Remapping Table for Non-PCIe I/O
+ virtualization block present on RD-N2-Cfg1 platform that
+ connects non-discoverable (non-PCIe) devices.
+ I/O virtualization blocks are combination of SMMUv3, GIC ITS,
+ a local interconnect and Root-Ports to connect PCIe or non-PCIe
+ devices.
+
+ Copyright (c) 2022, Arm Ltd. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Specification Reference:
+ - IORT specification version E.b
+**/
+
+#include "SgiAcpiHeader.h"
+
+#pragma pack(1)
+
+typedef struct
+{
+ EFI_ACPI_6_0_IO_REMAPPING_TABLE Header;
+ ARM_EFI_ACPI_6_0_IO_REMAPPING_ITS_NODE ItsNode;
+ ARM_EFI_ACPI_6_0_IO_REMAPPING_SMMU3_NODE SmmuNode;
+ ARM_EFI_ACPI_6_0_IO_REMAPPING_DMA_NC_NODE DmaNode[2];
+} ARM_EFI_ACPI_6_0_IO_REMAPPING_TABLE;
+
+#pragma pack ()
+
+ARM_EFI_ACPI_6_0_IO_REMAPPING_TABLE Iort =
+{
+ // EFI_ACPI_6_0_IO_REMAPPING_TABLE
+ {
+ ARM_ACPI_HEADER // EFI_ACPI_DESCRIPTION_HEADER
+ (
+ EFI_ACPI_6_2_IO_REMAPPING_TABLE_SIGNATURE,
+ ARM_EFI_ACPI_6_0_IO_REMAPPING_TABLE,
+ EFI_ACPI_IO_REMAPPING_TABLE_REVISION
+ ),
+ 4, // NumNodes
+ sizeof (EFI_ACPI_6_0_IO_REMAPPING_TABLE), // NodeOffset
+ 0, // Reserved
+ },
+
+ EFI_ACPI_ITS_INIT(1),
+
+ EFI_ACPI_SMMUv3_INIT(1),
+
+ // DMA Named Component nodes - DMA0 & DMA1
+ {
+ EFI_ACPI_DMA_NC_INIT(0, "\\_SB_.DMA0"),
+ EFI_ACPI_DMA_NC_INIT(1, "\\_SB_.DMA1"),
+ },
+};
+
+VOID* CONST ReferenceAcpiTable = &Iort;
--
2.17.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [edk2-platforms][PATCH V1 6/6] Platform/Sgi: add IORT table for IO virtualization block on RD-N2
2022-02-14 12:13 [edk2-platforms][PATCH V1 0/6] Add non-discoverable IO block for Rd-N2 Vivek Kumar Gautam
` (4 preceding siblings ...)
2022-02-14 12:13 ` [edk2-platforms][PATCH V1 5/6] Platform/Sgi: add IORT table for IO virtualization block on RD-N2-Cfg1 Vivek Kumar Gautam
@ 2022-02-14 12:13 ` Vivek Kumar Gautam
5 siblings, 0 replies; 10+ messages in thread
From: Vivek Kumar Gautam @ 2022-02-14 12:13 UTC (permalink / raw)
To: devel; +Cc: Sami Mujawar, Ard Biesheuvel, Leif Lindholm, Vivek Gautam
Arm reference design RD-N2 platform has multiple I/O virtualization
blocks that allow connecting PCIe root bus or non-PCIe devices to
the system. Each of the I/O virtualization blocks (IoVirtBlk)
consists of an Arm SMMUv3 compliant MMU-700 controller to handle
address translations and a GIC-700 Interrupt Translation Service
(ITS) to support message signaled interrupts (MSIs).
Add an IORT table for non-discoverable (non-PCIe) devices connected
to one of the I/O virtualization blocks - IoVirtBlk #4 on RD-N2. In
addition to SMMUv3 and ITS nodes, two Named Compoenent nodes are
also added for PL330 DMA controllers connected to IoVirtBlk #4.
While we are adding the IORT table entries for RD-N2 platform, remove
the source file entries for incorrect IORT table.
Signed-off-by: Vivek Gautam <vivek.gautam@arm.com>
---
Platform/ARM/SgiPkg/AcpiTables/RdN2AcpiTables.inf | 13 ++++-
Platform/ARM/SgiPkg/AcpiTables/RdN2/IortNonPciIoVirtBlk.aslc | 58 ++++++++++++++++++++
2 files changed, 70 insertions(+), 1 deletion(-)
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN2AcpiTables.inf b/Platform/ARM/SgiPkg/AcpiTables/RdN2AcpiTables.inf
index fe50a7b6e44a..efcd2ce48256 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdN2AcpiTables.inf
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN2AcpiTables.inf
@@ -18,8 +18,8 @@
Dbg2.aslc
Fadt.aslc
Gtdt.aslc
- Iort.aslc
RdN2/Dsdt.asl
+ RdN2/IortNonPciIoVirtBlk.aslc
RdN2/Madt.aslc
RdN2/Pptt.aslc
Spcr.aslc
@@ -58,6 +58,12 @@
gArmSgiTokenSpaceGuid.PcdGtFrame1Gsiv
gArmSgiTokenSpaceGuid.PcdOscLpiEnable
gArmSgiTokenSpaceGuid.PcdOscCppcEnable
+ gArmSgiTokenSpaceGuid.PcdSmmuBase
+ gArmSgiTokenSpaceGuid.PcdSmmuEventGsiv
+ gArmSgiTokenSpaceGuid.PcdSmmuGErrorGsiv
+ gArmSgiTokenSpaceGuid.PcdSmmuPriGsiv
+ gArmSgiTokenSpaceGuid.PcdSmmuSyncGsiv
+ gArmSgiTokenSpaceGuid.PcdSmmuDevIDBase
gArmSgiTokenSpaceGuid.PcdSp804DualTimerBaseAddress
gArmSgiTokenSpaceGuid.PcdSp804DualTimerSize
gArmSgiTokenSpaceGuid.PcdSp804DualTimerInterrupt
@@ -70,6 +76,11 @@
gArmSgiTokenSpaceGuid.PcdWdogWS0Gsiv
gArmSgiTokenSpaceGuid.PcdWdogWS1Gsiv
+ gArmSgiTokenSpaceGuid.PcdPciex16DevIDBase
+ gArmSgiTokenSpaceGuid.PcdPciex8DevIDBase
+ gArmSgiTokenSpaceGuid.PcdPciex41DevIDBase
+ gArmSgiTokenSpaceGuid.PcdPciex40DevIDBase
+
gArmSgiTokenSpaceGuid.PcdIoVirtBlkUart0Base
gArmSgiTokenSpaceGuid.PcdIoVirtBlkUart0End
gArmSgiTokenSpaceGuid.PcdIoVirtBlkUart0Size
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN2/IortNonPciIoVirtBlk.aslc b/Platform/ARM/SgiPkg/AcpiTables/RdN2/IortNonPciIoVirtBlk.aslc
new file mode 100644
index 000000000000..84f482d36cba
--- /dev/null
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN2/IortNonPciIoVirtBlk.aslc
@@ -0,0 +1,58 @@
+/** @file
+ I/O Remapping Table (IORT) for RD-N2 platform.
+
+ This file presents the I/O Remapping Table for Non-PCIe I/O
+ virtualization block present on RD-N2 platform that connects
+ non-discoverable (non-PCIe) devices.
+ I/O virtualization blocks are combination of SMMUv3, GIC ITS,
+ a local interconnect and Root-Ports to connect PCIe or non-PCIe
+ devices.
+
+ Copyright (c) 2022, Arm Ltd. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Specification Reference:
+ - IORT specification version E.b
+**/
+
+#include "SgiAcpiHeader.h"
+
+#pragma pack(1)
+
+typedef struct
+{
+ EFI_ACPI_6_0_IO_REMAPPING_TABLE Header;
+ ARM_EFI_ACPI_6_0_IO_REMAPPING_ITS_NODE ItsNode;
+ ARM_EFI_ACPI_6_0_IO_REMAPPING_SMMU3_NODE SmmuNode;
+ ARM_EFI_ACPI_6_0_IO_REMAPPING_DMA_NC_NODE DmaNode[2];
+} ARM_EFI_ACPI_6_0_IO_REMAPPING_TABLE;
+
+#pragma pack ()
+
+ARM_EFI_ACPI_6_0_IO_REMAPPING_TABLE Iort =
+{
+ // EFI_ACPI_6_0_IO_REMAPPING_TABLE
+ {
+ ARM_ACPI_HEADER // EFI_ACPI_DESCRIPTION_HEADER
+ (
+ EFI_ACPI_6_2_IO_REMAPPING_TABLE_SIGNATURE,
+ ARM_EFI_ACPI_6_0_IO_REMAPPING_TABLE,
+ EFI_ACPI_IO_REMAPPING_TABLE_REVISION
+ ),
+ 4, // NumNodes
+ sizeof (EFI_ACPI_6_0_IO_REMAPPING_TABLE), // NodeOffset
+ 0, // Reserved
+ },
+
+ EFI_ACPI_ITS_INIT(4),
+
+ EFI_ACPI_SMMUv3_INIT(4),
+
+ // DMA Named Component nodes - DMA0 & DMA1
+ {
+ EFI_ACPI_DMA_NC_INIT(0, "\\_SB_.DMA0"),
+ EFI_ACPI_DMA_NC_INIT(1, "\\_SB_.DMA1"),
+ },
+};
+
+VOID* CONST ReferenceAcpiTable = &Iort;
--
2.17.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [edk2-devel] [edk2-platforms][PATCH V1 2/6] Platform/Sgi: add ssdt table for non-discoverable IO virtualization block
2022-02-14 12:13 ` [edk2-platforms][PATCH V1 2/6] Platform/Sgi: add ssdt table for non-discoverable IO virtualization block Vivek Kumar Gautam
@ 2022-12-07 13:34 ` PierreGondois
2023-01-27 6:17 ` Vivek Kumar Gautam
0 siblings, 1 reply; 10+ messages in thread
From: PierreGondois @ 2022-12-07 13:34 UTC (permalink / raw)
To: devel, vivek.gautam; +Cc: Sami Mujawar, Ard Biesheuvel, Leif Lindholm
Hello Vivek,
Sorry for the long wait. I think the whole patchset needs to be
rebased on latest master. I just have some comments for patches:
- [PATCH V1 2/6] Platform/Sgi: add ssdt table for non-discoverable IO virtualization block
- [PATCH V1 3/6] Platform/Sgi: Initialize additional uart controllers
The other patches look good to me.
Regards,
Pierre
On 2/14/22 13:13, Vivek Kumar Gautam via groups.io wrote:
> Arm reference design platforms such as RD-N2 and RD-N2-Cfg1 have multiple
> IO virtualization blocks that allow connecting PCIe root bus or non-PCIe
> devices to the system. For platforms that connect non-discoverable (non-
> PCI) devices to IO virtualization block, add a SSDT table to describe
> such devices and use PCDs for the memory region and interrupts of these
> devices in the table entry.
> There are two PL011 UART controllers and two PL330 DMA controllers
> connected to the non-PCIe IO virtualization block on RD-N2 and
> RD-N2-Cfg1 platforms. List them in the SSDT ACPI table.
>
> While we are adding SSDT table entries for RD-N2 and RD-N2-Cfg1
> remove the source file entries for incorrect SSDT and MCFG tables
> for RD-N2 and RD-N2-Cfg1 platforms.
>
> Signed-off-by: Vivek Gautam <vivek.gautam@arm.com>
> ---
> Platform/ARM/SgiPkg/SgiPlatform.dec | 42 ++++
> Platform/ARM/SgiPkg/SgiMemoryMap2.dsc.inc | 40 ++++
> Platform/ARM/SgiPkg/AcpiTables/RdN2AcpiTables.inf | 45 ++++-
> Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1AcpiTables.inf | 45 ++++-
> Platform/ARM/SgiPkg/AcpiTables/SsdtNonPciIoVirtBlk.asl | 203 ++++++++++++++++++++
> 5 files changed, 369 insertions(+), 6 deletions(-)
>
> diff --git a/Platform/ARM/SgiPkg/SgiPlatform.dec b/Platform/ARM/SgiPkg/SgiPlatform.dec
> index 05079743c452..6b3e28c3a08e 100644
> --- a/Platform/ARM/SgiPkg/SgiPlatform.dec
> +++ b/Platform/ARM/SgiPkg/SgiPlatform.dec
> @@ -95,5 +95,47 @@
> gArmSgiTokenSpaceGuid.PcdOscLpiEnable|0|UINT32|0x00000025
> gArmSgiTokenSpaceGuid.PcdOscCppcEnable|0|UINT32|0x00000026
>
> + # IO virtualization block PL011 UARTs
> + gArmSgiTokenSpaceGuid.PcdIoVirtBlkUart0Base|0|UINT64|0x0000002C
> + gArmSgiTokenSpaceGuid.PcdIoVirtBlkUart0End|0|UINT64|0x0000002D
I think it should be possible to remove all the Pcd*End addresses and
replace them with (PcdIoVirtBlkUart0Base + PcdIoVirtBlkUart0Size - 1).
> + gArmSgiTokenSpaceGuid.PcdIoVirtBlkUart0Size|0|UINT64|0x0000002E
> + gArmSgiTokenSpaceGuid.PcdIoVirtBlkUart0Interrupt|0|UINT32|0x0000002F
> +
> + gArmSgiTokenSpaceGuid.PcdIoVirtBlkUart1Base|0|UINT64|0x00000030
> + gArmSgiTokenSpaceGuid.PcdIoVirtBlkUart1End|0|UINT64|0x00000031
> + gArmSgiTokenSpaceGuid.PcdIoVirtBlkUart1Size|0|UINT64|0x00000032
> + gArmSgiTokenSpaceGuid.PcdIoVirtBlkUart1Interrupt|0|UINT32|0x00000033
> +
[...]
> gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
> diff --git a/Platform/ARM/SgiPkg/AcpiTables/SsdtNonPciIoVirtBlk.asl b/Platform/ARM/SgiPkg/AcpiTables/SsdtNonPciIoVirtBlk.asl
> new file mode 100644
> index 000000000000..a035186b88db
> --- /dev/null
> +++ b/Platform/ARM/SgiPkg/AcpiTables/SsdtNonPciIoVirtBlk.asl
> @@ -0,0 +1,203 @@
> +/** @file
> + Secondary System Description Table (SSDT) for Non-PCIe IO
> + Virtualization Block.
> +
> + The IO virtualization block present on reference design platforms
> + such as RD-N2 and RD-N2-Cfg1 allows connecting PCIe and non-PCIe
> + devices. The non-discoverable (non-PCIe) devices that are connected
> + to the IO virtualization block include two PL011 UART and two PL330
> + DMA controllers.
> +
> + Copyright (c) 2022, Arm Ltd. All rights reserved.
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> + @par Specification Reference:
> + - ACPI 6.4, Chapter 5, Section 5.2.11.2, Secondary System Description Table
> +**/
> +
> +#include "SgiPlatform.h"
> +#include "SgiAcpiHeader.h"
> +
> +DefinitionBlock ("SsdtIoVirtBlk.aml", "SSDT", 2, "ARMLTD", "ARMSGI",
> + EFI_ACPI_ARM_OEM_REVISION) {
> + Scope (_SB) {
> +
> + // IO Virtualization Block - PL011 UART0
> + Device (COM4) {
> + Name (_HID, "ARMH0011")
> + Name (_UID, 4)
> + Name (_STA, 0xF)
> +
> + Name (_CRS, ResourceTemplate () {
> + QWordMemory (
> + ResourceProducer,
> + PosDecode,
> + MinFixed,
> + MaxFixed,
> + NonCacheable,
> + ReadWrite,
> + 0x0,
> + FixedPcdGet64 (PcdIoVirtBlkUart0Base),
> + FixedPcdGet64 (PcdIoVirtBlkUart0End),
> + 0x0,
> + FixedPcdGet32 (PcdIoVirtBlkUart0Size),
> + ,
> + ,
> + ,
> + AddressRangeMemory,
> + TypeStatic
> + )
> +
> + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) {
> + FixedPcdGet32 (PcdIoVirtBlkUart0Interrupt)
> + }
> + })
> + }
> +
> + // IO Virtualization Block - PL011 UART1
> + Device (COM5) {
> + Name (_HID, "ARMH0011")
> + Name (_UID, 5)
> + Name (_STA, 0xF)
> +
> + Name (_CRS, ResourceTemplate () {
> + QWordMemory (
> + ResourceProducer,
> + PosDecode,
> + MinFixed,
> + MaxFixed,
> + NonCacheable,
> + ReadWrite,
> + 0x0,
> + FixedPcdGet64 (PcdIoVirtBlkUart1Base),
> + FixedPcdGet64 (PcdIoVirtBlkUart1End),
> + 0x0,
> + FixedPcdGet32 (PcdIoVirtBlkUart1Size),
> + ,
> + ,
> + ,
> + AddressRangeMemory,
> + TypeStatic
> + )
> +
> + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) {
> + FixedPcdGet32 (PcdIoVirtBlkUart1Interrupt)
> + }
> + })
> + }
> +
> + // IO Virtualization Block - PL330 DMA0
> + Device (\_SB.DMA0) {
> + Name (_HID, "ARMH0330")
Is there a specification for the description of this _HID and how
it should be represented in ACPI ?
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [edk2-devel] [edk2-platforms][PATCH V1 3/6] Platform/Sgi: Initialize additional uart controllers
2022-02-14 12:13 ` [edk2-platforms][PATCH V1 3/6] Platform/Sgi: Initialize additional uart controllers Vivek Kumar Gautam
@ 2022-12-07 13:34 ` PierreGondois
0 siblings, 0 replies; 10+ messages in thread
From: PierreGondois @ 2022-12-07 13:34 UTC (permalink / raw)
To: devel, vivek.gautam; +Cc: Sami Mujawar, Ard Biesheuvel, Leif Lindholm
Hello Vivek,
I just have one minor comment,
On 2/14/22 13:13, Vivek Kumar Gautam via groups.io wrote:
> From: Shriram K <shriram.k@arm.com>
>
> The IO virtualization block on reference design platforms allow
> connecting non-discoverable devices such as PL011 UART. On platforms
> that support this, initialize the UART controller connected to the
> IO virtualization block.
>
> Signed-off-by: Shriram K <shriram.k@arm.com>
> Signed-off-by: Vivek Gautam <vivek.gautam@arm.com>
> ---
> Platform/ARM/SgiPkg/SgiPlatform.dec | 1 +
> Platform/ARM/SgiPkg/RdN2/RdN2.dsc | 4 ++
> Platform/ARM/SgiPkg/RdN2Cfg1/RdN2Cfg1.dsc | 6 +-
> Platform/ARM/SgiPkg/Drivers/PlatformDxe/PlatformDxe.inf | 7 +-
> Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.inf | 8 ++-
> Platform/ARM/SgiPkg/Drivers/PlatformDxe/PlatformDxe.c | 73 +++++++++++++++++++-
> Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLibMem.c | 19 ++++-
> 7 files changed, 112 insertions(+), 6 deletions(-)
>
[...]
> diff --git a/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLibMem.c b/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLibMem.c
> index 8139b75d8ee4..26fd873fa647 100644
> --- a/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLibMem.c
> +++ b/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLibMem.c
> @@ -1,6 +1,6 @@
> /** @file
> *
> -* Copyright (c) 2018-2020, ARM Limited. All rights reserved.
> +* Copyright (c) 2018-2022, ARM Limited. All rights reserved.
> *
> * SPDX-License-Identifier: BSD-2-Clause-Patent
> *
> @@ -17,7 +17,8 @@
>
> // Total number of descriptors, including the final "end-of-table" descriptor.
> #define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS \
> - (14 + (FixedPcdGet32 (PcdChipCount) * 2))
> + (14 + (FixedPcdGet32 (PcdChipCount) * 2)) + \
> + (FeaturePcdGet (PcdIoVirtBlkNonDiscoverable) * 2)
Shouldn't it be dependent on PcdIoVirtBlkNonDiscoverable's value ?
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [edk2-devel] [edk2-platforms][PATCH V1 2/6] Platform/Sgi: add ssdt table for non-discoverable IO virtualization block
2022-12-07 13:34 ` [edk2-devel] " PierreGondois
@ 2023-01-27 6:17 ` Vivek Kumar Gautam
0 siblings, 0 replies; 10+ messages in thread
From: Vivek Kumar Gautam @ 2023-01-27 6:17 UTC (permalink / raw)
To: Pierre Gondois, devel; +Cc: Sami Mujawar, Ard Biesheuvel, Leif Lindholm
Hi Pierre,
On 12/7/22 19:04, Pierre Gondois wrote:
> Hello Vivek,
> Sorry for the long wait. I think the whole patchset needs to be
> rebased on latest master. I just have some comments for patches:
> - [PATCH V1 2/6] Platform/Sgi: add ssdt table for non-discoverable IO
> virtualization block
> - [PATCH V1 3/6] Platform/Sgi: Initialize additional uart controllers
> The other patches look good to me.
>
Thank you for your review and apologies for responding late. I was able
to rework the patches and get a cleaner SSDT table implementation. I
will post the patches soon.
Please see my responses inline.
> Regards,
> Pierre
>
> On 2/14/22 13:13, Vivek Kumar Gautam via groups.io wrote:
>> Arm reference design platforms such as RD-N2 and RD-N2-Cfg1 have
>> multiple
>> IO virtualization blocks that allow connecting PCIe root bus or non-PCIe
>> devices to the system. For platforms that connect non-discoverable (non-
>> PCI) devices to IO virtualization block, add a SSDT table to describe
>> such devices and use PCDs for the memory region and interrupts of these
>> devices in the table entry.
>> There are two PL011 UART controllers and two PL330 DMA controllers
>> connected to the non-PCIe IO virtualization block on RD-N2 and
>> RD-N2-Cfg1 platforms. List them in the SSDT ACPI table.
>>
>> While we are adding SSDT table entries for RD-N2 and RD-N2-Cfg1
>> remove the source file entries for incorrect SSDT and MCFG tables
>> for RD-N2 and RD-N2-Cfg1 platforms.
>>
>> Signed-off-by: Vivek Gautam <vivek.gautam@arm.com>
>> ---
>> Platform/ARM/SgiPkg/SgiPlatform.dec | 42 ++++
>> Platform/ARM/SgiPkg/SgiMemoryMap2.dsc.inc | 40 ++++
>> Platform/ARM/SgiPkg/AcpiTables/RdN2AcpiTables.inf | 45 ++++-
>> Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1AcpiTables.inf | 45 ++++-
>> Platform/ARM/SgiPkg/AcpiTables/SsdtNonPciIoVirtBlk.asl | 203
>> ++++++++++++++++++++
>> 5 files changed, 369 insertions(+), 6 deletions(-)
>>
>> diff --git a/Platform/ARM/SgiPkg/SgiPlatform.dec
>> b/Platform/ARM/SgiPkg/SgiPlatform.dec
>> index 05079743c452..6b3e28c3a08e 100644
>> --- a/Platform/ARM/SgiPkg/SgiPlatform.dec
>> +++ b/Platform/ARM/SgiPkg/SgiPlatform.dec
>> @@ -95,5 +95,47 @@
>> gArmSgiTokenSpaceGuid.PcdOscLpiEnable|0|UINT32|0x00000025
>> gArmSgiTokenSpaceGuid.PcdOscCppcEnable|0|UINT32|0x00000026
>> + # IO virtualization block PL011 UARTs
>> + gArmSgiTokenSpaceGuid.PcdIoVirtBlkUart0Base|0|UINT64|0x0000002C
>> + gArmSgiTokenSpaceGuid.PcdIoVirtBlkUart0End|0|UINT64|0x0000002D
>
> I think it should be possible to remove all the Pcd*End addresses and
> replace them with (PcdIoVirtBlkUart0Base + PcdIoVirtBlkUart0Size - 1).
I will post the reworked patch-set addressing this.
>
>> + gArmSgiTokenSpaceGuid.PcdIoVirtBlkUart0Size|0|UINT64|0x0000002E
>> + gArmSgiTokenSpaceGuid.PcdIoVirtBlkUart0Interrupt|0|UINT32|0x0000002F
>> +
>> + gArmSgiTokenSpaceGuid.PcdIoVirtBlkUart1Base|0|UINT64|0x00000030
>> + gArmSgiTokenSpaceGuid.PcdIoVirtBlkUart1End|0|UINT64|0x00000031
>> + gArmSgiTokenSpaceGuid.PcdIoVirtBlkUart1Size|0|UINT64|0x00000032
>> + gArmSgiTokenSpaceGuid.PcdIoVirtBlkUart1Interrupt|0|UINT32|0x00000033
>> +
>
> [...]
>
>> gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
>> diff --git a/Platform/ARM/SgiPkg/AcpiTables/SsdtNonPciIoVirtBlk.asl
>> b/Platform/ARM/SgiPkg/AcpiTables/SsdtNonPciIoVirtBlk.asl
>> new file mode 100644
>> index 000000000000..a035186b88db
>> --- /dev/null
>> +++ b/Platform/ARM/SgiPkg/AcpiTables/SsdtNonPciIoVirtBlk.asl
>> @@ -0,0 +1,203 @@
>> +/** @file
>> + Secondary System Description Table (SSDT) for Non-PCIe IO
>> + Virtualization Block.
>> +
>> + The IO virtualization block present on reference design platforms
>> + such as RD-N2 and RD-N2-Cfg1 allows connecting PCIe and non-PCIe
>> + devices. The non-discoverable (non-PCIe) devices that are connected
>> + to the IO virtualization block include two PL011 UART and two PL330
>> + DMA controllers.
>> +
>> + Copyright (c) 2022, Arm Ltd. All rights reserved.
>> + SPDX-License-Identifier: BSD-2-Clause-Patent
>> +
>> + @par Specification Reference:
>> + - ACPI 6.4, Chapter 5, Section 5.2.11.2, Secondary System
>> Description Table
>> +**/
[snip]
>>
>> +
>> + // IO Virtualization Block - PL330 DMA0
>> + Device (\_SB.DMA0) {
>> + Name (_HID, "ARMH0330")
>
> Is there a specification for the description of this _HID and how
> it should be represented in ACPI ?
Yes, this can be found in the ACPI specification here [1]. The Linux
kernel documentation also describes it here [2] as the primary object to
use in device probing.
[1]
https://uefi.org/htmlspecs/ACPI_Spec_6_4_html/06_Device_Configuration/Device_Configuration.html#device-identification-objects
[2] https://docs.kernel.org/arm64/acpi_object_usage.html
Best regards
Vivek
^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2023-01-27 6:17 UTC | newest]
Thread overview: 10+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2022-02-14 12:13 [edk2-platforms][PATCH V1 0/6] Add non-discoverable IO block for Rd-N2 Vivek Kumar Gautam
2022-02-14 12:13 ` [edk2-platforms][PATCH V1 1/6] Platform/Sgi: add PCDs for SMMUv3 base address and interrupts Vivek Kumar Gautam
2022-02-14 12:13 ` [edk2-platforms][PATCH V1 2/6] Platform/Sgi: add ssdt table for non-discoverable IO virtualization block Vivek Kumar Gautam
2022-12-07 13:34 ` [edk2-devel] " PierreGondois
2023-01-27 6:17 ` Vivek Kumar Gautam
2022-02-14 12:13 ` [edk2-platforms][PATCH V1 3/6] Platform/Sgi: Initialize additional uart controllers Vivek Kumar Gautam
2022-12-07 13:34 ` [edk2-devel] " PierreGondois
2022-02-14 12:13 ` [edk2-platforms][PATCH V1 4/6] Platform/Sgi: add helper macros for ITS, SMMUv3 and DMA IORT nodes Vivek Kumar Gautam
2022-02-14 12:13 ` [edk2-platforms][PATCH V1 5/6] Platform/Sgi: add IORT table for IO virtualization block on RD-N2-Cfg1 Vivek Kumar Gautam
2022-02-14 12:13 ` [edk2-platforms][PATCH V1 6/6] Platform/Sgi: add IORT table for IO virtualization block on RD-N2 Vivek Kumar Gautam
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