From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.web12.33202.1644840808191154365 for ; Mon, 14 Feb 2022 04:13:28 -0800 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: arm.com, ip: 217.140.110.172, mailfrom: vivek.gautam@arm.com) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id C03221474; Mon, 14 Feb 2022 04:13:27 -0800 (PST) Received: from usa.arm.com (a074945.blr.arm.com [10.162.16.71]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 23DA23F718; Mon, 14 Feb 2022 04:13:25 -0800 (PST) From: "Vivek Kumar Gautam" To: devel@edk2.groups.io Cc: Sami Mujawar , Ard Biesheuvel , Leif Lindholm , Vivek Gautam Subject: [edk2-platforms][PATCH V1 6/6] Platform/Sgi: add IORT table for IO virtualization block on RD-N2 Date: Mon, 14 Feb 2022 17:43:07 +0530 Message-Id: <20220214121307.14608-7-vivek.gautam@arm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220214121307.14608-1-vivek.gautam@arm.com> References: <20220214121307.14608-1-vivek.gautam@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Arm reference design RD-N2 platform has multiple I/O virtualization blocks that allow connecting PCIe root bus or non-PCIe devices to the system. Each of the I/O virtualization blocks (IoVirtBlk) consists of an Arm SMMUv3 compliant MMU-700 controller to handle address translations and a GIC-700 Interrupt Translation Service (ITS) to support message signaled interrupts (MSIs). Add an IORT table for non-discoverable (non-PCIe) devices connected to one of the I/O virtualization blocks - IoVirtBlk #4 on RD-N2. In addition to SMMUv3 and ITS nodes, two Named Compoenent nodes are also added for PL330 DMA controllers connected to IoVirtBlk #4. While we are adding the IORT table entries for RD-N2 platform, remove the source file entries for incorrect IORT table. Signed-off-by: Vivek Gautam --- Platform/ARM/SgiPkg/AcpiTables/RdN2AcpiTables.inf | 13 ++++- Platform/ARM/SgiPkg/AcpiTables/RdN2/IortNonPciIoVirtBlk.aslc | 58 ++++++= ++++++++++++++ 2 files changed, 70 insertions(+), 1 deletion(-) diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN2AcpiTables.inf b/Platform= /ARM/SgiPkg/AcpiTables/RdN2AcpiTables.inf index fe50a7b6e44a..efcd2ce48256 100644 --- a/Platform/ARM/SgiPkg/AcpiTables/RdN2AcpiTables.inf +++ b/Platform/ARM/SgiPkg/AcpiTables/RdN2AcpiTables.inf @@ -18,8 +18,8 @@ Dbg2.aslc Fadt.aslc Gtdt.aslc - Iort.aslc RdN2/Dsdt.asl + RdN2/IortNonPciIoVirtBlk.aslc RdN2/Madt.aslc RdN2/Pptt.aslc Spcr.aslc @@ -58,6 +58,12 @@ gArmSgiTokenSpaceGuid.PcdGtFrame1Gsiv gArmSgiTokenSpaceGuid.PcdOscLpiEnable gArmSgiTokenSpaceGuid.PcdOscCppcEnable + gArmSgiTokenSpaceGuid.PcdSmmuBase + gArmSgiTokenSpaceGuid.PcdSmmuEventGsiv + gArmSgiTokenSpaceGuid.PcdSmmuGErrorGsiv + gArmSgiTokenSpaceGuid.PcdSmmuPriGsiv + gArmSgiTokenSpaceGuid.PcdSmmuSyncGsiv + gArmSgiTokenSpaceGuid.PcdSmmuDevIDBase gArmSgiTokenSpaceGuid.PcdSp804DualTimerBaseAddress gArmSgiTokenSpaceGuid.PcdSp804DualTimerSize gArmSgiTokenSpaceGuid.PcdSp804DualTimerInterrupt @@ -70,6 +76,11 @@ gArmSgiTokenSpaceGuid.PcdWdogWS0Gsiv gArmSgiTokenSpaceGuid.PcdWdogWS1Gsiv =20 + gArmSgiTokenSpaceGuid.PcdPciex16DevIDBase + gArmSgiTokenSpaceGuid.PcdPciex8DevIDBase + gArmSgiTokenSpaceGuid.PcdPciex41DevIDBase + gArmSgiTokenSpaceGuid.PcdPciex40DevIDBase + gArmSgiTokenSpaceGuid.PcdIoVirtBlkUart0Base gArmSgiTokenSpaceGuid.PcdIoVirtBlkUart0End gArmSgiTokenSpaceGuid.PcdIoVirtBlkUart0Size diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN2/IortNonPciIoVirtBlk.aslc= b/Platform/ARM/SgiPkg/AcpiTables/RdN2/IortNonPciIoVirtBlk.aslc new file mode 100644 index 000000000000..84f482d36cba --- /dev/null +++ b/Platform/ARM/SgiPkg/AcpiTables/RdN2/IortNonPciIoVirtBlk.aslc @@ -0,0 +1,58 @@ +/** @file + I/O Remapping Table (IORT) for RD-N2 platform. + + This file presents the I/O Remapping Table for Non-PCIe I/O + virtualization block present on RD-N2 platform that connects + non-discoverable (non-PCIe) devices. + I/O virtualization blocks are combination of SMMUv3, GIC ITS, + a local interconnect and Root-Ports to connect PCIe or non-PCIe + devices. + + Copyright (c) 2022, Arm Ltd. All rights reserved. + SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Specification Reference: + - IORT specification version E.b +**/ + +#include "SgiAcpiHeader.h" + +#pragma pack(1) + +typedef struct +{ + EFI_ACPI_6_0_IO_REMAPPING_TABLE Header; + ARM_EFI_ACPI_6_0_IO_REMAPPING_ITS_NODE ItsNode; + ARM_EFI_ACPI_6_0_IO_REMAPPING_SMMU3_NODE SmmuNode; + ARM_EFI_ACPI_6_0_IO_REMAPPING_DMA_NC_NODE DmaNode[2]; +} ARM_EFI_ACPI_6_0_IO_REMAPPING_TABLE; + +#pragma pack () + +ARM_EFI_ACPI_6_0_IO_REMAPPING_TABLE Iort =3D +{ + // EFI_ACPI_6_0_IO_REMAPPING_TABLE + { + ARM_ACPI_HEADER // EFI_ACPI_DESCRIPTION_HEADER + ( + EFI_ACPI_6_2_IO_REMAPPING_TABLE_SIGNATURE, + ARM_EFI_ACPI_6_0_IO_REMAPPING_TABLE, + EFI_ACPI_IO_REMAPPING_TABLE_REVISION + ), + 4, // NumNodes + sizeof (EFI_ACPI_6_0_IO_REMAPPING_TABLE), // NodeOffset + 0, // Reserved + }, + + EFI_ACPI_ITS_INIT(4), + + EFI_ACPI_SMMUv3_INIT(4), + + // DMA Named Component nodes - DMA0 & DMA1 + { + EFI_ACPI_DMA_NC_INIT(0, "\\_SB_.DMA0"), + EFI_ACPI_DMA_NC_INIT(1, "\\_SB_.DMA1"), + }, +}; + +VOID* CONST ReferenceAcpiTable =3D &Iort; --=20 2.17.1